A method for monitoring a psi5 signal

Abstract

This invention discloses a PSI5 signal monitoring method, relating to the field of automotive electronics technology, and applied to a PSI5 signal monitoring device. The device includes a digital processing unit and a synchronous communication mode. The synchronous communication mode includes the following steps: detecting synchronous pulses sent by corresponding ECUs through at least one synchronous pulse triggering circuit. This invention is compatible with both synchronous and asynchronous PSI5 communication monitoring modes. In synchronous mode, a synchronous pulse interrupt triggering mechanism is used to immediately read the data level when a valid synchronization signal is detected, significantly reducing the risk of data loss and timing offset caused by polling, and significantly improving decoding accuracy and real-time performance. In asynchronous mode, synchronization information is extracted by continuously monitoring level transitions, fully adapting to communication scenarios without synchronous pulses. The two modes operate independently and do not interfere with each other, comprehensively covering the monitoring needs of different communication standards of the PSI5 bus.

Description

Technical Field

[0001] This invention relates to the field of automotive electronics technology, and more specifically, to a method for monitoring PSI5 signals. Background Technology

[0002] As a mainstream sensor communication interface in the automotive electronics field, the PSI5 protocol is widely used for data interaction between key vehicle electronic control units (ECUs) and peripheral sensors, such as airbags, electronic suspension, and braking systems. During the development, debugging, testing, and fault diagnosis of ECUs and sensors, real-time and accurate monitoring and parsing of communication data on the bus is essential to ensure system functionality and reliability. Most existing PSI5 signal monitoring methods employ occupancy-based simulation and data reading schemes, requiring the interruption of existing bus communication or the occupation of bus nodes to complete data acquisition. This not only interferes with the normal interaction between the ECU and sensors but also fails to meet the requirement of interference-free monitoring during online operation, thus limiting its applicability.

[0003] Existing monitoring methods generally lack compatibility with both synchronous and asynchronous communication modes. In synchronous mode, they lack accurate detection and rapid response mechanisms for synchronization pulses, often relying on polling to read data, which is prone to timing deviations, data loss, or parsing misalignments. In asynchronous mode, they cannot effectively extract synchronization information from continuous data streams, resulting in low decoding success rates and poor stability. Furthermore, traditional monitoring solutions often rely on dedicated protocol chips or complex software algorithms, leading to high hardware costs, cumbersome deployment, and limited interface options. These limitations make them unsuitable for diverse testing and diagnostic scenarios such as PC debugging, vehicle data logging, and offline fault analysis, failing to meet the requirements for efficient, reliable, and flexible PSI5 bus monitoring.

[0004] No effective solutions have yet been proposed to address the problems in the relevant technologies. Summary of the Invention

[0005] To address the problems in related technologies, this invention provides a PSI5 signal monitoring method that is compatible with both synchronous and asynchronous communication modes, enables interference-free passive monitoring, accurately detects synchronization pulses, and efficiently reconstructs data frames, thus solving the problems of large monitoring interference, low parsing reliability, and single mode in existing methods.

[0006] The technical solution of this invention is implemented as follows:

[0007] One aspect of the present invention:

[0008] A PSI5 signal monitoring method is applied to a PSI5 signal monitoring device, the device including a digital processing unit and a synchronous communication mode, the synchronous communication mode including the following steps:

[0009] The synchronization pulses sent by the corresponding ECU are detected by at least one synchronization pulse triggering circuit, and a first digital signal is output to the corresponding first digital signal input terminal of the digital processing unit. Each first digital signal input terminal is configured as an interrupt trigger pin.

[0010] The differential signal corresponding to the sensor current change on the PSI5 bus is obtained by the DC blocking sampling circuit;

[0011] The differential signal input signal conditioning circuit converts it into a single-ended analog signal;

[0012] The single-ended analog signal is shaped into a second digital signal by a comparison and shaping circuit, and then connected to the corresponding second digital signal input terminal of the digital processing unit.

[0013] When any of the first digital signal input terminals receives the corresponding first digital signal and triggers an interrupt, the level state of the corresponding second digital signal input terminal is read in the corresponding interrupt service routine, and the data frame on the corresponding PSI5 bus is restored according to the PSI5 protocol timing.

[0014] The restored data frames are output to external devices via the communication module.

[0015] The first digital signal is a step signal used to trigger an external interrupt to the digital processing unit.

[0016] The DC blocking sampling circuit is connected to the PSI5 bus in series with a sampling resistor, and the differential signal is obtained through a DC blocking capacitor and a bias resistor.

[0017] The signal conditioning circuit converts the differential signal into a single-ended analog signal using a differential amplifier; the comparison shaping circuit shapes the single-ended analog signal into a second digital signal in Manchester encoding format by comparing it with a reference voltage.

[0018] The digital processing unit reads the level state of the second digital signal input terminal in real time during the interrupt service routine.

[0019] Another aspect of the present invention:

[0020] A PSI5 signal monitoring method is applied to a PSI5 signal monitoring device, the device including a digital processing unit and an asynchronous communication mode, the asynchronous communication mode including the following steps:

[0021] The differential signal corresponding to the sensor current change on the PSI5 bus is obtained by the DC blocking sampling circuit;

[0022] The differential signal input signal conditioning circuit converts it into a single-ended analog signal;

[0023] The single-ended analog signal is shaped into a second digital signal by a comparison and shaping circuit, and then connected to the corresponding second digital signal input terminal of the digital processing unit.

[0024] The digital processing unit continuously monitors the level status of the corresponding second digital signal input terminal and restores the data frame on the corresponding PSI5 bus according to the PSI5 protocol timing.

[0025] The restored data frames are output to external devices via the communication module.

[0026] In the asynchronous communication mode, the digital processing unit monitors the level transitions of the second digital signal through timed sampling or input capture of a hardware timer, extracts synchronization information from the monitored data stream, and then restores the data frame according to the PSI5 protocol timing.

[0027] The PSI5 signal monitoring device includes multiple channels, each channel is equipped with an independent synchronous pulse triggering circuit, DC blocking sampling circuit, signal conditioning circuit and comparison shaping circuit. The digital processing unit allocates an independent first digital signal input terminal and a second digital signal input terminal to each channel, and each channel performs monitoring in parallel and independently.

[0028] The beneficial effects of this invention are:

[0029] 1. This invention is compatible with both synchronous and asynchronous communication monitoring modes of PSI5. In synchronous mode, a synchronous pulse interrupt triggering mechanism is used to immediately read the data level when a valid synchronization signal is detected, which greatly reduces the risk of data loss and timing offset caused by polling and significantly improves decoding accuracy and real-time performance. In asynchronous mode, synchronization information is extracted by continuously monitoring level transitions, which fully adapts to communication scenarios without synchronization pulses. The two modes operate independently and do not interfere with each other, which can fully cover the monitoring needs of different communication standards of PSI5 bus.

[0030] 2. This invention adopts a non-occupied signal acquisition method, which does not change the original bus topology, does not occupy communication nodes, and does not affect the normal operation of ECU and sensors, enabling online interference-free monitoring; at the same time, it supports independent parallel analysis of multiple channels, with each channel's process separated and timing unaffected, effectively improving the efficiency of simultaneous testing of multiple buses; the overall method relies on a combination of hardware signal conditioning and software timing analysis, requiring no dedicated protocol chip, making it simple to implement, lower in cost, and with flexible communication interfaces, adaptable to various test equipment and diagnostic scenarios, with stronger versatility and practicality. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a block diagram of the overall structure of the PSI5 signal monitoring device provided in an embodiment of the present invention;

[0033] Figure 2 This is a circuit schematic diagram of the power module in an embodiment of the present invention;

[0034] Figure 3 This is a circuit diagram of the reference voltage generation unit in an embodiment of the present invention;

[0035] Figure 4 This is a circuit diagram of the synchronous pulse triggering circuit in an embodiment of the present invention;

[0036] Figure 5 This is a circuit diagram of the DC blocking sampling circuit in an embodiment of the present invention;

[0037] Figure 6 This is a circuit diagram of the signal conditioning circuit in an embodiment of the present invention;

[0038] Figure 7 This is a circuit diagram of the comparison shaping circuit in an embodiment of the present invention;

[0039] Figure 8 This is a circuit schematic diagram of the digital processing unit and the communication module in an embodiment of the present invention;

[0040] Figure 9 A flowchart of the PSI5 signal monitoring method provided in an embodiment of the present invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0042] Example 1;

[0043] According to Embodiment 1 of the present invention, a single-channel PSI5 signal monitoring method is provided.

[0044] like Figures 1-9As shown, the single-channel PSI5 signal monitoring method according to an embodiment of the present invention is applied to a PSI5 signal monitoring device, which includes a power supply module, a synchronous pulse triggering circuit, a DC blocking sampling circuit, a signal conditioning circuit, a comparison and shaping circuit, a digital processing unit, and a communication module.

[0045] Specifically, during implementation, the single-channel PSI5 signal monitoring device is as follows:

[0046] PSI5 bus connection instructions for this technical solution:

[0047] The PSI5 bus input terminal connects to the vehicle ECU and includes two wires: PSI5IN1+ and PSI5IN1-. PSI5IN1+ is connected to the PSI5 data line, and PSI5IN1- is grounded.

[0048] The PSI5 bus output terminal connects to the PSI5 sensor and includes two wires: PSI5OUT1+ and PSI5OUT1-. PSI5OUT1+ is connected to the PSI5 data line, and PSI5OUT1- is grounded.

[0049] PSI5IN1+ is connected to the first terminal of the sampling resistor R68, and also to the first terminal of the current-limiting resistor R71 of the synchronous pulse trigger circuit.

[0050] PSI5OUT1+ is connected to the second terminal of the sampling resistor R68.

[0051] Specifically, regarding the power module, refer to... Figure 2 The power module includes:

[0052] The power input terminal VBAT is used to connect to a DC voltage, such as a 12V car power supply or a 5V USB power supply.

[0053] The first voltage conversion unit uses a DC-DC step-down chip U18 to convert the input voltage into a stable first DC voltage (5V in this embodiment). The input terminal of U18 is connected to VBAT, and the output terminal is connected to 5V.

[0054] The second voltage conversion unit uses a low-dropout linear regulator U17 to convert the first DC voltage into a second DC voltage (3.3V in this embodiment) to power the digital processing unit, communication module, synchronous pulse trigger circuit, signal conditioning circuit, and comparison shaping circuit. The input terminal of U17 is connected to 5V, and the output terminal is connected to 3.3V.

[0055] The reference voltage generation unit, as a component of the power supply module, refers to... Figure 3The system includes a first reference voltage generation circuit and a second reference voltage generation circuit. The first reference voltage generation circuit consists of voltage divider resistors R72 and R73 and a filter capacitor C105. R72 and R73 are connected in series between the second DC voltage (3.3V) and ground. The midpoint of the second reference voltage generation circuit outputs the first reference voltage VREF1 through a voltage follower, which supplies the DC blocking sampling circuit. The second reference voltage generation circuit consists of voltage divider resistors R74 and R80 and a filter capacitor C107. R74 and R80 are connected in series between the second DC voltage (3.3V) and ground. The midpoint of the second reference voltage generation circuit outputs the second reference voltage VREF2 through a voltage follower, which supplies the comparison shaping circuit.

[0056] Specifically, for the synchronous pulse triggering circuit, refer to... Figure 4 The synchronous pulse triggering circuit includes:

[0057] The current-limiting resistor R71 has its first end connected to the PSI5 bus input terminal PSI5IN1+.

[0058] Zener diode D10 has its cathode connected to the second terminal of current-limiting resistor R71, and its anode connected to the base of transistor Q4.

[0059] The base resistor R69 is connected between the base of transistor Q4 and ground.

[0060] The base of transistor Q4 (NPN type) is connected to the anode of Zener diode D10 and the first terminal of base resistor R69, its emitter is grounded, and its collector is connected to the second DC voltage 3.3V through pull-up resistor R70.

[0061] The collector output of transistor Q4 is the first digital signal SYNC1, which is connected to the first input terminal (interrupt pin) of the digital processing unit.

[0062] Specifically, the DC blocking sampling circuit, refer to... Figure 5 The DC blocking sampling circuit in this embodiment includes:

[0063] A sampling resistor R68 is connected in series in the PSI5 bus. Its first end is connected to the PSI5 bus input terminal PSI5IN1+, and its second end is connected to the PSI5 bus output terminal PSI5OUT1+. A first DC blocking capacitor C103 and a second DC blocking capacitor C102 are connected. One end of the first DC blocking capacitor C103 is connected to the first end of the sampling resistor R68, and one end of the second DC blocking capacitor C102 is connected to the second end of the sampling resistor R68. A first bias resistor R75 is connected at one end to the other end of the first DC blocking capacitor C103, and the other end is connected to the first reference voltage VREF1. A second bias resistor R76 is connected at one end to the other end of the second DC blocking capacitor C102, and the other end is connected to the first reference voltage VREF1.

[0064] The other end of the first DC blocking capacitor C103 outputs the first differential signal PSI5IN1GL, and the other end of the second DC blocking capacitor C102 outputs the second differential signal PSI5IN1GR.

[0065] Specifically, for the signal conditioning circuit, refer to... Figure 6 The signal conditioning circuit in this embodiment includes:

[0066] Differential amplifier U23 has its non-inverting input connected to the first differential signal PSI5IN1GL, its inverting input connected to the second differential signal PSI5IN1GR, and its output terminal outputting the single-ended analog signal PSI5IN1A.

[0067] Specifically, compare the shaping circuits, refer to Figure 7 The comparison shaping circuit in this embodiment includes:

[0068] Comparator U26 has its non-inverting input connected to the single-ended analog signal PSI5IN1A, its inverting input connected to the second reference voltage VREF2, and its output outputting a second digital signal, which is connected to the second digital signal input of the digital processing unit.

[0069] Specifically, the digital processing unit and communication module, refer to Figure 8 The digital processing unit uses an MCU (such as the STM32 series). Its first input is configured as an external interrupt pin and connected to the first digital signal SYNC1; the second input is configured as a general-purpose input / output pin and connected to the data signal PSI5CH1.

[0070] The communication module integrates at least one of the following interfaces: serial port, CAN, and USB, enabling data output and external command reception.

[0071] Specifically, refer to Figure 9 This embodiment provides a single-channel PSI5 signal monitoring method, as detailed below:

[0072] The synchronous communication mode process is as follows:

[0073] Step S101: Configure the first digital signal input terminal of the digital processing unit as an interrupt trigger pin;

[0074] Step S102: The system waits and listens for synchronization pulse interruption;

[0075] Step S103: The synchronization pulse trigger circuit detects the synchronization pulse and outputs the first digital signal to trigger an interrupt;

[0076] Step S104: Immediately read the level state of the second digital signal input terminal in the interrupt service routine;

[0077] Step S105: Restore the complete data frame according to the PSI5 protocol timing;

[0078] Step S106: The data frame is output to an external device via the communication module;

[0079] Step S107: Return to the waiting state and listen for the next synchronization pulse.

[0080] The asynchronous communication mode process is as follows:

[0081] Step S201: The digital processing unit continuously monitors the second digital signal input terminal;

[0082] Step S202: Start recording the signal when a level transition is detected;

[0083] Step S203: Extract and restore the synchronous data frame from the data stream according to the PSI5 asynchronous protocol timing;

[0084] Step S204: The data frame is output via the communication module;

[0085] Step S205: Loop monitoring and process the next frame of data.

[0086] Example 2;

[0087] According to Embodiment 2 of the present invention, a multi-channel PSI5 signal monitoring method is provided.

[0088] Specifically, in the implementation process, based on the above embodiment one, it implements multi-channel expansion. By setting up multiple synchronous pulse trigger circuits, DC blocking sampling circuits, signal conditioning circuits and comparison shaping circuits, and allocating multiple interrupt pins and general-purpose IO pins of the digital processing unit, a multi-channel monitoring device is constructed. Each channel works independently and shares a power supply module and communication module, which can simultaneously monitor multiple PSI5 buses in real time.

[0089] In addition, specifically, its multi-channel PSI5 signal monitoring method involves configuring independent synchronous pulse triggering, DC blocking sampling, signal conditioning and comparison shaping circuits for each of the multiple PSI5 buses. The digital processing unit allocates independent interrupt pins and data input pins to each channel, and the synchronous / asynchronous monitoring process is executed independently for each channel, realizing multi-channel parallel interference-free monitoring.

[0090] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Those skilled in the art, upon considering the disclosure in the specification and embodiments, will readily conceive of other embodiments of this disclosure. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0091] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A PSI5 signal monitoring method, applied to a PSI5 signal monitoring device, the device comprising a digital processing unit, characterized in that, This includes a synchronous communication mode, which comprises the following steps: The synchronization pulses sent by the corresponding ECU are detected by at least one synchronization pulse triggering circuit, and a first digital signal is output to the corresponding first digital signal input terminal of the digital processing unit. Each first digital signal input terminal is configured as an interrupt trigger pin. The differential signal corresponding to the sensor current change on the PSI5 bus is obtained by the DC blocking sampling circuit; The differential signal input signal conditioning circuit converts it into a single-ended analog signal; The single-ended analog signal is shaped into a second digital signal by a comparison and shaping circuit, and then connected to the corresponding second digital signal input terminal of the digital processing unit. When any of the first digital signal input terminals receives the corresponding first digital signal and triggers an interrupt, the level state of the corresponding second digital signal input terminal is read in the corresponding interrupt service routine, and the data frame on the corresponding PSI5 bus is restored according to the PSI5 protocol timing. The restored data frames are output to external devices via the communication module.

2. The PSI5 signal monitoring method according to claim 1, characterized in that, In the synchronous communication mode, the first digital signal is a step signal used to trigger an external interrupt to the digital processing unit.

3. The PSI5 signal monitoring method according to claim 1, characterized in that, The DC blocking sampling circuit is connected in series to the PSI5 bus through a sampling resistor, and obtains the differential signal through a DC blocking capacitor and a bias resistor.

4. The PSI5 signal monitoring method according to claim 1, characterized in that, The signal conditioning circuit converts the differential signal into a single-ended analog signal through a differential amplifier; the comparison shaping circuit shapes the single-ended analog signal into a second digital signal in Manchester encoding format by comparing it with a reference voltage.

5. The PSI5 signal monitoring method according to claim 1, characterized in that, The digital processing unit reads the level state of the second digital signal input terminal in real time during the interrupt service routine.

6. A PSI5 signal monitoring method, applied to a PSI5 signal monitoring device, the device comprising a digital processing unit, characterized in that, This includes an asynchronous communication mode, which comprises the following steps: The differential signal corresponding to the sensor current change on the PSI5 bus is obtained by the DC blocking sampling circuit; The differential signal input signal conditioning circuit converts it into a single-ended analog signal; The single-ended analog signal is shaped into a second digital signal by a comparison and shaping circuit, and then connected to the corresponding second digital signal input terminal of the digital processing unit. The digital processing unit continuously monitors the level status of the corresponding second digital signal input terminal and restores the data frame on the corresponding PSI5 bus according to the PSI5 protocol timing. The restored data frames are output to external devices via the communication module.

7. The PSI5 signal monitoring method according to claim 6, characterized in that, In the asynchronous communication mode, the digital processing unit monitors the level transition of the second digital signal by timed sampling or input capture of a hardware timer, extracts synchronization information from the monitored data stream, and then restores the data frame according to the PSI5 protocol timing.

8. The PSI5 signal monitoring method according to claim 1 or 6, characterized in that, The PSI5 signal monitoring device includes multiple channels, each channel is equipped with an independent synchronous pulse triggering circuit, DC blocking sampling circuit, signal conditioning circuit and comparison shaping circuit. The digital processing unit allocates an independent first digital signal input terminal and a second digital signal input terminal to each channel, and each channel performs monitoring in parallel and independently.

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