Circuits and methods for service activation testing (SAT)

By using hardware mechanisms such as frame generators and data rate sniffers to dynamically monitor and control the generator's traffic rate, the accuracy and real-time performance issues of SAT under dynamic network conditions are resolved. This enables earlier identification and resolution of network bottlenecks, improving network reliability and user experience.

CN122496433APending Publication Date: 2026-07-31MARVELL ASIA PTE LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
MARVELL ASIA PTE LTD
Filing Date
2026-01-29
Publication Date
2026-07-31

AI Technical Summary

Technical Problem

Existing Service Activation Test (SAT) methods are insufficient for accurately and in real-time verifying the performance of Ethernet services under dynamic network conditions, and cannot effectively identify and resolve potential bottlenecks and performance issues.

Method used

A hardware mechanism consisting of a frame generator and a data rate sniffer is adopted to ensure that the incoming and injected traffic on the channel meets the target rate by dynamically monitoring and controlling the rate of the generator traffic, thereby achieving dynamic real-time adjustment to simulate real-world traffic conditions.

Benefits of technology

It improves the accuracy and real-time performance of service activation testing, enabling earlier identification and resolution of potential network bottlenecks, thereby improving network reliability and user experience.

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Abstract

Embodiments of this disclosure relate to circuitry and methods for Service Activation Testing (SAT). A circuit and corresponding method inject generator traffic into a channel used for SAT based on a configurable rate. The circuitry includes a frame generator that injects generator traffic into the channel used for SAT based on a configurable rate. The channel contains incoming traffic on the channel and injected generator traffic. The channel is associated with a target rate. The frame generator includes a controller. The circuitry also includes a data rate sniffer to monitor the channel and generate feedback influenced by the incoming traffic and injected generator traffic. The controller dynamically controls the configurable rate used for SAT based on the feedback generated by the data rate sniffer and the target rate. The circuitry and corresponding method add dynamic real-time capabilities, which contributes to more accurate and diverse measurements for SAT.
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Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more specifically, to circuits and methods for service activation testing (SAT). Background Technology

[0002] Service Activation Testing (SAT) is a standardized methodology used to verify and validate the performance of an Ethernet service before it is handed over (deployed) to a customer or in operational mode (before real traffic (frames, data) begins—i.e., actual user traffic relative to test (artificial) traffic). SAT ensures that the service meets a predefined Service Level Agreement (SLA) by testing performance indicators such as throughput, latency, jitter, and frame loss, for non-limiting examples. Summary of the Invention

[0003] According to an example embodiment, a circuit includes a frame generator configured to inject generator traffic into a channel used for Service Activation Test (SAT) based on a configurable rate. The channel contains incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The frame generator includes a controller. The circuit also includes a data rate sniffer configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate used for SAT based on the feedback generated by the data rate sniffer and the target rate.

[0004] The controller can also be configured to dynamically control the configurable rate for SAT by dynamically configuring the token bucket to cause the frame generator to produce generator traffic to supplement the actual line rate of the incoming traffic to achieve the target rate.

[0005] The data rate sniffer can also be configured to output at least one status indicator, wherein the at least one status indicator is configured to output at least one status indicator, wherein the at least one status indicator is configured to indicate the comparison result between the actual amount of injected generator traffic and the expected amount of generator traffic to be injected.

[0006] The channel can be a time-division multiplexed (TDM) channel. A data rate sniffer can be configured to monitor: the data rate of incoming traffic on the channel, the data rate of injected generator traffic, and the overall TDM data rate used for the channel.

[0007] The data rate sniffer can also be configured to output a status indication of the current and continuous average rates of the data rate for incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel.

[0008] The data rate sniffer can also be configured to monitor the data rate of incoming traffic on the channel, the data rate of injected generator traffic, and the overall TDM data rate for the channel based on the total number of clock cycles counted between sniffer analysis events. The value for the total number can be based on a power of 2 and a configured value for the token increment of the token counter in the token bucket of the frame generator.

[0009] Incoming traffic on the channel can have strict priority relative to injected generator traffic. The circuit may also include an output buffer. The output buffer may have a size of at least the maximum transmission unit (MTU).

[0010] Incoming traffic on the channel can have strict priority relative to injected generator traffic, and injected generator traffic can be restricted to single-word frames.

[0011] The data rate sniffer can also be configured to generate at least one sniffer statistic for SAT and output the generated at least one sniffer statistic.

[0012] At least one sniffer statistic may represent at least one performance indicator, and for a non-limiting example, the performance indicator may represent throughput, latency, jitter, frame loss, or a combination thereof.

[0013] According to another example embodiment, a method includes injecting generator traffic into a channel used for SAT based on a configurable rate. The channel contains incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The method also includes generating feedback by monitoring the channel. The generated feedback is influenced by the incoming traffic and the injected generator traffic. The method further includes dynamically controlling the configurable rate used for SAT based on the generated feedback and the target rate.

[0014] Further alternative embodiments are parallel to those described above in conjunction with the example circuit embodiments.

[0015] According to another example embodiment, an apparatus includes components for injecting generator traffic into a channel for SAT based on a configurable rate. The channel includes incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The apparatus also includes components for generating feedback by monitoring the channel. The generated feedback is influenced by the incoming traffic and the injected generator traffic. The apparatus also includes components for dynamically controlling the configurable rate for SAT based on the generated feedback and the target rate.

[0016] Further alternative device embodiments are parallel to those described above in conjunction with the example circuit embodiments.

[0017] According to another example embodiment, a system includes a network interface and a device. The device includes a frame generator configured to inject generator traffic into a channel for SAT based on a configurable rate. The channel contains incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The frame generator includes a controller. The device also includes a data rate sniffer configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate for SAT based on the feedback generated by the data rate sniffer and the target rate.

[0018] The system can be a server in at least one server in a data center, and the device can be a system-on-a-chip (SoC).

[0019] Further alternative system embodiments are parallel to those described above in conjunction with the example circuit embodiments.

[0020] According to another example embodiment, a Hardware Description Language (HDL) design construct is encoded on a machine-readable data storage medium. The HDL design construct includes elements that, when processed in a computer-aided design system, generate a machine-executable representation of the device. The HDL design construct includes a frame generator configured to inject generator traffic into a channel used for SAT based on a configurable rate. The channel contains incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The frame generator includes a controller. The HDL design construct also includes a data rate sniffer configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate used for SAT based on the feedback generated by the data rate sniffer and the target rate.

[0021] Further alternative HDL design architecture embodiments are parallel to those described above in conjunction with the example circuit embodiments.

[0022] It should be understood that the exemplary embodiments disclosed herein can be implemented in the form of circuits, methods, apparatus, systems or computer-readable media having program code embodied thereon. Attached Figure Description

[0023] The foregoing will become apparent from the following more detailed description of exemplary embodiments, as illustrated in the accompanying drawings, wherein the same reference numerals refer to the same parts in different views. The drawings are not necessarily drawn to scale, but rather focus on illustrating the embodiments.

[0024] Figure 1 This is a block diagram of an example embodiment of the circuit.

[0025] Figure 2 This is a block diagram of another example embodiment of the circuit.

[0026] Figure 3 This is a flowchart of an example embodiment of the method.

[0027] Figure 4 This is a block diagram of an example embodiment of a computer environment.

[0028] Figure 5 This is a block diagram of an example embodiment of a data center. Detailed Implementation

[0029] The example embodiment is described below.

[0030] In the context of a frame generator, the terms frame and multiple frames may be used interchangeably as group and multiple groups, respectively, since the generator may not know the type of payload being generated, such as a layer 2 (L2) frame or a layer 3 (L3) group.

[0031] It should be understood that the data rate sniffer referenced in this article may include multiple sniffers.

[0032] Frame generators used for Service Activation Test (SAT) are typically located at the chip's entry point, such as after the Receive (Rx) Media Access Controller (MAC) and before data path processing. Such frame generators can produce several artificial traffic streams, each typically configured to generate frames at a fixed (statically) configurable rate, implemented using a token bucket. The system containing this frame generator can be channelized and managed by Time Division Multiplexing (TDM), such that each channel contains both real Rx traffic (such as network traffic received from the network) and injected traffic from the SAT (the former having higher, stricter priority to prevent the SAT from affecting real traffic). For a given channel, the upstream data path can receive complete frames from start to finish (single source).

[0033] The example embodiments disclosed herein implement a hardware mechanism that monitors incoming Rx traffic on a channel and dynamically configures the token bucket of a SAT frame generator accordingly. This hardware mechanism may be referred to herein as a SAT generator (SATG). According to the example embodiments, the SAT frame generator can generate traffic that supplements the actual line rate to a target (desired) rate and measures performance under the generated conditions. The following conditions and terms may apply to this disclosure.

[0034] The SAT frame generator in this article can be simply referred to as the frame generator. The frame generation rate used by the frame generator can be handled by a Frame Rate Controller (FRTC), which can be called a Data Rate Controller, Rate Controller, or simply a controller. This controller can be configured to manage a single token bucket for each generated stream.

[0035] Token Increment: The controller can configure values ​​for the Tdelta and Tnum parameters per stream. The Tdelta parameter indicates the number of clock cycles to count between every two Tnum token increments. Token increments can ignore TDM, meaning they can count cycles continuously. Each token can allow a single data word to be generated (equivalent to 1 clock cycle). Another configuration parameter, Tburst, sets the upper limit of the token bucket for this stream.

[0036] Token decrement: Data words can only be generated if there is a match between the flow's configuration channel identifier (ID) (i.e., the TDM channel ID) and the incoming channel ID of the TDM mechanism. When the SAT generator needs to generate a new frame and the FRTC has enough tokens for the entire frame (i.e., the token counter is greater than the #words in the frame), the FRTC can decrement the token counter by the #words in the frame and generate a new word whenever a match with the TDM channel ID is found, until the frame is complete.

[0037] Regarding priority, Rx frames can be assigned a higher (stricter) priority than frames generated by SAT. This priority can be enforced by flow control instructions from upstream data path units. To alleviate the internal pipeline of SATG, a buffer can be implemented at the SATG output to temporarily absorb frame words when upstream units are busy with Rx data.

[0038] In a conventional approach, SATG can have four configurable streams, each with its own configured FRTC and associated parameter set (Tdelta, Tnum, Tburst). SATG can generate configured flow rates, but it does not indicate or relate to the existing "real" incoming Rx traffic on the channel. Users can change these configurations (e.g., via software), but these changes are not sensitive to Rx line utilization over time and are obviously too slow to respond to any real-time changes.

[0039] The example embodiments disclosed herein can implement a data rate sniffer, which may include multiple data rate sniffers, such as: a sniffer on incoming Rx traffic for channel [c], denoted as SI[c]; a sniffer on generated SATG words (generator traffic) for channel [c], denoted as SG[c]; and a sniffer on the overall TDM rate for channel [c], denoted as ST[c].

[0040] The example embodiments disclosed herein can represent the frequency of the data rate sniffer's analysis events (i.e., how many clock cycles to count between the data rate sniffer's analysis events) as Sdelta. The value of Sdelta can be a power of 2 of Tdelta, so the actual configuration value can be represented as update_factor = log2(Sdelta / Tdelta). The target data rate for channel [c], denoted as TR[c], may be affected by the actual Rx rate and the SATG generation rate. According to the example embodiments, the configuration can have two modes.

[0041] In the first mode, a total target (desired) rate can exist, i.e., the total actual combined rate from both the Rx line and SATG (dynamic mode). A reserved value can be provided for selecting the "full line rate". In the second mode, an additional target (desired) rate can exist, i.e., the target (desired) SATG generation rate (static mode).

[0042] According to the example embodiment, hardware logic can be implemented that checks SI[c], SG[c], and ST[c] every Sdelta time and calculates Snum based on TR, where Snum is the number of tokens that must be generated by SATG, until the next Sdelta event.

[0043] After calculating Snum[c], this type of hardware logic can update the value of Tnum[c] as follows:

[0044] Tnum[c] <= (Snum[c] >> update_factor), where Snum[c] can be calculated differently depending on the mode of TR[c]. For example, in dynamic mode: Snum[c] = TR[c] - SI[c] (if "full line rate" is selected, then ST[c] is used instead of TR[c]), while in static mode: Snum[c] = TR[c].

[0045] According to an example embodiment, SATG can provide a status indication for temporary and continuous average "SATG utilization," indicating how successful SATG is in opportunistically injecting its specified payload. For a single Sdelta (temporary), this figure is given by: SG[c][n] / Snum[c][n-1], Where “n” and “n-1” represent consecutive sniffer analysis events (“n” is the latter), and the utilization rate is measured as the actual amount injected during a specific Sdelta period divided by the expected amount injected. The cumulative average calculated over sniffer analysis events [N] is: ∑(n=1..N)(SG[c][n]) / ∑(n=0..N-1)(Snum[c][n]). Hardware logic can provide the numerator and denominator as two separate values ​​to the software.

[0046] According to an example embodiment, SATG can also provide status indications over time for both the current and continuous average values ​​of all data rate sniffer values, indicating both the current and continuous average rates of Rx / SATG / TDM. For non-limiting examples, such status indications can be output to a display screen or electronic document to provide statistical information to the user.

[0047] To mitigate the combination of the strict priority of Rx traffic over SATG traffic and the fact that frames are consumed from start to finish from a single source, two alternatives (methods) can be considered. The first method involves using a larger buffer (at least the size of the Maximum Transmission Unit (MTU)) at the SATG output, allowing for better regulation of local flow control effects and less impact on the SATG generation rate. The second method involves having SATG generate only single-word frames. These options aim to maximize opportunistic traffic injection into SATG.

[0048] Example implementations of hardware mechanisms for SAT add dynamic real-time capabilities, which facilitates more accurate and diverse measurements for service activation testing, as described in ITU Telecommunication Standardization Sector Y: Global Information Infrastructure, Internet Protocol Aspects and Next-Generation Networks, Internet of Things and Smart Cities, Internet Protocol Aspects—Quality of Service and Network Performance, Ethernet Service Activation Test Methodology, Y.1564 (02 / 2016) and Bradner et al., “Benchmarking Methodology for Network Interconnect Devices” RFC 2544, Internet Society, March 1999. Stress testing: Simulates real-world traffic conditions by dynamically adjusting the flow rate, which helps identify potential bottlenecks and performance issues. Real-time adjustment: Adapts to constantly changing network conditions in real time, thereby providing more accurate and relevant test results. Proactive problem identification: Identify and resolve potential problems before they impact service, thereby improving overall network reliability and client experience.

[0049] Using the example implementation of SATG's dynamic mode as described, past statistics can be used to infer future behavior. By utilizing a smaller Sdelta value, users can increase SATG's responsiveness to local (timely) changes. However, using too small a Sdelta value can lead to unstable behavior, preventing SATG from converging its FRTC parameters to generate the correct frame rate. Overcoming this challenge can be achieved using a stepwise approach, whereby Sdelta is gradually increased until it reaches a stable level (similar to a ramp load test). This method is more effective for traffic patterns that reach a stable level over a certain time interval. See below for reference. Figure 1 Example embodiments of circuits that can employ SATG dynamic mode are disclosed.

[0050] Figure 1 This is a block diagram of circuit 100 that can be used for SAT. Circuit 100 may include a frame generator 102 configured to inject generator traffic 106 into channel 108 for SAT based on a configurable rate 104. Channel 108 may contain incoming traffic 110 on channel 108 and injected generator traffic 106. Channel 108 may be associated with a target rate (not shown). Frame generator 102 may include a controller 112. Circuit 100 may also include a data rate sniffer 114 configured to monitor channel 108 and generate feedback 116. The generated feedback 116 may be influenced by the incoming traffic 110 and the injected generator traffic 106. Controller 112 may be configured to dynamically control the configurable rate 104 for SAT based on the feedback 116 generated by data rate sniffer 114 and the target rate.

[0051] It should be understood that frame generator 102 and data rate sniffer 114 do not necessarily have to be separate components. For example, frame generator 102 may include data rate sniffer 114.

[0052] The controller 112 can also be configured to dynamically control the configurable rate 104 for SAT by dynamically configuring the token bucket (not shown) to cause the frame generator 102 to generate generator traffic 106 to supplement the actual line rate of the incoming traffic 110 to achieve the target rate.

[0053] The data rate sniffer 114 can also be configured to output at least one status indicator (not shown), which is configured to indicate the result of a comparison between the actual amount of injected generator flow 106 and the expected amount of generator flow 106 to be injected. At least one status indicator may be included in the following reference. Figure 2 At least one sniffer statistic 220 was further disclosed.

[0054] Continue to refer to Figure 1 Channel 108 can be a time-division multiplexing (TDM) channel. Data rate sniffer 114 can be configured to monitor: the data rate of incoming traffic 110 on channel 108, the data rate of injected generator traffic 106, and the overall TDM data rate for channel 108, as described in the references below. Figure 2 Further details will be released.

[0055] Continue to refer to Figure 1 The data rate sniffer 114 can also be configured to output a status indication of the data rate of the incoming traffic 110 on the output channel, the data rate of the injected generator traffic 106, and the current and continuous average rates of the overall TDM data rate for channel 108. Such status indications may be included in the reference below. Figure 2 At least one sniffer statistic of 220 is publicly available.

[0056] Continue to refer to Figure 1 The data rate sniffer 114 can also be configured to monitor the data rate of incoming traffic 110 on channel 108, the data rate of injected generator traffic 106, and the overall TDM data rate for channel 108 based on the total number of clock cycles counted between sniffer analysis events. The value for the total number can be based on a power of 2 and a configured value for the token increment of the token counter (not shown) for the token bucket of frame generator 102.

[0057] The incoming traffic 110 on channel 108 can have strict priority relative to the injected generator traffic 106. Circuit 100 may also include an output buffer (not shown). The output buffer may have a size of at least MTU.

[0058] The incoming traffic 110 on channel 108 can have strict priority relative to the injected generator traffic 106, and the injected generator traffic 106 can be restricted to single-word frames.

[0059] Data rate sniffer 114 can also be configured to generate at least one sniffer statistic for SAT and output the generated at least one sniffer statistic, such as those disclosed below. Figure 2At least one sniffer statistic 220. At least one sniffer statistic 220 may represent at least one performance indicator. For non-limiting purposes, example performance indicators may represent throughput, latency, jitter, frame loss, or a combination thereof.

[0060] Figure 2 This is a block diagram of another circuit 200 that can be used for the SAT. Circuit 200 can be used as disclosed above. Figure 1 Circuit 100. Continue to refer to... Figure 1 and Figure 2 Circuit 200 may include a frame generator 202 configured to inject generator traffic 206 into channel 108 for SAT based on a configurable rate 104. Channel 108 may contain incoming traffic 210 on channel 108 and injected generator traffic 206. Channel 108 may be associated with a target rate (not shown). Frame generator 202 may include a controller 112. Circuit 200 may also include a data rate sniffer 214 configured to monitor channel 108 and generate feedback 216. The generated feedback 216 may be influenced by the incoming traffic 210 and the injected generator traffic 206. Controller 112 may be configured to dynamically control the configurable rate 104 for SAT based on the feedback 216 generated by data rate sniffer 214 and the target rate.

[0061] Circuit 200 may further include a multiplexer (mux) 226 to ensure that incoming traffic 210 on channel 108 has strict priority relative to injected generator traffic 206. Multiplexer 226 can output traffic 230 to the Rx path 232 of the core of switch 234, which can implement SAT. Data rate sniffer 214 may also be configured to perform rate sampling on output traffic 230 to generate an overall TDM data rate for channel 108. According to an example embodiment, Rx path 232 may loop back to transmit (Tx) traffic 239 via transmit (Tx) path 236, such that Tx traffic 239 is inspected by frame checker 238 as part of SAT. Circuits (100, 200) can be used to implement methods for SAT, such as those disclosed below. Figure 3 The method.

[0062] Figure 3This is a flowchart 300 of an example embodiment of the method. The method begins (302) and includes injecting generator traffic into a channel used for SAT based on a configurable rate (304). The channel contains incoming traffic on the channel and the injected generator traffic. The channel is associated with a target rate. The method also includes generating feedback by monitoring the channel (306). The generated feedback is influenced by the incoming traffic and the injected generator traffic. The method also includes dynamically controlling the configurable rate used for SAT based on the generated feedback and the target rate (308). In the example embodiment, the method then ends (310).

[0063] Figure 4 This is a block diagram of an example embodiment of a computer environment 440, in which a user 442 is viewing a display screen 445 of a computer-aided design system 446. The user 442 can use the computer-aided design system 446 to design a hardware description language (HDL) design structure 447. The HDL design structure 447 can be encoded on a machine-readable data storage medium (not shown). The HDL design structure 447 may include elements that, when processed in the computer-aided design system 446, generate a machine-executable representation 449 of a device 448.

[0064] refer to Figure 1 , Figure 2 and Figure 4 HDL design architecture 447 may include frame generators (102, 202) configured to inject generator traffic (106, 206) into channel 108 for SAT based on configurable rate 104. Channel 108 may contain incoming traffic (110, 210) and injected generator traffic (106, 206) on channel 108. Channel 108 may be associated with a target rate. Frame generators (102, 202) may include controller 112. HDL design architecture 447 may also include data rate sniffer 114 configured to monitor channel 108 and generate feedback (116, 216) influenced by incoming traffic (110, 210) and injected generator traffic (106, 206). Controller 112 may be configured to dynamically control configurable rate 104 for SAT based on feedback (116, 216) generated by data rate sniffer (114) and the target rate.

[0065] For non-limiting examples, the machine-executable representation of device 448 449 can be used as a server in a data center, for non-limiting examples, such as those described below. Figure 5 Publicly accessible data centers.

[0066] Figure 5This is a block diagram of an example embodiment of data center 552. For a non-limiting example, data center 552 may have consumers as entities, such as organizations 554 (i.e., enterprises) and individuals 556. Such consumers may utilize the services (not shown) and infrastructure 557 provided by data center 552 for storing, processing, and accessing data (not shown) and applications (not shown).

[0067] In data center 552, multiple servers 557 can serve as core computing resources, responsible for storing, processing, and managing data, applications, and services, forming the backbone of infrastructure 557. For a non-limiting example, consumers, such as organizations 554 and individuals 556, can utilize such computing resources via the Internet 553 coupled to the data center network 559 of data center 552. The multiple servers 557 can store and manage large amounts of data, acting as a repository for information that consumers can rely on. The servers in the multiple servers 557 can host various applications, from web servers providing content to database servers managing data. For a non-limiting example, the servers in the multiple servers 557 can provide services such as email and network management, enabling users to access and utilize the resources.

[0068] The servers in the plurality of servers 557 can provide processing power and storage for running applications and handling data requests. The servers in the plurality of servers 557 can be interconnected within a data center network 559, thereby facilitating communication and data transfer between different systems. For non-limiting examples, the servers in the plurality of servers 557 can be used for data center security, where dedicated servers act as firewalls, intrusion detection systems, and virtual private network (VPN) gateways. The servers in the plurality of servers 557 can be used for data backup and to facilitate disaster recovery. In data center 552, SAT can be useful for ensuring data integrity for the storage, management, and processing of information. In data center 552, at least one of the servers in the plurality of servers 557 can employ example embodiments of the devices disclosed below.

[0069] According to an example embodiment, a system (such as a server in a plurality of servers 557) may include a network interface (not shown) and devices, such as a system-on-a-chip (SoC) (not shown), for a non-limiting example. Continuing to reference... Figure 1 , Figure 2 and Figure 5For non-limiting examples, the device may be an integrated circuit (IC). The device for at least one of the servers in a plurality of servers 557 may include a frame generator (102, 202) configured to inject generator traffic (106, 206) into channel 108 for SAT based on a configurable rate 104. Channel 108 may contain incoming traffic (110, 210) and injected generator traffic (106, 206) on channel 108. Channel 108 may be associated with a target rate. The frame generator (102, 202) may include a controller 112. HDL design architecture 447 may also include a data rate sniffer 114 configured to monitor channel 108 and generate feedback (116, 216) influenced by the incoming traffic (110, 210) and injected generator traffic (106, 206). The controller 112 can be configured to dynamically control the configurable rate 104 for SAT based on feedback (116, 216) generated by the data rate sniffers (114, 216) and the target rate.

[0070] The exemplary embodiments disclosed herein may employ hardware, software, firmware, electronic control components, processing logic, and / or processor devices, individually or in any combination, including but not limited to: application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), electronic circuits, processors and memories that execute one or more software or firmware programs, and / or other suitable components that provide the described functionality.

[0071] The further example embodiments disclosed herein can be configured using a computer program product; for example, control can be programmed in software to implement the example embodiments. Further example embodiments may include a non-transitory computer-readable medium containing instructions executable by a processor and, when loaded and executed, causing the processor to perform the methods described herein. It should be understood that the elements of the block diagrams and flowcharts may be implemented in software or hardware, firmware, combinations thereof, or other similar implementations to be determined in the future. Furthermore, the elements of the block diagrams and flowcharts described herein may be combined or divided in any way in software, hardware, or firmware. If implemented in software, the software may be written in any language capable of supporting the example embodiments disclosed herein. The software may be stored in any form of computer-readable medium, such as random access memory (RAM), read-only memory (ROM), optical disc read-only memory (CD-ROM), etc. In operation, a general-purpose or special-purpose processor or processing core loads and executes the software in a manner known in the art. It should also be understood that the block diagrams and flowcharts may include more or fewer elements, be arranged or oriented differently, or be represented differently. It should be understood that the implementation method can determine the number of block diagrams, flowcharts, and / or network diagrams, as well as the number of block diagrams and flowcharts illustrating the execution of the embodiments disclosed herein. Furthermore, the exemplary embodiments and their elements may be combined in ways not explicitly disclosed herein.

[0072] The teachings of all patents, published applications and references cited in this article are incorporated herein by reference in their entirety.

[0073] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the embodiments covered by the appended claims.

Claims

1. A circuit comprising: A frame generator configured to inject generator traffic into a channel used for Service Activation Test (SAT) at a configurable rate, the channel containing incoming traffic and the injected generator traffic, the channel being associated with a target rate, the frame generator including a controller; and A data rate sniffer is configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate for the SAT based on the feedback generated by the data rate sniffer and the target rate.

2. The circuit of claim 1, wherein the controller is further configured to: The configurable rate for the SAT is dynamically controlled by dynamically configuring the token bucket so that the frame generator produces generator traffic to supplement the actual line rate of the incoming traffic to achieve the target rate.

3. The circuit of claim 2, wherein the data rate sniffer is further configured to output at least one status indicator, the at least one status indicator being configured to indicate a comparison result between the actual amount of injected generator traffic and the expected amount of generator traffic to be injected.

4. The circuit of claim 1, wherein the channel is a time-division multiplexing (TDM) channel, and wherein the data rate sniffer is further configured to monitor: the data rate of the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel.

5. The circuit of claim 4, wherein the data rate sniffer is further configured to output a status indication of the current and sustained average rates of the data rate for the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel.

6. The circuit of claim 4, wherein the data rate sniffer is further configured to monitor the data rate of the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel based on the total number of clock cycles counted between sniffer analysis events, and wherein the value for the total number is based on a power of 2 and a configured value for the token increment of the token counter of the token bucket of the frame generator.

7. The circuit of claim 1, wherein the incoming traffic on the channel has strict priority relative to the injected generator traffic, wherein the circuit further includes an output buffer, and wherein the output buffer has a size of at least the maximum transmission unit (MTU) size.

8. The circuit of claim 1, wherein the incoming traffic on the channel has strict priority relative to the injected generator traffic, and wherein the injected generator traffic is restricted to single-word frames.

9. The circuit of claim 1, wherein the data rate sniffer is further configured to generate at least one sniffer statistic for the SAT and output the generated at least one sniffer statistic.

10. The circuit of claim 9, wherein the at least one sniffer statistic represents at least one performance indicator, and wherein the performance indicator represents throughput, latency, jitter, frame loss, or a combination thereof.

11. A method comprising: Based on a configurable rate, generator traffic is injected into a channel used for Service Activation Test (SAT), the channel containing incoming traffic on the channel and the injected generator traffic, the channel being associated with a target rate; Feedback is generated by monitoring the channel, and the generated feedback is affected by the incoming traffic and the injected generator traffic; as well as Based on the generated feedback and the target rate, the configurable rate used for the SAT is dynamically controlled.

12. The method of claim 11, wherein dynamically controlling the configurable rate for the SAT includes dynamically configuring the token bucket to supplement the actual line rate of the incoming traffic with injected generator traffic to achieve the target rate.

13. The method of claim 12, further comprising outputting at least one status indicator configured to indicate a comparison between the actual amount of injected generator traffic and the expected amount of generator traffic to be injected.

14. The method of claim 11, wherein the channel is a time-division multiplexing (TDM) channel, and wherein the method further comprises monitoring: the data rate of the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel.

15. The method of claim 14, further comprising outputting a status indication of the current and sustained average rates of the data rate for the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel.

16. The method of claim 14, further comprising monitoring the data rate of the incoming traffic on the channel, the data rate of the injected generator traffic, and the overall TDM data rate for the channel based on the total number of clock cycles counted between sniffer analysis events, and wherein a value for the total number is based on a power of 2 and a configured value for the token increment of the token counter for the token bucket of the frame generator.

17. The method of claim 11, wherein the incoming traffic on the channel has strict priority relative to the injected generator traffic.

18. The method of claim 17, further comprising limiting the injected generator traffic to single-word frames.

19. The method of claim 11, further comprising generating at least one sniffer statistic for the SAT and outputting the generated at least one sniffer statistic.

20. The method of claim 19, wherein the at least one sniffer statistic represents at least one performance indicator, and wherein the performance indicator represents throughput, latency, jitter, frame loss, or a combination thereof.

21. An apparatus comprising: Components for injecting generator traffic into a channel used for Service Activation Test (SAT) based on a configurable rate, the channel containing incoming traffic on the channel and the injected generator traffic, the channel being associated with a target rate; A component for generating feedback by monitoring the channel, wherein the generated feedback is affected by the incoming traffic and the injected generator traffic; as well as A component for dynamically controlling the configurable rate for the SAT based on the generated feedback and the target rate.

22. A system comprising: Network interface; as well as The device includes: A frame generator configured to inject generator traffic into a channel used for Service Activation Test (SAT) at a configurable rate, the channel containing incoming traffic and the injected generator traffic, the channel being associated with a target rate, the frame generator including a controller; and A data rate sniffer is configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate for the SAT based on the feedback generated by the data rate sniffer and the target rate.

23. The system of claim 22, wherein the system is a server in at least one server in a data center, and wherein the device is a system-on-a-chip (SoC).

24. A hardware description language (HDL) design structure, the HDL design structure being encoded on a machine-readable data storage medium, the HDL design structure including elements that, when processed in a computer-aided design system, generate a machine-executable representation of a device, wherein the HDL design structure includes: A frame generator configured to inject generator traffic into a channel used for Service Activation Test (SAT) at a configurable rate, the channel containing incoming traffic and the injected generator traffic, the channel being associated with a target rate, the frame generator including a controller; and A data rate sniffer is configured to monitor the channel and generate feedback influenced by the incoming traffic and the injected generator traffic. The controller is configured to dynamically control the configurable rate for the SAT based on the feedback generated by the data rate sniffer and the target rate.