An AXI bus performance analysis method and apparatus

Abstract

This invention relates to the field of chip technology and provides a method and apparatus for AXI bus performance analysis. The method includes: collecting data packet-related information and signal-related information during AXI bus data transmission; reading and analyzing the data packet-related information and signal-related information to obtain AXI bus performance indicators; and generating corresponding charts based on the AXI bus performance indicators to visualize the AXI bus performance indicators. This invention visualizes AXI bus performance indicators by monitoring and analyzing various performance indicators and presenting them to the user in chart form, facilitating intuitive viewing and thus helping users locate performance problems.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to an AXI bus performance analysis method and apparatus. Background Technology

[0002] With the development of computer technology, many existing chips use the Advanced Dextensible Interface (AXI) bus protocol. AXI is a commonly used on-chip bus protocol widely applied in modern chip design. It supports efficient data transmission and communication, connecting various intellectual property (IP) cores within the system, such as processors, memory controllers, and peripheral controllers. The AXI bus provides a standardized, scalable communication architecture, enabling different IP cores to interoperate within the same system.

[0003] With the increasing complexity of chip designs and the growing diversity of chip systems, accurate evaluation and analysis of the performance of internal chips' buses have become increasingly important. Performance analysis of the AXI bus within a chip is a crucial part of chip performance analysis. Currently, the performance analysis of the AXI bus primarily relies on visual observation and comparison of simulation waveforms, or statistical analysis using verification components based on System Verilog (SV) language. While visual observation is intuitive, it is inefficient, hindering rapid problem location and analysis, and is prone to errors. Statistical analysis using SV-based verification components, although capable of performing specialized verification and statistics on AXI bus characteristics such as latency, bandwidth, and real-time performance, suffers from low visualization and lacks intuitiveness, making it difficult for chip developers to pinpoint performance issues.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] The technical problem that this invention aims to solve is that the existing AXI bus performance analysis methods have low visualization, are not intuitive enough, and are not convenient for chip developers to locate performance problems.

[0006] The present invention adopts the following technical solution: In a first aspect, the present invention provides an AXI bus performance analysis method, comprising: Collect data packet information and signal information during data transmission on the AXI bus; The data packet information and signal information are read and analyzed to obtain the performance indicators of the AXI bus; Based on the performance metrics of the AXI bus, corresponding charts are generated to visualize the performance metrics of the AXI bus.

[0007] Preferably, the data packet related information includes: the type of the received corresponding data packet, the address of the data packet, and the time of data packet reception; The signal-related information includes: each sampling time of the clock signal and the value of each signal at the sampling time of the clock signal.

[0008] Preferably, the step of reading and analyzing the data packet-related information and signal-related information to obtain the performance indicators of the AXI bus specifically includes: Based on the different addresses of the data packets, the relevant information of the data packets is divided into multiple data packet segments, and the following method is performed on each data packet segment: Obtain the corresponding preset type of data packet from the data packet content, and determine the corresponding first critical moment based on the reception time of the corresponding preset type of data packet; Based on each first key moment and the corresponding division rules, time periods are divided, the signal content within the divided time period is obtained from the signal-related information, and the data packet content and signal content within the divided time period are matched to obtain the corresponding second key moment. Calculate the performance metrics of the AXI bus based on the first critical moment and the second critical moment.

[0009] Preferably, when analyzing the write performance of the AXI bus, the process involves obtaining data packets of a corresponding preset type from the data packet content, determining the corresponding first key moment based on the reception time of the corresponding preset type of data packet, dividing time periods based on each first key moment and the corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment. Specifically, this includes: Match the Received WriteAddress string to the data packet content to obtain the first critical moment WT2 of the write address channel handshake; match the Received WLAST string to obtain the first critical moment WT5 of the write data channel LAST signal being valid; match the Received Write Response string to obtain the first critical moment WT7 of the write response channel handshake. Match the data packet content and signal content before the first critical moment WT2, find the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment and the AWVALID signal is high, and take it as the second critical moment WT1. Within the time interval between the first critical moment WT5 corresponding to the previous data packet content and the first critical moment WT5 corresponding to the next data packet content, find the earliest moment when the WVALID signal is high as the second critical moment WT3. Within the time period between the second critical moment WT3 and the first critical moment WT5, the earliest moment when both the WVALID signal and the WREADY signal are high is identified as the second critical moment WT4. After the first critical moment WT5, the earliest moment when the BVALID signal is high and BID is the same as AWID is taken as the second critical moment WT6.

[0010] Preferably, the performance metrics of the AXI bus include each critical delay and the total delay. The calculation of the AXI bus performance metrics based on the first critical moment and the second critical moment specifically includes: Following the order of second critical moment WT1, first critical moment WT2, second critical moment WT3, second critical moment WT4, first critical moment WT5, and second critical moment WT6, subtract the previous critical moment from the next critical moment to obtain the corresponding critical delay. Subtracting the second critical moment WT1 from the second critical moment WT6 yields the total delay of the AXI bus.

[0011] Preferably, the step of reading and analyzing the data packet-related information and signal-related information to obtain the performance indicators of the AXI bus further includes: Based on the data packet information, calculate the write operation bandwidth within each preset period; Based on signal-related information, the percentage of corresponding signal duration within each preset period is calculated. This percentage includes: the percentage of the preset period during which both the WVALID and WREADY signals are high; the percentage of the preset period during which the WVALID signal is high and the WREADY signal is low; the percentage of the preset period during which the WVALID signal is low and the WREADY signal is high; and the percentage of the preset period during which both the WVALID and WREADY signals are low.

[0012] Preferably, when analyzing the read performance of the AXI bus, the process involves obtaining data packets of a corresponding preset type from the data packet content, determining the corresponding first key moment based on the reception time of the corresponding preset type of data packet, dividing time periods based on each first key moment and the corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment. Specifically, this includes: Match the content of the data packet with the string "Received a ReadAddr" to obtain the first critical moment RT2 of the read address channel handshake; match the content of the data packet with the string "Received RLAST" to obtain the first critical moment RT5 when the read data channel LAST signal is valid. Match the data packet content and signal content before the first critical moment RT2, find the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment and the ARVALID signal is high, and take it as the second critical moment RT1. In the time period between the first critical moment RT2 and the first critical moment RT5, the earliest moment when the RVALID signal is high and RID and ARID are the same is taken as the second critical moment RT3. Within the time interval between the first critical moment RT2 and the first critical moment RT5, the earliest moment when both the RVALID signal and the RREADY signal are high is identified as the second critical moment RT4.

[0013] Preferably, the performance metrics of the AXI bus include each critical delay and the total delay. The calculation of the AXI bus performance metrics based on the first critical moment and the second critical moment specifically includes: Following the order of second critical moment RT1, first critical moment RT2, second critical moment RT3, second critical moment RT4, and first critical moment RT5, the corresponding critical delay is obtained by subtracting the previous critical moment from the next critical moment. Subtracting the second critical moment RT1 from the first critical moment RT5 yields the total delay of the AXI bus.

[0014] Preferably, the step of reading and analyzing the data packet-related information and signal-related information to obtain the performance indicators of the AXI bus further includes: Based on the data packet information, calculate the read operation bandwidth within each preset period; Based on signal-related information, the percentage of corresponding signal duration within each preset period is calculated. This percentage includes: the percentage of time during which both the RVALID and RREADY signals are high within the preset period; the percentage of time during which the RVALID signal is high and the RREADY signal is low within the preset period; the percentage of time during which the RVALID signal is low and the RREADY signal is high within the preset period; and the percentage of time during which both the RVALID and RREADY signals are low within the preset period.

[0015] In a second aspect, the present invention also provides an AXI bus performance analysis apparatus for implementing the AXI bus performance analysis method described in the first aspect, the apparatus comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the AXI bus performance analysis method described in the first aspect.

[0016] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the AXI bus performance analysis method described in the first aspect.

[0017] This invention visualizes the AXI bus performance metrics by monitoring and analyzing various performance indicators and presenting them to users in the form of charts. This allows users to view the performance metrics intuitively and pinpoint performance issues. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 This is a flowchart illustrating an AXI bus performance analysis method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating an application scenario of an AXI bus performance analysis method provided in an embodiment of the present invention; Figure 3 This is a flowchart illustrating the second AXI bus performance analysis method provided in this embodiment of the invention; Figure 4This is a flowchart illustrating the third AXI bus performance analysis method provided in this embodiment of the invention. Figure 5 This is a flowchart illustrating the fourth AXI bus performance analysis method provided in this embodiment of the invention. Figure 6 This is a schematic diagram of the architecture of an AXI bus performance analysis device provided in an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0021] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0022] In this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled" can refer to an electrical connection that enables signal transmission.

[0024] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] Existing AXI bus performance analysis methods suffer from low visualization and are not intuitive enough, making it difficult for chip developers to pinpoint performance issues. To address this problem, this invention provides an AXI bus performance analysis method, such as... Figure 1 As shown, it includes: In step 201, data packet information and signal information are collected during the data transmission process of the AXI bus. In an optional implementation, step 201 mainly involves writing a corresponding monitoring module in SV language and connecting the monitoring module to the corresponding AXI port using an AXI interface.

[0026] In step 202, the data packet information and signal information are read and analyzed to obtain the performance indicators of the AXI bus; wherein, the data packet information includes: the type of the received corresponding data packet, the address of the data packet, and the time of data packet reception.

[0027] The signal-related information includes: each sampling time of the clock signal and the value of each signal at the sampling time of the clock signal.

[0028] In step 203, corresponding charts are generated based on the performance metrics of the AXI bus, thus visualizing the AXI bus performance metrics. In practical use, steps 202 and 203 are implemented using languages ​​such as Python, for example, writing data packet information to the corresponding tracker.txt file and signal information to the signal.csv file. The performance metrics of the AXI bus include key delays, total delay, bandwidth, real-time performance, and bandwidth bottlenecks. The overall total delay, bandwidth, and real-time metrics of the AXI bus are displayed using line charts and bar charts, and the total delay and key delay data for each transmission are displayed in list format.

[0029] For example Figure 2 The example of a master-slave AXI application scenario shown includes: The monitor module is a monitoring module written in SV language. It connects to the AXI port to be monitored through the AXI interface, integrates into the simulation environment, and starts the simulation. The monitor module captures bus signals.

[0030] After the simulation, based on the monitor's data, a txt file (tracker.txt) recording data packet information and a csv file (signal.csv) recording signal timing information are generated. The tracker.txt file records the exact time of each transmission: Address Write channel handshake, slave receiving the WLAST signal, Response channel handshake, Address Read channel handshake, and slave sending the RLAST signal, as well as basic information such as ID, address, SIZE, LENTH, and DATA for each data transmission. The signal.csv file records the specific sampled values ​​of each bus signal at each clock rising edge.

[0031] The AXI bus performance analysis tool reads and analyzes the generated CSV and TXT files. It displays the overall Latency, Bandwidth, and Realtime metrics of the AXI bus in line and bar charts, and shows the Burst Time and Latency data for each transmission in a list format.

[0032] This embodiment monitors and analyzes various performance indicators of the AXI bus and presents these indicators to the user in the form of charts, thereby visualizing the AXI bus performance indicators and making it easier for users to view them intuitively and locate performance problems.

[0033] In an optional implementation, the process of reading and analyzing the data packet-related information and signal-related information to obtain the performance indicators of the AXI bus, such as... Figure 3 As shown, it specifically includes: In step 301, the data packet information is divided into multiple data packet segments according to the different addresses of the data packets. Each data packet segment contains multiple data packets with the same address, representing a data reception or retrieval process. The following method is performed on each data packet segment: In step 302, a data packet of a corresponding preset type is obtained from the data packet content, and the corresponding first key moment is determined by the reception time of the data packet of the corresponding preset type; the preset type includes write address channel handshake data packet, write reply channel handshake data packet, data packet of the write data channel receiving the LAST signal, read address channel handshake data packet, data packet of the read data channel receiving the LAST signal, etc.

[0034] In step 303, based on each first key moment and the corresponding division rules, time periods are divided. The signal content within the divided time periods is obtained from signal-related information. The data packet content and signal content within the divided time periods are matched to obtain the corresponding second key moments. It should be noted that the first and second key moments are classified based on the directness of moment acquisition. The moment that can be directly obtained from the data packet content is called the first key moment, and the moment that needs to be obtained in combination with the signal content is called the second key moment. It does not refer to a single moment. The first key moment, the second key moment, and the division rules will be described in detail in subsequent embodiments in conjunction with specific application scenarios, and will not be elaborated here.

[0035] In step 304, the performance metrics of the AXI bus are calculated based on the first critical moment and the second critical moment.

[0036] This embodiment divides data packet information into two categories based on address and time period, thereby accurately grasping each stage of transmission and obtaining the time required for calculating performance indicators.

[0037] The method described in this embodiment will be further explained below using reading and writing scenarios as examples.

[0038] When analyzing the write performance of the AXI bus, the process involves obtaining data packets of a preset type from the data packet content, determining the corresponding first key moment based on the reception time of the data packets of the preset type, dividing time periods based on each first key moment and corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment, such as... Figure 4 As shown, it specifically includes: In step 401, the content of the data packet is matched with the string "Received WriteAddress" to obtain the first key moment WT2 of the write address channel handshake; the content of the data packet is matched with the string "Received WLAST" to obtain the first key moment WT5 of the write data channel LAST signal being valid; and the content of the data packet is matched with the string "Received Write Response" to obtain the first key moment WT7 of the write response channel handshake.

[0039] In step 402, the data packet content and signal content before the first critical moment WT2 are matched to find the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment and the AWVALID signal is high, which is taken as the second critical moment WT1.

[0040] In step 403, within the time period between the first key moment WT5 corresponding to the previous data packet content and the first key moment WT5 corresponding to the next data packet content, the earliest moment when the WVALID signal is high is found as the second key moment WT3. It should be noted that the "previous data packet content" and "next data packet content" mentioned in this embodiment are relative to two adjacent data packet contents. For example, three data packet contents obtained by dividing according to different addresses are referred to as the first data packet content, the second data packet content, and the third data packet content in the order of receiving time for ease of description. Then, the first data packet content is the "previous data packet content" of the second data packet content, the second data packet content is the "next data packet content" of the first data packet content, the second data packet content is the "previous data packet content" of the third data packet content, and the third data packet content is the "next data packet content" of the second data packet content.

[0041] In step 404, the earliest moment when both the WVALID signal and the WREADY signal are high is found within the time period between the second critical moment WT3 and the first critical moment WT5, and is taken as the second critical moment WT4.

[0042] In step 405, after the first critical moment WT5, the earliest moment when the BVALID signal is high and the BID is the same as the AWID is identified as the second critical moment WT6. The AWID is the write address ID, and the BID is the write response ID, both obtained from the data packet content.

[0043] The performance metrics of the AXI bus include key delays and total delay. The calculation of the AXI bus performance metrics based on the first and second key moments specifically includes: Following the order of second critical moment WT1, first critical moment WT2, second critical moment WT3, second critical moment WT4, first critical moment WT5, and second critical moment WT6, the corresponding critical delay is obtained by subtracting the previous critical moment from the next critical moment.

[0044] Subtracting the second critical moment WT1 from the second critical moment WT6 yields the total delay of the AXI bus.

[0045] The step of reading and analyzing the data packet information and signal information to obtain the performance indicators of the AXI bus also includes: Based on data packet information, the write operation bandwidth within each preset period is calculated; based on signal information, the duration percentage of the corresponding signal within each preset period is calculated; wherein, the duration percentage of the corresponding signal includes: the percentage of the preset period in which both WVALID and WREADY signals are at a high level; the percentage of the preset period in which the WVALID signal is at a high level and the WREADY signal is at a low level; the percentage of the preset period in which the WVALID signal is at a low level and the WREADY signal is at a high level; and the percentage of the preset period in which both WVALID and WREADY signals are at a low level.

[0046] The following will explain the specific meanings of each key moment and each specific performance indicator in the writing scenario. HS stands for handshake, and VLD stands for VALID. WT1:AWVALID==1 is the moment when the write address channel first initiates a valid signal.

[0047] WT2: (AWVALID==1&AWREADY==1) The moment of the write address channel handshake.

[0048] WT3: WVALID==1 The moment when the write data channel first initiates a valid signal.

[0049] WT4: (WVALID==1&WREADY==1) The moment of the first handshake for writing the data channel.

[0050] WT5: WLAST==1 The time when the write data channel LAST signal is valid.

[0051] WT6: BVALID==1 The moment when the write reply channel first sends a valid signal.

[0052] WT7: (BVALID==1&BREADY==1) The moment of the write response channel handshake.

[0053] Write Latency1 (AW Real Time): This indicates the delay in the handshake from the master station initiating AWVALID to the AW (Address Write) channel, reflecting the real-time performance of the AW channel.

[0054] Write Latency2(AWHS->WVLD): This indicates the delay between the AW channel handshake and the master station initiating the WVALID.

[0055] Write Latency3(W Real Time): This indicates the delay in the handshake from the main station initiating the WVALID to the W (Write) channel, reflecting the real-time nature of the W channel.

[0056] Write Latency4(WHS->WLAST): This indicates the delay from the handshake of the W channel to the master station initiating the WLAST, reflecting the time of data transmission.

[0057] Write Latency5(WLAST->BVLD): This indicates the delay between the master site initiating WLAST and the slave site initiating BVALID.

[0058] Write Latency6(B Real Time): Indicates the delay in the handshake from the slave initiating BVALID to the B(Response) channel.

[0059] Write Burst Time: The sum of Latency1 to Latency6 reflects the overall latency of the write operation.

[0060] The total real time of write operations is the sum of Latency1, Latency3, and Latency6, reflecting the overall real-time performance of the write operation.

[0061] Write Bandwidth: Calculates the write operation bandwidth in units of 1µs.

[0062] Write Bandwidth Bottleneck: Calculates the time percentages of WVALID&WREADY, WVALID&~WREADY, ~WVALID&WREADY, and ~WVALID&~WREADY within each 1µs unit. WVALID&WREADY reflects bus utilization, WVALID&~WREADY reflects the presence of backpressure during slave write data reception, ~WVALID&WREADY reflects the presence of data bubbles during master write data transmission, and ~WVALID&~WREADY reflects any abnormal bus conditions, facilitating the analysis of bandwidth bottlenecks in write operations.

[0063] Based on the specific meanings of each key moment and each specific performance indicator, the AXI bus performance analysis method in the above embodiments includes: First, from the tracker.txt file, match the string "Received WriteAddress" to obtain WT2, match the string "Received WLAST" to obtain WT5, and match the string "Received Write Response" to obtain WT7. Then, search for the remaining timestamps in signal.csv.

[0064] Finding WT1: Based on the address of the data packets in the tracker file, using WT2 as the dividing line, search back along the timeline in signal.csv for the earliest time point with the same address and AWVALID set to 1. Simultaneously, AWVALID needs to be continuous; if a different address or AWVALID=0 is detected, the search immediately stops. For moments before this, even if AWVALID is 1 and the address is the same, the search continues. If no time point meeting the conditions is found, it means WT1 = WT2.

[0065] Finding WT3: We need to establish a correspondence between WT5 and WT1. Each data point has exactly one WT2 and one WT5, and these correspond strictly in chronological order. Therefore, we need to find the WT5 time of the previous data point, and then, starting from WT5 (<=WT5) of the previous data point, the time when WVALID first sets to 1 is WT3. For the first data point, since no reference point is found, we directly use the time when WVALID first sets to 1. Search range: [preWT5, curWT5].

[0066] Find WT4: the moment when WVALID=WREADY=1 for the first time between WT3 and WT5 ([WT3,WT5]). WT4 can be equal to WT3.

[0067] Finding WT6: From the current WT5 time point onwards (>WT5), find the earliest time when BVALID=1 is the same as both BID and AWID. When processing WT6, each data point needs to be processed sequentially according to the AW handshake time order. Once WT6 is determined, all BVALIDs within the time range [WT6, WT7] belong only to that current data point. When analyzing all subsequent data points, if the same AWID appears, previously analyzed BVALIDs cannot be assigned to it again.

[0068] After obtaining the times WT1~WT7 for each transmission, calculate the Latency, Real Time, and BurstTime metrics according to the definitions.

[0069] Based on the VALID, READY, and LAST initiation times in the CSV file and the Burst Length and Burst Size information in the TXT file, the Bandwidth and Bandwidth Bottleneck are calculated.

[0070] When analyzing the read performance of the AXI bus, the process involves obtaining data packets of a preset type from the data packet content, determining the corresponding first key moment based on the reception time of the data packets of the preset type, dividing time periods based on each first key moment and corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment, such as... Figure 5 As shown, it specifically includes: In step 501, the content of the data packet is matched with the string "Received a ReadAddr" to obtain the first key moment RT2 of the read address channel handshake, and the content of the data packet is matched with the string "Received RLAST" to obtain the first key moment RT5 of the read data channel LAST signal being valid.

[0071] In step 502, the data packet content and signal content before the first critical moment RT2 are matched, and the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment and the ARVALID signal is high is taken as the second critical moment RT1.

[0072] In step 503, within the time period between the first critical moment RT2 and the first critical moment RT5, the earliest moment when the RVALID signal is high and the RID and ARID are the same is identified as the second critical moment RT3. Here, ARID is the read address ID, and RID is the read response ID (i.e., the ID of a single read transmission), both obtained from the data packet content.

[0073] In step 504, the earliest moment when the RVALID signal is high and the RREADY signal is high is found within the time period between the first critical moment RT2 and the first critical moment RT5, and is taken as the second critical moment RT4.

[0074] The performance metrics of the AXI bus include key delays and total delay. The calculation of the AXI bus performance metrics based on the first and second key moments specifically includes: Following the sequence of second critical moment RT1, first critical moment RT2, second critical moment RT3, second critical moment RT4, and first critical moment RT5, subtract the previous critical moment from the next critical moment to obtain the corresponding critical delay; subtract the second critical moment RT1 from the first critical moment RT5 to obtain the total delay of the AXI bus.

[0075] The step of reading and analyzing the data packet information and signal information to obtain the performance indicators of the AXI bus also includes: Based on data packet information, the read operation bandwidth within each preset period is calculated; based on signal information, the duration percentage of the corresponding signal within each preset period is calculated; wherein, the duration percentage of the corresponding signal includes: the percentage of the preset period in which both RVALID and RREADY signals are high; the percentage of the preset period in which the RVALID signal is high and the RREADY signal is low; the percentage of the preset period in which the RVALID signal is low and the RREADY signal is high; and the percentage of the preset period in which both RVALID and RREADY signals are low.

[0076] The following section will explain the specific meanings of each key moment and each specific performance indicator in a reading scenario: RT1: ARVALID==1 The moment when the read address channel first initiates a valid signal.

[0077] RT2:(ARVALID==1&ARREADY==1) The moment of the address channel handshake.

[0078] RT3:RVALID==1 The moment when the read data channel first initiates a valid signal.

[0079] RT4: (RVALID=1&RREADY=1) The moment of the first handshake for the read data channel.

[0080] RT5: RLAST==1 indicates the moment when the LAST signal of the data channel is valid.

[0081] Read Latency1 (AR Real Time): This indicates the delay in the handshake from the master station initiating the ARVALID to the AR (Address Read) channel, reflecting the real-time nature of the AR channel.

[0082] Read Latency2(ARHS->RVLD): Indicates the delay from the AR channel handshake to the slave initiating RVALID.

[0083] Read Latency3 (R Real Time): This indicates the delay from when the slave initiates RVALID to the handshake on the R (Read) channel, reflecting the real-time performance of the R channel.

[0084] Read Latency4(RHS->RLAST): This indicates the delay from the R channel handshake to the slave initiating RLAST, reflecting the time of data transmission.

[0085] Read Burst Time: The sum of Latency1 to Latency4 reflects the overall latency of the read operation.

[0086] The total real time of read operations is the sum of Latency1 and Latency3.

[0087] Read Bandwidth: Measured in units of 1µs, representing the bandwidth of write operations within each unit of time.

[0088] Read Bandwidth Bottleneck: Calculated in 1µs units, this section represents the percentage of time allocated to RVALID&RREADY, RVALID&~RREADY, ~RVALID&RREADY, and ~RVALID&~RREADY within each unit of time. RVALID&RREADY reflects bus utilization, RVALID&~RREADY reflects the presence of backpressure during master data reception, ~RVALID&RREADY reflects the presence of data bubbles during slave data transmission, and ~RVALID&~RREADY reflects any abnormal bus conditions, facilitating the analysis of bandwidth bottlenecks in read operations.

[0089] Based on the specific meanings of each key moment and each specific performance indicator, the AXI bus performance analysis method in the above embodiments includes: First, from the tracker.txt file, match the string "Received a ReadAddr" to get RT2, and match the string "Received RLAST" to get RT5. Then, search for the remaining timestamps in signal.csv.

[0090] Finding RT1: Based on the address of the data packets in the tracker file, using RT2 as the dividing line, search back in the timeline for the earliest time in the signal where the address is the same and ARVALID is set to 1. It's important to note that ARVALID needs to be continuous; that is, if ARVALID = 0 or the address is different, immediately return and stop searching, taking the earliest time. If not found, then RT1 = RT2.

[0091] Find RT3: Within the closed interval [RT2,RT5], find the moment when RVALID is first set to 1 and RID and ARID are the same.

[0092] Find RT4: Within the closed interval [RT2,RT5], find the moment when RVALID and RREADY are first set to 1 simultaneously, and RID and ARID are the same.

[0093] After obtaining the RT1~RT7 times for each transmission, calculate the Latency, Real Time, and BurstTime metrics according to the definitions.

[0094] Based on the VALID, READY, and LAST initiation times in the CSV file and the Burst Length and Burst Size information in the TXT file, the Bandwidth and Bandwidth Bottleneck are calculated.

[0095] like Figure 6 The diagram shown is an architectural schematic of an AXI bus performance analysis device according to an embodiment of the present invention. The AXI bus performance analysis device of this embodiment includes one or more processors 21 and a memory 22. Figure 6 Take a processor 21 as an example.

[0096] Processor 21 and memory 22 can be connected via a bus or other means. Figure 6 Taking the example of a connection between China and Israel via a bus.

[0097] The memory 22, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the AXI bus performance analysis method in the above embodiment. The processor 21 executes the AXI bus performance analysis method by running the non-volatile software program and instructions stored in the memory 22.

[0098] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0099] The program instructions / modules are stored in the memory 22 and, when executed by one or more processors 21, perform the AXI bus performance analysis method in the above embodiments.

[0100] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0101] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0102] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for analyzing the performance of an AXI bus, characterized in that, include: Collect data packet information and signal information during the data transmission process of the AXI bus; The data packet information and signal information are read and analyzed to obtain the performance indicators of the AXI bus; Based on the performance metrics of the AXI bus, corresponding charts are generated to visualize the performance metrics of the AXI bus.

2. The AXI bus performance analysis method according to claim 1, characterized in that, The data packet information includes: the type of the received data packet, the address of the data packet, and the time when the data packet was received; The signal-related information includes: each sampling time of the clock signal and the value of each signal at the sampling time of the clock signal.

3. The AXI bus performance analysis method according to claim 2, characterized in that, The process of reading and analyzing the data packet information and signal information to obtain the performance indicators of the AXI bus specifically includes: Based on the different addresses of the data packets, the relevant information of the data packets is divided into multiple data packet segments, and the following method is performed on each data packet segment: Obtain the corresponding preset type of data packet from the data packet content, and determine the corresponding first critical moment based on the reception time of the corresponding preset type of data packet; Based on each first key moment and the corresponding division rules, time periods are divided, the signal content within the divided time period is obtained from the signal-related information, and the data packet content and signal content within the divided time period are matched to obtain the corresponding second key moment. Calculate the performance metrics of the AXI bus based on the first critical moment and the second critical moment.

4. The AXI bus performance analysis method according to claim 3, characterized in that, When analyzing the write performance of the AXI bus, the process involves obtaining data packets of a preset type from the data packet content, determining the corresponding first key moment based on the reception time of the data packets of the preset type, dividing time periods based on each first key moment and the corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment. Specifically, this includes: Match the Received WriteAddress string to the data packet content to obtain the first critical moment WT2 of the write address channel handshake; match the Received WLAST string to obtain the first critical moment WT5 of the write data channel LAST signal being valid; match the Received Write Response string to obtain the first critical moment WT7 of the write response channel handshake. Match the data packet content and signal content before the first critical moment WT2, find the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment WT2 and the AWVALID signal is high, and take it as the second critical moment WT1. Within the time interval between the first critical moment WT5 corresponding to the previous data packet content and the first critical moment WT5 corresponding to the next data packet content, find the earliest moment when the WVALID signal is high as the second critical moment WT3. In the time period between the second critical moment WT3 and the first critical moment WT5, the earliest moment when both the WVALID signal and the WREADY signal are high is taken as the second critical moment WT4. After the first critical moment WT5, the earliest moment when the BVALID signal is high and BID is the same as AWID is taken as the second critical moment WT6.

5. The AXI bus performance analysis method according to claim 4, characterized in that, The performance metrics of the AXI bus include key delays and total delay. The calculation of the AXI bus performance metrics based on the first and second key moments specifically includes: Following the order of second critical moment WT1, first critical moment WT2, second critical moment WT3, second critical moment WT4, first critical moment WT5, second critical moment WT6, and first critical moment WT7, the corresponding critical delay is obtained by subtracting the previous critical moment from the next critical moment. Subtracting the second critical moment WT1 from the second critical moment WT6 yields the total delay of the AXI bus.

6. The AXI bus performance analysis method according to claim 4, characterized in that, The step of reading and analyzing the data packet information and signal information to obtain the performance indicators of the AXI bus also includes: Based on the data packet information, calculate the write operation bandwidth within each preset period; Based on signal-related information, the percentage of corresponding signal duration within each preset period is calculated. This percentage includes: the percentage of the preset period during which both the WVALID and WREADY signals are high; the percentage of the preset period during which the WVALID signal is high and the WREADY signal is low; the percentage of the preset period during which the WVALID signal is low and the WREADY signal is high; and the percentage of the preset period during which both the WVALID and WREADY signals are low.

7. The AXI bus performance analysis method according to claim 3, characterized in that, When analyzing the read performance of the AXI bus, the process involves obtaining data packets of a preset type from the data packet content, determining the corresponding first key moment based on the reception time of the data packets of the preset type, dividing time periods based on each first key moment and the corresponding division rules, obtaining the signal content within the divided time periods from signal-related information, and matching the data packet content and signal content within the divided time periods to obtain the corresponding second key moment. Specifically, this includes: Match the content of the data packet with the string "Received a ReadAddr" to obtain the first critical moment RT2 of the read address channel handshake; match the content of the data packet with the string "Received RLAST" to obtain the first critical moment RT5 when the read data channel LAST signal is valid. Match the data packet content and signal content before the first critical moment RT2, find the earliest moment when the address of the data packet is consistent with the address of the data packet at the first critical moment and the ARVALID signal is high, and take it as the second critical moment RT1. In the time period between the first critical moment RT2 and the first critical moment RT5, the earliest moment when the RVALID signal is high and RID and ARID are the same is taken as the second critical moment RT3. Within the time interval between the first critical moment RT2 and the first critical moment RT5, the earliest moment when both the RVALID signal and the RREADY signal are high is identified as the second critical moment RT4.

8. The AXI bus performance analysis method according to claim 7, characterized in that, The performance metrics of the AXI bus include key delays and total delay. The calculation of the AXI bus performance metrics based on the first and second key moments specifically includes: Following the order of second critical moment RT1, first critical moment RT2, second critical moment RT3, second critical moment RT4 and first critical moment RT5, the corresponding critical delay is obtained by subtracting the previous critical moment from the next critical moment. Subtracting the second critical moment RT1 from the first critical moment RT5 yields the total delay of the AXI bus.

9. The AXI bus performance analysis method according to claim 7, characterized in that, The step of reading and analyzing the data packet information and signal information to obtain the performance indicators of the AXI bus also includes: Based on the data packet information, calculate the read operation bandwidth within each preset period; Based on signal-related information, the percentage of corresponding signal duration within each preset period is calculated. This percentage includes: the percentage of time during which both the RVALID and RREADY signals are high within the preset period; the percentage of time during which the RVALID signal is high and the RREADY signal is low within the preset period; the percentage of time during which the RVALID signal is low and the RREADY signal is high within the preset period; and the percentage of time during which both the RVALID and RREADY signals are low within the preset period.

10. An AXI bus performance analysis device, characterized in that, The device includes: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the AXI bus performance analysis method according to any one of claims 1-9.

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