Packet processing pipeline sharing in network switches

Abstract

This disclosure relates to sharing a packet processing pipeline in a network switch. In an example, a device in a network switch may include: a processing pipeline including outputs of switch circuitry coupled to the network switch; a first circuit coupled between a port group of the network switch and an input of the processing pipeline, the first circuit being configured to distribute packets output from the port group between the processing pipelines; and a memory coupled to the processing pipeline; wherein the processing pipeline is configured to process the stream of packets using digital logic based on the state of the port group to produce a result, supply the result to the switch circuitry to exchange the packets, and write the state to and read the state from the memory.

Description

Technical Field

[0001] This disclosure generally relates to a computer network, and more specifically, to a network switch. Background Technology

[0002] A computer network (also referred to herein as a network) can be a device consisting of network nodes connected for communication with each other. The range of devices can range from computing devices (e.g., personal computers, smartphones, wearable devices, etc.) to home appliances (e.g., appliances, doorbells, thermostats, etc.) to devices in automobiles or other types of transportation, and others. A network node can be a connection point in a network. Examples of network nodes include network switches, network hubs, bridges, network routers, wireless access points, and the like. The scope of a network may vary depending on the context. For example, a network can be a device connected to a single network switch. Therefore, a network switch (also referred to as a switch) can be a network node that connects devices to create a network. A network can be a device connected to multiple switches. A network can be a device connected to one or more switches and a network router. A network router (also referred to as a router) can be a network node that can connect multiple switches and thus form a larger network. A network can be a device and network node located in a specific location, which may be called a Local Area Network (LAN). A network can be multiple LANs connected together, which may be called a Wide Area Network (WAN). The public Internet is an example of a WAN. As used herein, the term network may have any scope unless otherwise specified, such as by location, by type, by a set of network nodes, etc.

[0003] A network switch may contain switch ports. A switch port (also referred to herein as a port) may be an entry point of the switch (e.g., network traffic entering the switch), an exit point of the switch (e.g., network traffic leaving the switch), or both. A switch port receiving inbound traffic may be coupled to a packet processing pipeline. A processing pipeline (PP) may be multiple hardware functions operating concurrently. Hardware functions may be circuitry that performs the function. Hardware functions may be heterogeneous. Alternatively, some hardware functions may be identical. A packet PP may be a PP that receives packets as input, processes the packets through the hardware function, and produces a result as output. The network switch may use the results from the packet PP to determine how to exchange packets between destinations. A network switch may have a static one-to-one relationship between a switch port and a packet PP, through which it processes its packets.

[0004] One limiting factor for the achievable performance of a network switch is its packet processing rate. The packet processing rate can be the number of packets processed per unit time. It can be determined at least in part by the number of packet PPs and the operating frequency. Increasing one or both of these parameters can improve performance. However, the operating frequency parameter may not be a meaningful way to improve performance. The impact of adding additional packet PPs on performance can be more subtle. Because a static one-to-one relationship can exist between switch ports and their corresponding packet PPs, only a limited number of switch ports connected to additional packet PPs can utilize the added capacity for packet processing. Consider an instance where a first switch port connected to a first PP has a low packet rate requirement, while a second switch port connected to a second PP has a packet rate requirement greater than that provided by the second PP. In this instance, some of the capacity provided by the first PP for packet processing is unused, while the capacity provided by the second PP for packet processing is 100% consumed and insufficient to meet the second switch port's requirements. In this instance, the capacity of the first PP can be considered "stranded" and cannot be used to meet the network switch's packet processing rate requirements. Summary of the Invention

[0005] In some embodiments, a device in a network switch may include a processing pipeline that includes outputs of switch circuitry coupled to the network switch. The device may include first circuitry coupled between a port group of the network switch and an input to the processing pipeline, the first circuitry being configured to distribute data packets output from the port group between processing pipelines. The device may include memory coupled to the processing pipeline. The processing pipeline may be configured to process a stream of data packets using digital logic based on the state of the port group to produce results, supply the results to switch circuitry to exchange data packets, and write and read states from the memory.

[0006] In some embodiments, a method for processing data packets in a network switch may include receiving data packets at a port group of the network switch. The method may include distributing the data packets output from the port group between processing pipelines of the network switch by a first circuit. The method may include processing a stream of data packets by the processing pipelines through digital logic based on the state of the port group to produce a result. The method may include supplying the result to switching circuitry of the network switch to exchange data packets. The method may include writing state to and reading state from the network switch's memory by the processing pipelines during the processing of the data packet stream.

[0007] In some embodiments, a network switch may include a port group, switch circuitry coupled to the port group, and a hardware platform coupled to the port group and the switch circuitry. The hardware platform may include a processing pipeline that includes outputs coupled to the switch circuitry. The hardware platform may include first circuitry coupled between the port group and the inputs of the processing pipeline, the first circuitry being configured to distribute data packets output from the port group between processing pipelines. The hardware platform may include memory coupled to the processing pipeline. The processing pipeline may be configured to process a stream of data packets using digital logic based on the state of the port group to produce results, supply the results to the switch circuitry to exchange data packets, and write and read states from the memory. Attached Figure Description

[0008] Figure 1 It is a block diagram depicting a network according to some embodiments.

[0009] Figure 2 This is a block diagram depicting a network switch according to some embodiments.

[0010] Figure 3 This is a block diagram depicting a processing pipeline (PP) according to some embodiments.

[0011] Figure 4 It is a block diagram depicting a set of power switches (PPs) in a network switch.

[0012] Figure 5 This is a block diagram depicting a set of PPs in a network switch according to some embodiments.

[0013] Figure 6 This is a flowchart depicting a method for processing data packets in a network switch according to some embodiments. Detailed Implementation

[0014] Figure 1 This is a block diagram depicting a network 100 according to some embodiments. Network 100 may include a network switch 14 connected to one or more devices 16. Devices 16 may be computing devices (e.g., personal computers, smartphones, wearable devices, etc.) to home appliances (e.g., appliances, doorbells, thermostats, etc.) to devices in automobiles or other types of vehicles, and others. Network switch 14 may be coupled to one or more other network nodes 12.

[0015] Communication between devices and nodes in network 100 can be organized into layers, such as those defined by the well-known Open Systems Interconnection (OSI) model. The physical layer (also known as layer 1) provides electrical, mechanical, and process interfaces to the transmission medium. The transmission medium is the physical path through which data can be transmitted. The transmission medium can be wired (e.g., twisted-pair cable, coaxial cable, fiber optic cable, etc.), wireless, or a combination thereof. The data link layer (also known as layer 2) transmits data between network nodes using addresses used for device identification while ensuring reliable transmission across the transmission medium. Ethernet, a widely used and well-known networking technology, implements the data link layer in the network. The network layer (also known as layer 3) is responsible for determining how data is transmitted between devices across different networks. Internet Protocol (IP), a widely used and well-known networking technology, implements the network layer in the network. The primary function of the network layer is routing, which ensures that data is sent to the correct destination even when traversing multiple networks.

[0016] Network switch 14 can send and receive network services. A network service (hereinafter referred to as a service) can be a certain amount of data packets transmitted or received within a given time. A data packet can be a formatted data unit. The data in a data packet can be divided into control data and payload data, where the control data provides information for delivering the payload data. Services can be transmitted and received using protocols at different network layers (e.g., different layers of the OSI model). A Protocol Data Unit (PDU) can be a data transmission unit used for a given network layer. Different network layers can specify different types of PDUs. As used herein, the term data packet can refer to a PDU at a layer (e.g., the data link layer or the network layer). A data packet at one layer can be encapsulated within a data packet at another layer.

[0017] Network switch 14 can receive inbound traffic from device 16 and node 12. Network switch 14 can process inbound traffic using packets PP, as discussed in the following embodiments. Network switch 14 can use the results generated by packets PP to forward packets in the inbound traffic as outbound traffic to device 16 and node 12.

[0018] Figure 2This is a block diagram depicting a network switch 14 according to some embodiments. The network switch 14 may include a hardware platform 203, a physical port 210 (shown as a PHY port 210), input / output (I / O) circuitry 214, and support circuitry 216. The hardware platform may be a physical component (sometimes referred to as hardware) of an electronic system. The hardware platform 203 may contain the physical components of the network switch 14. In some embodiments, the hardware platform 203 includes a central processing unit (CPU) 202, hardware functions 204, and memory 206. The CPU may be circuitry capable of interpreting and executing instructions for software and manipulating data for the software. The software may be instructions and data for operating a computing device. The memory may be one or more circuits for storing information. The memory 206 may include volatile memory, non-volatile memory, or a combination thereof. Volatile memory may be any type of memory circuitry (e.g., RAM 24) that requires power to maintain the stored information. Non-volatile memory can be any type of memory circuit that retains data even when the power is off or disconnected (e.g., read-only memory (ROM), erasable programmable ROM (EPROM), flash memory, etc.).

[0019] CPU 202 can execute software stored in memory 206. The software may include software function 208. Hardware function 204 can be any type of operation of a device executed using circuitry. Software function 205 can be any type of operation of a device executed using software. Hardware function 206 can be the operation of network device 200. CPU 202 can be coupled to hardware function 204 to control it. Software function 208 can be the operation of network device 200. CPU 202 can be coupled to memory 206 to execute software function 208.

[0020] Physical port 210 may be circuitry providing an ingress and / or egress point for network switch 200. Each physical port 210 may include a transceiver 212. The transceiver may be circuitry capable of transmitting and receiving signals. The transceiver 212 may transmit and receive signals from the network's transmission medium. Physical port 210 may be supported by hardware platform 203. Components may be supported by hardware platform 203 through control by hardware platform 203, through data exchange with hardware platform 203, through implementation by hardware platform 203, or any combination thereof. Hardware platform 203 may control physical port 210 (e.g., control the configurable settings of physical port 210). Hardware platform 203 and physical port 210 may exchange data.

[0021] The I / O circuit can be a circuit that facilitates the reception of input data and the transmission of output data. I / O circuit 214 can receive input data from hardware platform 203 and transmit output data from hardware platform 203. I / O circuit 214 may include circuitry other than physical port 210. The support circuitry can be circuitry that supports the hardware of the device. Support circuitry 216 can support hardware platform 203 and physical port 210. Support circuitry 216 may include power supply, circuit board, backplane, etc.

[0022] Figure 3 This is a block diagram depicting a processing pipeline (PP) 302 according to some embodiments. PP 302 may be implemented in a network switch 14. PP 302 may include digital logic 304. The digital logic may be circuitry for processing digital signals. Digital logic 304 may include hardware functions (HWF) 2041…204 N The hardware function may be circuitry that performs a certain function (e.g., a function for processing data packets). PP 302 can receive incoming data packets and output data to switch circuit 205. The incoming data packets can be processed by HWF 204 in digital logic 304 of PP 302. PP 302 may include inputs, including control inputs, power inputs, and clock inputs. The clock input can receive a clock signal for timing digital logic 304. The power input can receive power from a power source. The control input can receive control signals for controlling HWF 204 of digital logic 304.

[0023] Figure 4 This is a block diagram depicting a set of process panels (PPs) in a network switch. Network switch 14 may contain PPs 3021…302. M PP3021…302 M The input can be coupled to multiplexers 4041…404 M The output. PP 3021…302 M The output of multiplexer 4041 can be coupled to the input of switch circuit 205. The input of multiplexer 4041 can be coupled to the output of PHY port 2101; the input of multiplexer 4042 can be coupled to the output of PHY port 2102…; multiplexer 404… M The input can be coupled to PHY port 402. M The output of the PHY port 2101…210. M These can be configured in port groups 4021…402 respectively. M In the middle. A port group can consist of multiple physical ports. For example, each PP 3021…302 M Can Figure 3 The configuration is displayed in the middle.

[0024] In a network switch, the role of the packet producer (PP) is to parse the contents of each inbound packet and determine how the packet will be routed to its exit destination on the switch. The limiting factor for the achievable performance of a switch is typically the device's packet processing rate. The device's packet processing rate can be determined by the device's operating frequency and the number of packet processing pipelines implemented on the device. To increase device throughput, one or both of these parameters can be increased. Despite progress through multiple generations of semiconductor process nodes, the frequency parameter has not yet become a meaningful way to improve performance. This leaves only the second parameter: adding additional PPs. The main problem with simply adding additional PPs to increase device bandwidth is that there is a static one-to-one relationship between physical ports and PPs; all packets from a physical port must be processed through that PP. In other words, the packet rate capacity increased by adding additional PPs can only be used by a limited number of physical ports connected to them.

[0025] This fixed connection means that when a PP (e.g., PP 2101) has low load or low packet rate demand, the processing capacity of that PP will be largely unused, even if another PP (e.g., PP 2102) is overused and requires a higher packet rate than PP 2102 can provide. In this example, the processing capacity of PP 2101 is "idle" and cannot be used to meet the device's packet rate requirements. This idleness of packet processing capacity is a problem addressed by the embodiments below. Typical network traffic demand is not uniform, as it varies over time and across ports. As the total switching throughput of the device increases, dedicating a small percentage of each PP to the switching throughput is inefficient, as it leads to PPs being easily idled. The implementation area of ​​each PP is valuable, so enabling each PP to be utilized more extensively improves device performance.

[0026] The embodiments described below enable each PP to be accessed by a wider group of ports and allow each port to access more than one PP. This allows the device to perform significantly better in a wider range of more common service scenarios. A second problem addressed by the embodiments below is that reducing the device's maximum power will lead to a degradation of several other performance characteristics. Methods for reducing maximum power include restraining or limiting the maximum packet rate achievable by the PP. The expected trade-off for achieving this maximum power reduction is an increase in the average packet size under which the device achieves full throughput. However, when there is a fixed connection between a port and a single PP, reducing the maximum packet rate can also have other undesirable side effects on performance.

[0027] Different techniques can be used to reduce the packet rate. One technique is to force idle packet cycles into the PP (Power Processor). Another technique is to reduce the frequency of the PP. Since there is only one PP for a group of ports, idle cycles must be forced equally on all PPs. This achieves the intention of reducing power under maximum load, but it also reduces performance under lower load conditions. When only a small fraction of the ports are active, the maximum packet rate achievable by a single port is limited by the reduced packet rate of the PP. This is similar to "idle," where the port will ideally be able to consume the packet rate from a single full-rate PP without violating the lower maximum power requirement. When reducing maximum power by reducing the clock frequency of the PP, in addition to the above side effects, there may also be the side effect of increased latency. The PP can be a fixed-latency pipeline, so reducing the clock frequency directly increases the clock cycle, and therefore the packet latency through the device increases proportionally to the frequency change.

[0028] Figure 5 This is a block diagram depicting a set of PPs in a network switch according to some embodiments. Figure 5 The configuration in the file can provide access to Figure 4 The configuration improvements shown in the example. Figure 5 As shown in the diagram, network switch 14 may include PP 3021…302 K PP 302 is part of the aggregated PP 503. Network switch 14 may include a PG selector 502 coupled between port group 402 and aggregated PP 503. The output of PHY port 210 in port group 402 is coupled to the input of PG selector 502. The output of PG selector 502 is coupled to PP 3021…302. K The input. Network switch 14 may include demultiplexer 504. PP 3021…302 K The output can be coupled to the input of demultiplexer 504. The outputs of the demultiplexer are 5061…506. M It can be coupled to the input of switch circuit 205. Network switch 14 may include memory 508. Memory 508 can store PG status data 5101…510. M PP 3021…302 K It can be coupled to memory 508.

[0029] The ports of network switch 14 can be organized into port groups 402, where each port group 402 can represent a certain amount of I / O bandwidth allocated among combinations of port speeds. For example, it can be configured as a 3.2 Tbps port group consisting of 8 x 400 Gbps ports or 2 x 800 Gbps + 8 x 200 Gbps ports. Figure 4In a configuration, a switch may only be able to support a limited number of port groups bound to a single PP, so that the ports in those port groups can use that one and only PP. Figure 5 The embodiment described above addresses this issue by grouping multiple PP 302 (K) into an aggregated PP 503 and enabling multiple port groups 402 (M) to access any one of the K PP 302 within that aggregated PP 503. PP 302 within the aggregated PP 503 may be referred to as PP threads.

[0030] Creating a group containing M port groups and K PP threads has several direct benefits. A port can now access multiple PPs, so if a particular PP is busy reloading packets from other ports, different ports can still use another PP from the aggregated PP to process their next packet in the same cycle. Another result is that... Figure 4 Compared to the previous configuration, the amount of port I / O bandwidth that can share the packet processing capabilities of the aggregated PP is significantly increased, which reduces the possibility of PP resources being "idle". In the example, K=3 and M=4. That is, there can be 4 port groups, each with 3.2 Tbps, which share the packet processing capabilities of the aggregated PP 503 with 3 PP threads. The granularity of bandwidth sharing can be increased to 4 times, from 3.2 Tbps to 12.8 Tbps, while the number of PPs required only increases by 3 (in this example).

[0031] like Figure 5 As shown, packets from each port group are serviced by an arbitration block, PP selector 502. PP selector 502 can distribute packets across PPs 302 for processing within aggregated PPs 503. Each PP thread can process one packet per cycle, thus aggregated PPs 503 can have a processing capacity of K packets per cycle. Once processing is complete, the result is the packet destination and the packet's metadata used by downstream switching blocks. These results are sent downstream to each parallel packet stream (506) to allow packets to be switched to their final destination. In some embodiments, each PP 3021…302 K The first bandwidth is equal to or less than the second bandwidth of the aggregated PP 503.

[0032] A major challenge in using aggregated PP 503 is ensuring the processing results are the same as when using a single PP. The processing performed on packets can be based not only on the packet content but also on the state maintained for the stream or port. This state can be maintained by the PP, and it can change over time based on received packets. Figure 4In this configuration, when all packets from a port are processed through the same PP, the state can be maintained internally by the PP, and the order of packets passing through the PP matches the order in which state information is accessed. Using aggregated PP 503, the state cannot be maintained within the PP thread because consecutive packets from the same port can be processed by different PP threads, and they will need to access and update the same state in the correct order. Therefore, in this embodiment, PG state data 5101…510 M It can be stored in memory 508 outside the PP thread, but can be accessed by any PP thread. Each PG status data 510 can contain all the variable state information that needs to be maintained for a single port group. When a PP thread is processing a packet from a specific port group, it will access the corresponding PG status data 510 and retrieve the state of the port or stream required to process the packet.

[0033] In some embodiments, memory 508 may include multiple memory circuits, such as M memory circuits. Each memory circuit may store PG status data 5101…510. M The corresponding entity in each PP 3021…302 K It can be coupled to either of the memory circuits via a bus (e.g., another circuit that performs arbitration). In another embodiment, memory 508 includes storage of PG status data 5101…510. M A memory circuit. Each PP 3021…302 K It can be coupled to memory 508. In some embodiments, memory 508 may have multiple ports (e.g., multiple read ports and multiple write ports).

[0034] Another aspect of PG state data is ensuring that multiple PP threads do not attempt to access the same state simultaneously. Avoiding this conflict provides two benefits. First, it ensures a deterministic packet ordering for packets from the same port or stream, consistent with the packet ordering of a single PP structure. Second, it avoids significant implementation area loss because the bandwidth for accessing PG state data can be enforced to at most one access per cycle. An embodiment of avoiding this conflict is described below. In this embodiment, each PP thread can process one packet in a single clock cycle. While a port group can have packets processed by any of the K PP threads, a packet from the same port group can only be processed in a single PP cycle across all PP threads. The PP threads of aggregated PP 503 can all operate in the same clock domain and can be synchronized. Therefore, K packets entering the K threads within the same clock cycle can flow down each PP level in a lockstep manner. This strategy can be enforced by PG selector 502, which is responsible for selecting up to K packets from the M port groups to send aggregated PP 503 in each clock cycle.

[0035] PG selector 502 can select K packets from M port groups, selecting at most one packet from each port group. Each of these K packets can be sent to one of K PP threads, without restricting which threads are used by previous packets from the same port or stream. As mentioned above, PG status data 510 in memory 508 can be accessed by PP threads. Therefore, by limiting the number of simultaneous packets from the PG, this ensures that K memory accesses from the same PP level across K PP threads do not attempt to access the same PG status data 510. Note that in addition to enforcing the above selection strategy, PG selector 502 can also apply selection strategies for how packets are selected across M port groups. Different strategies may have different effects on behavior and efficiency, but the choice of strategy is not limited to this embodiment. Any known arbitration can be used.

[0036] Another benefit of this embodiment is the ability to achieve maximum power limiting without sacrificing performance under lower loads. When K PP threads are aggregated together, maximum power is consumed when the aggregated PP 503 processes a total of K packets per cycle. To enforce lower maximum power, this value can be limited to a lower value, such as, for example, ⅔ K or ½ K. PG selector 502 can be configured to select a smaller number of packets per cycle, which will moderate the packet rate and limit the maximum power. When a port group is served at one packet per clock cycle, the port group reaches its maximum performance. Therefore, as long as the packet rate limit is greater than or equal to one packet per cycle, the optimal performance of the port group is not affected by the maximum packet rate limit. If we compare... Figure 4Therefore, the maximum packet rate for a single PP is already one packet per cycle. Thus, if packet rate throttling is applied to limit maximum power, the packet rate must be reduced to less than 1. This means that the optimal performance of a port group will be affected, as it is now impossible to achieve a packet rate of one packet per cycle.

[0037] In this example, K=3 and the maximum performance mode allows a maximum packet rate of 3 packets per cycle. In low power mode, the packet rate limit can be reduced to 1.5, meaning that the PG selector 502 can limit the packet rate to an average of 1.5 packets per cycle. Since 1.5 is still greater than 1, a single port group can still achieve its optimal performance when it is under maximum load and other port groups are under low or no load.

[0038] In the above embodiments, inbound data packets received by the physical port are processed by the PP, and the results are delivered to the switch circuitry. In other embodiments, the PP can be used in the outbound direction. Therefore, similar to... Figure 3 As shown in the diagram, PP can receive outgoing data packets from the switch circuitry, and the results are delivered to the physical port. For example... Figure 4 As shown, when PP 302 processes outgoing packets instead of incoming packets, PHY port 210 and switch circuit 205 can be swapped. Similarly, as... Figure 5 As shown, when the aggregation PP 503 processes outgoing packets instead of incoming packets, the PHY port 210 and the switch circuit 205 can be swapped.

[0039] Figure 6 This is a flowchart depicting a method 600 for processing data packets in a network switch according to some embodiments. Method 600 begins at step 602, where ports in a port group are capable of receiving data packets. At step 604, a PG selector 602 can distribute data packets output from the port group among PPs in aggregated PPs 503. At step 606, the PPs can process the stream of data packets using digital logic based on the state of the port group to produce a result. At step 608, the PPs can read state from / write state to the port group's memory during the processing of the data packet stream. At step 610, the PPs can supply the result to switch circuitry 205 in the network switch.

[0040] While some processes and methods having various operations have been described, one or more embodiments also relate to apparatus or devices for performing these operations. The apparatus may be specially configured for the desired purpose, or the apparatus may be a general-purpose computer selectively activated or configured by a computer program stored in a computer. Various general-purpose machines may be used with computer programs written according to the teachings herein, or it may be more convenient to construct more specialized devices to perform the desired operations.

[0041] As used herein, the phrase “at least one of…” following a series of items (where the terms “and” or “or” are used to separate any of the items) modifies the entire list, not each member of the list (i.e., each item). The phrase “at least one of…” does not require the selection of at least one of every listed item; rather, the phrase allows for the inclusion of at least one of any of the items and / or at least one of any combination of the items. For example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and / or any combination of A, B, and C. This is explicitly stated in examples where the intention is to select “at least one of each of A, B, and C” or alternatively, “at least one of A, at least one of B, and at least one of C.”

[0042] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0043] As used herein, the term “coupling” and its derivatives include: (a) electrical, magnetic and communication coupling; and (b) does not mean a direct connection but may include intermediate elements unless described as “direct coupling”.

[0044] While one or more embodiments of the invention have been described in some detail for clarity, certain changes may be made within the scope of the claims. Therefore, the described embodiments should be considered illustrative rather than restrictive, and the scope of the claims is not limited to the details given herein, but may be modified within the scope of the claims and their equivalents. In the claims, unless expressly stated in the claims, elements and / or steps do not imply any particular order of operation.

[0045] The boundaries between components, operations, and data storage are somewhat arbitrary, and specific operations are described in the context of the specific illustrative configuration. Other allocations of functionality are contemplated and may fall within the scope of this invention. Generally, structures and functionalities presented as individual components in the exemplary configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as single components may be implemented as single components. These and other variations, additions, and modifications may fall within the scope of the appended claims.

Claims

1. A device in a network switch, comprising: A processing pipeline that includes the outputs of switch circuitry coupled to the network switch; A first circuit is coupled between the port group of the network switch and the input of the processing pipeline, the first circuit being configured to distribute data packets output from the port group between the processing pipeline; and Memory, which is coupled to the processing pipeline; The processing pipeline is configured to process the stream of data packets using digital logic based on the state of the port group to produce results, supply the results to the switch circuitry to exchange the data packets, and write the state to and read the state from the memory.

2. The device according to claim 1, wherein the memory comprises: A memory circuit configured to store the state of the port group, each of the memory circuits being configured to store a corresponding portion of the state of at least one of the port groups; The device includes a second circuit configured to arbitrate access to the memory circuit between the processing pipelines.

3. The device of claim 1, wherein the memory is configured to store a corresponding portion of the state of a corresponding entity in the port group, wherein the memory comprises a plurality of ports, and wherein the processing pipeline is configured to access the memory via the ports.

4. The apparatus of claim 1, wherein the first bandwidth of each of the processing pipelines is equal to or less than the second bandwidth of the aggregated processing pipelines.

5. The device according to claim 1, further comprising: A second circuit is configured to couple the output of the processing pipeline to the input of the switch circuit.

6. The device of claim 5, comprising M port groups and K processing pipelines, wherein M and K are integers, and wherein the second circuitry is configured to couple a stream of K data packets to the M inputs of the switch circuitry.

7. The device according to claim 6, wherein K is less than M.

8. A method for processing data packets in a network switch, comprising: Receive data packets at the port group of the network switch; The first circuit distributes the data packets output from the port group across the processing pipeline of the network switch; The processing pipeline processes the data packet stream using digital logic based on the state of the port group to produce a result; The results are supplied to the switching circuitry of the network switch to exchange the data packets; and During the processing of the data packet stream, the processing pipeline writes the state to and reads the state from the network switch's memory.

9. The method of claim 8, wherein the memory comprises memory circuitry, and each of the memory circuitry is configured to store a corresponding portion of the state of at least one of the port groups.

10. The method of claim 8, wherein the memory is configured to store a corresponding portion of the state of a corresponding entity in the port group, wherein the memory comprises a plurality of ports, and wherein the processing pipeline is configured to access the memory via the ports.

11. The method of claim 8, wherein the first bandwidth of each of the processing pipelines is equal to or less than the second bandwidth of the aggregated processing pipelines.

12. The method of claim 8, further comprising: The output of the processing pipeline is coupled to the input of the switch circuit by the second circuit.

13. The method of claim 12, comprising M port groups and K processing pipelines, wherein M and K are integers, and wherein the second circuit is configured to couple a stream of K packets to the M inputs of the switch circuit.

14. The method of claim 13, wherein K is less than M.

15. A network switch, comprising: Port groups; A switch circuitry coupled to the port group; A hardware platform coupled to the port group and the switch circuitry, the hardware platform comprising: A processing pipeline that includes outputs coupled to the switch circuitry; A first circuit, coupled between the port group and the input of the processing pipeline, is configured to distribute data packets output from the port group between the processing pipelines; and Memory, which is coupled to the processing pipeline; The processing pipeline is configured to process the stream of data packets using digital logic based on the state of the port group to produce results, supply the results to the switch circuitry to exchange the data packets, and write the state to and read the state from the memory.

16. The network switch of claim 15, wherein the memory comprises: A memory circuit configured to store the state of the port group, each of the memory circuits being configured to store a corresponding portion of the state of at least one of the port groups; The device includes a second circuit configured to arbitrate access to the memory circuit between the processing pipelines.

17. The network switch of claim 16, wherein the memory is configured to store a corresponding portion of the state of a corresponding entity in the port group, wherein the memory comprises a plurality of ports, and wherein the processing pipeline is configured to access the memory via the ports.

18. The network switch of claim 16, wherein the first bandwidth of each of the processing pipelines is equal to or less than the second bandwidth of the aggregated processing pipelines.

19. The network switch of claim 16, further comprising: A second circuit is configured to couple the output of the processing pipeline to the input of the switch circuit.

20. The network switch of claim 19, comprising M port groups and K processing pipelines, wherein M and K are integers, and wherein the second circuitry is configured to couple a stream of K data packets to the M inputs of the switch circuitry.

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