Cache management method, system, device and readable storage medium

Abstract

This invention provides a cache management method, system, device, and readable storage medium. The method includes: acquiring the link status of each port and determining whether the link status of each port is abnormal; if the port is an abnormal port, stopping the writing of packet fragments from the abnormal port to the shared cache, and generating a cache forced ejection instruction based on the abnormal port to release the storage space occupied by packet fragments from the abnormal port in the shared cache. Compared with the prior art, this invention autonomously generates and executes the cache forced ejection instruction after detecting an anomaly, without CPU intervention. The anomaly handling latency depends only on the response speed of the hardware logic, avoiding performance degradation caused by waiting for the CPU. At the same time, forcibly ejecting all stored fragments from the abnormal port can help quickly release cache space and completely eliminate the risk of backlog and congestion.

Description

Technical Field

[0001] This invention belongs to the field of cache management technology, specifically relating to a cache management method, system, device, and readable storage medium. Background Technology

[0002] In integrated circuits such as network switching chips, shared buffer mechanisms are widely used to absorb bursts of traffic and improve data forwarding efficiency. Normally, packet fragments received by each port are written to the shared buffer, and after the complete packet is received, it is dequeued by the arbitrator, releasing the buffer space. However, in practical applications, due to abnormal link conditions or packet transmission anomalies, some ports may fail to complete the writing of the complete packet. In this case, the packet fragments already written to that port occupy the buffer space for a long time because they cannot be scheduled, causing buffer accumulation and congestion. In severe cases, this may lead to a decline in the performance of the entire switching system or even functional failure.

[0003] To address the aforementioned issues, existing technologies typically employ a chip-CPU collaborative processing approach: upon detecting a port anomaly, the chip stops writing packets to that port and generates an interrupt to notify the CPU; upon receiving the interrupt, the CPU issues a flush command via software, forcing the chip to clear the cached data of the abnormal port. While this method can alleviate cache accumulation to some extent, it relies on CPU intervention, resulting in a long anomaly handling path and significant response latency. Especially in high-throughput, low-latency data center or industrial network environments, untimely CPU response or excessively high interrupt handling latency can lead to the continuous spread of cache anomalies, impacting the overall reliability and stability of the system.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a cache management method, system, device, and readable storage medium.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a cache management method, system, device, and readable storage medium that can solve the problem of abnormal messages not being released.

[0007] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0008] In a first aspect, the present invention provides a cache management method, comprising:

[0009] Obtain the link status of each port and determine whether the link status of each port is abnormal;

[0010] If the port is an abnormal port, stop writing packet fragments from the abnormal port to the shared cache, and generate a cache forced ejection command based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

[0011] In one or more embodiments of the present invention, after stopping the writing of packet fragments from the abnormal port to the shared buffer, the method further includes:

[0012] Determine whether a complete message written based on the abnormal port exists in the shared cache;

[0013] If a complete message exists, the complete message is dequeued, and after the complete message is dequeued, in response to the cache forced pop instruction, the remaining message fragments written by the abnormal port are popped.

[0014] If no complete message exists, all message fragments written to the abnormal port will be forcibly popped.

[0015] In one or more embodiments of the present invention, determining whether a complete packet corresponding to the abnormal port exists in the shared cache includes:

[0016] Check whether the packet fragmentation number information is stored in the memory corresponding to the abnormal port;

[0017] If the message fragment number information has already been stored in the memory, then the shared cache contains a complete message written from the abnormal port;

[0018] If the message fragment number information is not stored in the memory, then the shared cache does not contain a complete message written from the abnormal port.

[0019] In one or more embodiments of the present invention, when the port receives packet fragmentation, the method further includes:

[0020] Parse the message fragment to determine whether the message fragment is the last fragment of the message;

[0021] If so, the packet fragmentation number information of the packet is stored in the memory corresponding to the port.

[0022] In one or more embodiments of the present invention, determining whether the message fragment is the last fragment of a message includes:

[0023] Obtain the effective data length of the packet fragment; if the effective data length is less than the fixed fragment length, then the packet fragment is the last fragment of the packet; and / or

[0024] Obtain the effective data length of the packet fragment. If the cumulative length of the packet received by the current port is equal to the expected total length of the packet, then the packet fragment is the last fragment of the packet; and / or

[0025] If a predefined end control word is detected on the data bus, then the message fragment is the last fragment of the message.

[0026] In one or more embodiments of the present invention, the method further includes:

[0027] The port starts counting when it receives the first fragment of the packet and stops counting when it receives the last fragment of the packet, and uploads the count value to the memory corresponding to the port.

[0028] In one or more embodiments of the present invention, the method further includes:

[0029] Monitor the link status of the abnormal port. When the abnormal port receives the first fragment of a packet,

[0030] Allow packet fragmentation for the abnormal port to be written to the shared cache.

[0031] Secondly, the present invention provides a cache management system, comprising:

[0032] The determination module is used to obtain the link status of each port and determine whether the link status of each port is abnormal.

[0033] The release module is used to stop writing packet fragments from the abnormal port to the shared cache when the port is an abnormal port, and to generate a cache forced pop command based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

[0034] Thirdly, the present invention provides an electronic device comprising:

[0035] At least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the cache management method.

[0036] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the cache management method described above.

[0037] Compared to existing technologies, the cache management method provided by this invention autonomously generates and executes a forced cache ejection instruction upon detecting an anomaly, without CPU intervention. The anomaly handling latency depends solely on the hardware logic's response speed, reaching nanosecond levels, thus avoiding performance degradation caused by waiting for the CPU. Simultaneously, forcibly ejecting all stored fragments from the abnormal port helps to quickly release cache space, completely eliminating the risk of congestion. It is suitable for various Ethernet environments with high real-time data transmission requirements, such as data center networks, industrial networks, and vehicle networks, and is particularly suitable for devices such as multi-port shared cache switches, routers, and network processors. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating an implementation scenario of the cache management method in one embodiment of the present invention;

[0040] Figure 2 This is a flowchart of a cache management method in one embodiment of the present invention;

[0041] Figure 3 This is a structural block diagram of the cache management system in another embodiment of the present invention;

[0042] Figure 4 This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0044] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0045] Existing solutions for cache congestion primarily rely on real-time monitoring of port status by chip logic. When a delimitation error or port link failure is detected, the storage of subsequent packet fragments on that port is terminated, and an interrupt is generated to notify the upper-layer CPU. After completing the interrupt handling, the CPU issues a flush command to force the chip to clear the exception cache. However, in this solution, there are unpredictable delays between exception detection and CPU communication, interrupt handling, and software scheduling. Furthermore, before the CPU issues the flush command, the exception packet fragments have already occupied cache resources for a long time, inevitably leading to low exception handling efficiency, continuous blocking of normal packets, and even deterioration of the overall chip performance.

[0046] Through in-depth analysis, the inventors discovered that the root cause of the aforementioned defects lies in the fact that the chip only assumes the role of anomaly detection and passive execution, while the critical cache management decision-making power is entirely delegated to the CPU. This results in an excessively long processing chain, making it difficult to meet real-time response requirements. Based on this defect, the present invention proposes a new approach that completely changes the original technical path. This approach decentralizes the entire process of anomaly detection, decision-making, and execution to the chip hardware logic. The chip hardware autonomously completes the link status judgment, immediately terminates writing, and automatically generates a cache forced pop instruction. Furthermore, before popping the abnormal cache, it intelligently distinguishes between "completely received packets" and "abnormal residual fragments," prioritizing the normal dequeueing of complete packets before releasing the cache occupied by abnormal fragments. Simultaneously, the hardware automatically monitors the link recovery status and allows packet writing again.

[0047] Please refer to Figure 1 The diagram illustrates an application scenario of the cache management method provided by the present invention under one embodiment. The scenario specifically includes: a port, a shared cache, and an arbitrator.

[0048] exist Figure 1 In the example shown, there are four ports, denoted as Port0, Port1, Port2, and Port3. These four ports share the same buffer. The data bus width can be 64 bytes. For ease of explanation, it can be assumed that the length of all data packets is fixed at 640 bytes. Therefore, each data packet will be divided into 10 fragments on the data bus, denoted as fragment 0 to fragment 9, where fragment 9 is the last fragment of the packet.

[0049] All packet fragments are sent to the shared buffer to await scheduling. When each port receives its last fragment, it stores the total number of packet fragments for that packet in the first-in-first-out queue corresponding to that port.

[0050] The arbitrator polls the first-in-first-out queues of each port. Once it finds a non-empty queue, it selects a dequeue request for a port and pops the corresponding packet fragment from the shared buffer. Figure 1 The application scenario shown constitutes the basic hardware environment for the cache management method of the present invention, and all the following implementation methods can be implemented in this scenario.

[0051] Please refer to Figure 2 The diagram shown illustrates a cache management process according to an embodiment of the present invention. The cache management method specifically includes the following steps:

[0052] S201: Obtain the link status of each port and determine whether the link status of each port is abnormal;

[0053] It should be noted that, in the embodiments of the present invention, the link status can refer to the normal working status of the physical layer and data link layer during the process of the port receiving Ethernet data packets. For example, whether the physical connection between the port and the peer device is established, whether the received packet fragments can be correctly identified in terms of fragmentation boundaries, and whether the received packets have check errors, abnormal lengths, etc.

[0054] Furthermore, determining link anomalies may include, but is not limited to: physical link disconnection, inability to receive any data, loss of packet fragmentation boundaries, inability to determine the start / end position of fragmentation, etc., and this embodiment of the invention does not impose any limitations on these.

[0055] For example, link status signals such as LOS and link_down can be monitored. When a link switch signal becomes invalid, it can be considered that the port has lost its link, and the port with the lost link is an abnormal port. In addition, if the receiving logic detects alignment loss or fragmentation synchronization failure, it is considered that the port has a delimitation error, and the port with the delimitation error is an abnormal port.

[0056] S202: If the port is an abnormal port, stop writing packet fragments from the abnormal port to the shared cache, and generate a cache forced pop instruction based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

[0057] It should be noted that a shared buffer refers to on-chip storage resources shared by multiple input or output ports in a multi-port switching chip. Due to the limited width of the data bus, larger data packets are usually divided into multiple fixed-length fragments, which can be temporarily stored in the aforementioned shared buffer after being received by the port.

[0058] In one implementation, when any port receives a packet fragment under normal link conditions, the receive control logic inside the chip will parse the control header information carried by each arriving packet fragment to determine whether the received current packet fragment is the last fragment of the corresponding packet.

[0059] The control header may include at least a fragment type identifier and the effective data length carried by the fragment. The receiving logic determines whether the current fragment is the last fragment of the message by detecting the type identifier in the control header, or by determining whether the fragment length is less than the fixed fragment length or the cumulative received length is equal to the expected total length of the message.

[0060] For example, it can be determined whether the current fragment is the last fragment of a message in any of the following ways: If the effective data length is less than the fixed fragment length, then the fragment is determined to be the last fragment; or, if the cumulative length of the same message received by the current port is equal to the expected total length of the message, then the fragment is determined to be the last fragment; or, if a predefined end control word is detected on the data bus, then the fragment is determined to be the last fragment.

[0061] Furthermore, if it is determined that the current fragment is not the last fragment of the message, the next fragment of the message is received, and the received fragment count is updated. If it is determined that the current fragment is the last fragment of the message, it indicates that all fragments of the message have been written to the shared buffer. At this time, the chip logic can calculate the total number of message fragments occupied by the message from the first fragment to the last fragment, and store the total number of message fragments in the memory corresponding to the port.

[0062] In one implementation, each port can be configured with an independent memory, and the memory can be a first-in-first-out queue (FIFO) or other forms of storage unit. The present invention does not limit the selection of memory.

[0063] The fragment count information stored in memory can be used for subsequent scheduling and dequeueing. The arbitrator polls the memory of each port. If it finds that the memory corresponding to a port is not empty, it reads the total number of packet fragments from it, and based on this information, reads the corresponding number of fragments from the shared buffer to form a complete packet and forwards it. At the same time, the total number of packet fragments information in the memory is popped, and the corresponding buffer unit is released.

[0064] It should be noted that the process of receiving and storing fragment count information described above only occurs when the port link is normal and the message can be received completely. Once the port is detected as abnormal, the chip will immediately stop writing new message fragments to the shared buffer and will no longer store any new fragment count information in the port's memory. This ensures that the port's memory status can accurately reflect whether there are complete messages in the shared buffer, providing a basis for subsequent buffer management judgments.

[0065] The aforementioned link status anomalies typically prevent the receiving port from receiving or identifying the last fragment of a packet. Since switching chips usually schedule and forward packets in complete units, packets lacking the last fragment are considered invalid data and cannot trigger the arbitrator to schedule them out of the queue. Although these incomplete packet fragments are invalid, they still occupy storage units in the shared buffer. The total capacity of the shared buffer is limited. The buffer space occupied by the abnormal port for an extended period cannot be reused by other ports. When the buffer occupancy rate reaches a threshold, it can cause packet writing to be blocked on all ports, and may even lead to packet loss or a sharp performance drop across the entire chip.

[0066] Therefore, in this embodiment of the invention, if a port abnormality is detected, the writing of packet fragments from the abnormal port to the shared cache is stopped first, and a cache forced pop instruction is further generated, instructing the shared cache controller to perform the operation of ignoring normal scheduling rules, directly reading out and discarding all stored packet fragments of the specified port one by one.

[0067] It's important to note that if the chip detects a port anomaly and immediately forces the ejection of all packet fragments from that port's shared buffer, while quickly freeing up buffer space, the port may have already successfully received and fully stored several packets before the anomaly occurred. This means the last fragment has been received, and the fragment count information is stored in memory. These packets themselves are valid and error-free; they are only affected by subsequent link anomalies. Furthermore, if the discarded complete packets belong to a reliable transport protocol (such as TCP), the upper-layer protocol will trigger retransmissions due to timeouts or missing packets, consuming network bandwidth and increasing end-to-end latency. In high-performance networks such as data centers, retransmissions significantly reduce effective throughput.

[0068] Therefore, in one embodiment of the present invention, after the chip stops writing packet fragments from the abnormal port to the shared cache, it can further determine whether a complete packet written by the abnormal port already exists in the shared cache. If a complete packet exists, these complete packets are prioritized for normal dequeueing. After all of them have been dequeued, the incomplete fragments written by the abnormal port are popped in response to the previously generated cache forced pop instruction. Conversely, if no complete packets exist in the shared cache, the cache forced pop instruction is directly responded to, and all packet fragments written by the abnormal port are popped at once.

[0069] Regarding how to determine whether a complete packet exists in the shared buffer, the packet dequeue strategy described above can be used. In an exemplary implementation, the chip can make this determination by checking whether packet fragment count information is stored in the memory corresponding to the abnormal port. Specifically, if the memory already contains packet fragment count information, it means that there is at least one complete packet written from the abnormal port in the shared buffer; if the memory has not yet stored any packet fragment count information, it means that there are only incomplete abnormal fragments in the shared buffer.

[0070] After completing the forced buffer ejection operation and completely releasing the shared storage space occupied by the abnormal port, this invention also provides an automated port recovery and write reentry mechanism. This mechanism enables the abnormal port to seamlessly resume receiving packets and writing fragments to the shared buffer without manual or software intervention after the link status returns to normal.

[0071] In one implementation, after detecting that a port has been marked as abnormal and buffer management has been triggered, the link monitoring logic inside the chip continuously observes the physical layer status, receive error flags, and fragmentation synchronization status of the port. When the physical layer reports a valid link connectivity signal, meaning the port is no longer in a disconnected state and no delimitation or checksum errors have occurred within multiple consecutive receive cycles, the chip determines that the link status of the port has returned to normal.

[0072] To further ensure the security and reliability of the recovery process, in another embodiment of the invention, link state recovery is not the sole condition for allowing rewriting. Instead, it requires that, based on a normal link state recovery, the port must successfully receive the first fragment of a complete packet. This first fragment is the first fragment of the packet and typically carries a fragment type identifier or a start flag. The chip confirms that it is the first fragment by parsing the fragment's control header, and that the fragment is not accompanied by any abnormal indications. Only when both of these conditions are met does the chip consider the port ready to receive new packets and then perform the recovery write operation.

[0073] The specific process for resuming write operations is as follows: The chip clears the write-disable flag of the port, allowing the port to write subsequently received packet fragments to the shared buffer again. Simultaneously, the chip resets the packet fragment counter and related state machine of the port to their initial values ​​to ensure that the reception of new packets is not affected by historical residual states. From this moment on, the port will operate according to the normal packet reception process: each received packet fragment is written to the shared buffer; when the last fragment is received, the packet fragment count information is stored in the corresponding memory for the arbitrator to schedule dequeueing.

[0074] Through the above mechanism, this invention achieves fully automatic recovery of abnormal ports without any software or CPU intervention. This mechanism, together with the aforementioned steps of anomaly detection, write stop, and forced ejection, constitutes a complete closed-loop processing flow, enabling the multi-port shared cache system to quickly self-repair after link jitter or brief failures, thereby ensuring the long-term stable operation of the switching chip and high cache utilization.

[0075] Please refer to Figure 3 As shown, based on the same inventive concept as the aforementioned cache management method, one embodiment of the present invention provides a cache management system 300, including: a determination module 301 and a release module 302.

[0076] Specifically, the determination module 301 is used to obtain the link status of each port and determine whether the link status of each port is abnormal; the release module 302 is used to stop writing packet fragments from the abnormal port to the shared cache when the port is an abnormal port, and generate a cache forced pop instruction based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

[0077] Please refer to Figure 4 As shown, embodiments of the present invention also provide an electronic device 400, which includes at least one processor 401, a memory 402 (e.g., non-volatile memory), a main memory 403, and a communication interface 404, wherein the at least one processor 401, the memory 402, the main memory 403, and the communication interface 404 are connected together via an internal bus 405. The at least one processor 401 is used to invoke at least one program instruction stored or encoded in the memory 402, causing the at least one processor 401 to perform various operations and functions of the cache management methods described in the various embodiments of this specification.

[0078] In the embodiments of this specification, electronic device 400 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile electronic device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable electronic device, consumer electronic device, etc.

[0079] This invention also provides a computer-readable medium carrying computer-executable instructions. When executed by a processor, these instructions can be used to implement various operations and functions of the cache management methods described in the various embodiments of this specification.

[0080] The computer-readable medium in this invention can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0081] In this invention, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0082] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, as well as combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0084] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

[0085] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0086] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A cache management method, characterized in that, include: Obtain the link status of each port and determine whether the link status of each port is abnormal; If the port is an abnormal port, stop writing packet fragments from the abnormal port to the shared cache, and generate a cache forced pop command based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

2. The cache management method according to claim 1, characterized in that, After stopping the writing of packet fragments from the abnormal port to the shared buffer, the method further includes: Determine whether a complete message written based on the abnormal port exists in the shared cache; If a complete message exists, the complete message is dequeued, and after the complete message is dequeued, in response to the cache forced pop instruction, the remaining message fragments written by the abnormal port are popped. If no complete message exists, all message fragments written to the abnormal port will be popped up directly.

3. The cache management method according to claim 2, characterized in that, Determine whether the complete packet corresponding to the abnormal port exists in the shared cache, including: Check whether the packet fragmentation number information is stored in the memory corresponding to the abnormal port; If the message fragment number information has already been stored in the memory, then the shared cache contains a complete message written from the abnormal port; If the message fragment number information is not stored in the memory, then the shared cache does not contain a complete message written from the abnormal port.

4. The cache management method according to claim 1, characterized in that, When receiving fragmented packets at the port, the method further includes: Parse the message fragment to determine whether the message fragment is the last fragment of the message; If so, the packet fragmentation number information of the packet is stored in the memory corresponding to the port.

5. The cache management method according to claim 4, characterized in that, Determining whether the message fragment is the last fragment of a message includes: Obtain the effective data length of the packet fragment; if the effective data length is less than the fixed fragment length, then the packet fragment is the last fragment of the packet; and / or Obtain the effective data length of the packet fragment. If the cumulative length of the packet received by the current port is equal to the expected total length of the packet, then the packet fragment is the last fragment of the packet; and / or If a predefined end control word is detected on the data bus, then the message fragment is the last fragment of the message.

6. The cache management method according to claim 4, characterized in that, The method further includes: The port starts counting when it receives the first fragment of the packet and stops counting when it receives the last fragment of the packet, and uploads the count value to the memory corresponding to the port.

7. The cache management method according to claim 1, characterized in that, The method further includes: Monitor the link status of the abnormal port. When the abnormal port receives the first fragment of a packet, Allow packet fragmentation for the abnormal port to be written to the shared cache.

8. A cache management system, characterized in that, include: The determination module is used to obtain the link status of each port and determine whether the link status of each port is abnormal. The release module is used to stop writing packet fragments from the abnormal port to the shared cache when the port is an abnormal port, and to generate a cache forced pop command based on the abnormal port to release the storage space occupied by the packet fragments from the abnormal port in the shared cache.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory that stores instructions, which, when executed by the at least one processor, cause the at least one processor to perform the cache management method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the cache management method according to any one of claims 1-7.

Images