A sampling method and device of an oversampling IO module
By autonomously controlling the sampling timing using timer interrupt operations in EtherCAT slave stations, the problem of frame loss in sampling data caused by reliance on distributed clocks and SYNC0 hardware pulses in existing oversampling technologies is solved, thereby improving the reliability and anti-interference capability of sampling transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SUPCON TECH CO LTD
- Filing Date
- 2026-05-28
- Publication Date
- 2026-07-31
AI Technical Summary
Existing oversampling techniques rely on distributed clocks and SYNC0 hardware pulses, which are susceptible to electromagnetic interference and clock drift, leading to frame loss in the sampled data.
By using timers for interrupt operations in EtherCAT slave stations, the sampling timing can be autonomously controlled. The sampling cycle is triggered only when the synchronization pulse arrives, and the data is uploaded uniformly after the sampling is completed, avoiding the synchronization deviation and cumulative error caused by relying on the distributed clock and SYNC0 hardware pulse.
It improves the reliability and anti-interference capability of oversampling transmission, and effectively solves the problem of frame loss of sampling data caused by clock jitter and bus load fluctuation.
Smart Images
Figure CN122496530A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of automatic control technology, and in particular to a sampling method and apparatus for an oversampling I / O module. Background Technology
[0002] Industrial automation has an urgent need for high-speed synchronous sampling, and EtherCAT (Ethernet Control Automation Technology) has become the mainstream real-time bus due to its distributed clock. Traditional I / O samples only once per cycle, and aliasing is prone to occur when the signal is faster than the cycle. To address this, oversampling technology has been introduced, which achieves a high equivalent sampling rate with low bandwidth by sampling multiple times within a single cycle and uploading them in batches.
[0003] To address the aforementioned oversampling requirements, existing solutions generally employ distributed clock and SYNC0 hardware pulse technology. This involves first achieving full network DC synchronization to sub-microsecond levels, configuring the master station's ESC SYNC0 cycle as a sub-sampling cycle, triggering an ESC hardware interrupt with each SYNC0 pulse, then having the slave station immediately sample and store the data in the ESC's internal buffer, and finally, after a standard bus cycle, having the master station read all oversampling fragments in batches via data frames.
[0004] However, existing oversampling technologies rely on distributed clocks and SYNC0 hardware pulses, with the number of slices determined by the ESC cache depth and SYNC0 frequency. Although high-end chips support 100~256 slices per cycle (sampling period 5~10μs), electromagnetic interference, clock drift, and transmission fluctuations in industrial environments can easily disrupt sub-microsecond synchronization, leading to sampling errors or data frame loss. Summary of the Invention
[0005] In view of the shortcomings of the prior art, this application provides a sampling method and apparatus for an oversampling I / O module to solve the problem of frame loss in sampling data caused by relying on distributed clock and hardware pulse technology.
[0006] To achieve the above objectives, this application provides the following technical solution:
[0007] The first aspect of this application provides a sampling method for an oversampling I / O module, applied to the oversampling I / O module, comprising:
[0008] Obtain the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station;
[0009] In response to the current synchronization pulse signal, a timer in the EtherCAT slave station is started, and an interrupt operation is periodically performed on the timer;
[0010] Whenever the timer is interrupted, the current input signal in the IO sampling and conditioning circuit is sampled to obtain sampled data, and the current value of the sampling count is incremented by one.
[0011] Based on the current value of the sampling count and the slicing parameters, determine whether the IO sampling conditioning circuit has completed sampling;
[0012] If the IO sampling and conditioning circuit completes sampling, it receives the next synchronization pulse signal and packages all the sampled data within the communication window corresponding to the next synchronization pulse signal to obtain packaged data.
[0013] The packaged data is stored in the EtherCAT master station, and the next synchronization pulse signal is used as the current synchronization pulse signal. Then, the process of obtaining the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station is returned.
[0014] Optionally, in the sampling method of the oversampling I / O module described above, the periodic interrupt operation on the timer includes:
[0015] Based on the sharding parameters, multiple sub-cycles are generated;
[0016] An interrupt operation is performed on the timer according to each of the sub-cycles.
[0017] Optionally, in the above-described sampling method for the oversampling I / O module, determining whether the I / O sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters includes:
[0018] Determine whether the current value of the sampling count is equal to the fragmentation parameter;
[0019] If the current value of the sampling count is equal to the slicing parameter, then the sampling of the IO sampling conditioning circuit is determined to be complete.
[0020] If the current value of the sampling count is not equal to the slicing parameter, then it is determined that the IO sampling conditioning circuit has not completed sampling.
[0021] Optionally, in the above-described sampling method for the oversampling I / O module, after determining whether the I / O sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters, the method further includes:
[0022] If the IO sampling and conditioning circuit fails to complete sampling, it returns to the previous step of periodically interrupting the timer.
[0023] Optionally, in the sampling method of the oversampling I / O module described above, before receiving the next synchronization pulse signal, the method further includes:
[0024] Obtain the sampling time of all the sampled data;
[0025] Sort each sample data according to its sampling time;
[0026] Each sorted sampled data is stored sequentially in the buffer.
[0027] Optionally, in the sampling method of the above-described oversampling IO module, after storing the packaged data in the EtherCAT master station, the method further includes:
[0028] Clear all sampled data in the buffer.
[0029] A second aspect of this application provides a sampling device for an oversampling I / O module, comprising:
[0030] The acquisition unit is used to acquire the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station;
[0031] An interrupt unit is used to start a timer in the EtherCAT slave station in response to the current synchronization pulse signal, and periodically perform an interrupt operation on the timer;
[0032] The sampling unit is used to sample the current input signal in the IO sampling conditioning circuit whenever the timer is interrupted, obtain the sampled data, and increment the current value of the sampling count by one.
[0033] The sampling judgment unit is used to determine whether the IO sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters;
[0034] The packaging unit is used to receive the next synchronization pulse signal when the IO sampling conditioning circuit has completed sampling, and to package all the sampled data in the communication window corresponding to the next synchronization pulse signal to obtain packaged data.
[0035] The data storage unit is used to store the packaged data in the EtherCAT master station, use the next synchronization pulse signal as the current synchronization pulse signal, and return to execute the process of obtaining the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station.
[0036] Optionally, in the sampling device of the above-described oversampling I / O module, the interrupt unit includes:
[0037] The generation unit is used to generate multiple sub-cycles based on the sharding parameters;
[0038] An interrupt subunit is used to perform an interrupt operation on the timer according to each of the sub-cycles.
[0039] Optionally, in the sampling device of the above-mentioned oversampling I / O module, the sampling determination unit includes:
[0040] A judgment unit is used to determine whether the current value of the sampling count is equal to the fragmentation parameter;
[0041] The first determining unit is configured to determine that the sampling of the IO sampling conditioning circuit is complete if the current value of the sampling count is equal to the slicing parameter.
[0042] The second determining unit is used to determine that the IO sampling conditioning circuit has not completed sampling if the current value of the sampling count is not equal to the slicing parameter.
[0043] Optionally, the sampling device of the above-mentioned oversampling I / O module further includes:
[0044] An execution unit is configured to return to the periodic interrupt operation performed on the timer if the IO sampling and conditioning circuit has not completed sampling.
[0045] Optionally, the sampling device of the above-mentioned oversampling I / O module further includes:
[0046] A time acquisition unit is used to acquire the sampling time of all the sampled data;
[0047] A sorting unit is used to sort each of the sampled data according to the sampling time of each sampled data.
[0048] A storage unit is used to sequentially store each of the sorted sampled data into a cache area.
[0049] Optionally, the sampling device of the above-mentioned oversampling I / O module further includes:
[0050] The clearing unit is used to clear all sampled data in the buffer area.
[0051] A third aspect of this application provides an oversampling I / O module, which includes: a sampling module, an MCU microcontroller module, an ESC chip, and a cache module;
[0052] The MCU microcontroller module is connected to the ESC chip and the sampling module respectively;
[0053] The cache module is connected to the MCU microcontroller module and the ESC chip respectively;
[0054] The MCU microcontroller module acquires the current synchronization pulse signal sent by the EtherCAT master station, and starts a timer in response to the current synchronization pulse signal. Whenever the timer interrupt is triggered, it samples the current input signal in the IO sampling and conditioning circuit to obtain sampled data. After sampling is completed, it waits for the next synchronization pulse signal so that all the sampled data is packaged and uploaded to the EtherCAT master station within the communication window corresponding to the next synchronization pulse signal.
[0055] This application provides a sampling method for an oversampling I / O module. The method involves acquiring the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station. In response to the current synchronization pulse signal, a timer in the EtherCAT slave station is started, and an interrupt operation is periodically performed on the timer. Whenever the timer is interrupted, the current input signal in the I / O sampling conditioning circuit is sampled to obtain sampled data, and the current value of the sampling count is incremented. Then, based on the current value of the sampling count and the fragmentation parameters, it is determined whether the I / O sampling conditioning circuit has completed sampling. If the I / O sampling conditioning circuit has completed sampling, the next synchronization pulse signal is received, and all sampled data is packaged within the communication window corresponding to the next synchronization pulse signal to obtain packaged data. Finally, the packaged data is stored in the EtherCAT master station, and the next synchronization pulse signal is used as the current synchronization pulse signal. The process then returns to acquire the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station. This allows for autonomous control of the sampling timing via timer interrupts. The sampling cycle is only started and stopped when the synchronization pulse arrives, and the data is uploaded uniformly after sampling is completed, avoiding synchronization deviations and accumulated errors caused by relying on distributed clocks and SYNC0 hardware pulses. This effectively solves the problem of frame loss of sampling data caused by clock jitter and bus load fluctuations, and improves the reliability and anti-interference capability of oversampling transmission. Attached Figure Description
[0056] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0057] Figure 1 This is a schematic diagram of the structure of an oversampling I / O module provided in an embodiment of this application;
[0058] Figure 2 A schematic flowchart illustrating a sampling method for an oversampling I / O module provided in an embodiment of this application;
[0059] Figure 3 A flowchart illustrating an interruption operation according to another embodiment of this application;
[0060] Figure 4 A schematic flowchart illustrating a sampling determination method for an IO sampling conditioning circuit, provided in another embodiment of this application;
[0061] Figure 5 A flowchart illustrating a method for storing sampling data according to another embodiment of this application;
[0062] Figure 6 This is a schematic diagram of a test road generation example provided in another embodiment of this application. Detailed Implementation
[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0064] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0065] This application provides an oversampling I / O module to solve the problem of frame loss in sampled data caused by relying on distributed clock and hardware pulse technology.
[0066] Optionally, such as Figure 1 As shown in the figure, this application embodiment provides an oversampling I / O module, which includes: a sampling module, an MCU microcontroller module, an ESC chip, and a cache module.
[0067] The MCU microcontroller module is connected to the ESC chip and the sampling module respectively.
[0068] The cache module is connected to both the MCU microcontroller module and the ESC chip.
[0069] The MCU microcontroller module obtains the current synchronization pulse signal sent by the EtherCAT master station. In response to the current synchronization pulse signal, it starts a timer. Whenever the timer interrupt is triggered, it samples the current input signal in the IO sampling and conditioning circuit to obtain sampled data. After sampling is completed, it waits for the next synchronization pulse signal so that all the sampled data is packaged and uploaded to the EtherCAT master station within the communication window corresponding to the next synchronization pulse signal.
[0070] It should be noted that the MCU microcontroller module is a general-purpose industrial-grade microcontroller, equipped with a high-precision microsecond-level timer and a buffer chip interface. The SYNC1 signal of the ESC chip is connected to the interrupt pin of the MCU microcontroller module. The MCU mainly performs write operations, while the ESC chip performs data fetch operations.
[0071] Therefore, based on the oversampling I / O module provided above, this application embodiment correspondingly provides a sampling method for the oversampling I / O module, such as... Figure 2 As shown, the specific steps include:
[0072] S201. Obtain the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station.
[0073] The current synchronization pulse signal refers to the synchronization signal broadcast by the EtherCAT master station to the slave station based on a distributed clock or periodic communication mechanism. In this embodiment, a SYNC1 type synchronization pulse is specifically used. This signal is used to calibrate the start point of the bus cycle between the IO module and the master station, enabling multiple slave stations to work collaboratively under the same time base. The fragmentation parameter represents the number of oversampling operations expected to be completed within a bus cycle. For example, 100 fragments correspond to 100 equally spaced sampling operations within a bus cycle (usually 1ms), i.e., a sub-cycle of 10μs. The fragmentation parameter is issued by the master station to the slave station according to the field control requirements and is stored in the configuration register of the MCU microcontroller module.
[0074] It should be noted that after the system is powered on, the EtherCAT master station and the ESC chip complete the network handshake. The master station sends out core configuration parameters, including a 1ms fixed bus cycle and the number of oversampling slices required on site. The parameters are fixed to the MCU microcontroller module and the ESC chip, and the MCU microcontroller module enters the standby state.
[0075] It should also be noted that the ETHERCAT master station sends a SYNC1 synchronization pulse. The system will then lock into SYNC1 synchronization mode. The MCU captures the SYNC1 synchronization pulse sent by the EtherCAT bus in real time through ESC, accurately identifies the valid rising edge of the pulse, and uses this moment as the timing reference point for oversampling to ensure that the sampling timing is synchronized with the bus cycle.
[0076] It is easy to understand that the purpose of obtaining the above information is to provide a time base and sampling density basis for subsequent local timing sampling, thereby avoiding dynamic negotiation of sampling parameters in each bus cycle.
[0077] S202. In response to the current synchronization pulse signal, start the timer in the EtherCAT slave station and periodically perform interrupt operations on the timer.
[0078] It should be noted that the "current synchronization pulse signal" refers to the SYNC1 pulse obtained in step S201, which serves as the starting boundary of the current bus cycle. After the MCU microcontroller module captures the SYNC1 pulse, it immediately triggers the start of the built-in microsecond-level hardware timer.
[0079] Optionally, in another embodiment of this application, a specific implementation of the periodic interrupt operation on the timer in step S202 is as follows: Figure 3 As shown, the specific steps include:
[0080] S301. Generate multiple sub-cycles based on the slicing parameters.
[0081] Specifically, the MCU microcontroller module divides the bus cycle duration (e.g., 1ms) by the slicing parameter (e.g., 100) to obtain the sub-cycle duration (e.g., 100 slices correspond to 10us sub-cycles).
[0082] S302. Perform an interrupt operation on the timer according to each sub-cycle.
[0083] Specifically, the timer's auto-reload register is configured according to each sub-cycle so that subsequent timers generate an interrupt request every sub-cycle duration.
[0084] S203. Whenever the timer is interrupted, the current input signal in the IO sampling and conditioning circuit is sampled to obtain the sampled data, and the current value of the sampling count is incremented by one.
[0085] The IO sampling and conditioning circuit refers to the signal processing link located at the front end of the IO module. It typically includes signal isolation, filtering, and level conversion, and is used to adjust the analog or digital signals input from external field devices into an electrical form that the MCU microcontroller module can safely read. The "current input signal" refers to the instantaneous signal value presented at the output of the conditioning circuit at the moment the interrupt is triggered. The MCU microcontroller module reads this value through its internal analog-to-digital converter (ADC) or digital input port to form a sample data.
[0086] In addition, whenever the timer generates an interrupt, the MCU immediately schedules the IO sampling and conditioning circuit to sample the field signal.
[0087] Specifically, the current value of the sample count is an internal variable maintained by the MCU microcontroller module, initially set to zero. In each interrupt service routine, a sample read is performed first, followed by an increment operation on this variable. This variable is used to track the number of samples completed within the current bus cycle.
[0088] S204. Based on the current value of the sampling count and the slicing parameters, determine whether the IO sampling conditioning circuit has completed sampling.
[0089] The current value of the sampling count records the number of valid samples completed within the current SYNC1 synchronization pulse cycle, and its initial value is zero. The fragmentation parameter represents the total number of oversampling operations required by the EtherCAT master to be completed within one bus cycle, such as 100 or 200. This parameter is issued by the master during system initialization and stored in the MCU's configuration register, remaining constant throughout the sampling process.
[0090] It should be noted that "whether the IO sampling conditioning circuit has completed sampling" is essentially a logical judgment on whether the sampling progress within the current bus cycle has reached the preset target. Therefore, if it is determined that "sampling is complete", then step S205 is executed.
[0091] Optionally, in another embodiment of this application, one specific implementation of step S204 is as follows: Figure 4 As shown, the specific steps include:
[0092] S401. Determine whether the current value of the sampling count is equal to the slice parameter.
[0093] Specifically, the current value of the sampling count is compared with the slicing parameters. If they are equal, it means that the total number of samples performed in this cycle is exactly equal to the number of samples required by the master station, so step S402 is executed. If they are not equal, it means that the IO sampling conditioning circuit has not yet completed sampling in this cycle, so step S403 is executed.
[0094] S402. Confirm that the IO sampling conditioning circuit has completed sampling.
[0095] Specifically, when the "sampling completed" condition is determined, the MCU should stop responding to subsequent timer interrupts within the current bus cycle (timer interrupts can be masked or timer reload can be disabled), and then proceed to step S205 to wait for the arrival of the next SYNC1 synchronization pulse.
[0096] S403. It is determined that the IO sampling conditioning circuit has not completed sampling.
[0097] Optionally, after performing step S204, in another embodiment of this application, the following step is further included:
[0098] If the I / O sampling and conditioning circuit has not completed sampling, it will return to the execution of periodic interrupt operations on the timer.
[0099] Specifically, when the IO sampling conditioning circuit has not completed sampling, it is necessary to return to step S202 to periodically perform an interrupt operation on the timer, so that the timer continues to run and waits for the next interrupt to arrive, thereby ensuring that all chip sampling is completed continuously within one SYNC1 cycle.
[0100] S205. Receive the next synchronization pulse signal, and pack all the sampled data into a package within the communication window corresponding to the next synchronization pulse signal to obtain the packaged data.
[0101] The "next synchronization pulse signal" refers to the second SYNC1 pulse immediately following the current bus cycle. The sampling process within the current cycle has been completed before this pulse arrives, and the MCU is in a waiting state. When the rising edge of this pulse is detected, the MCU confirms that the bus communication window is open.
[0102] Specifically, after the MCU completes the slicing sampling, it will wait for the next 1ms bus cycle to arrive. That is, when the IO sampling and conditioning circuit completes sampling, the MCU will receive the next synchronization pulse signal. In the next bus communication window, the MCU will package all the buffered oversampled data in the standard format and upload it to the EtherCAT master station via ESC. The master station will then complete the data parsing and archiving.
[0103] Optionally, to avoid frame loss of sampled data, in another embodiment of this application, after determining that the IO sampling conditioning circuit has completed sampling and before receiving the next synchronization pulse signal, a method for storing the sampled data is also provided, such as... Figure 5 As shown, the specific steps include:
[0104] S501, Obtain the sampling time of all sampled data.
[0105] Specifically, the sampling time can be recorded directly by the count value of the timer interrupt or the system clock.
[0106] S502. Sort each sample data according to its sampling time.
[0107] It should be noted that since the timer interrupts are strictly equal in interval, the sampled data itself is generated in chronological order. However, in order to cope with possible out-of-order buffer writes or the dependence of subsequent processing on timing, the MCU still sorts the data according to the recorded timestamps to ensure that the packaging order is consistent with the sampling order.
[0108] S503. Store each sorted sample data into the buffer in sequence.
[0109] Optionally, the sorted data is written to a buffer one by one. This buffer can be the internal RAM of the MCU or an external dual-port memory, and the ESC chip can read data from the same buffer.
[0110] S206. Store the packaged data in the EtherCAT master station and use the next synchronization pulse signal as the current synchronization pulse signal.
[0111] It should be noted that "storing to the EtherCAT master station" actually refers to uploading the packaged data to the master station's process memory within the communication window via the ESC chip. The MCU does not write directly to the master station; instead, it places the data in the buffer module, and the ESC completes the transfer in DMA or bus transactions. Then, the next captured synchronization pulse signal is used as the new "current synchronization pulse signal," and the process returns to step S201, thus forming a cyclic control flow of "synchronization-sampling-buffering-upload," thereby achieving continuous and stable oversampling.
[0112] Optionally, in another embodiment of this application, after storing the packaged data in the EtherCAT master, the method further includes:
[0113] Clear all sampled data in the buffer.
[0114] Optionally, the clear operation can be achieved by the MCU resetting the write pointer of the buffer or by filling it with zero values, while resetting the current value of the sample count to zero.
[0115] This application provides a sampling method for an oversampling I / O module. The method involves acquiring the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station. In response to the current synchronization pulse signal, a timer in the EtherCAT slave station is started, and an interrupt operation is periodically performed on the timer. Whenever the timer is interrupted, the current input signal in the I / O sampling conditioning circuit is sampled to obtain sampled data, and the current value of the sampling count is incremented. Then, based on the current value of the sampling count and the fragmentation parameters, it is determined whether the I / O sampling conditioning circuit has completed sampling. If the I / O sampling conditioning circuit has completed sampling, the next synchronization pulse signal is received, and all sampled data is packaged within the communication window corresponding to the next synchronization pulse signal to obtain packaged data. Finally, the packaged data is stored in the EtherCAT master station, and the next synchronization pulse signal is used as the current synchronization pulse signal. The process then returns to acquire the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station. This allows for autonomous control of the sampling timing via timer interrupts. The sampling cycle is only started and stopped when the synchronization pulse arrives, and the data is uploaded uniformly after sampling is completed, avoiding synchronization deviations and accumulated errors caused by relying on distributed clocks and SYNC0 hardware pulses. This effectively solves the problem of frame loss of sampling data caused by clock jitter and bus load fluctuations, and improves the reliability and anti-interference capability of oversampling transmission.
[0116] Another embodiment of this application provides a sampling device for an oversampling I / O module, such as... Figure 6 As shown, it includes the following units:
[0117] The acquisition unit 601 is used to acquire the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station.
[0118] Interrupt unit 602 is used to start the timer in the EtherCAT slave station in response to the current synchronization pulse signal, and periodically perform interrupt operations on the timer.
[0119] The sampling unit 603 is used to sample the current input signal in the IO sampling conditioning circuit whenever the timer is interrupted, obtain the sampled data, and increment the current value of the sampling count by one.
[0120] The sampling judgment unit 604 is used to determine whether the IO sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters.
[0121] Packaging unit 605 is used to receive the next synchronization pulse signal when the IO sampling conditioning circuit has completed sampling, and to package all the sampled data in the communication window corresponding to the next synchronization pulse signal to obtain packaged data.
[0122] The data storage unit 606 is used to store the packaged data in the EtherCAT master station, use the next synchronization pulse signal as the current synchronization pulse signal, and return to execute the acquisition of the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station.
[0123] It should be noted that the specific working process of the above modules in the embodiments of this application can be referred to steps S201 to S206 in the above method embodiments, and will not be repeated here.
[0124] Optionally, in another embodiment of this application, an interrupt unit 602 in a sampling device for an oversampling I / O module includes:
[0125] The generation unit is used to generate multiple sub-cycles based on the sharding parameters.
[0126] The interrupt subunit is used to perform interrupt operations on the timer according to each sub-cycle.
[0127] Optionally, in another embodiment of this application, a sampling device for an oversampling I / O module includes a sampling determination unit 604, comprising:
[0128] The judgment unit is used to determine whether the current value of the sampling count is equal to the slice parameter.
[0129] The first determining unit is used to determine that the sampling of the IO sampling conditioning circuit is complete if the current value of the sampling count is equal to the slicing parameter.
[0130] The second determining unit is used to determine that the IO sampling conditioning circuit has not completed sampling if the current value of the sampling count is not equal to the slicing parameter.
[0131] Optionally, in another embodiment of this application, a sampling device for an oversampling I / O module further includes:
[0132] The execution unit is used to return to periodically perform interrupt operations on the timer if the IO sampling and conditioning circuit has not completed sampling.
[0133] Optionally, in another embodiment of this application, a sampling device for an oversampling I / O module further includes:
[0134] The time acquisition unit is used to acquire the sampling time of all sampled data.
[0135] The sorting unit is used to sort each sample data according to the sampling time of each sample data.
[0136] The storage unit is used to sequentially store each sorted sampled data into the cache area.
[0137] Optionally, in another embodiment of this application, a sampling device for an oversampling I / O module further includes:
[0138] The clear unit is used to clear all sampled data in the buffer.
[0139] It should be noted that the specific working process of each module provided in the above embodiments of this application can be referred to the corresponding steps in the above method embodiments, and will not be repeated here.
[0140] It should also be noted that the sampling device for an oversampling I / O module provided in this application has the technical effects of any of the above embodiments, and will not be described in detail here.
[0141] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0142] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method of oversampling an input / output (IO) module, comprising: Applied to oversampling I / O modules, including: Obtain the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station; In response to the current synchronization pulse signal, a timer in the EtherCAT slave station is started, and an interrupt operation is periodically performed on the timer; Whenever the timer is interrupted, the current input signal in the IO sampling and conditioning circuit is sampled to obtain sampled data, and the current value of the sampling count is incremented by one. Based on the current value of the sampling count and the slicing parameters, determine whether the IO sampling conditioning circuit has completed sampling; If the IO sampling and conditioning circuit completes sampling, it receives the next synchronization pulse signal and packages all the sampled data within the communication window corresponding to the next synchronization pulse signal to obtain packaged data. The packaged data is stored in the EtherCAT master station, and the next synchronization pulse signal is used as the current synchronization pulse signal. Then, the process of obtaining the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station is returned.
2. The method of claim 1, wherein, The periodic interrupt operation performed on the timer includes: Based on the sharding parameters, multiple sub-cycles are generated; An interrupt operation is performed on the timer according to each of the sub-cycles.
3. The method of claim 1, wherein, The step of determining whether the IO sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters includes: Determine whether the current value of the sampling count is equal to the fragmentation parameter; If the current value of the sampling count is equal to the slicing parameter, then the sampling of the IO sampling conditioning circuit is determined to be complete. If the current value of the sampling count is not equal to the slicing parameter, then it is determined that the IO sampling conditioning circuit has not completed sampling.
4. The method of claim 1, wherein, After determining whether the I / O sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters, the method further includes: If the IO sampling and conditioning circuit fails to complete sampling, it returns to the previous step of periodically interrupting the timer.
5. The method of claim 1, wherein, Before receiving the next synchronization pulse signal, the process also includes: Obtain the sampling time of all the sampled data; Sort each sample data according to its sampling time; Each sorted sampled data is stored sequentially in the buffer.
6. The method of claim 5, wherein, After storing the packaged data in the EtherCAT master station, the process further includes: Clear all sampled data in the buffer.
7. A sampling device of an oversampling IO module, characterized by include: The acquisition unit is used to acquire the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station; An interrupt unit is used to start a timer in the EtherCAT slave station in response to the current synchronization pulse signal, and periodically perform an interrupt operation on the timer; The sampling unit is used to sample the current input signal in the IO sampling conditioning circuit whenever the timer is interrupted, obtain the sampled data, and increment the current value of the sampling count by one. The sampling judgment unit is used to determine whether the IO sampling conditioning circuit has completed sampling based on the current value of the sampling count and the slicing parameters; The packaging unit is used to receive the next synchronization pulse signal when the IO sampling conditioning circuit has completed sampling, and to package all the sampled data in the communication window corresponding to the next synchronization pulse signal to obtain packaged data. The data storage unit is used to store the packaged data in the EtherCAT master station, use the next synchronization pulse signal as the current synchronization pulse signal, and return to execute the process of obtaining the current synchronization pulse signal and fragmentation parameters sent by the EtherCAT master station.
8. The apparatus of claim 7, wherein, The interrupt unit includes: The generation unit is used to generate multiple sub-cycles based on the sharding parameters; An interrupt subunit is used to perform an interrupt operation on the timer according to each of the sub-cycles.
9. The apparatus of claim 7, wherein, The sampling judgment unit includes: A judgment unit is used to determine whether the current value of the sampling count is equal to the fragmentation parameter; The first determining unit is configured to determine that the sampling of the IO sampling conditioning circuit is complete if the current value of the sampling count is equal to the slicing parameter. The second determining unit is used to determine that the IO sampling conditioning circuit has not completed sampling if the current value of the sampling count is not equal to the slicing parameter.
10. An oversampling IO module characterized by, The oversampling I / O module includes: a sampling module, an MCU microcontroller module, an ESC chip, and a cache module; The MCU microcontroller module is connected to the ESC chip and the sampling module respectively; The cache module is connected to the MCU microcontroller module and the ESC chip respectively; The MCU microcontroller module acquires the current synchronization pulse signal sent by the EtherCAT master station, and starts a timer in response to the current synchronization pulse signal. Whenever the timer interrupt is triggered, it samples the current input signal in the IO sampling and conditioning circuit to obtain sampled data. After sampling is completed, it waits for the next synchronization pulse signal so that all the sampled data is packaged and uploaded to the EtherCAT master station within the communication window corresponding to the next synchronization pulse signal.