Deep N-well driven ramp buffer

Abstract

This disclosure relates to a deep N-well driven ramp buffer. A partial ramp buffer includes: a deep N-well layer disposed in a P-substrate below a surface therein; a P-well disposed between the surface of the P-substrate and the deep N-well layer; and an N-well structure disposed in the P-substrate and coupled to the deep N-well layer. The N-well structure is disposed between the surface of the P-substrate and the deep N-well layer. The P-well is disposed within an opening in the N-well structure. The N-well structure and the deep N-well layer are configured to isolate the P-well within the opening. A source follower transistor is disposed in the P-well. The source follower transistor includes a gate terminal coupled to the N-well structure and a ramp generator.

Description

[0001] Information related to divisional application This case is a divisional application. The parent application of this divisional application is the invention patent application filed on January 31, 2024, with application number 202410142570.8 and invention title "Deep N-well Driven Inclined Wave Buffer". Technical Field

[0002] This disclosure generally relates to image sensors, and specifically, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. Background Technology

[0003] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and so on in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition and processing. The technologies used to manufacture image sensors continue to advance rapidly. For example, the demand for higher resolution and lower power consumption has spurred further miniaturization and integration of these devices.

[0004] A typical image sensor operates in response to image light incident on it from an external scene. The image sensor includes an array of pixels with photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and immediately generate an image charge upon absorption. The image charge generated by the pixel light can be measured as an analog output image signal on a bit line, which varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and this image charge is read out from the bit line as an analog image signal and converted into a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit line is coupled to a readout circuit that includes an input stage with an analog-to-digital converter (ADC) circuitry to convert those analog image signals from the pixel array into digital image signals. Summary of the Invention

[0005] In one aspect, this disclosure provides a local ramp buffer comprising: a deep N-well layer disposed in a P-substrate below a surface thereon; a P-well disposed between the surface of the P-substrate and the deep N-well layer; an N-well structure disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed within an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the P-substrate and the deep N-well layer; and a source follower transistor disposed in the P-well, wherein the source follower transistor includes a gate terminal coupled to the N-well structure and a ramp generator.

[0006] In another aspect, this disclosure provides a method for fabricating a plurality of local ramp buffers, comprising: disposing a deep N-well layer in a P-substrate below a surface thereon; disposing an N-well structure having a plurality of openings in the P-substrate and between the surface of the P-substrate and the deep N-well layer; coupling the N-well structure to the deep N-well layer; disposing a plurality of P-wells within the plurality of openings in the N-well structure, wherein the N-well structure and the deep N-well layer are configured to isolate each of the plurality of P-wells within the plurality of openings in the N-well structure between the surface of the P-substrate and the deep N-well layer, and wherein each of the plurality of P-wells corresponds to one of the plurality of local ramp buffers; and disposing a plurality of source follower transistors in the plurality of P-wells, wherein each of the plurality of source follower transistors includes a gate terminal coupled to the N-well structure and a ramp generator.

[0007] In another aspect, this disclosure provides a local ramp buffer comprising: a deep N-well layer disposed in a P-substrate below a surface therein; a P-well disposed between the surface of the P-substrate and the deep N-well layer; and an N-well structure disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed within an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-substrate. The P-well within the opening of the N-well structure between the surface and the deep N-well layer; and a source follower transistor disposed in the P-well, wherein the source follower transistor includes an N+ doped region in the P-well to provide a source terminal of the source follower transistor, and includes a P+ doped region in the P-well to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and configured to provide an output node of the local ramp buffer, and wherein the source terminal and the body terminal are coupled to the N-well structure. Attached Figure Description

[0009] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following figures, wherein similar reference numerals refer to similar parts unless otherwise specified.

[0010] Figure 1 The illustration shows an example of an imaging system comprising a pixel array according to the teachings of this disclosure.

[0011] Figure 2 The diagram illustrates a portion of a readout circuit including a local ramp buffer, according to the teachings of this disclosure.

[0012] Figure 3A and 3B The diagrams and cross-sections illustrate an example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure.

[0013] Figure 4A and 4B A schematic diagram and cross-section of another example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure are illustrated respectively.

[0014] Figure 5A and 5B The diagrams and cross-sections illustrate yet another example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure.

[0015] Figure 6The diagram illustrates a top view layout of an example of multiple local ramp buffers included in the same readout circuit according to the teachings of this disclosure.

[0016] Figure 7A and 7B The top view layout and cross-section of another example of multiple local ramp buffers included in the same readout circuit according to the teachings of this disclosure are illustrated separately.

[0017] Several views throughout the diagrams correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of this disclosure, some elements in the figures may be enlarged relative to other elements. Additionally, common and well-known elements that are not typically depicted in commercially viable embodiments are shown to facilitate a less obstructed view of these various embodiments of this disclosure. Detailed Implementation

[0018] Examples of imaging systems with local ramp buffers in the pixel unit readout circuitry are disclosed, which provide improved power supply rejection ratio (PSRR) and reduced lateral layout size. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring specific aspects.

[0019] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one instance of this disclosure. Therefore, the appearance of the phrase "in an example" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0020] For ease of description, spatially related terms (e.g., "below," "under," "above," "underneath," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein to describe the relationship of one element or feature to another element(s), as illustrated in the figures. It will be understood that, in addition to the orientations depicted in the figures, these spatially related terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figures is rotated or flipped, an element described as "below," "under," or "beneath" of other elements or features will then be oriented "above" of those elements or features. Thus, the exemplary terms "below" and "underneath" may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially related descriptions used herein will be interpreted accordingly. Furthermore, it will be understood that when an element is described as being "between" two other elements, it may be the only element between those two other elements, or there may be one or more intervening elements.

[0021] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that component names and symbols are used interchangeably in this document (e.g., Si and silicon); however, they have the same meaning.

[0022] As discussed below, various examples of imaging systems involving local ramp buffers in the pixel unit readout circuitry are disclosed, which provide improved power supply rejection ratio (PSRR) and reduced lateral layout size. PSRR is a measure of a circuit's ability to suppress changes in the supply voltage. It is a ratio, typically measured in decibels (dB), that compares the amplitude of the circuit's output signal to the amplitude of a disturbance in the supply voltage. In various examples, the gate terminal of a source follower transistor housed in a P-well is coupled to an N-well structure and a global ramp generator. In other examples, the source terminal of a source follower transistor housed in a P-well is coupled to an N-well structure and an output node.

[0023] Local ramp buffers with improved power supply rejection ratio (PSRR) performance and smaller lateral layout size offer several advantages. Note that the AC coupling path from the power line to the output node caused by parasitic diodes can degrade PSRR performance. In various examples, according to the teachings of this disclosure, local ramp buffers without an AC coupling path from the power line to the output node provide improved PSRR performance and a reduced lateral layout size.

[0024] In various embodiments of this disclosure, the local ramp buffer includes a deep N-well layer disposed below the surface of a P-substrate in the P-substrate, a P-well disposed between the surface of the P-substrate and the deep N-well layer, and an N-well structure disposed in the P-substrate and coupled to the deep N-well layer. The N-well structure is disposed between the surface of the P-substrate and the deep N-well layer. The P-well is disposed within an opening in the N-well structure. The N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the P-substrate and the deep N-well layer. A source follower transistor is disposed in the P-well. The source follower transistor includes a gate terminal coupled to the N-well structure and the global ramp generator. In other embodiments, the source follower transistor includes a source terminal that can be coupled to the N-well structure.

[0025] For illustration purposes, Figure 1 An example of an imaging system 100 with readout circuitry 106 according to the teachings of this disclosure is shown. Specifically, Figure 1 The illustration depicts an imaging system 100 comprising a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to reproduce images of people, places, objects, etc.

[0026] In various instances, the readout circuit 106 may be configured to read out the image signal via the column bit line 112. As will be discussed, in various instances, the readout circuit 106 may include an analog-to-digital converter (ADC) according to the teachings of this disclosure. In an example, the digital image data value generated by the ADC in the readout circuit 106 may then be received by functional logic 108. The functional logic 108 may simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or otherwise).

[0027] In one example, control circuitry 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuitry 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with illumination effects such as flash.

[0028] In one example, imaging system 100 may be included in a digital, mobile phone, laptop computer, endoscope, security camera, or imaging device for automobiles. Additionally, imaging system 100 may be coupled to other hardware components, such as processors (general purpose or other), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), lighting / flash, electrical inputs (keyboards, touch displays, tracking pads, mice, microphones, etc.), and / or displays. These other hardware components can deliver instructions to imaging system 100, retrieve image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0029] Figure 2 The diagram illustrates an example of a readout circuit incorporating a partial ramp buffer according to the teachings of this disclosure. It should be understood that... Figure 2 The readout circuit 206 can be included in, for example Figure 1 The example shown is the readout circuit 106 in the imaging system 100, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0030] The readout circuit 206 includes a plurality of column circuits 218 coupled to the global ramp generator 214. In various embodiments, each column circuit 218 corresponds to a column of pixels in the pixel array 202. Each column circuit 218 includes a comparator 216 having a first input coupled to the pixel array 202 via a bit line 212 and a second input coupled to the global ramp generator 214 via a local ramp buffer 220. Each comparator 216 outputs an output signal to a counter 222 included in each column circuit 218.

[0031] In operation, a global ramp generator 214 generates a ramp signal for single-ramp analog-to-digital conversion (ADC). Each of the comparators 216 generates a corresponding comparator output in response to a comparison of a corresponding analog image data signal received via a corresponding bit line 212 with the ramp signal. When the two signals are equal, the comparator 216 changes its output to a counter 222, which then changes its counting code over time and stores the value as the output signal from the comparator 216 changes, such that the stored code is correlated with the signal from the pixel array 202. A local ramp buffer 220 is configured to smooth any fluctuations in the ramp signal, ensuring that the signal is read out at a consistent rate, allowing the ADC to operate at its own speed without hindering the rest of the system, and facilitating image processing.

[0032] Figure 3A and 3B Schematic diagrams and cross-sections of an example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure are provided. It should be understood that... Figure 3Aand 3B The local ramp buffer 320 can be included in, for example Figure 2 The example shown is the local ramp buffer 220 in the readout circuit 206, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0033] refer to Figure 3A and 3B Both, the local ramp buffer 320 includes a deep N-well layer 344 disposed below the surface 370 of the P-substrate 348 in the P-substrate 348, a P-well 346 disposed between the surface 370 of the P-substrate 348 and the deep N-well layer 344, and an N-well structure 342 disposed in the P-substrate 348 and coupled to the deep N-well layer 344. The N-well structure 342 is disposed between the surface 370 of the P-substrate 348 and the deep N-well layer 344. The P-well 346 is disposed inside an opening 372 in the N-well structure 342. The N-well structure 342 and the deep N-well layer 344 are configured to isolate the P-well 346 within the opening 372 in the N-well structure 342 between the surface 370 of the P-substrate 348 and the deep N-well layer 344.

[0034] The local ramp buffer 320 also includes a source follower transistor 330 disposed in a P-well 346 and coupled between the power line AVDD 324 and ground. The source follower transistor 330 includes a gate terminal 334 coupled to the global ramp generator Vramp 314, a first N+ doped region in the P-well 346 adjacent to the gate terminal 334 (which provides a drain terminal 332 coupled to AVDD 324), a second N+ doped region in the P-well 346 adjacent to the gate terminal 334 (which provides a source terminal 336), and a first P+ doped region in the P-well 346 providing a body terminal 338, the body terminal being coupled to the source terminal 336 and configured to provide the output node VOUT 360 of the local ramp buffer 320.

[0035] A first diode 326 is formed at a first interface between the N-well structure 342 and the P-well 346. The anode of the first diode 326 is coupled to the output node VOUT 360, the body terminal 338, and the source terminal 336. In the depicted example, the cathode of the first diode 326, and therefore the N-well structure 342, is coupled to AVDD 324 via connection 340. A second diode 328 is formed at a second interface between the N-well structure 342 and the P-substrate 348. The anode of the second diode 328 is coupled to ground through a second P+ doped region in the P-substrate 348. The cathode of the second diode 328 is coupled to AVDD 324 via connection 340.

[0036] The local ramp buffer 320 further includes a current source 350 coupled between the output node VOUT 360 and ground. In the illustrated example, the current source 350 includes a first transistor 356 with its gate terminal coupled to receive a current source bias voltage, a cascode transistor 352 with its gate terminal coupled to receive a cascode bias voltage, and a second transistor 354 configured to be turned on and off in response to a control signal. In various other examples, it should be understood that the current source 350 may have different components and configurations (e.g., fewer or more transistors, switches).

[0037] In the depicted example, the AC coupling path between AVDD 324 and output node VOUT 360 is due to the first diode 326 acting as a parasitic diode. Therefore, in various examples, the local ramp buffer 320 exhibits relatively poor power supply rejection ratio (PSRR) performance (e.g., -26 dB PSRR in the case of AVDD 324 with a 2 MHz AC component).

[0038] Figure 4A and 4B Schematic diagrams and cross-sections of another example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure are illustrated respectively. It should be understood that... Figure 4A and 4B The local ramp buffer 420 can be included in, for example Figure 2 The example shown is the local ramp buffer 220 in the readout circuit 206, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0039] refer to Figure 4A and Figure 4B Both, the local ramp buffer 420 includes a deep N-well layer 444 disposed below the surface 470 of the P-substrate 448 in the P-substrate 448, a P-well 446 disposed between the surface 470 of the P-substrate 448 and the deep N-well layer 444, and an N-well structure 442 disposed in the P-substrate 448 and coupled to the deep N-well layer 444. The N-well structure 442 is disposed between the surface 470 of the P-substrate 448 and the deep N-well layer 444. The P-well 446 is disposed inside an opening 472 in the N-well structure 442. The N-well structure 442 and the deep N-well layer 444 are configured to isolate the P-well 446 within the opening 472 in the N-well structure 442 between the surface 470 of the P-substrate 448 and the deep N-well layer 444.

[0040] The local ramp buffer 420 also includes a source follower transistor 430 disposed in a P-well 446 and coupled between the power line AVDD 424 and ground. The source follower transistor 430 includes a gate terminal 434 coupled to the global ramp generator Vramp 414, a first N+ doped region in the P-well 446 adjacent to the gate terminal 434 (which provides a drain terminal 432 coupled to AVDD 424), a second N+ doped region in the P-well 446 adjacent to the gate terminal 434 (which provides a source terminal 436), and a first P+ doped region in the P-well 446 providing a body terminal 438, which is coupled to the source terminal 436 and configured to provide the output node VOUT 460 of the local ramp buffer 420.

[0041] A first diode 426 is formed at a first interface between the N-well structure 442 and the P-well 446. The anode of the first diode 426 is coupled to the output node VOUT 460, the body terminal 438, and the source terminal 436. In the depicted example, the cathode of the first diode 426, and therefore the N-well structure 442, is also coupled to the output node VOUT 460, the body terminal 438, and the source terminal 436 via connection 440. A second diode 428 is formed at a second interface between the N-well structure 442 and the P-substrate 448. The anode of the second diode 428 is coupled to ground through a second P+ doped region in the P-substrate 448. The cathode of the second diode 428 is coupled to the output node VOUT 460, the body terminal 438, and the source terminal 436 via connection 440.

[0042] The local ramp buffer 420 further includes a current source 450 coupled between the output node VOUT 460 and ground. In the illustrated example, the current source 450 includes a first transistor 456 with its gate terminal coupled to receive a current source bias voltage, a cascode transistor 452 with its gate terminal coupled to receive a cascode bias voltage, and a second transistor 454 configured to be turned on and off in response to a control signal. It should be understood that the current source 450 may have different components and configurations (e.g., fewer or more transistors, switches).

[0043] and Figure 3A and 3B The local ramp buffer 320 illustrated in the diagram is different. Figure 4A and 4BThe local ramp buffer 420 illustrated herein does not contain an AC coupling path between AVDD 424 and the output node VOUT 460 caused by parasitic diodes. Therefore, in various instances, the local ramp buffer 420 exhibits relatively high power supply rejection ratio (PSRR) performance (e.g., -35.2 dB PSRR with a 2 MHz AC component in AVDD 424). However, since the output node VOUT 460 is coupled to the N-well structure 442, each local ramp buffer 420 requires its own local N-well structure 442, which is isolated or decoupled from the output nodes of other local ramp buffers. In various instances, it should be understood that the readout circuitry of an imaging system may contain thousands of local ramp buffers, meaning that using a local ramp buffer 420 with an output node VOUT 460 coupled to the N-well structure 442 as shown may require thousands of separate or isolated N-well structures 442 and deep N-well layers 444. This can result in an undesirable large lateral layout size.

[0044] Figure 5A and 5B Schematic diagrams and cross-sections of yet another example of a local ramp buffer with a source follower transistor according to the teachings of this disclosure are illustrated. It should be understood that... Figure 5A and 5B The local ramp buffer 520 can be included in, for example Figure 2 The example shown is the local ramp buffer 220 in the readout circuit 206, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0045] refer to Figure 5A and 5B Both, the local ramp buffer 520 includes a deep N-well layer 544 disposed below the surface 570 of the P-substrate 548 in the P-substrate 548, a P-well 546 disposed between the surface 570 of the P-substrate 548 and the deep N-well layer 544, and an N-well structure 542 disposed in the P-substrate 548 and coupled to the deep N-well layer 544. The N-well structure 542 is disposed between the surface 570 of the P-substrate 548 and the deep N-well layer 544. The P-well 546 is disposed inside an opening 572 in the N-well structure 542. The N-well structure 542 and the deep N-well layer 544 are configured to isolate the P-well 546 within the opening 572 in the N-well structure 542 between the surface 570 of the P-substrate 548 and the deep N-well layer 544.

[0046] The local ramp buffer 520 also includes a source follower transistor 530 disposed in a P-well 546 and coupled between the power line AVDD 524 and ground. The source follower transistor 530 includes a gate terminal 534 coupled to the global ramp generator Vramp 514, a first N+ doped region in the P-well 546 adjacent to the gate terminal 534 (which provides a drain terminal 532 coupled to AVDD 524), a second N+ doped region in the P-well 546 adjacent to the gate terminal 534 (which provides a source terminal 536), and a first P+ doped region in the P-well 546 providing a body terminal 538, which is coupled to the source terminal 536 and configured to provide the output node VOUT 560 of the local ramp buffer 520.

[0047] A first diode 526 is formed at a first interface between the N-well structure 542 and the P-well 546. The anode of the first diode 526 is coupled to the output node VOUT 560, the body terminal 538, and the source terminal 536. In the depicted example, the cathode of the first diode 526, and therefore the N-well structure 542, is coupled to the gate terminal 534 and the global ramp generator Vramp 514 via connection 540. A second diode 528 is formed at a second interface between the N-well structure 542 and the P-substrate 548. The anode of the second diode 528 is coupled to ground through a second P+ doped region in the P-substrate 548. The cathode of the second diode 528 is coupled to the gate terminal 534 and the global ramp generator Vramp 514 via connection 540.

[0048] The local ramp buffer 520 further includes a current source 550 coupled between the output node VOUT 560 and ground. In the illustrated example, the current source 550 includes a first transistor 556 with its gate terminal coupled to receive a current source bias voltage, a cascode transistor 552 with its gate terminal coupled to receive a cascode bias voltage, and a second transistor 554 configured to be turned on and off in response to a control signal. It should be understood that the current source 550 may have different components and configurations (e.g., fewer or more transistors, switches).

[0049] as Figure 4A and 4B The partial ramp buffer 420 illustrated in the figure is... Figure 5A and 5BThe local ramp buffer 520 illustrated herein does not contain an AC coupling path between AVDD 524 and the output node VOUT 560 caused by parasitic diodes. Therefore, in various embodiments, the local ramp buffer 520 exhibits relatively high power supply rejection ratio (PSRR) performance (e.g., -35.5 dB PSRR with a 2 MHz AC component in AVDD 524). Furthermore, since the N-well structure 542 is coupled to the gate terminal 534 and the global ramp generator Vramp 514 rather than the local output node VOUT 560, the N-well structure 542 can be shared with other local ramp buffers according to the teachings of this disclosure.

[0050] Figure 6 The diagram illustrates a top view layout of an example of multiple local ramp buffers included in the same readout circuit according to the teachings of this disclosure. It should be understood that... Figure 6 Each local ramp buffer 620 can be included in, for example Figure 2 The local ramp buffer 220 and / or in the readout circuit 206 shown herein Figure 4A and 4B The example of the local ramp buffer 420 shown in the text, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0051] It should be understood that each of the output nodes of the local ramp buffer 620 is isolated or separate from each other. Thus, the local ramp buffer 620 cannot share the N-well structure 642 (e.g., for the reasons stated above regarding...). Figure 4A and 4B The reason for the partial ramp buffer 420 illustrated in the diagram is as follows. When fabricating the partial ramp buffer 620, each P-well 646 is disposed inside the opening 672 in each N-well structure 642 and between the surface of the P-substrate 648 and each deep N-well layer 644 (illustrated with dashed lines to show that the deep N-well layer 644 is located below both the P-well 646 and the N-well structure 642). When the partial ramp buffer 620 is arranged laterally, as... Figure 6 As illustrated in the diagram, each P-well 646 has a dimension P in the lateral direction. Each N-well structure 642 has a dimension W on both sides of the P-well 646 in the lateral direction. Each N-well structure 642 is separated from its adjacent N-well structure 642 by a dimension S. Assuming there are n local ramp buffers, and ignoring the portion of the N-well structure 642 at either end, the total width (i.e., the total dimension along the lateral direction) is equal to P. n + (2W+S) (n-1).

[0052] Figure 7A and7B The diagrams illustrate a top view layout and a cross-section along the dashed line A-A' of another example of multiple local ramp buffers in the same readout circuit according to the teachings of this disclosure. It should be understood that... Figure 7A and 7B Each local ramp buffer 720 can be included in, for example Figure 2 The local ramp buffer 220 and / or in the readout circuit 206 shown herein Figure 5A and 5B The example of the local ramp buffer 520 shown in the text, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0053] In the depicted example, it should be understood that each of the gate terminals of the source follower transistors of the local ramp buffer 720 is coupled to the global ramp generator and thus can share the N-well structure 742 (e.g., for the purposes of the above description). Figure 5A and 5B (The reasons discussed in the illustration of the local ramp buffer 520). When fabricating the local ramp buffer 720, each of the plurality of P-wells 746 is disposed within a corresponding opening of the plurality of openings 772 in the shared N-well structure 742, and is located between the surface of the P-substrate 748 and the shared deep N-well layer 744 (illustrated with dashed lines to show that the shared deep N-well layer 744 is located below the plurality of P-wells 746 and the shared N-well structure 742). When the local ramp buffer 720 is arranged laterally, as... Figure 7A and 7B As illustrated in the diagram, each of the plurality of P-wells 746 has a dimension P in the lateral arrangement direction. Adjacent P-wells 746 are separated by a dimension W in the lateral arrangement direction by a portion of a shared N-well structure 742. Assuming the existence of n local ramp buffers, ignoring the portion of the shared N-well structure 742 at either end, the total width (i.e., the total dimension along the lateral arrangement direction) is equal to P. n + W (n-1).

[0054] Therefore, Figure 7A and 7B The examples illustrated in the diagrams are as follows Figure 6 Compared to the examples illustrated in the diagram, the total width is reduced [P] n + (2W+S) [(n-1)] - [P] n + W [(n-1)] = (W+S) (n-1), and the area reduction rate is [(W+S)]. (n-1)] / [P n + (2W+S) (n-1)]. This reduction in lateral layout size has the advantage of lowering the total cost associated with the die size. In one example, the readout circuit has 512 local ramp buffers (i.e., n = 512), P = 4.8 μm, W = 0.8 μm, and S = 2.4 μm, so the area reduction rate will be approximately 36%. It should be understood that the parameters n, P, W, and S can have different values ​​and the area reduction rate can vary accordingly.

[0055] The above description of the illustrated examples of this disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit the disclosure to its precise form. Although specific examples of the disclosure have been described herein for illustrative purposes, various modifications will be recognized by those skilled in the art within the scope of this disclosure.

[0056] These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific instances disclosed in this specification. Rather, the scope of this disclosure will be determined entirely by the appended claims, which will be interpreted in accordance with the established principles of claim interpretation.

Claims

1. A local ramp buffer, comprising: A deep N-well layer is disposed in the P-substrate below the surface of the P-substrate; A P-well is disposed between the surface of the P-substrate and the deep N-well layer; An N-well structure is disposed in the P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the P-substrate and the deep N-well layer, wherein the P-well is disposed inside an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the P-substrate and the deep N-well layer. and A source follower transistor disposed in the P-well, wherein the source follower transistor includes an N+ doped region in the P-well to provide a source terminal of the source follower transistor, and includes a P+ doped region in the P-well to provide a body terminal of the source follower transistor, wherein the source terminal is coupled to the body terminal and configured to provide an output node of the local ramp buffer, and wherein the source terminal and the body terminal are coupled to the N-well structure.

2. The local ramp buffer according to claim 1, wherein the N+ doped region is a first N+ doped region, and wherein the source follower transistor further comprises: A gate terminal, which is close to the source terminal and coupled to the ramp generator; and A second N+ doped region is located in the P-well, close to the gate terminal, to provide the drain terminal of the source follower transistor, wherein the drain terminal is coupled to the power line.

3. The local ramp buffer of claim 1, wherein a diode is formed at the interface between the N-well structure and the P-substrate, wherein the anode of the diode is coupled to ground through the P-substrate, and wherein the cathode of the diode is coupled to the body terminal and the source terminal of the source follower transistor.

4. The local ramp buffer of claim 1, wherein the local ramp buffer is one of a plurality of local ramp buffers, each of the local ramp buffers comprising a corresponding (i) deep N-well layer, (ii) P-well, (iii) N-well and (iv) source follower, wherein the deep N-well layer of each of the local ramp buffers is disposed in the P-substrate.

5. The local ramp buffer according to claim 4, wherein the (i) deep N-well layer, (ii) P-well, (iii) N-well and (iv) source follower of each of the local ramp buffers are isolated from each other by the P-substrate.

6. The local ramp buffer according to claim 1, further comprising a current source coupled between the output node of the local ramp buffer and ground.

7. The local ramp buffer according to claim 6, wherein the current source comprises: A first transistor has a gate terminal coupled to receive a current source bias voltage; and A common-source cascode transistor coupled to the first transistor, wherein the gate of the common-source cascode transistor is coupled to receive a common-source cascode bias voltage. The first transistor and the common-source common-gate transistor are coupled between the output node of the local ramp buffer and ground.

8. The local ramp buffer of claim 7, wherein the current source further includes a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.

9. A method for fabricating multiple local ramp buffers, the method comprising: A deep N-well layer is disposed in the P-substrate below the surface of the P-substrate; A plurality of N-well structures are disposed in the P-substrate and between the surface of the P-substrate and the deep N-well layer, wherein each of the N-well structures defines an opening; Couple the N-well structure to the deep N-well layer; A plurality of P-wells are disposed within the openings of the respective N-well structures in the N-well structure, wherein the deep N-well layer and the N-well structure are configured to isolate each of the P-wells within the openings of the respective N-well structures between the surface of the P-substrate and the deep N-well layer, and wherein each of the P-wells corresponds to one of the plurality of local ramp buffers. and Multiple source follower transistors are disposed in corresponding P-wells in the P-well, wherein the source terminal and body terminal of each of the source follower transistors are coupled together, (ii) configured to provide the output node of the corresponding local ramp buffer, and (iii) coupled to the corresponding N-well structure.

10. The method of claim 9, wherein each of the source follower transistors includes an N+ doped region in a respective P-well to provide the source terminal of the source follower transistor, and includes a P+ doped region in a respective P-well to provide the body terminal of the source follower transistor.

11. The method of claim 10, wherein the N+ doped region is a first N+ doped region, and each of the source follower transistors comprises: A gate terminal, which is close to the source terminal and coupled to the ramp generator; and A second N+ doped region is located in the P-well, close to the gate terminal, to provide the drain terminal of the source follower transistor, wherein the drain terminal is coupled to the power line.

12. The method of claim 9, further comprising coupling a plurality of current sources between the output node of a respective local ramp buffer and ground in the local ramp buffer.

13. The method of claim 12, wherein each of the current sources comprises: A first transistor has a gate terminal coupled to receive a current source bias voltage; and A common-source cascode transistor coupled to the first transistor, wherein the gate of the common-source cascode transistor is coupled to receive a common-source cascode bias voltage. The first transistor and the common-source common-gate transistor are coupled between the output node of the local ramp buffer and ground.

14. The method of claim 13, wherein each of the current sources further includes a second transistor coupled to the first transistor and the cascode transistor, wherein the first transistor, the second transistor and the cascode transistor are coupled between the output node and ground, and wherein the second transistor is configured to be turned on and off in response to a control signal.

15. The method of claim 9, wherein, For each of the local ramp buffers: The diode is formed at the interface between the N-well structure and the P-substrate. The anode of the diode is coupled to ground through the P-substrate, and The cathode of the diode is coupled to the body terminal and the source terminal of the source follower transistor.

16. A readout circuit, comprising: Multiple column circuits, each of which includes one of a plurality of local ramp buffers, each of the local ramp buffers comprising: A deep N-well layer is disposed in the shared P-substrate below the surface of the shared P-substrate; A P-well is disposed between the surface of the shared P-substrate and the deep N-well layer; An N-well structure is disposed in the shared P-substrate and coupled to the deep N-well layer, wherein the N-well structure is disposed between the surface of the shared P-substrate and the deep N-well layer, wherein the P-well is disposed inside an opening in the N-well structure, and wherein the N-well structure and the deep N-well layer are configured to isolate the P-well within the opening in the N-well structure between the surface of the shared P-substrate and the deep N-well layer. and A source follower transistor disposed in the P-well and having a source terminal and a body terminal, wherein the source terminal is coupled together with the body terminal (i), (ii) configured to provide the output node of the local ramp buffer, and (iii) coupled to the N-well structure.

17. The readout circuit of claim 16, wherein each source follower transistor includes an N+ doped region in the P-well to provide the source terminal of the source follower transistor, and includes a P+ doped region in the P-well to provide the body terminal of the source follower transistor.

18. The readout circuit according to claim 16, wherein: The plurality of local ramp buffers comprises n local ramp buffers arranged laterally. Each P-well has a lateral dimension P and is laterally centered relative to the corresponding N-well structure. Each N-well has a lateral dimension W on both sides of the corresponding P-well. Adjacent N-wells are spaced apart by a lateral dimension S, and The first and last ones in the local ramp buffer define the lateral dimension of S(n-1)+(2W+P)*n.

19. The readout circuit of claim 16, wherein each of the column circuits further comprises one of a plurality of comparators, wherein each of the comparators comprises a first input coupled to the pixel array and a second input coupled to the output node of a corresponding local ramp buffer.

20. The readout circuit of claim 16, further comprising a global ramp generator operatively coupled to the gate terminal of each of the local ramp buffers.

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