A radio frequency chip low-power consumption data processing and optimization method and system

Abstract

This invention relates to the field of electronic digital data processing technology. It discloses a low-power data processing and optimization method and system for radio frequency (RF) chips. The method includes: adaptive segmentation and feature extraction of the input data stream; dynamic adjustment of the sampling rate based on information entropy; probabilistic sparsification preprocessing based on the sampling rate and data features to reduce the data volume; hierarchical sleep scheduling of processing units according to the processing queue status; and closed-loop optimization of parameters in each step by monitoring energy efficiency and bit error rate. This invention effectively solves the problem of low energy efficiency caused by static and isolated power control strategies in continuous data transmission of existing RF chips through data feature perception, cross-layer collaboration between acquisition, processing, and power consumption, and adaptive closed-loop optimization. It can significantly reduce chip operating power consumption, extend device battery life, and improve the system's adaptability to dynamic environments.

Description

Technical Field

[0001] This invention relates to the field of electronic digital data processing technology, and in particular to a low-power data processing and optimization method and system for radio frequency chips. Background Technology

[0002] Radio frequency (RF) chips, as core components of wireless communication, are widely used in all aspects of modern society's production and daily life. Their low-power performance directly determines the battery life and user experience of terminal devices.

[0003] In the consumer electronics field, devices such as smartphones, smartwatches, and wireless headphones heavily rely on radio frequency (RF) connections like Bluetooth and Wi-Fi for continuous data synchronization, audio streaming, and internet access. Users expect these devices to have "all-day" battery life, which places extreme demands on the power consumption of RF chips during continuous data transmission. For example, when a smartwatch is monitoring heart rate and syncing data to a phone in real time, its internal Bluetooth RF chip is in a continuous working state, and power consumption is a key factor affecting whether it can last for more than a week.

[0004] In the Internet of Things (IoT) field, hundreds of millions of sensor nodes are deployed in scenarios such as environmental monitoring, smart agriculture, industrial automation, and smart homes. These nodes are typically battery-powered, and the batteries are difficult to replace after deployment. They need to periodically collect data such as temperature, humidity, and light intensity, and transmit the data to a gateway via radio frequency (RF) links (such as LoRa, Zigbee, and NB-IoT). RF communication power consumption accounts for the vast majority of the total power consumption of these nodes. For example, a soil moisture sensor deployed in the field may send data every few minutes; the power consumption of its RF chip directly determines whether it can continue to operate for several years.

[0005] In the healthcare field, implantable or wearable medical devices, such as continuous glucose monitors and pacemaker data telemetry modules, need to transmit vital sign data securely and reliably to external receivers with extremely low power consumption. The device's battery life is not only crucial for convenience but also for patient safety, placing extremely stringent requirements on the energy efficiency of radio frequency chips.

[0006] In the industrial and automotive sectors, wireless sensor networks are used for equipment status monitoring and V2X (vehicle-to-everything) communication in autonomous vehicles. These applications have high requirements for real-time and reliability of communication, and the equipment is often in harsh or unattended environments for extended periods, with strict limitations on power consumption and heat dissipation.

[0007] In summary, low-power operation of radio frequency chips is a core technological challenge for extending the battery life of various wireless terminal devices, reducing maintenance costs, and improving system reliability and user experience.

[0008] Although low-power design has always been a focus in the field of RF chips, the following technical challenges still exist in continuous data transmission scenarios:

[0009] The first technical problem is the mismatch between static power consumption strategies and dynamic data streams. Existing technologies often employ fixed low-power strategies, such as fixed reduction of sampling rate and fixed periodic sleep. However, data streams in actual communication are highly dynamic, such as silent periods in voice calls, I / P / B frame differences in video streams, and event-triggered bursts in sensor data. Fixed strategies may lead to insufficient performance (such as increased bit error rate) during active data periods, while there is insufficient optimization during silent data periods, making it impossible to achieve "power supply on demand".

[0010] The second technical problem is that power consumption optimization in each link of the data processing chain is isolated. Traditional optimization often considers the power consumption of the RF front-end, ADC, or DSP in isolation. For example, the ADC may use oversampling and then filter and reduce noise by the DSP, which leads to a disconnect between the power consumption of the front-end acquisition and the power consumption of the back-end processing. The data acquisition rate, the characteristics of the data itself and the complexity of subsequent processing are not considered in conjunction at the system level, resulting in the problem of "saving power in one place but wasting power in another".

[0011] The third technical problem is the lack of a fine-grained, adaptive computational load reduction mechanism. After the data has entered the digital processing channel, existing methods mainly save power by reducing the operating voltage / frequency (DVFS). However, this is a "coarse" global adjustment that fails to address the redundancy characteristics of the data itself. For many applications, there is a large amount of redundant or low-value information in the continuously acquired data. Performing complex full-process calculations (such as demodulation, decoding, and filtering) on ​​this information results in a large amount of unnecessary energy waste.

[0012] The fourth technical problem is the lack of closed-loop energy efficiency feedback. Most low-power solutions use open-loop control, and once the parameters are set, they remain fixed and cannot adapt to changes in channel conditions, data modes, and battery voltage. For example, in environments with strong signals and little interference, overly conservative error correction coding and transmission power will waste energy. When the environment deteriorates, a fixed and simple strategy may lead to a sharp decline in communication quality, triggering retransmissions and increasing total energy consumption.

[0013] Therefore, those skilled in the art urgently need a technical solution for low-power data processing and optimization of radio frequency chips based on data feature perception, cross-layer collaboration, and adaptive closed-loop optimization. Summary of the Invention

[0014] The core technical problem addressed by this invention is that existing radio frequency (RF) chips, in continuous data processing, employ static, isolated, and coarse open-loop power consumption control strategies, which fail to dynamically adapt to the time-varying characteristics and information content of real-time data streams. This results in significant unnecessary energy consumption and overall low energy efficiency throughout the entire "data acquisition → preprocessing → core computation" chain.

[0015] To address the aforementioned core technical issues, this invention designs a low-power data processing and optimization method and system for radio frequency chips. The aim is to treat the chip as a complete energy efficiency system, dynamically adjust the front-end acquisition rate (sampling rate) by real-time analysis of the statistical characteristics of the input data (time-domain activity, frequency-domain sparsity, information entropy), and perform intelligent sparsification preprocessing on the data in the digital domain to reduce computational load, while simultaneously coordinating the scheduling of the processing unit's working state. Finally, by monitoring the system's energy efficiency and performance indicators, a closed-loop feedback is formed to continuously optimize control parameters and achieve long-term optimal energy efficiency balance.

[0016] This invention first performs adaptive segmentation and feature extraction (i.e., segmented feature extraction) on the original data stream; then, it dynamically adjusts the analog-to-digital conversion sampling rate based on the features; next, it performs probabilistic sparsification preprocessing on the data based on the features and sampling rate to reduce the amount of data to be processed; then, it performs hierarchical sleep and wake-up scheduling on units such as digital signal processors according to the data processing queue status; finally, it adaptively optimizes the key parameters in the aforementioned steps through an energy efficiency feedback loop to form an intelligent closed-loop control system.

[0017] To achieve the above objectives, the specific technical solution of the present invention is a low-power data processing and optimization method for radio frequency chips, which includes the following steps:

[0018] S1: Adaptive data stream segmentation and feature extraction. This involves real-time analysis of the continuous data stream input to the RF chip. Based on time-domain activity and frequency-domain sparsity indices, a segmentation decision function dynamically divides the data stream into active or silent segments and extracts segmentation features. It should be noted that S1 primarily involves real-time analysis of the raw continuous data stream input to the RF front-end analog-to-digital converter (ADC). Based on the inherent statistical characteristics of the data (such as time-domain activity indices (primarily amplitude change rate) and frequency-domain sparsity indices (primarily spectral energy distribution), it dynamically divides the data into "data segments" with different characteristics, rather than fixed-length data packets.

[0019] In the process of real-time data stream analysis, set The original data points at time 1 are Define a length of observation window but:

[0020] Time-domain activity index The calculation expression is:

[0021] ,in ;

[0022] The average absolute deviation of the data within the characterization window reflects the severity of the signal's time-domain fluctuations, i.e., the rate of change of the signal's amplitude.

[0023] Frequency domain sparsity index The calculation is for The frequency domain representation is obtained by performing a Fast Fourier Transform (FFT). The degree to which its energy is concentrated on a few principal components is calculated, and its expression is:

[0024]

[0025] in, For the highest energy A set of indices for each frequency component. For frequency component energy, For total energy, The closer it is to 1, the sparser the signal frequency domain, meaning the lower the distribution density of spectral energy.

[0026] The piecewise decision function is: when or When the current data segment is active, it is determined to be an "active segment"; otherwise, it is determined to be a "silent segment". and All are preset thresholds;

[0027] It is important to note that time-domain activity ( It is mainly used to sense the degree of change of a signal on the time axis, to distinguish between the "active" and "silent" states of data, and to provide a basis for subsequent sparsity reduction. The greater the fluctuation of the signal in the time domain, the richer the information, and the more attention and processing is required. Time domain activity ( ) is the "mean absolute deviation" in mathematical statistics. It is more robust than variance, less sensitive to outliers, and simple to calculate, making it suitable for hardware implementation; while frequency domain sparsity ( It is mainly used to sense the degree of energy concentration of a signal in the frequency domain, and to help distinguish between "active" and "silent" segments (for example, single-frequency noise may be inactive in the time domain but sparse in the frequency domain). The more concentrated the energy (such as a single-frequency signal), the better. The closer the value is to 1, the simpler (sparser) the frequency domain structure is, and the less information it may contain; this is the frequency domain sparsity. The complexity of a signal can be determined by analyzing the distribution of energy in the frequency spectrum.

[0028] S2: Dynamic sampling rate control based on information entropy. Based on the segmented characteristics of the divided data stream, the information entropy is calculated, and the sampling rate of the analog-to-digital converter is dynamically adjusted according to the information entropy, i.e., the sampling rate of the ADC is dynamically adjusted. To minimize power consumption during data acquisition while ensuring that necessary information is not lost;

[0029] For data within a "data segment", calculate its normalized information entropy. Information entropy is used to quantify the uncertainty or information content of a data segment. The calculation expression is:

[0030]

[0031] in, The number of intervals to divide the data amplitude. This data falls within the first... The probability of a range of amplitudes;

[0032] It is important to note that information entropy ( (i.e., "information entropy" in Shannon's information theory, a mathematical measure of uncertainty) is mainly used to quantify the amount or uncertainty of information content within a data segment, and to decide how high a sampling rate should be used to collect that data segment. The higher the entropy, the more disordered the data and the greater the amount of information, requiring a higher sampling rate to capture it.

[0033] S3: Probabilistic sparsity data preprocessing. Based on the sampling rate and the temporal activity index, the retention probability of data points is determined, and sparsity preprocessing is performed on the sampled data according to the retention probability to generate a sparse data sequence. That is, before the data is sent to the core digital signal processor (DSP) for complex operations (such as demodulation and decoding), the redundant data points that still exist under the high sampling rate are "zeroed" or "retained" with a certain probability to generate sparse data, thereby greatly reducing the amount of computation required for subsequent processing.

[0034] For the sampled data sequence Generate a mask sequence of the same length that follows a Bernoulli distribution. .

[0035]

[0036] Among them, the probability of preservation The results of steps S1 and S2 together determine:

[0037]

[0038] here It is a weighting factor ( ), Temporal activity Normalized reference values, preprocessed sparse data for:

[0039] ;

[0040] S4: Hierarchical sleep and wake-up scheduling of processing units. Based on the status of the queue to be processed and the expected processing delay of the sparse data sequence, hierarchical sleep and wake-up scheduling is performed on the digital signal processing units in the chip, thereby realizing dynamic management of the power status (active, idle, sleep, off) of each processing unit (such as DSP core, coprocessor, cache controller) inside the chip, and realizing fine power consumption control.

[0041] Define a decision function based on queue length and expected processing latency, where the current queue length of the sparse data to be processed is . The average time for the DSP to process a single data point is The wake-up latency-power tradeoff model is as follows:

[0042] like ,in To account for the delay time from waking up from deep sleep to being ready, the DSP is put into a shallow sleep; otherwise, it remains active. This decision aims to avoid the additional power consumption caused by frequent wake-ups being greater than the power savings from sleep.

[0043] S5: Energy efficiency feedback and parameter adaptive optimization, monitor the chip's real-time power consumption, data processing throughput and bit error rate, calculate energy efficiency indicators, and adaptively optimize the control parameters in S1 to S4 based on the energy efficiency indicators and bit error rate constraints.

[0044] Real-time power consumption of monitoring chip Data processing throughput and bit error rate Key indicators, forming a closed-loop feedback system, dynamically optimize key threshold parameters (such as...) in S1 to S4. ).

[0045] The time-domain activity index in S1 The calculation expression is:

[0046]

[0047] in, For data points, For viewing window The mean of the internal data. Window length; frequency domain sparsity index To observe the energy of the main frequency components after the window data undergoes a Fast Fourier Transform. With total energy The ratio of total energy As the denominator for calculating frequency domain sparsity, it provides a normalized benchmark for calculating the proportion of principal energy, which obeys Passevar's theorem, i.e., the total energy of the signal in the time domain is equal to its total energy in the frequency domain; total energy As a calculation The normalization factor makes It becomes a dimensionless proportional value, which makes it easier to set thresholds and make comparisons.

[0048] The dynamic adjustment of the sampling rate in S2 The expression is a piecewise function:

[0049] When information entropy hour, ;

[0050] when hour, ;

[0051] when hour, ;

[0052] Simplifying the above equation, we get:

[0053]

[0054] in, , These are the maximum and minimum sampling rates supported by the chip, respectively. , These are the high and low entropy thresholds, respectively. The minimum guarantee factor ( This ensures that a certain sampling rate is still maintained even at medium entropy values;

[0055] It should be noted that the independent variable for the dynamic adjustment of the sampling rate based on information entropy is the information entropy of the data segment. The dependent variable is the target sampling rate. Its construction process is as follows:

[0056] Objective: To establish With the required sampling rate The mapping relationship is such that high entropy (rich in information, strong uncertainty) requires a high sampling rate to capture details; low entropy (redundant information, predictable) can reduce the sampling rate.

[0057] constraint: Must be supported by the chip Within the range;

[0058] Design: A piecewise function is used, with two entropy thresholds set. and The state is divided into three levels: high, medium, and low. The medium level uses linear interpolation to ensure a smooth transition.

[0059] set up and They exhibit a positive correlation within the effective interval, and the simplest model represents a linear relationship.

[0060] ;

[0061] Substitute boundary conditions: When hour, ;when hour, However, it directly linearly decreases to Information may be lost at the critical point, therefore a safety margin factor is introduced. Set the starting point of the medium-range relationship as ;

[0062] Thus, the medium-range expression is derived:

[0063] ;

[0064] By combining the constant settings for high and low levels, the final piecewise function expression is obtained.

[0065] The retention probability of data points in S3 The calculation formula is:

[0066]

[0067] in, As a weighting factor, The time-domain activity normalization reference value is used; the probability sparsity preprocessing is performed by normalizing the original data points to a Bernoulli distribution. The mask sequence multiplication is implemented.

[0068] The independent variable in the probability sparsification preprocessing is the proportion of the current sampling rate. Temporal activity (After normalization), the dependent variable is the probability of data points being preserved. The construction process of probabilistic sparsification preprocessing:

[0069] Objective: To determine the probability of retaining each data point. The sampling rate itself reflects the information density, and the activity level reflects the temporal variation.

[0070] Principle: The higher the sampling rate and the more active the data, the greater the probability of retention should be;

[0071] Design: Combine the two influencing factors with a linear weighted average to form... ;

[0072] Two normalized indicators ( and This is considered a reflection of the "importance of data". The contribution factor of "" is used to fuse the two using the simplest linear weighted sum:

[0073] .

[0074] Let the weighting factor ,but ;Will Directly mapped to the probability of preservation And ensure that its value is within a reasonable range (e.g., [0.3, 1.0]), that is, obtain In practical applications, a pruning function may also be needed to ensure... Not exceeding the set range;

[0075] It is important to note that the contribution factor is not an independent metric, but rather an intermediate quantity used to construct the "preservation probability," referring to the normalized sampling rate ( ) and normalized temporal activity ( These are considered as two factors influencing the importance of the data; while maintaining the probability ( This determines the probability that each data point should be retained for subsequent processing, and is used to generate a mask sequence to achieve probabilistic sparsity. It serves as a bridge connecting data features and computational load, determining whether a data point is worth processing based on its importance (determined by both sampling rate and activity), thus achieving the effect of "using the best resources where they are most needed".

[0076] The decision-making basis for hierarchical hibernation and wake-up scheduling in S4 is as follows:

[0077] Compare the total expected processing time of the queue of data to be processed. The wake-up delay of the digital signal processing unit from deep sleep to readiness If the former is smaller than the latter, the unit is controlled to enter a shallow sleep or idle state; otherwise, it remains active.

[0078] The energy efficiency index in S5 Defined as data processing throughput With real-time power consumption The ratio, its expression is:

[0079] ;

[0080] The adaptive optimization process of the control parameters in S1 to S4 is based on satisfying the bit error rate. Maximize under constraints With the goal, For bit error rate, The target bit error rate;

[0081] Lightweight gradient descent or heuristic rules are used to fine-tune parameters online, for example, if the current... far below and If it's not high, the system can automatically lower it. Or increase The baseline value was used to attempt to further reduce power consumption;

[0082] Among them, energy efficiency indicators ( (Used in the fields of system design and performance evaluation, the ratio of performance (throughput) to cost (power consumption) is used as the core indicator for measuring the quality of a system.) It is mainly used to measure "how much data can be processed per unit of power consumption", to evaluate the overall effect of the current parameter settings, and directly reflects the efficiency of energy utilization. It is the ultimate goal of this invention and the performance evaluation standard.

[0083] It should be noted that the method described in this invention constitutes a complete scheme of serial triggering, parallel coordination, and closed-loop optimization, wherein:

[0084] In terms of serial triggering: S1 is the starting point, and its output "data segment characteristics" are the main inputs of S2 and S3. S2 adjusts the sampling rate according to the characteristics, and its output sampled data stream is the input of S3. The length and characteristics of the sparse data queue generated by S3 are the core basis for S4 to perform sleep scheduling.

[0085] In terms of parallel collaboration: S1, S2, and S3 are mainly for power consumption optimization of the "data path", while S4 is for power consumption optimization of the "control path" and "computing unit". The two are executed in parallel in time and work together on the chip as a whole.

[0086] In terms of closed-loop optimization: S5 acts as the "brain" to continuously monitor the final system effect (energy efficiency EE, bit error rate BER) produced by the combined action of S1 to S4, and adjusts the key parameters in S1 to S4 in reverse; this enables the entire system to adapt to different communication environments, channel conditions and data modes, and achieve optimal energy efficiency performance in the long term.

[0087] It should be noted that the hardware requirements for the method described in this invention are as follows:

[0088] The radio frequency chip needs to have an ADC with a dynamically adjustable sampling rate;

[0089] The chip's internal power management unit (PMU) needs to support partitioned and hierarchical power supply and status control for major modules such as the DSP and cache;

[0090] It needs to have on-chip sensors for monitoring key indicators such as power consumption and temperature;

[0091] A timer with sufficient accuracy and resolution is required for precise scheduling of sleep.

[0092] Regarding software / firmware features:

[0093] The algorithms for S1 and S2 need to be designed with low computational complexity, and can be completed in real time by a front-end task of a lightweight coprocessor or DSP to avoid introducing excessive overhead.

[0094] The S4 scheduler needs to be embedded in the power management framework of a real-time operating system (RTOS) or as a standalone power management interrupt service routine.

[0095] All parameters in the mathematical model need to be stored in non-volatile memory and supported for online updates via S5;

[0096] The entire method must ensure a definite and tolerable additional latency in data processing, without affecting the real-time requirements of the communication protocol.

[0097] A low-power data processing and optimization system for radio frequency chips, the system comprising the steps of implementing the method, including:

[0098] The feature extraction module is configured to perform S1;

[0099] A dynamic sampling and control module, configured to execute S2;

[0100] A sparsification preprocessing module, configured to perform S3;

[0101] The power consumption scheduling module is configured to execute S4;

[0102] An energy efficiency feedback optimization module is configured to execute S5.

[0103] The feature extraction module and the dynamic sampling control module are integrated into the configurable coprocessor within the RF chip; the power consumption scheduling module is integrated into the power management unit of the RF chip or the power management framework of the real-time operating system.

[0104] It should be noted that the system is set up with five core modules in order to systematically solve the four core pain points of existing technologies: "static, isolated, extensive, and open-loop". The goal is to build a "dynamic, collaborative, refined, and closed-loop" low-power solution. Each module targets a key link in the problem chain and none of them can be omitted.

[0105] The feature extraction module is primarily designed to address the "static" problem: existing technologies employ a "static" approach, treating all data equally. However, actual data streams (such as voice and sensor data) are highly "dynamic," containing information-rich "active segments" and redundant "silent segments." The feature extraction module serves as the perception layer of the entire solution. By calculating temporal activity and frequency sparsity in real time, it dynamically identifies the inherent characteristics and changes in the data stream, providing a basis for all subsequent power optimization actions. Without the feature extraction module, subsequent adjustments would be blind, unable to distinguish when to save power and when to ensure performance, and still unable to adapt to the time-varying characteristics of the data.

[0106] The dynamic sampling control module addresses the "isolation" problem: In traditional methods, the ADC sampling rate is often fixed, and its power consumption is "isolated" from the power consumption of the back-end processing (DSP). The dynamic sampling control module acts as a bridge for "acquisition-processing" collaboration. Based on the "information entropy" provided by the feature extraction module, it dynamically adjusts the ADC sampling rate. When the information content is high, a high sampling rate is used to capture details, and when the information content is low, a low sampling rate is used to save front-end power consumption. This step directly links data features with hardware acquisition power consumption, breaking down the power optimization barrier between the front-end and back-end, and is the first step in achieving cross-layer collaboration.

[0107] The sparsity preprocessing module is designed to address the "coarse" problem: even with a reduced sampling rate, redundancy may still exist in the data. Traditional DVFS is a "coarse" global adjustment, while the sparsity preprocessing module is key to achieving "fine" computational load reduction. Before the data enters the core DSP, it "selectively" discards (zeros) redundant data points based on the sampling rate and temporal activity in a probabilistic manner. This directly reduces the amount of data that the subsequent DSP needs to process, thereby reducing the power consumption of the core computation. It moves power optimization from "voltage / frequency adjustment" to the "data computation load" level, which is a more refined and fundamental way to save power.

[0108] The power scheduling module also addresses the "isolation" problem: even if the amount of data is reduced, the processing unit (DSP) will still consume power if it remains active. The power scheduling module is a controller that enables "processing-state" coordination. Based on the length of the sparsed data queue, it dynamically and hierarchically schedules the sleep and wake-up of the processing unit, ensuring that the processing unit only runs at full speed when there is enough data to process, and enters a low-power state when there is nothing to do. This avoids the power consumption of the processing unit while it is idling, tightly coupling the data processing load with the power state of the hardware, and further exploring the space for system-level power optimization.

[0109] The energy efficiency feedback optimization module addresses the "open-loop" problem: the four modules mentioned above form a complete forward control link, but the environment (channel conditions, data mode) is dynamic. Without feedback, once the parameters are set, they remain fixed and cannot guarantee long-term optimal performance. The energy efficiency feedback optimization module acts as the "brain" and closed-loop controller of the entire system. It monitors the system's final performance (energy efficiency EE, bit error rate BER) in real time and adaptively optimizes all key parameters (such as thresholds and weights) in the first four modules based on this. This transforms the entire system from a "statically configured" system into an "intelligent closed-loop" system capable of self-learning, continuous evolution, and always operating near the optimal energy efficiency point.

[0110] The entire system works as follows:

[0111] First, the raw data is entered into the system;

[0112] Secondly, calculations are performed in the feature extraction module. and Complete data segmentation;

[0113] Then, in the dynamic sampling and control module, based on the segmented calculations... To adjust the ADC Next, in the sparsity preprocessing module, combined with and Calculate The data is then processed to generate a mask and sparsified. The sparsified data is then queued, and the power scheduling module determines the processing time based on the queue length. Determine whether to put the DSP to sleep;

[0114] Finally, the energy efficiency feedback optimization module monitors the entire process. , and Calculate And adjust in reverse , , , These parameters form a complete closed loop.

[0115] Therefore, the above five modules constitute a complete control loop of "perception-decision-execution-coordination-optimization". They are progressive and synergistic with each other, and together solve the problems of static, isolated, extensive and open-loop in existing technologies, and achieve optimal global energy efficiency.

[0116] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method.

[0117] A radio frequency chip comprising the aforementioned system. Compared with the prior art, the technical solution disclosed in this application has the following non-obvious technical features:

[0118] First, this application employs a dynamic sampling rate control mechanism based on the joint determination of information entropy and signal characteristics. It combines the concept of "entropy" from information theory with "temporal activity" and "frequency sparsity" in signal processing to construct a multi-dimensional feature space, and then dynamically and smoothly adjusts the ADC sampling rate based on this space. This precise control from the perspective of "information content" goes beyond simple signal energy detection and is more theoretically sound and adaptable.

[0119] Second, this application constructs a "probabilistic sparsification preprocessing" step to reduce computational power consumption. Before the data enters the core DSP, based on the data characteristics and the current sampling rate, some data points are actively discarded (set to zero) in a probabilistic manner, artificially constructing sparse data. This step moves power consumption optimization from traditional voltage / frequency adjustment to the "data itself" and "computational load" levels, and works in conjunction with subsequent DSP algorithms that can be accelerated by sparse matrix operations, significantly reducing computational power consumption.

[0120] Third, this application adopts a cross-layer collaborative closed loop of "data feature perception - hardware state scheduling". This method establishes a vertical optimization path from physical layer data feature extraction (S1, S2), to link layer data processing (S3), and then to system layer power management (S4), with closed-loop feedback provided by application layer / system layer energy efficiency monitoring (S5). This deep hardware and software collaboration and cross-abstraction level joint optimization architecture achieves global energy efficiency optimization, rather than local power saving of a single module.

[0121] Fourth, this application has an online adaptive parameter optimization mechanism, which is achieved by defining "energy efficiency ( ")" is used as the optimization objective, and the bit error rate (BER) is also considered. Under constraints, a lightweight algorithm is used to fine-tune the threshold and weight parameters of all preceding steps online. This enables the system to learn and adapt to constantly changing communication environments and workloads, achieving a leap from "static low-power configuration" to "dynamic energy-efficient optimal control".

[0122] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention can significantly extend the battery life of the device. Through multi-level and collaborative power consumption optimization, it can reduce the average power consumption of the radio frequency chip in continuous data transmission mode by 20%-50% while ensuring communication quality, thereby significantly extending the battery life of battery-powered devices such as IoT sensors and wearable devices.

[0123] 2. This invention can improve the overall system energy efficiency ratio ( This method takes maximizing the throughput / power consumption ratio as its core objective. Through closed-loop optimization, it enables the chip to always operate at a near-optimal energy efficiency point under the current channel conditions and data mode, thereby improving energy utilization efficiency.

[0124] 3. This invention reduces the chip's operating temperature and improves reliability. The reduction in power consumption directly reduces the chip's heat generation, which helps to lower the junction temperature, thereby improving the chip's operational stability and long-term reliability in high-temperature environments and reducing performance degradation or failure caused by overheating.

[0125] 4. This invention enhances system adaptability. Its adaptive nature allows the same solution to be applicable to a variety of different application scenarios (such as constant sensor readings, sudden control commands, and high-speed audio and video streams) without the need for manual reconfiguration for each scenario, thus reducing development and usage complexity.

[0126] 5. This invention creates conditions for the application of advanced algorithms. The reduced power consumption "budget" can be reallocated to more complex communication algorithms (such as advanced coding, machine learning-driven signal processing), improving system performance with the same battery life, or achieving longer battery life with the same performance requirements. Attached Figure Description

[0127] Figure 1 This is a flowchart of the method described in Embodiment 1 of the present invention;

[0128] Figure 2 This is the implementation parameter table of the method described in Embodiment 1 of the present invention;

[0129] Figure 3 This is a comparison table of the implementation effects of the method described in Embodiment 1 of the present invention;

[0130] Figure 4 This is a power consumption curve diagram of the conventional technical solution described in Embodiment 1 of the present invention and the technical solution of the present invention within one event cycle;

[0131] Figure 5 This is a schematic diagram of the system described in Embodiment 3 of the present invention;

[0132] Figure 6 This is the operating parameter table of the system described in Embodiment 3 of the present invention;

[0133] Figure 7 This is a comparison table of the operating effects of the system described in Embodiment 3 of the present invention;

[0134] Figure 8 This is a bar chart showing the power consumption of a traditional RF SoC and an RF SoC integrating the system described in Embodiment 3 of the present invention over 24 hours. Detailed Implementation

[0135] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings;

[0136] Example 1:

[0137] A low-power data processing and optimization method for radio frequency chips, such as Figure 1 As shown, this method is mainly applied to low-power data processing of IoT temperature and humidity sensors, especially a wireless temperature and humidity sensor node deployed in an agricultural greenhouse. Its radio frequency chip uses the Zigbee protocol to periodically report data. The data stream characteristics are: most of the time, a slowly changing temperature and humidity baseline (quiet segment), occasionally experiencing rapid changes due to events such as ventilation or watering (active segment). The specific implementation process of the method is as follows:

[0138] Initialization parameters: After the chip powers on, default parameters are loaded from non-volatile memory, such as... Figure 2 As shown;

[0139] Data stream processing (executed in a loop from S1 to S4):

[0140] S1: ADC at the highest sampling rate Acquire raw sensor voltage signals The coprocessor uses Real-time window calculation and When temperature and humidity are stable, Low value A high value (spectrum concentrated in low frequencies close to DC) is identified as the "quiet zone." When a sudden door opening causes a rapid temperature change, Rapidly increased, exceeding This segment is marked as an "active segment";

[0141] S2: For the "silent segment", calculate its information entropy. Lower (e.g.) =0.2). According to the piecewise function, the lowest sampling rate is used at this time. Subsequent data acquisition resulted in a significant reduction in ADC power consumption; for the "active segment"... Higher (e.g.) =0.8), sampling rate increased to To capture the details of the changes;

[0142] Algorithms based on S1 and S2 need to be designed with low computational complexity, which can be completed by a lightweight coprocessor, thereby achieving controllable algorithm complexity. The operations involved (mean, absolute deviation, FFT, entropy calculation) all have mature low-power hardware acceleration solutions.

[0143] S3: In The silent segment, The calculated value is relatively low (e.g., 0.4). The Bernoulli mask sequence preserves data points with a 40% probability, generating a sparse sequence. This means the DSP only needs to process about 40% of the data points;

[0144] S4: The DSP processes sparse data very quickly, and the queue Q is frequently emptied. The scheduler determines... This allows the DSP to quickly enter a shallow sleep state during data acquisition intervals;

[0145] Energy Efficiency Feedback (S5): The background task calculates the average energy efficiency every 10 minutes. and bit error rate Discover the current 10 -6 Far below the target of 10 -4 ,and There is room for improvement. Therefore, the parameters are automatically fine-tuned. The value was reduced from 0.3 to 0.25, making more time periods eligible for downsampling and further optimizing energy efficiency.

[0146] The implementation parameters of Embodiment 1 are as follows: Figure 2 As shown, Figure 2 Specific initialization parameters are provided, such as , , =0.15, , , These parameters are the starting point for the algorithm's execution;

[0147] The implementation effect of Embodiment 1 is as follows: Figure 3 As shown, Figure 3 The paper presents a quantitative comparison between the present invention and the traditional solution (fixed sampling rate of 1kHz) in the case of temperature and humidity sensors. The data shows that, while ensuring the same bit error rate, the present invention reduces the ADC sampling rate from 1kHz to an average of 165Hz, reduces the DSP load by 60%, reduces the overall system power consumption by 41%, and extends the battery life from 30 days to 51 days.

[0148] Specific power consumption details are as follows Figure 4 As shown, Figure 4 The graph shows the power consumption curves of the traditional technical solution and the technical solution of this embodiment 1 within one event cycle, which fully demonstrates the power consumption changes of the traditional technical solution and the technical solution of this embodiment 1 within the event cycle.

[0149] Example 2:

[0150] A low-power data processing and optimization system for radio frequency chips, such as Figure 5As shown, this system is integrated within a radio frequency SoC (System-on-a-Chip) and includes the following modules:

[0151] Feature extraction module: Implemented by a small, configurable coprocessor, containing hardware-accelerated moving average and FFT calculation units for real-time computation. and ;

[0152] Dynamic sampling control module: Integrated into the ADC controller, it receives segment markers from the feature extraction module and the output of the entropy calculation unit. The value is changed in real time by configuring the clock divider inside the ADC. ;

[0153] The sparsity preprocessing module, located on the data path between the ADC output and the main DSP, contains a pseudo-random number generator and a comparator, based on... Real-time mask generation And multiply it with the data stream;

[0154] Power scheduling module: As part of the chip power management unit (PMU), it monitors the data queue status register and system timer, and performs sleep / wake-up by controlling the switching of the DSP power domain and clock gating;

[0155] Energy efficiency feedback optimization module: It runs in software on a low-power monitoring microcontroller (MCU), periodically reads the bit error statistics of the on-chip power sensor, DSP throughput counter and forward error correction module, and runs optimization algorithms to update the global parameter table stored in shared memory.

[0156] The specific operation process of the system is as follows:

[0157] The system starts up, and each module loads its initial parameters;

[0158] ADC with current The sampled data is sent to the feature extraction module and the sparsity preprocessing module;

[0159] The feature extraction module outputs segment labels and The dynamic sampling control module and the sparsification preprocessing module are simultaneously triggered to calculate entropy.

[0160] The dynamic sampling control module adjusts the parameters based on the newly calculated values. And segment markers, update ADC ;

[0161] The sparsity preprocessing module is based on the latest and calculate The data flowing through it is sparsified in real time, and the result is stored in the DSP input queue (FIFO).

[0162] The power scheduling module monitors the depth of the FIFO. ,when Below the threshold (corresponding to) ), sends a request to the PMU to reduce the DSP clock frequency or turn off some of its power domains;

[0163] After the DSP is woken up, it reads sparse data from the FIFO and performs core operations such as demodulation and decoding.

[0164] The energy efficiency feedback optimization module runs in the background, every Performance data is collected periodically for evaluation. ,like For safety, the parameter table is adjusted using the gradient search method, and the relevant modules are notified to update their operating parameters via an interrupt.

[0165] The operating parameters of embodiment 3 are as follows: Figure 6 As shown, Figure 6 The dynamic parameter changes of the system-on-a-chip during operation are presented, demonstrating whether the data indicates "mute" or "voice" within a 2-second time window. , How to dynamically adjust DSP status, etc.;

[0166] The operational effect of implementation 3 is as follows: Figure 7 As shown, Figure 7 The study compared the average power consumption of the RF SoC integrating this system with that of a traditional SoC over 24 hours. The results showed that, in mixed service scenarios, the SoC integrating this system reduced the average power consumption by 36.5% and improved the energy efficiency ratio (MOPS / mW) by 58%.

[0167] Specific power consumption details are as follows Figure 8 As shown, Figure 8 The graph shows the power consumption of a traditional RF SoC and an RF SoC integrating the system described in Example 3 over 24 hours, providing a clearer description of their power consumption over different time periods.

[0168] Example 3:

[0169] A computer-readable storage medium, such as an internal read-only memory (ROM), flash memory, or an external EEPROM, stores a computer program (instruction sequence). When the program is executed by a processor within the radio frequency chip (such as a coprocessor, main DSP, or management MCU), the processor performs the steps of the method described in Embodiment 1 or Embodiment 2, specifically including:

[0170] Execute instructions for adaptive segmentation and feature extraction of the data stream;

[0171] Execute instructions to dynamically adjust the sampling rate based on information entropy;

[0172] Instructions for performing probabilistic sparse data preprocessing;

[0173] Execute instructions for hierarchical sleep and wake-up scheduling of the processing unit;

[0174] Execute instructions for energy efficiency feedback and parameter adaptive optimization.

[0175] The storage medium also stores the method's initialization parameter table, adaptive optimization history, and constants required for program execution.

[0176] Example 4:

[0177] A radio frequency chip, used for a Zigbee chip in the Internet of Things (IoT), a Bluetooth chip for audio, or an NB-IoT chip for cellular communication, integrates a low-power data processing and optimization system as described in Example 3. Specifically, it includes:

[0178] An analog-to-digital converter (ADC) with a dynamically adjustable sampling rate;

[0179] Digital signal processors (DSPs) are used to perform physical layer functions in communications.

[0180] The power management unit (PMU) supports multiple voltage domains and clock gating;

[0181] Also includes:

[0182] A configurable coprocessor connected to the ADC and DSP is used to implement feature extraction and dynamic sampling control logic;

[0183] The hardware sparsification unit located at the ADC data output interface is used to implement probabilistic sparsification preprocessing.

[0184] An intelligent scheduler embedded in the PMU is used to implement hierarchical sleep and wake-up scheduling;

[0185] A microcontroller for energy efficiency management connects to various sensors inside the chip and is used to run energy efficiency feedback and parameter adaptive optimization algorithms;

[0186] This RF chip, by embedding the optimized process of the present invention at the hardware level, can provide upper-layer applications with significantly better energy efficiency than traditional chips, while reducing the load on the main processor, making it particularly suitable for battery-powered devices that are extremely sensitive to power consumption.

[0187] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A low-power data processing and optimization method for radio frequency chips, characterized in that, Includes the following steps: S1: Perform real-time analysis on the continuous data stream input to the RF chip, and dynamically divide the data stream into active segments or silent segments and extract segment features based on the time-domain activity index and the frequency-domain sparsity index. S2: Based on the segmentation characteristics of the divided data stream, calculate its information entropy, and dynamically adjust the sampling rate of the analog-to-digital converter according to the information entropy; S3: Based on the sampling rate and the temporal activity index, determine the retention probability of the data points, and perform sparsification preprocessing on the sampled data according to the retention probability to generate a sparse data sequence. S4: Based on the status of the queue to be processed and the expected processing delay of the sparse data sequence, perform hierarchical sleep and wake-up scheduling on the digital signal processing unit in the chip; S5: Monitor the chip's real-time power consumption, data processing throughput, and bit error rate, calculate energy efficiency indicators, and adaptively optimize the control parameters in S1 to S4 based on the energy efficiency indicators and bit error rate constraints.

2. The method according to claim 1, characterized in that, The time-domain activity index in S1 The calculation expression is: ； in, For data points, For viewing window The mean of the internal data. Window length; frequency domain sparsity index This is used to observe the ratio of the energy of the main frequency components to the total energy after the data in the observation window has undergone a Fast Fourier Transform.

3. The method according to claim 1, characterized in that, The dynamic adjustment of the sampling rate in S2 The expression is a piecewise function: When information entropy hour, ; when hour, ; when hour, ; in, , These are the maximum and minimum sampling rates supported by the chip, respectively. , These are the high and low entropy thresholds, respectively. As a minimum guarantee factor, This refers to information entropy.

4. The method according to claim 1, characterized in that, The retention probability of data points in S3 The calculation formula is: ； in, As a weighting factor, The time-domain activity normalization reference value is used; sparsity preprocessing is achieved by fusing the original data points with a Bernoulli distribution. The mask sequence multiplication is implemented.

5. The method according to claim 1, characterized in that, The decision-making basis for hierarchical hibernation and wake-up scheduling in S4 is as follows: Compare the total expected processing time of the queue of data to be processed. The wake-up delay of the digital signal processing unit from deep sleep to readiness If the former is smaller than the latter, the unit is controlled to enter a shallow sleep or idle state; otherwise, it remains active.

6. The method according to claim 1, characterized in that, The energy efficiency index in S5 Defined as data processing throughput With real-time power consumption The ratio, its expression is: ； The adaptive optimization process of the control parameters in S1 to S4 is based on satisfying the bit error rate. Maximize under constraints With the goal, The target bit error rate.

7. A low-power data processing and optimization system for radio frequency chips, the system being used to implement the steps of the method as described in any one of claims 1 to 6, characterized in that, include: The feature extraction module is configured to perform S1; A dynamic sampling and control module, configured to execute S2; A sparsification preprocessing module, configured to perform S3; The power consumption scheduling module is configured to execute S4; An energy efficiency feedback optimization module is configured to execute S5.

8. The system according to claim 7, characterized in that, The feature extraction module and the dynamic sampling control module are integrated into the configurable coprocessor within the RF chip; the power consumption scheduling module is integrated into the power management unit of the RF chip or the power management framework of the real-time operating system.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 6.

10. A radio frequency chip, characterized in that, The system comprising any one of claims 7 to 8.

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