Multilayer circuit boards and their fabrication methods

Abstract

This application proposes a multilayer circuit board and its fabrication method. By placing transmission lines at the bottom of the trench, this application can provide a shorter current path, thereby increasing wiring density and reducing parasitic capacitance and inductance of the transmission lines. This helps to reduce signal delay and distortion, and improve signal integrity, thus meeting the requirements of high-density and high-frequency high-speed transmission.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and in particular to a multilayer circuit board and its fabrication method. Background Technology

[0002] In the design of high-density / multilayer PCBs, while increasing wiring density can reduce product size, it also introduces several problems. Firstly, with increased wiring density, signal crosstalk and signal integrity issues become more prominent, especially in high-frequency applications where even minor electrical interference can cause system instability. Furthermore, matching material selection with manufacturing processes is also a challenge. For example, high-speed signal transmission requires low-loss dielectric materials, but these materials are difficult to process (e.g., mass production of polytetrafluoroethylene (PTFE) is quite challenging).

[0003] Therefore, circuit boards that can simultaneously meet the requirements of high-density technology and high-frequency, high-speed transmission are one of the technical challenges that future consumer electronics products need to overcome. Summary of the Invention

[0004] In view of this, this application provides a method for fabricating a multilayer circuit board, so as to fabricate a multilayer circuit board that simultaneously meets the requirements of high density and high-frequency high-speed transmission.

[0005] A method for fabricating a multilayer circuit board includes the following steps: providing a substrate, the substrate comprising a first adhesive layer, a first circuit layer, a first dielectric layer, a second circuit layer, and a second adhesive layer sequentially disposed therefrom; laminating a second dielectric layer and a third circuit layer onto the side of the second adhesive layer opposite to the second circuit layer; forming a first trench on the substrate, the first trench penetrating the first adhesive layer and the first dielectric layer; forming a first transmission line at the bottom of the first trench; laminating a copper-clad laminate onto the side of the first adhesive layer opposite to the first circuit layer, the copper-clad laminate comprising a third dielectric layer and a copper foil layer, the third dielectric layer being located between the first adhesive layer and the copper foil layer; after lamination, the opening of the first trench is covered to form a first cavity; and fabricating the copper foil layer to form a fourth circuit layer, thereby obtaining the multilayer circuit board.

[0006] In one embodiment, the depth of the first trench is H1, and the thickness of the first transmission line is h1. Wherein, h1 ≤ 0.5H1.

[0007] In one embodiment, after the step of pressing the second dielectric layer and the third circuit layer onto the side of the second adhesive layer opposite to the first dielectric layer, the preparation method further includes: forming a second trench that penetrates the third circuit layer, the second dielectric layer, and the second adhesive layer; forming a second transmission line at the bottom of the second trench; and forming a protective layer on the surface of the second transmission line.

[0008] In one embodiment, the fabrication method further includes: laminating a copper-clad laminate onto the side of the third circuit layer opposite to the second dielectric layer, the copper-clad laminate comprising a fourth dielectric layer and a copper foil layer, the fourth dielectric layer being located between the third circuit layer and the copper foil layer; after lamination, the opening of the second trench is covered by the fourth dielectric layer to form a second cavity; fabricating the copper foil layer to form a fifth circuit layer; and providing a protective layer on the side of the fifth circuit layer opposite to the fourth dielectric layer. Wherein, the depth of the second trench is H2, and the thickness of the second transmission line is h2, where h2 ≤ 0.5H2.

[0009] In one embodiment, after the step of forming the fourth circuit layer by fabricating the copper foil layer, the preparation method further includes: pressing a third adhesive layer onto the side of the fourth circuit layer opposite to the third dielectric layer; forming a third trench that penetrates the third adhesive layer, the fourth circuit layer, the third dielectric layer, and the first adhesive layer; forming a third transmission line at the bottom of the third trench; and forming a protective layer on the surface of the third transmission line.

[0010] In one embodiment, the preparation method further includes: laminating a copper-clad laminate onto the side of the third adhesive layer opposite to the fourth circuit layer, the copper-clad laminate comprising a fifth dielectric layer and a copper foil layer, the fifth dielectric layer being located between the third adhesive layer and the copper foil layer; after lamination, the opening of the third trench is covered by the fifth dielectric layer to form a third cavity; fabricating the copper foil layer to form a sixth circuit layer; and providing a protective layer on the side of the sixth circuit layer opposite to the fifth dielectric layer. Wherein, the depth of the third trench is H3, and the thickness of the third transmission line is h3, where h3 ≤ 0.5H3.

[0011] In one embodiment, the preparation method further includes forming a protective layer on the surface of the first transmission line.

[0012] This application also proposes a multilayer circuit board, including a first circuit board, a second circuit board, and a third circuit board. The first circuit board includes a first adhesive layer, a first circuit layer, a first dielectric layer, a second circuit layer, and a second adhesive layer sequentially disposed therefrom. The first circuit board has a first cavity penetrating the first dielectric layer and a portion of the first adhesive layer, and a first transmission line is disposed at the bottom of the first cavity away from the first adhesive layer. The second circuit board includes a second dielectric layer and a third circuit layer, with the second dielectric layer located between the second adhesive layer and the third circuit layer. The third circuit board includes a third dielectric layer and a fourth circuit layer, with the third dielectric layer located between the first adhesive layer and the fourth circuit layer.

[0013] In one embodiment, the multilayer circuit board further includes a fourth circuit board and a second cavity. The fourth circuit board includes a fourth dielectric layer and a fifth circuit layer, with the fourth dielectric layer located between the third and fifth circuit layers. The second cavity penetrates the second adhesive layer, the second dielectric layer, and the third circuit layer, and a second transmission line is provided in the second cavity near the bottom of the second adhesive layer.

[0014] In one embodiment, the multilayer circuit board further includes a fifth circuit board and a third cavity. The fifth circuit board includes a third adhesive layer, a fifth dielectric layer, and a sixth circuit layer disposed sequentially. The third adhesive layer is located between the fourth circuit layer and the fifth dielectric layer, and the sixth circuit layer is located on the surface of the fifth dielectric layer opposite to the third adhesive layer. The third cavity penetrates the third adhesive layer, the fourth circuit layer, the third dielectric layer, and the first adhesive layer, and a third transmission line is provided in the third cavity near the bottom of the first adhesive layer.

[0015] This application provides a shorter current path by placing the transmission line at the bottom of the trench, which can increase the wiring density, reduce the parasitic capacitance and inductance of the transmission line, thereby helping to reduce signal delay and distortion, and improve signal integrity, thus meeting the requirements of high density and high frequency and high speed transmission. Attached Figure Description

[0016] Figures 1A to 1C This is a cross-sectional view of the substrate fabrication provided in one embodiment of this application.

[0017] Figure 2 In order to be in Figure 1C The diagram shows a cross-sectional view of a cover film and a copper-clad laminate laminated on both sides of the substrate.

[0018] Figure 3 In order to be in Figure 2 The structure shown is a cross-sectional view forming a third circuit diagram, a first trench, and a second trench.

[0019] Figures 4A to 4B In order to be in Figure 3 A cross-sectional view showing the bottom of the first trench of the structure to form the first transmission line.

[0020] Figure 5 In order to be in Figure 4B A cross-sectional view of the protective layer formed on the surface of the first transmission line of the structure shown.

[0021] Figure 6 In order to be in Figure 5 A cross-sectional view of one side of the copper-clad laminate of the structure shown.

[0022] Figure 7 To be Figure 6A cross-sectional view of a multilayer circuit board obtained after the copper foil layer of the structure shown is fabricated to form the fourth circuit layer, as shown in one embodiment.

[0023] Figure 8 In order to be in Figure 7 A cross-sectional view of the structure shown, in which a third adhesive layer is pressed onto one side to form a third groove.

[0024] Figure 9 In order to be in Figure 8 A cross-sectional view showing the formation of a third transmission line at the bottom of the third trench in the structure shown.

[0025] Figure 10 In order to be in Figure 9 The cross-sectional view of the structure shown is provided, showing copper-clad laminates pressed onto both sides.

[0026] Figure 11 To be Figure 10 A cross-sectional view of a multilayer circuit board obtained after forming a circuit layer on a copper-clad laminate with the structure shown in another embodiment.

[0027] Explanation of key component symbols for multilayer circuit boards 100

[0028] Substrate 10A

[0029] First adhesive layer 11

[0030] First line layer 12

[0031] First dielectric layer 13

[0032] Second line layer 14

[0033] Second adhesive layer 15

[0034] Protective film 16

[0035] First transmission line 17

[0036] Protective layers 18, 24, 34

[0037] Third adhesive layer 19

[0038] Conductor layers 17a, 17b, 23a, 23b

[0039] Copper clad laminates 10a, 20a, 30a, 40a, 50a Copper foil layers 12a, 14a, 22a, 32a, 42a, 52a

[0040] Second dielectric layer 21

[0041] Third line layer 22

[0042] Second transmission line 23

[0043] Third dielectric layer 31

[0044] Fourth line layer 32

[0045] Third transmission line 33

[0046] Fourth dielectric layer 41

[0047] Fifth line layer 42

[0048] Fifth dielectric layer 51

[0049] Sixth line layer 52

[0050] First circuit board 10

[0051] Second circuit board 20

[0052] Third circuit board 30

[0053] Fourth circuit board 40

[0054] Fifth circuit board 50

[0055] Protective layer 60

[0056] First trench 101

[0057] First cavity 102

[0058] Second trench 201

[0059] Second cavity 202

[0060] Third trench 301

[0061] Third cavity 302

[0062] The following detailed description, in conjunction with the accompanying drawings, further illustrates the embodiments of this application. Detailed Implementation

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the embodiments of this application. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all commercially available products.

[0064] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0065] It will be understood that when a layer is referred to as "on" another layer, it can be directly on that other layer or there may be an intermediate layer in between. Conversely, when a layer is referred to as "directly on" another layer, there is no intermediate layer. When a component is referred to as "attached to," "mounted to," "set on," or "connected to" another component, it can be directly on that other component or there may be an intervening component. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0066] Embodiments of this application are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments (and intermediate configurations) of this application. Therefore, variations in the shapes illustrated due to manufacturing processes and / or tolerances are foreseeable. Consequently, embodiments of this application should not be construed as limited to the specific shapes of the areas illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. The areas shown in the figures are merely illustrative, and their shapes are not intended to represent the actual shapes of the illustrated devices, nor are they intended to limit the scope of this application.

[0067] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0068] Please see Figures 1A to 11 The first aspect of this application provides a method for fabricating a multilayer circuit board 100, which includes steps S10 to S160. It is understood that the step numbers are intended to clearly describe the specific fabrication method and do not imply a limitation on the order of the steps.

[0069] Please see Figures 1A to 1C S10, a substrate 10A is provided. The substrate 10A includes a first adhesive layer 11, a first circuit layer 12, a first dielectric layer 13, a second circuit layer 14, and a second adhesive layer 15 disposed sequentially.

[0070] In some embodiments, the substrate 10 may be formed by steps S11 to S13.

[0071] like Figure 1AAs shown in S11, a copper-clad laminate 10a is provided. The copper-clad laminate 10a may include a first dielectric layer 13, a copper foil layer 12a located on one surface of the first dielectric layer 13, and a copper foil layer 14a located on the other surface of the first dielectric layer 13. The first dielectric layer 13 may be, but is not limited to, polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate two-formicacid glycol ester (PEN), polydimethylsiloxane (PDMS), liquid crystal polymer (LCP), modified polyimide (MPI), etc.

[0072] like Figure 1B As shown, in step S12, a dry film (not shown) can be laminated onto the surfaces of copper foil layers 12a and 14a respectively. Then, exposure, development, etching, and film removal operations are performed to fabricate copper foil layer 12a into the first circuit layer 12 and copper foil layer 14a into the second circuit layer 14. The lamination, exposure, development, etching, and film removal steps are common techniques in the field and will not be described in detail here.

[0073] like Figure 1C As shown, in step S13, a first adhesive layer 11 is bonded to the surface of the first circuit layer 12 opposite to the first dielectric layer 13, and a second adhesive layer 15 is bonded to the surface of the second circuit layer 14 opposite to the first dielectric layer 13, thereby obtaining a substrate 10A. The pattern gaps in the first circuit layer 12 can be filled by the first adhesive layer 11, and the pattern gaps in the second circuit layer 14 can be filled by the second adhesive layer 15. Both the first adhesive layer 11 and the second adhesive layer 15 can be formed from pure adhesive (AD).

[0074] Please see Figure 2 and Figure 3 S20, the second dielectric layer 21 and the third circuit layer 22 are pressed together on the side of the second adhesive layer 15 away from the second circuit layer 14.

[0075] In some embodiments, S20 may further include S21 to S23.

[0076] like Figure 2 As shown, in step S21, a copper-clad laminate 20a is laminated onto the side of the second adhesive layer 15 opposite to the second circuit layer 14. The copper-clad laminate 20a includes a second dielectric layer 21 and a copper foil layer 22a, with the second dielectric layer 21 located between the copper foil layer 22a and the second dielectric layer 21.

[0077] like Figure 2As shown, in step S22, a protective film 16 can be adhered to the side of the first adhesive layer 11 opposite to the first circuit layer 12. The protective film 16 ensures that the subsequent copper plating process only occurs in the required area, improving the accuracy of electroplating. The protective film 16 can be, but is not limited to, a PET film, which has good tearability. In some embodiments, the protective film 16 may also be omitted.

[0078] like Figure 3 As shown in S23, the copper foil layer 22a can be fabricated into the third circuit layer 22 by means of pressing, exposure, development, etching, and film removal.

[0079] Please continue reading. Figure 3 S30, a first trench 101 may be formed on the substrate 10A by means of, but not limited to, laser etching. Along the thickness direction (i.e., Figure 3 In the vertical direction, the first trench 101 penetrates the first adhesive layer 11 (including the portion filling the pattern gaps in the first circuit layer 12) and the first dielectric layer 13, and the bottom wall of the first trench 101 is the second adhesive layer 15. It can be understood that when the surface of the first adhesive layer 11 is provided with a protective film 16, the first trench 101 also penetrates the protective film 16.

[0080] In some embodiments, such as Figure 3 As shown, along the extension direction of substrate 10A (i.e. Figure 3 The horizontal direction in the first groove 101 can be either the length direction or the width direction. The number of first grooves 101 can be one or more, and this application does not impose any restrictions.

[0081] Please continue reading. Figure 3 S40, the second trench 201 can be formed by means of, but not limited to, laser. Along the thickness direction (i.e. Figure 3 (In the vertical direction), the second groove 201 penetrates the third circuit layer 22 (at the pattern gap), the second dielectric layer 21 and the second adhesive layer 15, and the base plate of the second groove 201 is the first dielectric layer 13.

[0082] Please see Figure 4A and Figure 4B S50, a first transmission line 17 is formed at the bottom of the first trench 101 (i.e., the part opposite to the opening of the first trench 101).

[0083] like Figure 4AAs shown, a conductor layer 17a can be formed on the bottom wall of the first trench 101 by means of electroplating, but not limited to electroplating, and a conductor layer 17b can be formed on the side wall of the first trench 101. The conductor layer 17a and the conductor layer 17b are connected, and both conductor layers 17a and 17b can be formed of copper. The conductor layer 17a on the bottom wall of the first trench 101 has a certain thickness, and the thickness of the conductor layer 17a can be set according to a preset value. For example, in this embodiment, the surface of the conductor layer 17a on the bottom wall that faces away from the second adhesive layer 15 can be flush with the surface of the first dielectric layer 13 that is close to the first circuit layer 12.

[0084] like Figure 4B As shown, the conductor layer 17b extending beyond the conductor layer 17a and close to the surface of the first line layer 12 can be removed by means of flash etching or fixed-depth drilling, leaving only the bottom conductor layer 17a, thereby forming the first transmission line 17.

[0085] Please continue reading. Figure 4A and Figure 4B In S60, a second transmission line 23 can be formed at the bottom of the second trench 201 (i.e., the part opposite to the opening of the second trench 201) in a manner similar to that in S40.

[0086] like Figure 4A As shown, a conductor layer 23a can be formed on the bottom wall of the second trench 201 by means of electroplating, but not limited to electroplating, and a conductor layer 23b can be formed on the side wall of the second trench 201. The conductor layer 23a and the conductor layer 23b are connected, and both conductor layers 23a and 23b can be formed of copper. The conductor layer 23a on the bottom wall of the second trench 201 has a certain thickness, and the thickness of the conductor layer 23a can be set according to a preset value. For example, in this embodiment, the surface of the conductor layer 23a on the bottom wall that faces away from the first dielectric layer 13 can be flush with the surface of the second adhesive layer 15 that is close to the second dielectric layer 21.

[0087] like Figure 4B As shown, the conductor layer 23b that extends beyond the surface of the conductor layer 23a and faces away from the first dielectric layer 13 can be removed by means of flash etching or fixed-depth drilling, leaving only the bottom conductor layer 23a, thereby forming the second transmission line 23.

[0088] Please see Figure 5 In step S70, the first transmission line 17 and the second transmission line 23 can be surface treated to form a protective layer 18 on the surface of the first transmission line 17 and a protective layer 24 on the surface of the second transmission line 23. The surface treatment can be, but is not limited to, gold plating, electroless nickel-palladium-gold plating, and the application of organic solderable corrosion inhibitors. The protective layers 18 and 24 can reduce the probability of oxidation of the first transmission line 17 and the second transmission line 23, respectively.

[0089] Please see Figure 6S80, a copper-clad laminate 30a is laminated onto the side of the first adhesive layer 11 opposite to the first circuit layer 12. The copper-clad laminate 30a includes a third dielectric layer 31 and a copper foil layer 32a, with the third dielectric layer 31 located between the first adhesive layer 11 and the copper foil layer 32a. After lamination, the third dielectric layer 31 of the copper-clad laminate 30a covers the opening of the first trench 101, forming an embedded first cavity 102. By adjusting the lamination parameters, the copper-clad laminate 30a can be laminated onto the first adhesive layer 11 while ensuring that the formed first cavity 102 does not collapse. Figure 6 As shown, the first groove 101 is along the thickness direction (i.e. Figure 6 The first cavity 102 is a blank area formed after the first trench 101 forms the first transmission line 17 at its bottom and the opening is covered. The first adhesive layer 11 (including the part that fills the pattern gap of the first circuit layer 12) and the first dielectric layer 13 are penetrated in the vertical direction.

[0090] In some embodiments, such as Figure 6 As shown, the depth of the first trench 101 is H1, the thickness of the first transmission line 17 is h1, and the depth of the first cavity 102 is equal to the depth of the first trench 101 minus the thickness of the first transmission line 17 and its surface protective layer 18. Where h1 ≤ 0.5H1. This ensures that there is sufficient space within the first cavity 102 to accommodate air, thereby effectively reducing the overall dielectric constant of the multilayer circuit board 100 and improving high-frequency transmission performance. The depth of the first cavity 102 can be set as needed for better signal transmission. For example, the depth of the first cavity 102 can be the same as the thickness of the first transmission line 17.

[0091] In some embodiments, if a protective film 16 has been applied in the preceding steps, the protective film 16 needs to be removed before laminating the copper clad laminate 30a.

[0092] Please see Figure 7 S90, the copper foil layer 32a can be fabricated into a fourth circuit layer 32 by means of laser ablation, but not limited to laser ablation, to obtain a multilayer circuit board 100.

[0093] like Figure 7 As shown, in the multilayer circuit board 100, the upper surface of the first transmission line 17 has a ground line (GND) of the fourth circuit layer 32 corresponding to it, and the lower surface has a ground line of the third circuit layer 22 corresponding to it, thus forming a stripline structure. Between the first transmission line 17 and the ground line above it, there is a third dielectric layer 31 and a first adhesive layer 11; between the first transmission line 17 and the ground line below it, there is a second adhesive layer 15 and a second dielectric layer 21. This increases the thickness between the first transmission line 17 and the reference GND, thereby widening the width of the first transmission line 17 to adjust impedance matching and reduce conductor loss.

[0094] Furthermore, by electroplating the bottom of the first trench 101 to create the first transmission line 17, a shorter current path can be provided, thus increasing wiring density and reducing parasitic capacitance and inductance of the first transmission line 17. In high-frequency applications, this helps reduce signal delay and distortion, and also improves signal integrity. Specifically, the design of the depth and width of the first trench 101 allows for the creation of a more compact path in the vertical or horizontal direction, thereby reducing the current transmission distance on the multilayer circuit board 100. This design helps to form a more direct current path, avoiding long-distance transmission and thus reducing parasitic effects caused by the first transmission line 17. In the multilayer circuit board 100, parasitic capacitance is typically generated by the space between conductive parts (such as power and ground). The design of the first trench 101 can reduce capacitive coupling between two conductive parts, further improving signal integrity. Parasitic inductance mainly originates from the magnetic field generated by changes in current flowing through conductors. The first trench 101 can connect conductors with shorter distances, reducing the perimeter of the current loop and thus reducing parasitic inductance. When the current path is shortened, the rate of change of the current flowing through the conductor also decreases accordingly, which can also reduce parasitic inductance.

[0095] Furthermore, by electroplating the bottom of the first trench 101 to fabricate the first transmission line 17, the thickness of the first transmission line 17 can be adjusted according to the thickness of the stack, thereby effectively controlling impedance matching and increasing the flexibility of transmission line design.

[0096] Please see Figures 8 to 11 In some embodiments, it is also possible to... Figure 7 The multilayer circuit board shown continues to add layers and form more transmission lines.

[0097] Please see Figure 8 S100, a third adhesive layer 19 is pressed onto the side of the fourth circuit layer 32 opposite to the third dielectric layer 31, and a third trench 301 can be formed by means of, but not limited to, laser engraving. Along the thickness direction (i.e. Figure 8 (In the vertical direction), the third groove 301 penetrates the third adhesive layer 19, the fourth circuit layer 32 (pattern gap), the third dielectric layer 31 and the first adhesive layer 11.

[0098] Please see Figure 9 In step S110, a third transmission line 33 is formed at the bottom of the third trench 301. The specific fabrication method of the third transmission line 33 can be referred to that of the first transmission line 17, and will not be repeated here.

[0099] Please continue reading. Figure 9 In step S120, a protective layer 34 can be formed on the surface of the third transmission line 33 to reduce the probability of oxidation of the third transmission line 33. The protective layer 34 can be, but is not limited to, gold plating, nickel-palladium-gold plating, organic solderable corrosion inhibitors, etc.

[0100] Please see Figure 10 In step S130, a copper-clad laminate 40a can be laminated on the side of the third circuit layer 22 opposite to the second dielectric layer 21. The copper-clad laminate 40a includes a fourth dielectric layer 41 and a copper foil layer 42a, with the fourth dielectric layer 41 located between the third circuit layer 22 and the copper foil layer 42a. After lamination, the opening of the second trench 201 is covered by the fourth dielectric layer 41, thereby forming a second cavity 202. By adjusting the lamination parameters, it is possible to laminate the copper-clad laminate 40a onto the third circuit layer 22 while ensuring that the formed second cavity 202 does not collapse. Figure 10 As shown, the second groove 201 is along the thickness direction (i.e. Figure 10 The vertical direction of the second cavity 202 penetrates the third line layer 22 (at the pattern gap), the second dielectric layer 21, and the second adhesive layer 15. The second cavity 202 is the blank area formed after the second trench 201 forms the second transmission line 23 at its bottom and the opening is covered.

[0101] In some embodiments, such as Figure 10 As shown, the depth of the second trench 201 is H2, the thickness of the second transmission line 23 is h2, and the depth of the second cavity 202 is equal to the depth of the second trench 201 minus the thickness of the second transmission line 23 and its surface protective layer 24. Where h2 ≤ 0.5H2. This ensures that there is sufficient space within the second cavity 202 to accommodate air, thereby effectively reducing the overall dielectric constant of the multilayer circuit board 100 and improving high-frequency transmission performance. The depth of the second cavity 202 can be set as needed for better signal transmission. For example, the depth of the second cavity 202 can be the same as the thickness of the second transmission line 23.

[0102] Please continue reading. Figure 10 In step S140, a copper-clad laminate 50a can be laminated on the side of the third adhesive layer 19 opposite to the fourth circuit layer 32. The copper-clad laminate 50a includes a fifth dielectric layer 51 and a copper foil layer 52a, with the fifth dielectric layer 51 located between the third adhesive layer 19 and the copper foil layer 52a. After lamination, the opening of the third trench 301 is covered by the fifth dielectric layer 51, thus forming a third cavity 302. By adjusting the lamination parameters, it is possible to laminate the copper-clad laminate 50a onto the third circuit layer 22 while ensuring that the formed third cavity 302 does not collapse. Figure 10 As shown, the third groove 301 is along the thickness direction (i.e. Figure 10 The vertical direction of the third adhesive layer 19, the fourth circuit layer 32 (pattern gap), the third dielectric layer 31 and the first adhesive layer 11 are penetrated. The third cavity 302 is the blank area formed after the third trench 301 forms the third transmission line 33 at its bottom and the opening is covered.

[0103] In some embodiments, such as Figure 10As shown, the depth of the third trench 301 is H3, the thickness of the third transmission line 33 is h3, and the depth of the third cavity 302 is equal to the depth of the third trench 301 minus the thickness of the third transmission line 33 and its surface protective layer 34. Where h3 ≤ 0.5H3. This ensures that there is sufficient space within the third cavity 302 to accommodate air, thereby effectively reducing the overall dielectric constant of the multilayer circuit board 100 and improving high-frequency transmission performance. The depth of the third cavity 302 can be set according to requirements for better signal transmission. For example, the depth of the third cavity 302 can be the same as the thickness of the third transmission line 33.

[0104] Please see Figure 11 S150, copper foil layers 42a and 52a are respectively fabricated to form the fifth circuit layer 42 and the sixth circuit layer 52.

[0105] like Figure 11 As shown, the upper surface of the second transmission line 23 has a ground line (GND) corresponding to the first line layer 12, and the lower surface has a ground line corresponding to the fifth line layer 42, thus forming a stripline structure. The upper surface of the third transmission line 33 has a ground line (GND) corresponding to the sixth line layer 52, and the lower surface has a ground line corresponding to the second line layer 14, thus forming a stripline structure.

[0106] like Figure 11 As shown, along the extension direction of the multilayer circuit board 100 (i.e. Figure 11 The horizontal direction (which can be either the length or the width) of the transmission lines is staggered. That is, the orthographic projections of the first transmission line 17, the second transmission line 23, and the third transmission line 33 along the thickness direction do not overlap.

[0107] Please continue reading. Figure 11 S160, a protective layer 60 may also be provided on the side of the fifth circuit layer 42 opposite to the fourth dielectric layer 41, and on the side of the sixth circuit layer 52 opposite to the fifth dielectric layer 51. The protective layer 60 may be, but is not limited to, a cover film layer (CVL).

[0108] Please see Figure 7 and Figure 11 The second aspect of this application provides a multilayer circuit board 100 prepared by the above-described preparation method, which includes a first circuit board 10 and a second circuit board 20 and a third circuit board 30 located on opposite sides of the first circuit board 10.

[0109] The first circuit board 10 includes a first adhesive layer 11, a first circuit layer 12, a first dielectric layer 13, a second circuit layer 14, and a second adhesive layer 15 arranged sequentially. The first circuit board 10 has a first cavity 102, which penetrates the first dielectric layer 13 and a portion of the first adhesive layer 11 along the thickness direction. A first transmission line 17 is provided at the bottom of the first cavity 102 away from the first adhesive layer 11.

[0110] The second circuit board 20 includes a second dielectric layer 21 and a third circuit layer 22, with the second dielectric layer 21 located between the second adhesive layer 15 and the third circuit layer 22.

[0111] The third circuit board 30 includes a third dielectric layer 31 and a fourth circuit layer 32, with the third dielectric layer 31 located between the first adhesive layer 11 and the fourth circuit layer 32.

[0112] Please see Figure 11 In some embodiments, the multilayer circuit board 100 further includes a fourth circuit board 40 and a second cavity 202. The fourth circuit board 40 includes a fourth dielectric layer 41 and a fifth circuit layer 42, with the fourth dielectric layer 41 located between the third circuit layer 22 and the fifth circuit layer 42. The second cavity 202 penetrates the second adhesive layer 15, the second dielectric layer 21, and the third circuit layer 22 (pattern gap), and a second transmission line 23 is provided near the bottom of the second cavity 202 close to the second adhesive layer 15.

[0113] Please continue reading. Figure 11 In some embodiments, the multilayer circuit board 100 further includes a fifth circuit board 50 and a third cavity 302. The fifth circuit board 50 includes a third adhesive layer 19, a fifth dielectric layer 51, and a sixth circuit layer 52 disposed sequentially. The third adhesive layer 19 is located between the fourth circuit layer 32 and the fifth dielectric layer 51, and the sixth circuit layer 52 is located on the surface of the fifth dielectric layer 51 opposite to the third adhesive layer 19. The third cavity 302 penetrates the third adhesive layer 19, the fourth circuit layer 32 (pattern gap), the third dielectric layer 31, and the first adhesive layer 11. A third transmission line 33 is provided near the bottom of the third cavity 302 close to the first adhesive layer 11.

[0114] The multilayer circuit board 100 and its fabrication method provided in this application embodiment can provide a shorter current path by setting transmission lines at the bottom of the trench. Therefore, the wiring density can be increased, and the parasitic capacitance and parasitic inductance of the transmission lines can be reduced, which helps to reduce signal delay and distortion, and also improve signal integrity, thereby taking into account the requirements of high density and high frequency and high speed transmission.

[0115] The above description describes some specific embodiments of this application, but in actual applications, the application should not be limited to these embodiments. For those skilled in the art, other modifications and alterations made based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A method of manufacturing a multilayer circuit board, characterized by, Includes the following steps: A substrate is provided, the substrate comprising a first adhesive layer, a first circuit layer, a first dielectric layer, a second circuit layer, and a second adhesive layer disposed sequentially. A second dielectric layer and a third circuit layer are laminated onto the side of the second adhesive layer opposite to the second circuit layer; A first trench is formed on the substrate, the first trench penetrating the first adhesive layer and the first dielectric layer; A first transmission line is formed at the bottom of the first trench; A copper-clad laminate is laminated on the side of the first adhesive layer away from the first circuit layer. The copper-clad laminate includes a third dielectric layer and a copper foil layer, with the third dielectric layer located between the first adhesive layer and the copper foil layer. After lamination, the opening of the first trench is covered to form a first cavity. The copper foil layer is used to form a fourth circuit layer, resulting in the multilayer circuit board.

2. The production method according to claim 1, wherein The depth of the first trench is H1, and the thickness of the first transmission line is h1, wherein h1 ≤ 0.5H1.

3. The production method according to claim 1, wherein After the step of laminating the second dielectric layer and the third circuit layer onto the side of the second adhesive layer opposite to the first dielectric layer, the preparation method further includes: A second trench is formed, which penetrates the third circuit layer, the second dielectric layer, and the second adhesive layer; A second transmission line is formed at the bottom of the second trench; A protective layer is formed on the surface of the second transmission line.

4. The production method according to claim 3, wherein The preparation method further includes: A copper-clad laminate is laminated on the side of the third circuit layer away from the second dielectric layer. The copper-clad laminate includes a fourth dielectric layer and a copper foil layer. The fourth dielectric layer is located between the third circuit layer and the copper foil layer. After lamination, the opening of the second trench is covered by the fourth dielectric layer to form a second cavity. The copper foil layer is then fabricated to form the fifth circuit layer; A protective layer is provided on the side of the fifth circuit layer that is opposite to the fourth dielectric layer; The depth of the second trench is H2, and the thickness of the second transmission line is h2, where h2 ≤ 0.5H2.

5. The production method according to claim 1, wherein After the step of forming the fourth circuit layer from the copper foil layer, the preparation method further includes: A third adhesive layer is pressed onto the side of the fourth circuit layer opposite to the third dielectric layer; A third trench is formed, the third trench penetrating the third adhesive layer, the fourth circuit layer, the third dielectric layer, and the first adhesive layer; A third transmission line is formed at the bottom of the third trench; A protective layer is formed on the surface of the third transmission line.

6. The production method according to claim 5, wherein The preparation method further includes: A copper-clad laminate is laminated on the side of the third adhesive layer away from the fourth circuit layer. The copper-clad laminate includes a fifth dielectric layer and a copper foil layer. The fifth dielectric layer is located between the third adhesive layer and the copper foil layer. After lamination, the opening of the third trench is covered by the fifth dielectric layer to form a third cavity. The copper foil layer is then used to form the sixth circuit layer; A protective layer is provided on the side of the sixth circuit layer that is opposite to the fifth dielectric layer; The depth of the third trench is H3, and the thickness of the third transmission line is h3, where h3 ≤ 0.5H3.

7. The production method according to claim 1, wherein The preparation method further includes forming a protective layer on the surface of the first transmission line.

8. A multilayer circuit board, characterized in that, include: The first circuit board includes a first adhesive layer, a first circuit layer, a first dielectric layer, a second circuit layer, and a second adhesive layer arranged sequentially; the first circuit board has a first cavity, the first cavity penetrating the first dielectric layer and a portion of the first adhesive layer, and a first transmission line is provided at the bottom of the first cavity away from the first adhesive layer. The second circuit board includes a second dielectric layer and a third circuit layer, wherein the second dielectric layer is located between the second adhesive layer and the third circuit layer; and The third circuit board includes a third dielectric layer and a fourth circuit layer, wherein the third dielectric layer is located between the first adhesive layer and the fourth circuit layer.

9. The multilayer circuit board as described in claim 8, characterized in that, The multilayer circuit board further includes a fourth circuit board and a second cavity; the fourth circuit board includes a fourth dielectric layer and a fifth circuit layer, the fourth dielectric layer being located between the third circuit layer and the fifth circuit layer; the second cavity penetrates the second adhesive layer, the second dielectric layer and the third circuit layer, and a second transmission line is provided near the bottom of the second adhesive layer in the second cavity.

10. The multilayer circuit board as described in claim 8, characterized in that, The multilayer circuit board further includes a fifth circuit board and a third cavity; the fifth circuit board includes a third adhesive layer, a fifth dielectric layer and a sixth circuit layer arranged sequentially, the third adhesive layer is located between the fourth circuit layer and the fifth dielectric layer, and the sixth circuit layer is located on the surface of the fifth dielectric layer opposite to the third adhesive layer; the third cavity penetrates the third adhesive layer, the fourth circuit layer, the third dielectric layer and the first adhesive layer, and a third transmission line is provided near the bottom of the first adhesive layer in the third cavity.

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