A current sharing structure based on parallel connection of PCB embedded devices

Abstract

This application relates to a current sharing structure based on parallel connection of PCB embedded devices. The current sharing structure includes: a PCB stack-up structure, a three-dimensional symmetrical circuit structure, and an active current sharing structure. The PCB stack-up structure includes a PCB substrate and multiple parallel-connected PCB embedded power devices. These multiple parallel-connected PCB embedded power devices are embedded in the PCB substrate and grouped into minimum power units, each of which has a current island. The three-dimensional symmetrical circuit structure includes power loops and drive loops to ensure symmetry of the current path and drive signal for each power device. The active current sharing structure includes distributed current sensing units independently configured for each power device, used to achieve physical current separation and detection of current in each branch, and works in conjunction with the three-dimensional symmetrical circuit structure to achieve dynamic active current sharing. This improves the consistency of parallel current sharing, enables measurable and controllable branch currents, and supports high-density intelligent power integration.

Description

Technical Field

[0001] This application mainly relates to the field of power electronics technology, and in particular to a current sharing structure based on parallel connection of PCB embedded devices. Background Technology

[0002] In high-power power electronic devices, multiple power semiconductor devices often need to be connected in parallel to carry larger currents. However, uneven current distribution in each branch during parallel operation is a key technical challenge. Uneven current distribution can cause overloaded devices to overheat, degrade in performance, or even fail, severely limiting the overall capacity and reliability of the system.

[0003] Meanwhile, when multiple devices are embedded in a PCB and operate in parallel, their current sharing design and testing face a fundamental challenge that traditional surface mount technology does not present: the parallel devices are encapsulated together inside the PCB medium, and their current paths are physically intertwined or even share part of the inner layer plane, making it impossible to measure the operating current of each individual device directly and non-destructively from the outside.

[0004] Traditional passive parallel current sharing solutions rely on symmetrical layouts, optimizing PCB two-dimensional routing to ensure consistent parasitic parameters. However, under high frequency and high current conditions, the three-dimensional electromagnetic field distribution is complex, making it difficult to achieve ideal current sharing with simple two-dimensional symmetry, resulting in limited design margins. Active current sharing relies on current sampling and control. In PCB embedded scenarios, the output current of each parallel branch is internally merged and then uniformly led out to the surface terminals, losing the ability to independently monitor the operating status of individual devices and thus failing to perform active current sharing.

[0005] Therefore, in PCB embedded scenarios, there is an urgent need for a method that can achieve active current sharing and passive current sharing in tandem, enabling real-time measurement of the current of individual devices and embedding the current sharing capability into the PCB of the power module. Summary of the Invention

[0006] One objective of this application is to provide a current sharing structure based on parallel connection of PCB embedded devices, which solves the problems of unmeasurable current and current sharing of parallel devices in the prior art in PCB embedded scenarios.

[0007] According to one aspect of this application, a current sharing structure based on parallel connection of PCB embedded devices is provided, the current sharing structure including: PCB stack-up structure, three-dimensional symmetrical circuit structure and active current sharing structure; The PCB stack-up structure includes a PCB substrate and multiple parallel PCB embedded power devices. The multiple parallel PCB embedded power devices are embedded in the PCB substrate and grouped into minimum power units, each of which is equipped with a current island. The three-dimensional symmetrical circuit structure includes a power circuit and a drive circuit, which are used to ensure the symmetry of the current path and drive signal of each power device. The active current sharing structure includes a distributed current sensing unit independently set for each power device, used to realize physical current separation and detection of current in each branch, and in conjunction with the three-dimensional symmetrical circuit structure, to achieve dynamic active current sharing.

[0008] Optionally, the PCB substrate includes, from top to bottom, at least a PCB surface layer, a first signal layer, a first power layer, a second power layer, a second signal layer, a current detection layer, a chip embedding layer, and a PCB bottom layer.

[0009] Optionally, passive current sharing is achieved based on the three-dimensional symmetrical circuit structure, wherein a connection structure of parallel branches is formed in the power circuit through the first power layer and the second power layer, so that the current paths of each parallel branch overlap on the projection perpendicular to the PCB plane. In the drive circuit, the gate drive signal line extends to each power device in a symmetrical routing pattern within the PCB layer, and the drive line and power circuit are arranged orthogonally in space.

[0010] Optionally, the plurality of parallel PCB embedded power devices are embedded in the chip embedding layer in a mirror-symmetric manner, with each pair of power devices forming a minimum power unit, and copper is deposited and etched on each minimum power unit to form a first current island. The source of the power device is connected to the current detection layer through a copper-plated buried via, and the drain is connected to the corresponding power layer through a copper-plated buried via.

[0011] Optionally, the drain is connected to the corresponding power layer through a copper-plated buried via to satisfy the following conditions: the smallest power units in parallel are connected to the same power layer at the same potential point; the drain and source of the upper tube forming the bridge arm are connected to the second power layer; the source of the lower tube forming the bridge arm is connected to the first power layer, and the drain of the lower tube is connected to the second power layer.

[0012] Optionally, the total length of the current path flowing through each power device, the number of interlayer vias, and the area of ​​the parasitic inductance loop are matched in three-dimensional space.

[0013] Optionally, in the power circuit, the DC input bus consists of a common conductive region on the second power layer and the drain of the smallest power unit connected by a symmetrical via array; the AC output bus consists of a common conductive region on the second power layer, a symmetrical via array, and a current collecting copper layer on the current sensing layer connected to the symmetrical via array.

[0014] Optionally, the number, aperture, and spacing of the symmetrical via array are consistent.

[0015] Optionally, the minimum power unit includes a first current island, a copper-plated buried via array, and a miniature current sensor; the first current island is an independent conductive area that surrounds the source pad and via array of the power device, is etched, and is isolated by an insulating trench. The copper-plated buried via array penetrates upward through the dielectric layer and connects to the second current island disposed in the current detection layer; The miniature current sensor is integrated at the end of the conductive region, and the signal output terminal is connected to the signal conditioning circuit or additional surface signal pad on the first signal layer.

[0016] Optionally, a current sharing controller is provided on the surface of the PCB to collect the current signals of each branch in real time, calculate the current difference based on the collected current signals, and dynamically adjust the voltage or timing of the gate drive signals of each power device.

[0017] Compared with existing technologies, this application utilizes a PCB stack-up structure, a three-dimensional symmetrical circuit structure, and an active current sharing structure. The PCB stack-up structure includes a PCB substrate and multiple parallel PCB-embedded power devices. These parallel PCB-embedded power devices are embedded in the PCB substrate and grouped into minimum power units, each with a current island. The three-dimensional symmetrical circuit structure includes power loops and drive loops to ensure symmetry in the current paths and drive signals of each power device. The active current sharing structure includes distributed current sensing units independently configured for each power device, used to achieve physical current separation and detection of current in each branch, and works in conjunction with the three-dimensional symmetrical circuit structure to achieve dynamic active current sharing. This improves the consistency of parallel current sharing, enables measurable and controllable branch currents, and supports high-density intelligent power integration. Attached Figure Description

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 An exploded view of a current sharing structure based on parallel connection of PCB embedded devices is shown according to one aspect of this application; Figure 2 This is a top view of a structure in one embodiment of the present application, showing the overlapping of the PCB surface layer, power layer, and chip embedding layer; Figure 3 This diagram shows a planar structure of the chip embedding layer and the current detection layer in one embodiment of this application.

[0019] Figure label: 1 PCB surface layer 2 First Signal Layer 3 First Power Layer 4 Second power layer 5 Second signal layer 6 Current Detection Layer 7. Chip Embedding Layer 8 PCB bottom layer 9 Current-collecting copper layer 10 Copper-plated buried vias 11 Minimum Power Unit 12 Copper-plated buried holes II 13 First Current Island 14 Power Chips 15 Current Sensor 16 Second Current Island 17 Symmetrical drive circuit 18 Drive Convergence Points The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0020] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0021] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.

[0022] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] Furthermore, the terms “up,” “down,” “left,” “right,” “top,” “bottom,” “horizontal,” and “vertical” used in the following description should be understood as the orientations shown in the paragraph and related figures. This relative terminology is for illustrative purposes only and does not imply that the described device must be manufactured or operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0024] It is understood that although terms such as “first,” “second,” “third,” etc., may be used here to describe various pipes, channels, components, areas, layers, and / or parts, these components, areas, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different pipes, channels, components, areas, layers, and / or parts.

[0025] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0026] (1) PCB embedded devices refer to power semiconductor devices that achieve three-dimensional interconnection with the inner layer circuit of PCB through advanced packaging processes such as embedding and cavity, forming highly integrated modules.

[0027] (2) A current black box refers to a system whose current is limited by physical structure and cannot be directly measured in a specific path.

[0028] (3) Current separation path refers to a dedicated conductive path created inside the PCB for the current of a single device, which is electrically isolated from other branches.

[0029] Figure 1 An exploded view of a current sharing structure based on parallel PCB embedded devices according to one aspect of this application is shown. The current sharing structure includes: a PCB stack-up structure, a three-dimensional symmetrical circuit structure, and an active current sharing structure. The PCB stack-up structure includes a PCB substrate and multiple parallel PCB embedded power devices. The multiple parallel PCB embedded power devices are embedded in the PCB substrate and grouped into minimum power units 11, each minimum power unit 11 having a current island. The three-dimensional symmetrical circuit structure includes a power loop and a drive loop to ensure symmetry of the current path and drive signal of each power device. The active current sharing structure includes a distributed current sensing unit independently configured for each power device to achieve physical current separation and detection of current in each branch, and to coordinate with the three-dimensional symmetrical circuit structure to achieve dynamic active current sharing.

[0030] This current sharing structure does not rely solely on control algorithms to achieve current sharing. Instead, it first constructs symmetrical parallel branches at the physical structure level, making each power device as consistent as possible in terms of current path length, number of interlayer vias, parasitic parameters, and propagation conditions of drive signals. This forms a natural passive current sharing foundation at the structural level. On this basis, the branch current is detected by the distributed current sensing unit of each branch, and closed-loop calibration is performed in conjunction with the current sharing controller to compensate for the residual current unevenness caused by differences in device parameters, temperature rise, and operating condition disturbances.

[0031] Active current sharing is achieved through integrated distributed current sensing and control. Specifically, in terms of current isolation and routing, an independent current island surrounded by insulating trenches is designed on the inner layer of the PCB corresponding to the source of each device, and connected to the lower layer isolation leads through vertical interconnect holes, thereby forcibly achieving physical current isolation. In terms of sensing unit integration, a miniature current sensing structure is integrated in the PCB dielectric layer above the source current loop of each power device using PCB manufacturing processes. The signal output lines of these sensors are directly led to the adjacent inner layer signal processing area through microvias or buried vias, or led out to the surface for easy testing. In terms of system coordination, passive current sharing provides the system with excellent initial current sharing characteristics and a high-frequency electromagnetic environment, significantly reducing the compensation range and bandwidth pressure required for active control; active current sharing, on this basis, performs fine calibration and dynamic adaptation, and the two work together to achieve better parallel branch current consistency.

[0032] In one embodiment of this application, the PCB substrate includes, from top to bottom, at least a PCB surface layer 1, a first signal layer 2, a first power layer 3, a second power layer 4, a second signal layer 5, a current detection layer 6, a chip embedding layer 7, and a PCB bottom layer 8.

[0033] The layers of the PCB substrate function in tandem. The PCB surface layer 1 can be used to arrange surface-mount devices and current sharing control components; the first signal layer 2 and the second signal layer 5 are mainly used for the routing of drive signals, sensing signals, and signal conditioning circuits. The second signal layer 5 serves both as an auxiliary signal layer for transmitting control signals and as a collection layer for the current passing through the current sensor 15 from the same minimum power unit; the first power layer 3 and the second power layer 4 are mainly used for power current transmission, busbar construction, and bridge arm potential connection; the current detection layer 6 is used for the extraction, collection, and detection path construction of branch currents; the chip embedding layer 7 is used to embed the power chip 14 and form the minimum power unit 11; the PCB bottom layer 8, together with the other layers, forms a complete PCB stack-up structure and provides mechanical support, insulation, and bottom routing. Through this multi-layer stack-up method, the three-dimensional integration of power circuits, drive circuits, and branch current detection circuits can be achieved simultaneously within a limited volume.

[0034] exist Figure 2 The illustrated embodiment shows a top view of the overlapping structure of the PCB surface layer 1, the power layer, and the chip embedding layer 7. Passive current sharing is achieved based on the three-dimensional symmetrical circuit structure. In the power loop, the first power layer 3 and the second power layer 4 form a parallel branch connection structure, so that the current paths of each parallel branch overlap on the projection perpendicular to the PCB plane. In the drive loop, the gate drive signal lines extend to each power device in a symmetrical routing pattern within the PCB layer, and the drive lines and the power loop are arranged orthogonally in space.

[0035] Passive current sharing based on a three-dimensional symmetrical circuit structure mainly consists of two parts: power loop symmetry and drive loop symmetry. For power loop symmetry, the DC bus input and AC output terminals of the power devices are connected through a three-dimensional symmetrical bridge formed by multiple layers of copper foil within the PCB. Specifically, the physical paths through which the power current flows in each parallel branch overlap on the projection perpendicular to the PCB plane, and the path lengths, via numbers, and adjacent loop areas are equal or matched. This minimizes the differences in parasitic resistance, parasitic inductance, and coupling conditions among the branches, ensuring that the parallel branches have similar current distribution conditions during turn-on, turn-off, and steady-state conduction.

[0036] For symmetrical drive circuits, the gate drive signal lines of each power device are symmetrically routed from a common drive source within the PCB. Specifically, symmetrical routing methods such as star-shaped radial or parallel serpentine patterns can be used to ensure high consistency in transmission delay and waveform integrity of the drive signals reaching each gate. In practical applications, the drive lines and power circuits are spatially orthogonal or isolated to reduce magnetic field coupling and crosstalk between the drive signal circuit and the high-current power circuit.

[0037] Specifically, the three-dimensional symmetrical drive circuit is characterized by starting from the drive convergence point 18, passing through symmetrical drive lines 17 of equal length to the upper layer of the four power chips 14 respectively, and then connecting to the gate and source / emitter of the power chip 14 through corresponding vias, so as to ensure that each power chip 14 receives a drive signal of equal amplitude at the same time.

[0038] exist Figure 3 The illustrated embodiment shows a schematic diagram of the planar structure of the chip embedding layer 7 and the current sensing layer 6. The plurality of parallel PCB embedded power devices are embedded in the chip embedding layer 7 in a mirror-symmetrical manner. Each pair of power devices forms a minimum power unit 11, and copper plating and etching are performed on each minimum power unit 11 to form a first current island 13. The source of each power device is connected to the current sensing layer 6 through copper-plated buried vias, and the drain is connected to the corresponding power layer through copper-plated buried vias.

[0039] Four power chips 14 are embedded in the chip embedding layer 7 in a mirror-symmetrical manner, with each pair of power chips 14 forming a minimum power unit 11. This mirror-symmetrical arrangement ensures that adjacent parallel branches maintain as consistent a spatial distribution, thermal distribution, and upper / lower layer connection conditions as possible. Copper is deposited and etched onto the minimum power unit 11 to form a first current island 13. This first current island 13 surrounds the source pads and corresponding via arrays of the power chips 14, serving as the necessary area for branch current to flow out of the device, while also being electrically isolated from other copper areas through insulation. The source (S) of the power chip 14 is connected to the current sensing layer 6 via a copper-plated buried via 12, allowing the source current of each parallel branch to be introduced into the corresponding sensing channel; the drain of the power chip 14 is connected to the corresponding power layer via a copper-plated buried via, thus being incorporated into the power current path of the bridge arm.

[0040] Furthermore, the drain is connected to the corresponding power layer through a copper-plated buried via to satisfy the following conditions: the smallest power units 11 connected in parallel are connected to the same power layer at the same potential point; the drain and source of the upper tube forming the bridge arm are connected to the second power layer 4; the source of the lower tube forming the bridge arm is connected to the first power layer 3, and the drain of the lower tube is connected to the second power layer 4.

[0041] In practical applications, a single fixed inter-layer connection method is not used as the only implementation method. Instead, the principle is to connect the same potential points of the parallel minimum power units 11 to the same layer. The connection method will affect the circuit noise, but when the condition of "the same potential points of the parallel minimum power units are connected to the same layer" is met, the basic symmetry required for passive current sharing can be guaranteed.

[0042] In one embodiment of this application, the total length of the current path flowing through each power device, the number of interlayer vias, and the area of ​​the parasitic inductance loop are matched in three-dimensional space.

[0043] Through the aforementioned stacked design, mirror-symmetric embedding method, symmetrical via array, and power layer connection structure, the total physical path length of the power current flowing through each power device from the DC input terminal to the AC output terminal, the number of interlayer vias, and the area of ​​the main parasitic inductance loop formed by the traces and vias are matched in three-dimensional space.

[0044] In one embodiment of this application, in the power circuit, the DC input bus is composed of a common conductive area on the second power layer 4 and the drain of the smallest power unit 11 connected by a symmetrical via array; the AC output bus is composed of a common conductive area on the second power layer 4, a symmetrical via array, and a current collecting copper layer 9 on the current detection layer 6 connected to the symmetrical via array.

[0045] A three-dimensional symmetrical power circuit can be represented, taking the upper tube forming the bridge arm as an example, as follows: the DC positive input bus is composed of a common conductive region located on the second power layer 4, and the drain of the smallest power unit 11 located in the chip embedding layer 7, which is vertically interconnected with it through a symmetrical via array. The number, aperture, and spacing of this symmetrical via array are the same to ensure the consistency of interlayer conductivity and parasitic parameters of each parallel branch.

[0046] The AC output bus is formed by a common conductive area on the second power layer 4, a conductive collection structure in the current sensing layer 6 connected to it via a symmetrical via array, and a via structure connected to the source of the minimum power unit 11. In this embodiment, the conductive collection structure in the current sensing layer 6 can be composed of a current collecting copper layer 9, which, after being connected to the symmetrical via array, realizes current guidance and interlayer connection on the AC output side of each branch, and is connected to the source of the minimum power unit 11 through the corresponding via structure. The power chip 14 forms a first current island 13 on the minimum power unit 11 by etching, and the branch current is separated and guided through the first current island 13 when flowing through the source region.

[0047] Furthermore, the number, aperture, and spacing of the symmetrical via array are consistent.

[0048] Continue to refer to Figure 1 The copper-plated buried vias 10 and 12 shown in the figure are used to achieve vertical electrical connections between different layers. In practical applications, the copper-plated buried vias 10 and 12 can be used in parallel branches with the same or symmetrical number, diameter, and spacing to further ensure the consistency of the current path in each branch.

[0049] In one embodiment of this application, the minimum power unit 11 includes a first current island 13, a copper-plated buried via array, and a miniature current sensor; the first current island 13 is an independent conductive region formed by etching and isolated by an insulating trench, surrounding the source pad and via array of the power device; the copper-plated buried via array penetrates upward through the dielectric layer and is connected to a second current island 16 disposed in the current detection layer 6; the miniature current sensor is integrated at the end of the conductive region, and its signal output terminal is connected to a signal conditioning circuit or an additional surface signal pad on the first signal layer 2.

[0050] The integrated branch current isolation and sensing channel structure is the core of achieving independent current monitoring, and an independent set can be set for each parallel power device. For each device, an independent conductive region, defined as the first current island 13, is etched around its source pad and via array on the smallest power unit 11, completely isolated from other copper areas by annular or square insulating trenches. This first current island 13 is the necessary path for the source current of the device to flow out and achieves physical isolation from the current of other devices.

[0051] A dedicated array of copper-plated buried vias 12 extends from the first current island 13. This array passes through the corresponding dielectric layer and connects to the second current island 16 disposed in the current sensing layer 6. The second current island 16 constitutes a dedicated conductive region for further guiding the branch current, used in conjunction with the current sensor 15 to form a branch current sensing channel. In this embodiment, the miniature current sensor 15 is disposed at the end of the conductive region, preferably a miniature current sensor chip based on the Hall effect principle. The signal output terminal of the current sensor 15 is connected to the signal conditioning circuit on the first signal layer 2 via fine traces and vias, or directly to an additional surface-mount signal pad.

[0052] The copper-plated buried via array 12 serves to introduce current from the chip embedding layer 7 into the detection path of the current detection layer 6; the copper-plated buried via array 10 serves to further vertically guide the current passing through the current sensor 15 to the second signal layer 5. When the current flows from the second current island 16 to the current sensor 15, it can be turned on through the pins of the current sensor 15 itself without passing through additional vias. The vias corresponding to the control signals are not shown in the attached drawings.

[0053] In one embodiment of this application, a current sharing controller is provided on the surface layer of the PCB to collect the current signals of each branch in real time, calculate the current difference based on the collected current signals, and dynamically adjust the voltage or timing of the gate drive signals of each power device.

[0054] The power module further includes a current sharing controller located on the PCB surface. The current signal input terminal of the current sharing controller is connected to the signal output terminal of the current sensor 15 of each branch, and its drive signal output terminal is connected to the gate drive circuit of each power device. The current sharing controller is configured to: acquire the current signal of each parallel branch in real time, calculate the difference between the currents of each branch, and dynamically adjust the voltage amplitude, drive timing, or a combination of both of the gate drive signal applied to each power device based on the difference results, in order to compensate for current unevenness caused by slight deviations in device parameters, differences in thermal distribution, or asymmetric operating conditions. For devices with smaller currents, the current flowing through the device is increased by reducing the current sharing resistance or increasing the gate drive signal voltage, thereby achieving current sharing.

[0055] The present invention has been further described in a non-limiting manner with reference to the preferred embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments, not all embodiments. The above embodiments are illustrated using a power module comprising four parallel PCB-embedded power devices, with each pair of devices forming a minimum power unit; however, the present invention is not limited to this and can be extended to multiple devices connected in parallel.

[0056] A simplified three-dimensional symmetry approach can be adopted, where strict three-dimensional symmetry is implemented only in the critical converter loops that most significantly affect dynamic current sharing, while other auxiliary connections can use conventional symmetrical wiring. If full integration is not required, spaces can be reserved during the design phase to allow testing from externally clip-on or snap-on miniature current probes to designated current feed areas after module packaging. Partial branch monitoring scheme: When cost is extremely limited, current isolation and sensing channels can be designed only for the critical or representative branches most likely to experience current imbalance, with other branches relying on symmetry for protection. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection.

[0057] This application addresses the challenges of current sharing in PCB-embedded parallel devices under high-frequency switching conditions, including difficulties in independent monitoring of branch currents and the integration of distributed sensing into high-density packages. It proposes a PCB-embedded device parallel current sharing structure that balances passive and active current sharing. First, to address the severe dynamic current imbalance caused by transient parasitic parameter differences due to asymmetrical layout between parallel branches, a physical architecture for an embedded PCB power module with a three-dimensional symmetrical bus and symmetrical drive circuit is proposed and constructed. Through the three-dimensional physical symmetry design, the total loop inductance, resistance, and drive loop impedance of each parallel branch are precisely matched, providing an excellent initial current sharing foundation for the parallel devices and effectively suppressing dynamic current imbalance.

[0058] To address the issue of embedded parallel devices forming a "black box" after current convergence, making independent monitoring impossible, a built-in current isolation and test channel was designed. By creating an electrical isolation channel consisting of a first current island, a second current island, and a dedicated buried via array for the current path of each device, the "invisible and unmeasurable" state of branch current is fundamentally broken, enabling in-situ measurement of the current in each parallel branch. This provides a direct and clear signal path for testing, fault diagnosis, and current sharing control.

[0059] Furthermore, addressing the challenge of integrating distributed current sensing solutions into high-density embedded packages, a miniature current sensing structure is integrated using PCB technology at key locations in the current separation channel. This achieves compact, embedded, in-situ sensing of branch currents, providing a localized and precise feedback signal source for active current sharing. This fundamentally integrates passive and active current sharing. The three-dimensional symmetrical passive structure lays an excellent foundation for initial current sharing, suppressing dynamic current imbalances to a minimum. The integrated current sensing provides precise feedback for active drive control, enabling the system to perform fine calibration and dynamic adaptation based on branch current differences, further improving the consistency and stability of parallel operation.

[0060] Therefore, the technical solution proposed in this application not only realizes branch-level current monitoring of high-density embedded parallel power devices, but also embeds the symmetrical structure and sensing structure required for current sharing into the power carrier PCB, promoting the integration of high-density intelligent power modules and providing a feasible technical path for developing next-generation intelligent power modules with higher power density, higher reliability and self-monitoring and self-regulation capabilities.

[0061] The basic concepts have been described above. Obviously, for those skilled in the art, the above disclosure is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0062] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0063] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. A current sharing structure based on parallel connection of PCB embedded devices, characterized in that, The current sharing structure includes: PCB stack-up structure, three-dimensional symmetrical circuit structure and active current sharing structure; The PCB stack-up structure includes a PCB substrate and multiple parallel PCB embedded power devices. The multiple parallel PCB embedded power devices are embedded in the PCB substrate and grouped into minimum power units, each of which is equipped with a current island. The three-dimensional symmetrical circuit structure includes a power circuit and a drive circuit, which are used to ensure the symmetry of the current path and drive signal of each power device. The active current sharing structure includes a distributed current sensing unit independently set for each power device, used to realize physical current separation and detection of current in each branch, and in conjunction with the three-dimensional symmetrical circuit structure, to achieve dynamic active current sharing.

2. The flow equalization structure according to claim 1, characterized in that, The PCB substrate, from top to bottom, includes at least a PCB surface layer, a first signal layer, a first power layer, a second power layer, a second signal layer, a current detection layer, a chip embedding layer, and a PCB bottom layer.

3. The flow equalization structure according to claim 2, characterized in that, Passive current sharing is achieved based on the three-dimensional symmetrical circuit structure, wherein a connection structure of parallel branches is formed in the power circuit through the first power layer and the second power layer, so that the current paths of each parallel branch overlap on the projection perpendicular to the PCB plane. In the drive circuit, the gate drive signal line extends to each power device in a symmetrical routing pattern within the PCB layer, and the drive line and power circuit are arranged orthogonally in space.

4. The flow equalization structure according to claim 2, characterized in that, The multiple parallel PCB embedded power devices are embedded in the chip embedding layer in a mirror-symmetric manner. Each pair of power devices forms a minimum power unit, and copper is deposited and etched on each minimum power unit to form a first current island. The source of the power device is connected to the current detection layer through a copper-plated buried via, and the drain is connected to the corresponding power layer through a copper-plated buried via.

5. The flow equalization structure according to claim 4, characterized in that, The drain electrode is connected to the corresponding power layer via a copper-plated buried via to satisfy the following: The smallest power units connected in parallel are connected to the same power layer at the same potential point; The drain and source of the upper transistor in the bridge arm are connected to the second power layer; The source of the lower transistor forming the bridge arm is connected to the first power layer, and the drain of the lower transistor is connected to the second power layer.

6. The flow equalization structure according to claim 1, characterized in that, The total length of the current path flowing through each power device, the number of interlayer vias, and the area of ​​the parasitic inductance loop are matched in three-dimensional space.

7. The flow equalization structure according to claim 2, characterized in that, In the power circuit, the DC input bus consists of a common conductive region on the second power layer and the drain of the smallest power unit connected by a symmetrical via array; The AC output bus consists of a common conductive area on the second power layer, a symmetrical via array, and a current collecting copper layer on the current sensing layer connected to the symmetrical via array.

8. The flow equalization structure according to claim 7, characterized in that, The number, aperture, and spacing of the symmetrical via array are consistent.

9. The flow equalization structure according to claim 2, characterized in that, The minimum power unit includes a first current island, a copper-plated buried via array, and a miniature current sensor. The first current island is an independent conductive region that surrounds the source pads and via array of the power device, is etched, and is isolated by an insulating trench. The copper-plated buried via array penetrates upward through the dielectric layer and connects to the second current island disposed in the current detection layer; The miniature current sensor is integrated at the end of the conductive region, and the signal output terminal is connected to the signal conditioning circuit or additional surface signal pad on the first signal layer.

10. The flow equalization structure according to claim 2, characterized in that, A current sharing controller is installed on the surface of the PCB to collect the current signals of each branch in real time, calculate the current difference based on the collected current signals, and dynamically adjust the voltage or timing of the gate drive signals of each power device.

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