Semiconductor device

Abstract

A semiconductor device includes: a substrate; a plurality of semiconductor patterns stacked and spaced apart from each other on the substrate; a bit line connected to a first end of the plurality of semiconductor patterns in a first direction and extending in a direction perpendicular to an upper surface of the substrate; a word line overlapping each of the plurality of semiconductor patterns in the direction perpendicular to the upper surface of the substrate and extending in a second direction intersecting the first direction; a capacitor connected to a second end of each of the plurality of semiconductor patterns in the first direction; a metal silicide pattern located between each semiconductor pattern and the capacitor; and an intermediate insulating layer overlapping the metal silicide pattern in the direction perpendicular to the upper surface of the substrate.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] The demand for technologies that increase the integration density of semiconductor devices is growing. In the case of two-dimensional semiconductor devices, the integration density is primarily determined by the area occupied by a unit memory cell, and this integration density may depend on the level of fine patterning technology.

[0003] However, fine patterning techniques require expensive equipment, so the integration density of two-dimensional semiconductor devices remains limited despite continuous improvements. Therefore, three-dimensional semiconductor memory devices in which memory cells are arranged in a three-dimensional structure have been proposed. Summary of the Invention

[0004] Some aspects of this disclosure provide a semiconductor device with improved element characteristics.

[0005] A semiconductor device according to some implementations includes: a substrate; a plurality of semiconductor patterns stacked and spaced apart from each other on the substrate; a bit line connected to a first end of the plurality of semiconductor patterns in a first direction and extending in a direction perpendicular to an upper surface of the substrate; a word line overlapping each of the plurality of semiconductor patterns in the direction perpendicular to the upper surface of the substrate and extending in a second direction intersecting the first direction; a capacitor connected to a second end of each of the plurality of semiconductor patterns in the first direction; a metal silicide pattern located between each semiconductor pattern and the capacitor; and an intermediate insulating layer overlapping the metal silicide pattern in the direction perpendicular to the upper surface of the substrate.

[0006] A semiconductor device according to some implementations includes: a substrate; a plurality of semiconductor patterns stacked and spaced apart from each other on the substrate; a bit line connected to a first end of the plurality of semiconductor patterns in a first direction and extending in a direction perpendicular to an upper surface of the substrate; a word line overlapping each of the plurality of semiconductor patterns in the direction perpendicular to the upper surface of the substrate and extending in a second direction intersecting the first direction; a capacitor connected to a second end of each of the plurality of semiconductor patterns in the first direction; a metal silicide pattern located between each semiconductor pattern and the capacitor; and an intermediate insulating layer surrounding the metal silicide pattern.

[0007] A semiconductor device according to some implementations includes: a substrate; an intermediate insulating layer extending in a direction perpendicular to an upper surface of the substrate; a plurality of metal silicide patterns spaced apart by the intermediate insulating layer; a plurality of semiconductor patterns respectively connected to a first side surface of the plurality of metal silicide patterns in a first direction; bit lines connected to a first end of the plurality of semiconductor patterns in the first direction and extending in the direction perpendicular to the upper surface of the substrate; a plurality of word lines respectively adjacent to the plurality of semiconductor patterns and extending in a second direction intersecting the first direction; and a plurality of capacitors respectively connected to a second side surface of the plurality of metal silicide patterns in the first direction, wherein the intermediate insulating layer is located on two opposite sides of each of the plurality of metal silicide patterns in the second direction and on two opposite sides of each of the plurality of metal silicide patterns in the direction perpendicular to the upper surface of the substrate.

[0008] A method of manufacturing a semiconductor device according to some implementations may include: forming a preliminary intermediate insulating layer that penetrates a plurality of first semiconductor layers and a plurality of second semiconductor layers on the substrate in a direction perpendicular to an upper surface of the substrate; forming a unit isolation insulating layer that penetrates the plurality of first semiconductor layers and the plurality of second semiconductor layers on the substrate in the direction perpendicular to the upper surface of the substrate and is separated in a first direction parallel to the upper surface of the substrate and in a second direction intersecting the first direction; removing the plurality of first semiconductor layers and thinning the plurality of second semiconductor layers to form a plurality of semiconductor patterns spaced apart and stacked in a third direction perpendicular to the upper surface of the substrate; removing a portion of the preliminary intermediate insulating layer to expose one end of the plurality of semiconductor patterns in the first direction; forming a plurality of sacrificial metal silicide patterns covering one end of the plurality of semiconductor patterns in the first direction; and forming an intermediate insulating layer overlapping the plurality of sacrificial metal silicide patterns in the third direction.

[0009] The cell isolation insulating layer may include an intermediate cell isolation insulating layer and a side cell isolation insulating layer, the intermediate cell isolation insulating layer being located on one side surface of the intermediate insulating layer in the first direction, and the side cell isolation insulating layer being located on another side surface of the intermediate insulating layer in the first direction. The plurality of semiconductor patterns may include a plurality of first semiconductor patterns and a plurality of second semiconductor patterns, the plurality of first semiconductor patterns being located on one side surface of the plurality of sacrificial metal silicide patterns in the first direction, and the plurality of second semiconductor patterns being located on another side surface of the plurality of sacrificial metal silicide patterns in the first direction. The method of manufacturing a semiconductor device may further include: etching the intermediate cell isolation insulating layer until one side surface of the intermediate insulating layer in the first direction is exposed to expose the plurality of first semiconductor patterns; forming word lines on the plurality of first semiconductor patterns; and forming bit lines connected to one end of the plurality of first semiconductor patterns in the first direction.

[0010] The method of manufacturing a semiconductor device may include: etching the side cell isolation layer until the other side surface of the intermediate insulating layer in the first direction is exposed to expose the plurality of second semiconductor patterns; forming a capacitor mold between the plurality of second semiconductor patterns; removing the plurality of second semiconductor patterns; and removing the plurality of sacrificial metal silicide patterns to expose the other ends of the plurality of first semiconductor patterns in the first direction.

[0011] The method of manufacturing a semiconductor device may include: forming a plurality of metal silicide patterns covering another end of the plurality of first semiconductor patterns in the first direction; and forming a plurality of capacitors on the plurality of metal silicide patterns.

[0012] Each of the plurality of metal silicide patterns may be located between the capacitor and the semiconductor pattern, and may overlap with the intermediate insulating layer in the third direction. Each of the plurality of metal silicide patterns may further overlap with the intermediate insulating layer in the second direction.

[0013] In some implementations, the two side surfaces of each of the plurality of metal silicide patterns in the third direction and the two side surfaces of each of the plurality of metal silicide patterns in the second direction may contact the intermediate insulating layer.

[0014] In some implementations, the width of each of the plurality of metal silicide patterns in the third direction may be the same as the width of each of the plurality of first semiconductor patterns in the third direction. The width of each of the plurality of metal silicide patterns in the second direction may be the same as the width of each of the plurality of first semiconductor patterns in the second direction.

[0015] In some implementations, the width of each of the plurality of metal silicide patterns in the first direction may be smaller than the width of the intermediate insulating layer in the first direction.

[0016] The steps of forming the plurality of capacitors may include: forming a plurality of first electrodes on the plurality of metal silicide patterns; removing the capacitor mold; and forming a dielectric layer and a second electrode covering the plurality of first electrodes.

[0017] Depending on the implementation method, the component characteristics of semiconductor devices can be improved. Attached Figure Description

[0018] Figure 1 It is a top view of a semiconductor device based on some implementation methods.

[0019] Figure 2 It is along Figure 1 A cross-sectional view of a semiconductor device according to some implementations, taken by line A-A'.

[0020] Figure 3 It is along Figure 1 A cross-sectional view of a semiconductor device taken by line B-B' according to some implementation methods.

[0021] Figure 4 It is along Figure 1 A cross-sectional view of a semiconductor device taken by line C-C' according to some implementation methods.

[0022] Figure 5 yes Figure 2 Enlarged cross-sectional view of region P.

[0023] Figure 6 and Figure 7 It is an enlarged cross-sectional view of a semiconductor device based on some implementation methods.

[0024] Figure 8 and Figure 9 It is a cross-sectional view of a semiconductor device based on some implementation methods.

[0025] Figures 10 to 57 This is a diagram showing the manufacturing process of semiconductor devices according to some implementation methods. Detailed Implementation

[0026] In the following description, various implementations of this disclosure will be illustrated in detail with reference to the accompanying drawings, so that those skilled in the art to which this disclosure pertains can readily implement them. This disclosure may be embodied in various different forms and is not limited to the implementations described herein.

[0027] For clarity of description in this disclosure, parts irrelevant to the description may have been omitted, and throughout this disclosure, the same reference numerals may be assigned to the same or similar elements.

[0028] Furthermore, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily depicted for illustrative purposes, and therefore, this disclosure is not limited to the illustrations. In the drawings, thicknesses are enlarged to clearly represent multiple layers and regions. In the drawings, the thicknesses of some layers and regions are depicted in an enlarged manner for illustrative purposes.

[0029] When a layer, membrane, region, plate, etc., is said to be "on" or "above" another part, this includes not only the case where it is directly on the other part, but also the case where the other part is in between. Conversely, when a part is said to be directly "on" another part, it means that there is no other part between them. In addition, when a part is said to be "on" or "above" a reference part, it can be located above or below the reference part, and does not necessarily mean that it is "on" or "above" the reference part in a direction opposite to gravity.

[0030] Throughout this disclosure, when a portion is said to "include" an element, it means that other elements may be included, rather than excluded, unless otherwise specifically stated.

[0031] Throughout this disclosure, when referring to a “top view,” it means viewing the target portion from above, and when referring to a “section view,” it means viewing a vertical section of the target portion from the side.

[0032] refer to Figures 1 to 5 This will describe semiconductor devices based on some implementation methods.

[0033] Figure 1 It is a top view of a semiconductor device based on some implementation methods. Figure 2 It is along Figure 1 A cross-sectional view of a semiconductor device according to some implementations, taken by line A-A'. Figure 3 It is along Figure 1 A cross-sectional view of a semiconductor device taken by line B-B' according to some implementation methods. Figure 4 It is along Figure 1 A cross-sectional view of a semiconductor device taken by line C-C' according to some implementation methods. Figure 5 yes Figure 2 Enlarged cross-sectional view of region P.

[0034] refer to Figures 1 to 5 A semiconductor device according to some implementations includes: a substrate 110; a plurality of semiconductor patterns SP stacked and spaced apart from each other on the substrate 110; a bit line BL connected to one end of the plurality of semiconductor patterns SP in a first direction DR1 and extending in a direction perpendicular to the upper surface of the substrate 110; a word line WL overlapping each of the plurality of semiconductor patterns SP in a direction perpendicular to the upper surface of the substrate 110 (e.g., a third direction DR3) and extending in a second direction DR2 intersecting the first direction DR1; a capacitor CP connected to the other end of each of the plurality of semiconductor patterns SP in the first direction DR1; a metal silicide pattern SC located between the semiconductor patterns SP and the capacitor CP; and an intermediate insulating layer ST overlapping the metal silicide pattern SC in the third direction DR3. As used herein, "extend" includes "extend" or "oriented along". For example, "extend in a second direction" includes "extend in a second direction" or "oriented along a second direction".

[0035] Substrate 110 may include semiconductor materials. For example, substrate 110 may include group IV semiconductors, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, substrate 110 may include semiconductors such as Si and Ge, or compound semiconductors such as SiGe, SiC, GaAs, InAs, or InP. For example, substrate 110 may be an epitaxial layer grown on a single-crystal silicon substrate. However, the material of substrate 110 is not limited to these and can vary widely.

[0036] Multiple semiconductor patterns SP can be stacked and spaced apart from each other on substrate 110. Multiple semiconductor patterns SP can be stacked and spaced apart on a third direction DR3 perpendicular to the upper surface of substrate 110. Multiple semiconductor patterns SP can be arranged and spaced apart on a first direction DR1 parallel to the upper surface of substrate 110. In some implementations, two adjacent semiconductor patterns SP on the first direction DR1 may have a symmetrical structure with reference to bit lines BL, but this is not limiting. Multiple semiconductor patterns SP can be arranged and spaced apart on a second direction DR2 intersecting the first direction DR1. The second direction DR2 may be a direction parallel to the upper surface of substrate 110. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1.

[0037] A semiconductor pattern SP may extend along a first direction DR1. The semiconductor pattern SP may have a rod shape extending along the first direction DR1. One end of the semiconductor pattern SP along the first direction DR1 may be connected to a bit line BL. For example, the semiconductor pattern SP may contact the bit line BL, but is not limited thereto. Other predetermined layers may also be located between the semiconductor pattern SP and the bit line BL. At least one of the plurality of semiconductor patterns SP adjacent to the upper surface of the substrate 110 may not be connected to the bit line BL. At least one semiconductor pattern SP adjacent to the upper surface of the substrate 110 may contact the lower insulating layer 158, which will be described later. The other end of the semiconductor pattern SP along the first direction DR1 may be connected to a capacitor CP. A metal silicide pattern SC may be located between the semiconductor pattern SP and the capacitor CP.

[0038] The semiconductor pattern SP can include semiconductor materials. For example, the semiconductor pattern SP can include silicon, germanium, or silicon-germanium. In one example, the semiconductor pattern SP can include monocrystalline silicon or polycrystalline silicon. However, the implementation is not limited to this.

[0039] A word line WL can be positioned adjacent to a semiconductor pattern SP. The word line WL can be spaced apart from the semiconductor pattern SP by a gate insulating layer Gox. The word line WL can overlap with the semiconductor pattern SP on a third direction DR3. In some implementations, the word line WL can surround the semiconductor pattern SP. The word line WL can surround a portion of the outer peripheral surface of the semiconductor pattern SP centered on a first direction DR1. The word line WL can surround the portion of the semiconductor pattern SP located between its two ends in the first direction DR1. A channel can be formed along the surface of the semiconductor pattern SP surrounded by the word line WL.

[0040] However, it is not limited to the aforementioned implementation. For example, the word line WL may overlap with the semiconductor pattern SP only in the third direction DR3 and may not overlap in the second direction DR2. For example, a word line WL may be located on one side surface of the semiconductor pattern SP along the third direction DR3. As another example, two word lines WL may each be located on opposite sides of the semiconductor pattern SP along the third direction DR3.

[0041] Word lines WL may extend along a second direction DR2. Word lines WL extending along the second direction DR2 may be electrically connected to a plurality of semiconductor patterns SP arranged spaced apart along the second direction DR2. In some implementations, word lines WL may surround the plurality of semiconductor patterns SP arranged along the second direction DR2 and extend along the second direction DR2.

[0042] According to some implementations, a semiconductor device may include multiple word lines WL. The multiple word lines WL may be stacked and spaced apart from each other on a third-direction DR3. Each of the multiple word lines WL stacked on the third-direction DR3 may be electrically connected to each of a plurality of semiconductor patterns SP stacked on the third-direction DR3. In some implementations, each of the multiple word lines WL stacked on the third-direction DR3 may surround each of a plurality of semiconductor patterns SP stacked on the third-direction DR3. The multiple word lines WL may be positioned and spaced apart from each other on a first direction DR1. In some implementations, two adjacent word lines WL on the first direction DR1 may have a symmetrical structure with reference to a bit line BL, but are not limited thereto.

[0043] Word lines (WL) may include conductive materials. For example, word lines (WL) may include: doped semiconductor materials, such as doped silicon or doped germanium; conductive metal nitrides, such as titanium nitride or tantalum nitride; metals, such as tungsten, titanium, or tantalum; metal semiconductor compounds, such as tungsten silicide, cobalt silicide, or titanium silicide; or combinations thereof.

[0044] The gate insulating layer Gox may be located between the word line WL and the semiconductor pattern SP. The gate insulating layer Gox may also be located between the word line WL and the third interlayer dielectric layer 146, which will be described later.

[0045] The gate insulating layer Gox may include at least one of a high-k material, silicon oxide, silicon nitride, or silicon oxynitride. The high-k material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0046] The word line overlay layer WLC may be located on one end of the word line WL in the first direction DR1. The word line overlay layer WLC may cover one side surface of the word line WL in the first direction DR1. The word line overlay layer WLC may be located between the word line WL and the bit line BL, and between the word line WL and the lower insulating layer 158 described later. In some implementations, the gate insulating layer Gox may be located between the word line overlay layer WLC and the semiconductor pattern SP, but is not limited thereto. For example, the word line overlay layer WLC may also be located directly on the semiconductor pattern SP.

[0047] The word line overlay (WLC) may include an insulating material. For example, the word line overlay (WLC) may include silicon nitride, but is not limited to this.

[0048] In some implementations, the first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may be located between multiple semiconductor patterns SP stacked on the third direction DR3. The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may be sequentially stacked on the multiple semiconductor patterns SP. The first interlayer dielectric layer 142 and the second interlayer dielectric layer 144 may be located on opposite sides of the semiconductor pattern SP in the first direction DR1. For example, the first interlayer dielectric layer 142 and the second interlayer dielectric layer 144 may surround the other end of the semiconductor pattern SP in the first direction DR1. The first interlayer dielectric layer 142 and the second interlayer dielectric layer 144 may cover the two side surfaces of the other end of the semiconductor pattern SP in the first direction DR1 on the second direction DR2 and the two side surfaces of the other end of the semiconductor pattern SP in the first direction DR1 on the third direction DR3. The first interlayer dielectric layer 142 may further cover the upper surface of the substrate 110. The second interlayer dielectric layer 144 may cover the other side surface of the word line WL on the first direction DR1. The third interlayer dielectric layer 146 may be located between two adjacent word lines WL. The third interlayer dielectric layer 146 may cover the facing surfaces of the two adjacent word lines WL on the third direction DR3. The gate insulating layer Gox may be located between the third interlayer dielectric layer 146 and the word line WL.

[0049] The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may include insulating materials. For example, the first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may all include silicon oxide or silicon nitride, but are not limited thereto. The second interlayer dielectric layer 144 may include a material that is etch-selective relative to the material of the first interlayer dielectric layer 142. The third interlayer dielectric layer 146 may include a material that is etch-selective relative to the material of the second interlayer dielectric layer 144. For example, the first interlayer dielectric layer 142 and the third interlayer dielectric layer 146 may include silicon oxide, and the second interlayer dielectric layer 144 may include silicon nitride, but are not limited thereto.

[0050] Figure 2 The interlayer dielectric layer between multiple semiconductor pattern SPs stacked on the third-party DR3 is shown as three layers, but the implementation is not limited to this. For example, the number of interlayer dielectric layers between multiple semiconductor pattern SPs stacked on the third-party DR3 can vary.

[0051] The bit line BL may extend on the substrate 110 along a third direction DR3. For example, the bit line BL may have a pillar shape extending in the third direction DR3, but is not limited thereto. The first interlayer dielectric layer 142 and the lower insulating layer 158, which will be described later, may be located between the lower surface of the bit line BL and the upper surface of the substrate 110. The bit line BL may be insulated from the substrate 110 by the first interlayer dielectric layer 142 and the lower insulating layer 158.

[0052] Bit line BL can be connected to multiple semiconductor patterns SP stacked on the third direction DR3. Bit line BL can be connected to one end of the multiple semiconductor patterns SP stacked on the third direction DR3. Bit line BL can be located between two semiconductor patterns SP spaced apart on the first direction DR1. In some implementations, a bit line BL can be connected to two semiconductor patterns SP spaced apart on the first direction DR1, but this is not limited to. For example, two semiconductor patterns SP spaced apart on the first direction DR1 can be connected to different bit lines BL.

[0053] A semiconductor device, according to some implementations, may include multiple bit lines BL. The multiple bit lines BL may be spaced apart from each other and positioned along a second direction DR2. An insulating layer 156, described later, may be located between the multiple bit lines BL spaced apart along the second direction DR2. Each of the multiple bit lines BL spaced apart along the second direction DR2 may be connected to one end of each of a plurality of semiconductor patterns SP along the first direction DR1. The plurality of semiconductor patterns SP may be spaced apart along the second direction DR2. Although not shown, the multiple bit lines BL may be further positioned and spaced apart from each other along the first direction DR1.

[0054] Bit lines BL can include conductive materials. For example, bit lines BL can include: doped semiconductor materials, such as doped silicon or doped germanium; conductive metal nitrides, such as titanium nitride or tantalum nitride; metals, such as tungsten, titanium or tantalum; metal semiconductor compounds, such as tungsten silicide, cobalt silicide or titanium silicide; or combinations thereof.

[0055] The first insulating pad 152 and the second insulating pad 154 may be located on the semiconductor pattern SP, the gate insulating layer Gox, the word line overlay layer WLC, and the third interlayer dielectric layer 146. The first insulating pad 152 and the second insulating pad 154 may be located between multiple bit lines BL spaced apart in the second direction DR2. The first insulating pad 152 and the second insulating pad 154 may surround one end of the multiple semiconductor patterns SP in the first direction DR1. The first insulating pad 152 and the second insulating pad 154 may not be located between the semiconductor pattern SP and the bit lines BL. The first insulating pad 152 and the second insulating pad 154 may cover both sides of one end of the semiconductor pattern SP in the first direction DR1 in the second direction DR2 and both sides of one end of the semiconductor pattern SP in the first direction DR1 in the third direction DR3. In some implementations, the first insulating pad 152 and the second insulating pad 154 may cover a portion of one side surface of the semiconductor pattern SP in the first direction DR1. The first insulating pad 152 and the second insulating pad 154 may cover a portion of one side surface of the semiconductor pattern SP in the first direction DR1, except for the portion connected to the bit line BL. However, the implementation is not limited to this. For example, the entire side surface of the semiconductor pattern SP in the first direction DR1 may be connected to the bit line BL, and the first insulating pad 152 and the second insulating pad 154 may not cover one side surface of the semiconductor pattern SP in the first direction DR1.

[0056] Figure 1 and Figure 2 The insulating pad between the word line WL and the bit line BL of a semiconductor device, according to some implementations, is shown as a double layer, but the implementation is not limited to this. For example, the insulating pad may be a single layer or three or more layers.

[0057] An insulating layer 156 may be located on the second insulating pad 154. The insulating layer 156 may be located between multiple bit lines BL spaced apart in the second direction DR2. The insulating layer 156 may cover the surfaces of two adjacent bit lines BL facing each other in the second direction DR2. Through the insulating layer 156, the multiple bit lines BL can be spaced apart and insulated. In some implementations, a portion of the insulating layer 156 may be located between two adjacent semiconductor patterns SP in the first direction DR1 and between two adjacent semiconductor patterns SP in the second direction DR2, but is not limited thereto.

[0058] The first insulating pad 152, the second insulating pad 154, and the insulating layer 156 may comprise insulating materials. For example, each of the first insulating pad 152, the second insulating pad 154, and the insulating layer 156 may comprise silicon oxide or silicon nitride, but is not limited thereto. The second insulating pad 154 may comprise a material that is etch-selective relative to the material of the first insulating pad 152. The insulating layer 156 may comprise a material that is etch-selective relative to the material of the second insulating pad 154. For example, the first insulating pad 152 and the insulating layer 156 may comprise silicon oxide, and the second insulating pad 154 may comprise silicon nitride, but is not limited thereto.

[0059] In some implementations, the first insulating pad 152, the second insulating pad 154, and the isolation insulating layer 156 may be located between the word line WL and the bit line BL among a plurality of semiconductor patterns SP stacked along the third direction DR3. The first insulating pad 152, the second insulating pad 154, and the isolation insulating layer 156 may cover a side surface of the gate insulating layer Gox along the first direction DR1, a side surface of the word line overlay layer WLC along the first direction DR1, and a side surface of the third interlayer dielectric layer 146 along the first direction DR1 among the plurality of semiconductor patterns SP stacked along the third direction DR3. However, the implementation is not limited to this. For example, the isolation insulating layer 156 may not be located between the second insulating pad 154 and the bit line BL.

[0060] The lower insulating layer 158 may be located on a portion of the first interlayer dielectric layer 142 covering the upper surface of the substrate 110. The lower insulating layer 158 may be located between the bit line BL and the first interlayer dielectric layer 142. The lower insulating layer 158 may cover one side surface of at least one semiconductor pattern SP in the first direction DR1. At least one semiconductor pattern SP may be adjacent to the upper surface of the substrate 110. The lower insulating layer 158 may cover one side surface of a first insulating pad 152, one side surface of a second insulating pad 154, and one side surface of an isolation insulating layer 156 in the first direction DR1. The first insulating pad 152, the second insulating pad 154, and the isolation insulating layer 156 may be located between at least one semiconductor pattern SP and the upper surface of the substrate 110. The lower insulating layer 158 may cover one side surface of the first insulating pad 152, one side surface of the second insulating pad 154, and one side surface of the isolation insulating layer 156 in the first direction DR1. The first insulating pad 152, the second insulating pad 154, and the isolation insulating layer 156 are located between the bottommost semiconductor pattern SP and the substrate 110 among the plurality of semiconductor patterns SP stacked on the third-direction DR3.

[0061] The lower insulating layer 158 may include an insulating material. For example, the lower insulating layer 158 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but is not limited thereto.

[0062] The other end of the semiconductor pattern SP in the first direction DR1 can be connected to a capacitor CP. The capacitor CP may include a first electrode 171, a second electrode 175, and a dielectric layer 173 located between the first electrode 171 and the second electrode 175. The first electrode 171 can be connected to the other end of the semiconductor pattern SP in the first direction DR1. A metal silicide pattern SC can be located between the first electrode 171 and the semiconductor pattern SP. One side surface of the first electrode 171 in the first direction DR1 can contact the metal silicide pattern SC.

[0063] The first electrode 171 may extend in the first direction DR1. In some implementations, the first electrode 171 may have a cylindrical shape extending in the first direction DR1, but is not limited thereto. For example, the first electrode 171 may have a hollow cylindrical shape.

[0064] The dielectric layer 173 may cover the first electrode 171. The dielectric layer 173 may cover the surface of the first electrode 171 except for one side surface of the first electrode 171 in the first direction DR1. For example, the dielectric layer 173 may cover the other side surface of the first electrode 171 in the first direction DR1, the two side surfaces of the first electrode 171 in the second direction DR2, and the two side surfaces of the first electrode 171 in the third direction DR3.

[0065] The second electrode 175 may be covered by the dielectric layer 173. The second electrode 175 may be spaced apart from the first electrode 171 by the dielectric layer 173. The first electrode 171 may be surrounded by the dielectric layer 173 and the second electrode 175. The other side surface of the first electrode 171 in the first direction DR1, the two side surfaces of the first electrode 171 in the second direction DR2, and the two side surfaces of the first electrode 171 in the third direction DR3 may be surrounded by the dielectric layer 173 and the second electrode 175.

[0066] A semiconductor device, according to some implementations, may include a plurality of capacitors CP. Each of the plurality of capacitors CP may be connected to each of a plurality of semiconductor patterns SP. The first electrode 171 of each of the plurality of capacitors CP may be spaced apart from each other on a second direction DR2 and a third direction DR3. The plurality of first electrodes 171 spaced apart from each other on the second direction DR2 and the third direction DR3 may be connected to each of a plurality of semiconductor patterns SP spaced apart on the second direction DR2 and the third direction DR3. The dielectric layer 173 of each of the plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3 may be interconnected. The second electrode 175 of each of the plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3 may be interconnected.

[0067] Multiple capacitors CP can be spaced apart from each other along the first direction DR1. In some implementations, two adjacent capacitors CP along the first direction DR1 can have a symmetrical structure with reference to bit line BL, but this is not a limitation.

[0068] According to some implementations, the semiconductor device may include a plate electrode PL connected to a plurality of capacitors CP. The plate electrode PL may be connected to the plurality of capacitors CP arranged along a second direction DR2 and a third direction DR3. The plate electrode PL may cover a second electrode 175 of the plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3.

[0069] In some implementations, the plate electrode PL may include a first portion PL_1 and a second portion PL_2. The first portion PL_1 extends from one side of the first electrode 171 of the plurality of capacitors CP in a first direction DR1 in a third direction DR3 perpendicular to the upper surface of the substrate 110. The second portion PL_2 extends in the first direction DR1 parallel to the upper surface of the substrate 110 and is located between the first electrodes 171.

[0070] In some implementations, the first portion PL_1 may extend along the third direction DR3 and the second direction DR2. The first portion PL_1 may have a wall shape extending along the third direction DR3 and the second direction DR2. The second portion PL_2 may surround the first electrode 171 of a plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3. However, the implementation is not limited to this, and the structure and shape of the plate electrode PL may be changed differently from the structure and shape of the capacitors CP.

[0071] Each of the first electrode 171, the second electrode 175, and the plate electrode PL may include a conductive material. Each of the first electrode 171, the second electrode 175, and the plate electrode PL may include at least one of the following: a metallic material, such as titanium, tantalum, tungsten, copper, or aluminum; a conductive metal nitride, such as titanium nitride or tantalum nitride; or a doped semiconductor material, such as doped silicon or doped germanium. The first electrode 171 and the second electrode 175 may include the same material, and the plate electrode PL may include a material different from the materials of the first electrode 171 and the second electrode 175. For example, the first electrode 171 and the second electrode 175 may include titanium nitride, and the plate electrode PL may include doped silicon-germanium.

[0072] The dielectric layer 173 may include at least one of a dielectric, a ferroelectric, or an antiferroelectric. The dielectric may include a high permittivity material. For example, the dielectric may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0073] In some implementations, a semiconductor pattern SP, a bit line BL connected to one end of the semiconductor pattern SP in a first direction DR1, a capacitor CP connected to the other end of the semiconductor pattern SP in the first direction DR1, and a word line WL extending in a second direction DR2 adjacent to the semiconductor pattern SP and intersecting the first direction DR1 can form a memory cell MC. A semiconductor device according to some implementations may include multiple memory cells MC. Each of the multiple memory cells MC may include a transistor and a capacitor connected to that transistor. For example, each of the multiple memory cells MC may be DRAM (Dynamic Random Access Memory), but is not limited thereto. The multiple memory cells MC may be stacked on a third direction DR3 perpendicular to the upper surface of the substrate 110. The multiple memory cells MC may be arranged in the same layer on the first direction DR1 and the second direction DR2 parallel to the upper surface of the substrate 110. That is, a semiconductor device according to some implementations may include multiple memory cells stacked in three dimensions.

[0074] In some implementations, the metal silicide pattern SC can be located between the semiconductor pattern SP and the capacitor CP. The semiconductor pattern SP and the capacitor CP can be respectively disposed on both sides of the metal silicide pattern SC in the first direction DR1. The intermediate insulating layer ST can be located on both sides of the metal silicide pattern SC in the third direction DR3 and on both sides of the metal silicide pattern SC in the second direction DR2.

[0075] In some implementations, the intermediate insulating layer ST may extend in a third direction DR3 perpendicular to the upper surface of the substrate 110. The intermediate insulating layer ST may further extend in a second direction DR2 parallel to the upper surface of the substrate 110 and intersecting with the semiconductor pattern SP. The intermediate insulating layer ST may have a wall shape extending in the third direction DR3 and the second direction DR2. Multiple semiconductor patterns SP and multiple capacitors CP can be connected through an opening penetrating the intermediate insulating layer ST in the first direction DR1.

[0076] According to some implementations, the semiconductor device may include multiple metal silicide patterns SC. The multiple metal silicide patterns SC may be connected to multiple semiconductor patterns SP and multiple capacitors CP. The multiple metal silicide patterns SC may be located within an opening penetrating the intermediate insulating layer ST in a first direction DR1.

[0077] In some implementations, multiple metal silicide patterns SC can be spaced apart on a third direction DR3 and a second direction DR2, corresponding to multiple semiconductor patterns SP and multiple capacitors CP. The multiple metal silicide patterns SC can be spaced apart by an intermediate insulating layer ST. The intermediate insulating layer ST can be located between the multiple metal silicide patterns SC spaced apart and arranged on the third direction DR3 and the second direction DR2. The intermediate insulating layer ST can overlap with each of the multiple metal silicide patterns SC on the third direction DR3. The intermediate insulating layer ST can overlap with each of the multiple metal silicide patterns SC on the second direction DR2.

[0078] In some implementations, an intermediate insulating layer ST may surround each of the plurality of metal silicide patterns SC. The intermediate insulating layer ST may be located on both sides of each of the plurality of metal silicide patterns SC in a third direction DR3 (e.g., the upper and lower surfaces of the metal silicide patterns SC) and on both sides of each of the plurality of metal silicide patterns SC in a second direction DR2. The intermediate insulating layer ST may cover both sides of each of the plurality of metal silicide patterns SC in the third direction DR3 and both sides of each of the plurality of metal silicide patterns SC in the second direction DR2.

[0079] In some implementations, the width of the metal silicide pattern SC in the first direction DR1 may be smaller than the width of the intermediate insulating layer ST in the first direction DR1, but this is not a limitation. For example, the width of the metal silicide pattern SC in the first direction DR1 may be substantially the same as the width of the intermediate insulating layer ST in the first direction DR1. In another example, the width of the metal silicide pattern SC in the first direction DR1 may be greater than the width of the intermediate insulating layer ST in the first direction DR1.

[0080] In some implementations, the width of the metal silicide pattern SC in the third direction DR3 is substantially the same as the width of the semiconductor pattern SP in the third direction DR3, and the width of the metal silicide pattern SC in the second direction DR2 can be substantially the same as the width of the semiconductor pattern SP in the second direction DR2.

[0081] In some implementations, the metal silicide pattern SC can contact the intermediate insulating layer ST. The two side surfaces of the metal silicide pattern SC on the third direction DR3 (e.g., the upper and lower surfaces of the metal silicide pattern SC) can contact the intermediate insulating layer ST. The two side surfaces of the metal silicide pattern SC on the second direction DR2 can contact the intermediate insulating layer ST.

[0082] In some implementations, the metal silicide pattern SC can connect the semiconductor pattern SP and the capacitor CP on the first direction DR1. One side surface of the metal silicide pattern SC on the first direction DR1 can be connected to the semiconductor pattern SP. The other side surface of the metal silicide pattern SC on the first direction DR1 can be connected to the capacitor CP.

[0083] In some implementations, the metal silicide pattern SC can contact the semiconductor pattern SP on the first direction DR1. The metal silicide pattern SC can contact the capacitor CP on the first direction DR1. One side surface of the metal silicide pattern SC on the first direction DR1 can contact the semiconductor pattern SP. The other side surface of the metal silicide pattern SC on the first direction DR1 can contact the first electrode 171 of the capacitor CP.

[0084] Based on the above description, one end of the semiconductor pattern SP in the first direction DR1 can contact the bit line BL. The metal silicide pattern SC can contact the other end of the semiconductor pattern SP in the first direction DR1. In some implementations, the metal silicide pattern SC can contact the other side surface of the semiconductor pattern SP in the first direction DR1.

[0085] In some implementations, the metal silicide pattern SC, on one side surface of the semiconductor pattern SP in the first direction DR1, may be aligned with one side surface of the first interlayer dielectric layer 142 in the first direction DR1 in the third direction DR3. The metal silicide pattern SC, on one side surface of the semiconductor pattern SP in the first direction DR1, may also be aligned with one side surface of the first interlayer dielectric layer 142 in the second direction DR2. The metal silicide pattern SC may only contact the other side surface of the semiconductor pattern SP in the first direction DR1. The other end of the semiconductor pattern SP may have its two side surfaces in the second direction DR2 and its two side surfaces in the third direction DR3 covered by the first interlayer dielectric layer 142. The other end of the semiconductor pattern SP may be adjacent to the metal silicide pattern SC. The metal silicide pattern SC may only contact the semiconductor pattern SP in the first direction DR1, and may not contact the semiconductor pattern SP in the second direction DR2 and the third direction DR3.

[0086] One side surface of the first interlayer dielectric layer 142 in the first direction DR1 may be covered by the intermediate insulating layer ST. In some implementations, one side surface of the first interlayer dielectric layer 142 in the first direction DR1 may be completely covered by the intermediate insulating layer ST. The metal silicide pattern SC may not be located on one side surface of the first interlayer dielectric layer 142 in the first direction DR1. The metal silicide pattern SC may not cover one side surface of the first interlayer dielectric layer 142 in the first direction DR1.

[0087] In some implementations, because the width of the metal silicide pattern SC in the first direction DR1 is smaller than the width of the intermediate insulating layer ST in the first direction DR1, the plurality of first electrodes 171 can be further located within the opening of the intermediate insulating layer ST. The inner surface of the opening of the intermediate insulating layer ST, for example, the surfaces of the intermediate insulating layer ST facing each other in the third direction DR3 and the second direction DR2, can be covered by the metal silicide pattern SC and the first electrodes 171.

[0088] In some implementations, the first electrode 171 may be further located on a side surface of the intermediate insulating layer ST in the first direction DR1. The first electrode 171 may cover a portion of a side surface of the intermediate insulating layer ST in the first direction DR1.

[0089] In some implementations, the width of the portion of the first electrode 171 adjacent to the metal silicide pattern SC can be the same as the width of the metal silicide pattern SC. The width of the portion of the first electrode 171 adjacent to the plate electrode PL can be greater than the width of the metal silicide pattern SC. Here, the width of the portion of the first electrode 171 and the width of the metal silicide pattern SC can refer to the width in the third direction DR3 and the width in the second direction DR2, respectively.

[0090] In some implementations, the dielectric layer 173 of the capacitor CP may be located on one side surface of the intermediate insulating layer ST in the first direction DR1. The first electrode 171 and the dielectric layer 173 may be located on one side surface of the intermediate insulating layer ST in the first direction DR1. One side surface of the intermediate insulating layer ST in the first direction DR1 may be covered by the first electrode 171 and the dielectric layer 173.

[0091] The metal silicide pattern SC may include a metal silicide material. The work function of the metal silicide pattern SC may have a value between the work function of the material of the first electrode 171 and the work function of the material of the semiconductor pattern SP. The metal silicide pattern SC can reduce the work function difference between the material of the first electrode 171 and the material of the semiconductor pattern SP, thereby reducing the contact resistance between the semiconductor pattern SP and the capacitor CP. For example, the metal silicide pattern SC may include cobalt silicide, titanium silicide, nickel silicide, or titanium silicon nitride, but is not limited thereto.

[0092] The intermediate insulating layer ST may include an insulating material. For example, the intermediate insulating layer ST may include silicon nitride, silicon boron nitride, silicon carbonitride, or combinations thereof, but is not limited thereto. In some implementations, the intermediate insulating layer ST may include a material different from the material of the semiconductor pattern SP. The intermediate insulating layer ST may include a material that has etch selectivity relative to the material of the semiconductor pattern SP. For example, the semiconductor pattern SP includes silicon, and the intermediate insulating layer ST may include silicon carbonitride, but is not limited thereto.

[0093] Figure 1 , Figure 2 and Figure 5 The intermediate insulating layer ST is shown as a single layer, but is not limited to this. For example, the intermediate insulating layer ST can be formed of multiple layers.

[0094] In the semiconductor device manufacturing process, during the steps of forming word lines WL and capacitors CP, an intermediate insulating layer ST can be used as an etch stop layer. For example, etching can be stopped when the side surface of the intermediate insulating layer ST on the first direction DR1 is exposed during the etching process. Accordingly, each of the multiple word lines WL and multiple capacitors CP formed between multiple semiconductor patterns SP stacked along the third direction DR3 can be formed on a flat surface on the first direction DR1. In addition, the multiple word lines WL and multiple capacitors CP can be aligned on the third direction DR3. According to some implementations, the semiconductor device may include a metal silicide pattern SC located between the semiconductor pattern SP connected on the first direction DR1 and the first electrode 171, and an intermediate insulating layer ST overlapping on the third direction DR3, thereby improving device characteristics.

[0095] The following will refer to Figure 6 and Figure 7 Description based on Figure 5 The semiconductor device shown is a variation of the implementation method.

[0096] Figure 6 and Figure 7 Each represents an enlarged cross-sectional view of a semiconductor device according to some implementation method, which can be... Figure 2 The enlarged cross-sectional view corresponding to region P. Figure 6 and Figure 7 The implementation shown has the ability to be combined with Figures 1 to 5 The implementations shown partially differ in their structures of the metal silicide pattern SC, semiconductor pattern SP, first electrode 171, and intermediate insulating layer ST. Below, descriptions overlapping with prior implementations will be brief or omitted, emphasizing the differences.

[0097] refer to Figure 6 and Figure 7 The other end of the semiconductor pattern SP on the first direction DR1 may further lie within an opening in the intermediate insulating layer ST. The semiconductor pattern SP may include a portion overlapping the intermediate insulating layer ST on a third direction DR3 perpendicular to the upper surface of the substrate 110. Figures 1 to 5 In the implementation shown, the semiconductor pattern SP and the first interlayer dielectric layer 142 are aligned on the third direction DR3 and the second direction DR2. On the other hand, in Figure 6 and Figure 7 In the implementation shown, the semiconductor pattern SP and the first interlayer dielectric layer 142 may not be aligned in the third direction DR3 and the second direction DR2. The semiconductor pattern SP may protrude more than the first interlayer dielectric layer 142 in the first direction DR1, adjacent to the capacitor CP.

[0098] In some implementations, the metal silicide pattern SC may surround the other end of the semiconductor pattern SP in the first direction DR1. The metal silicide pattern SC may include a portion located between the semiconductor pattern SP and the intermediate insulating layer ST. Figures 1 to 5 In the implementation shown, the metal silicide pattern SC can contact the semiconductor pattern SP only in the first direction DR1. However, in Figure 6 and Figure 7 In the illustrated implementation, the metal silicide pattern SC can contact the semiconductor pattern SP on both the first direction DR1 and the third direction DR3. Although not shown, the metal silicide pattern SC can also contact the semiconductor pattern SP on the second direction DR2. The metal silicide pattern SC can cover the other side surface of the semiconductor pattern SP on the first direction DR1. The metal silicide pattern SC can cover both side surfaces of the semiconductor pattern SP on the third direction DR3, that is, portions of the upper and lower surfaces of the semiconductor pattern SP. Although not shown, the metal silicide pattern SC can also cover portions of both side surfaces of the semiconductor pattern SP on the second direction DR2.

[0099] In some implementations, the metal silicide pattern SC may further be located on a side surface of the first interlayer dielectric layer 142 in the first direction DR1. Figures 1 to 5 In the illustrated implementation, one side surface of the first interlayer dielectric layer 142 in the first direction DR1 may be covered only by the intermediate insulating layer ST. For example, the metal silicide pattern SC and the first interlayer dielectric layer 142 may not overlap in the first direction DR1. On the other hand, in Figure 6 and Figure 7 In the illustrated implementation, one side surface of the first interlayer dielectric layer 142 in the first direction DR1 can be covered by an intermediate insulating layer ST and a metal silicide pattern SC. The metal silicide pattern SC and the first interlayer dielectric layer 142 can overlap in the first direction DR1.

[0100] The following will describe Figure 6 The implementation method shown is the same as Figure 7 The differences between the implementation methods shown.

[0101] exist Figure 6In the illustrated implementation, the first electrode 171 may be located between the intermediate insulating layer ST and the metal silicide pattern SC. The first electrode 171 may include portions located between the upper surface of the metal silicide pattern SC and the intermediate insulating layer ST, and between the lower surface of the metal silicide pattern SC and the intermediate insulating layer ST. The intermediate insulating layer ST may be spaced apart from the metal silicide pattern SC by the first electrode 171. One side surface of the first interlayer dielectric layer 142 in the first direction DR1 may contact the metal silicide pattern SC, the first electrode 171, and the intermediate insulating layer ST.

[0102] exist Figure 7 In the illustrated implementation, the intermediate insulating layer ST can contact the metal silicide pattern SC. The first interlayer dielectric layer 142 contacts the metal silicide pattern SC and the intermediate insulating layer ST along one side surface of the first direction DR1, and may not contact the first electrode 171. The metal silicide pattern SC can be located between the first interlayer dielectric layer 142 and the first electrode 171. The first electrode 171 can be spaced apart from the first interlayer dielectric layer 142 by the metal silicide pattern SC.

[0103] In the following text, see references Figure 8 and Figure 9 The description will be based on Figure 2 The semiconductor device shown is a variation of the implementation method.

[0104] Figure 8 and Figure 9 It is a cross-sectional view of a semiconductor device based on some implementation methods, which can correspond to Figure 2 The cross-section shown. Figure 8 and Figure 9 The implementation methods shown can each have the same characteristics as... Figures 1 to 5 The capacitor CP structure shown is partially different from the implementation described below. Descriptions overlapping with prior implementations are omitted or abbreviated, emphasizing the differences.

[0105] refer to Figure 8 and Figure 9 The first electrode 171 may have a hollow cylindrical shape. The first electrode 171 may include a side surface covering a metal silicide pattern SC and an intermediate insulating layer ST along a first direction DR1 and a portion extending along a third direction DR3, as well as a portion extending away from the semiconductor pattern SP along the first direction DR1. A portion of the dielectric layer 173 and the second electrode 175 may be located within an internal space surrounded by the portion of the first electrode 171 extending along the first direction DR1.

[0106] In some implementations, the plate electrode PL may extend in a third direction DR3 perpendicular to the upper surface of the substrate 110. Although not shown, the plate electrode PL may also extend in a second direction DR2. The plate electrode PL may have a wall shape extending in both the second direction DR2 and the third direction DR3. The plate electrode PL may contact a side surface of the second electrode 175 in the first direction DR1.

[0107] exist Figure 8 and Figure 9 In the illustrated implementation, the plate electrode PL may not be located between the plurality of first electrodes 171 spaced apart in the third direction DR3. Although not shown, the plate electrode PL may also not be located between the plurality of first electrodes 171 spaced apart in the second direction DR2. For example, the plate electrode PL may overlap with the plurality of first electrodes 171 only in the first direction DR1. Figure 8 and Figure 9 In the implementation shown, the plate electrode PL may only contact one side surface of the second electrode 175 in the first direction DR1. The plate electrode PL may not contact the two side surfaces of the second electrode 175 in the third direction DR3 and the two side surfaces of the second electrode 175 in the second direction DR2.

[0108] However, the structure of the plate electrode PL is not limited to the implementation described above. For example, as in... Figures 1 to 5 As in the illustrated implementation, a portion of the plate electrode PL may be located between a plurality of first electrodes 171 spaced apart and arranged in the third direction DR3 and the second direction DR2. For example, the plate electrode PL may overlap with the plurality of first electrodes 171 in the first direction DR1, and also overlap with the plurality of first electrodes 171 in the third direction DR3 and the second direction DR2. The plate electrode PL may further contact the two side surfaces of the second electrode 175 along the third direction DR3 and the two side surfaces of the second electrode 175 along the second direction DR2.

[0109] Below, will be described Figure 8 The implementation method shown is the same as Figure 9 The differences between the implementation methods shown.

[0110] exist Figure 8 In the illustrated implementation, the dielectric layer 173 and the second electrode 175 may cover the inner and outer surfaces of the first electrode 171. The dielectric layer 173 and the second electrode 175 may cover one side surface of the intermediate insulating layer ST in the first direction DR1. The dielectric layer 173 may contact one side surface of the intermediate insulating layer ST in the first direction DR1. The dielectric layer 173 and the second electrode 175 may be located between a plurality of first electrodes 171 spaced apart in the third direction DR3.

[0111] exist Figure 9 In the illustrated implementation, dielectric layer 173 and second electrode 175 may cover the inner surface of first electrode 171. Dielectric layer 173 and second electrode 175 do not cover the outer surface of first electrode 171, and dielectric layer 173 and second electrode 175 may only cover the inner surface of first electrode 171. Dielectric layer 173 may be spaced apart from one side surface of the intermediate insulating layer ST in the first direction DR1. An interlayer dielectric layer 180 may be located between a plurality of first electrodes 171 spaced apart in the third direction DR3. Figure 8 In a different implementation, the dielectric layer 173 and the second electrode 175 may not be located between the plurality of first electrodes 171 spaced apart on the third direction DR3. The interlayer dielectric layer 180 may be located between the dielectric layer 173 and one side surface of the intermediate insulating layer ST on the first direction DR1. The dielectric layer 173 may be spaced apart from the intermediate insulating layer ST by the interlayer dielectric layer 180.

[0112] In the following text, see references Figures 10 to 57 This will describe methods for manufacturing semiconductor devices according to some implementations.

[0113] Figures 10 to 57 This is a diagram showing the manufacturing process of semiconductor devices according to some implementation methods. Figure 10 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 26 , Figure 30 , Figure 34 , Figure 37 , Figure 40 , Figure 43 , Figure 46 , Figure 49 , Figure 52 and Figure 55 It is a top view showing the manufacturing process of semiconductor devices according to some implementation methods. Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 31 , Figure 35 , Figure 38 , Figure 41 , Figure 44 , Figure 47 , Figure 50 , Figure 53 and Figure 56 These are cross-sectional views showing the manufacturing processes of semiconductor devices according to some implementations, which are cross-sectional views cut along line A-A' in the top view. Figure 24 , Figure 28 and Figure 32 They are shown respectively Figure 23 , Figure 27 and Figure 31 A cross-sectional view of the variant. Figure 12 , Figure 15 , Figure 18 , Figure 21 , Figure 25 , Figure 29 , Figure 33 , Figure 36 and Figure 39 These are cross-sectional views showing the manufacturing processes of semiconductor devices according to some implementations, cut along line B-B' in the top view. Figure 42 , Figure 45 , Figure 48 , Figure 51 , Figure 54 and Figure 57 These are cross-sectional views showing the manufacturing processes of semiconductor devices according to some implementations, cut along the C-C' line in the top view.

[0114] refer to Figures 10 to 12 A plurality of first semiconductor layers 112 and a plurality of second semiconductor layers 114 are formed on the substrate 110, and a preliminary intermediate insulating layer 120 that penetrates the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 can be formed.

[0115] First, a plurality of first semiconductor layers 112 and a plurality of second semiconductor layers 114 can be alternately formed on the substrate 110. For example, the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 can be formed by a deposition process. For example, the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), but are not limited thereto. As another example, the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 can also be formed by an epitaxial growth method.

[0116] Both the first semiconductor layer 112 and the second semiconductor layer 114 may comprise semiconductor materials. The first semiconductor layer 112 and the second semiconductor layer 114 may comprise different semiconductor materials. The second semiconductor layer 114 may comprise a material that is etch-selective relative to the material of the first semiconductor layer 112. In some implementations, the first semiconductor layer 112 comprises SiGe, and the second semiconductor layer 114 may comprise Si, but is not limited thereto.

[0117] In some implementations, the second semiconductor layer 114 may be formed to be thicker than the first semiconductor layer 112, but this is not a limitation. For example, the second semiconductor layer 114 may also be formed to be thinner than the first semiconductor layer 112. In this case, the thinning process of the second semiconductor layer 114 in subsequent processes can be omitted.

[0118] Subsequently, a preliminary intermediate insulating layer 120 can be formed by penetrating multiple first semiconductor layers 112 and multiple second semiconductor layers 114. The preliminary intermediate insulating layer 120 can penetrate the multiple first semiconductor layers 112 and multiple second semiconductor layers 114 in a third direction DR3 perpendicular to the upper surface of the substrate 110 and is connected to the substrate 110. A portion of the preliminary intermediate insulating layer 120 can be embedded in the upper part of the substrate 110. The lower part of the preliminary intermediate insulating layer 120 can be surrounded by the substrate 110. Parts of the lower surface and side surfaces of the preliminary intermediate insulating layer 120 can be covered by the substrate 110.

[0119] The preliminary intermediate insulating layer 120 may extend in the third direction DR3 and the second direction DR2. The preliminary intermediate insulating layer 120 may have a wall shape extending in the third direction DR3 and the second direction DR2.

[0120] In some implementations, multiple preliminary intermediate insulating layers 120 may be formed at intervals on the first direction DR1.

[0121] The preliminary intermediate insulating layer 120 may include an insulating material. The preliminary intermediate insulating layer 120 may include an insulating material that has etch selectivity relative to the material of the first semiconductor layer 112 and the material of the second semiconductor layer 114. For example, the preliminary intermediate insulating layer 120 may include silicon nitride, silicon boron nitride, silicon carbonitride, or combinations thereof, but is not limited thereto.

[0122] refer to Figures 13 to 15 Multiple first unit isolation insulation layers 132 can be formed on the two side surfaces of the initial intermediate insulation layer 120 in the first direction DR1.

[0123] First, a plurality of first unit isolation holes can be formed by penetrating a plurality of first semiconductor layers 112 and a plurality of second semiconductor layers 114. Each of the plurality of first unit isolation holes can recess a portion of the upper surface of the substrate 110. The bottom surface of each of the plurality of first unit isolation holes can be formed from the upper surface of the substrate 110. The sidewalls of each of the plurality of first unit isolation holes can be formed from portions of the side surface of the substrate 110, the side surface of the first semiconductor layer 112, and the side surface of the second semiconductor layer 114.

[0124] Subsequently, the plurality of first unit isolation holes can be filled with an insulating material to form a plurality of first unit isolation insulating layers 132. The first unit isolation insulating layers 132 may include, for example, silicon oxide, but are not limited thereto. The first unit isolation insulating layers 132 may penetrate the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 and be connected to the substrate 110. The first unit isolation insulating layers 132 may cover the upper surface of the substrate 110 and partially cover the side surfaces of the substrate 110. The first unit isolation insulating layers 132 may cover the side surfaces of the plurality of first semiconductor layers 112 facing the first direction DR1 and the side surfaces of the plurality of second semiconductor layers 114 facing the first direction DR1.

[0125] Multiple first-unit insulating layers 132 may be located on both sides of a preliminary intermediate insulating layer 120 in a first direction DR1. Multiple first-unit insulating layers 132 may be spaced apart and arranged in a second direction DR2. Two first-unit insulating layers 132 may be spaced apart and arranged in the first direction DR1 between adjacent preliminary intermediate insulating layers 120.

[0126] refer to Figures 16 to 18 Second unit insulating layers 134 can be formed on the side surfaces of the plurality of first unit insulating layers 132 in the first direction DR1. The plurality of first unit insulating layers can be spaced apart and arranged in the second direction DR2. In some implementations, the plurality of second unit insulating layers 134 can be formed to be spaced apart in the first direction DR1.

[0127] First, a plurality of second-cell isolation holes can be formed by penetrating a plurality of first semiconductor layers 112 and a plurality of second semiconductor layers 114. Each of the plurality of second-cell isolation holes can partially recess the upper surface of the substrate 110. The bottom surface of each of the plurality of second-cell isolation holes can be formed from the upper surface of the substrate 110. The sidewalls of each of the plurality of second-cell isolation holes can be formed from portions of the side surfaces of the substrate 110, the side surfaces of the plurality of first semiconductor layers 112, the side surfaces of the plurality of second semiconductor layers 114, and the side surfaces of the plurality of first-cell isolation insulating layers 132.

[0128] Subsequently, insulating material can be filled into the plurality of second unit isolation holes to form a plurality of second unit isolation insulating layers 134. In some implementations, the second unit isolation insulating layers 134 may include the same material as the first unit isolation insulating layers 132, but are not limited thereto. For example, the second unit isolation insulating layers 134 may include silicon oxide, but are not limited thereto. The second unit isolation insulating layers 134 may penetrate the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114 and be connected to the substrate 110. The second unit isolation insulating layers 134 may cover the upper surface of the substrate 110 and a portion of the side surface of the substrate 110. The second unit isolation insulating layers 134 may cover the facing side surfaces of the plurality of first semiconductor layers 112 and the facing side surfaces of the plurality of second semiconductor layers 114 in the first direction DR1. The second unit isolation insulating layers 134 may cover one side surface of the plurality of first unit isolation insulating layers 132 in the first direction DR1. The plurality of first unit isolation insulating layers 132 may be arranged to be spaced apart in the second direction DR2.

[0129] The second unit insulating layer 134 may be located between two first unit insulating layers 132, which are located between adjacent preliminary intermediate insulating layers 120. The second unit insulating layer 134 may cover the side surfaces of the two first unit insulating layers 132 facing each other in the first direction DR1. The two first unit insulating layers 132 may be located between adjacent preliminary intermediate insulating layers 120.

[0130] Multiple first semiconductor layers 112 and multiple second semiconductor layers 114 can be separated on the second direction DR2 by multiple first unit isolation insulating layers 132. Multiple first semiconductor layers 112 and multiple second semiconductor layers 114 can be separated on the first direction DR1 by multiple second unit isolation insulating layers 134.

[0131] exist Figures 10 to 18 In the illustrated implementation, a preliminary intermediate insulating layer 120 is first formed, followed by the formation of a first unit insulating layer 132, and then a second unit insulating layer 134. However, the implementation is not limited to this. For example, the first unit insulating layer 132 may be formed first, followed by the formation of the preliminary intermediate insulating layer 120, and then the formation of the second unit insulating layer 134. In another example, the first unit insulating layer 132 may be formed first, followed by the formation of the second unit insulating layer 134, and then the formation of the preliminary intermediate insulating layer 120.

[0132] refer to Figures 19 to 21 Multiple first semiconductor layers 112 can be removed, and multiple second semiconductor layers 114 can be thinned to form multiple semiconductor patterns SP, and a unit isolation insulating layer 130 can be formed.

[0133] First, portions of a plurality of first unit isolation insulating layers 132 and a plurality of second unit isolation insulating layers 134 can be etched to expose the side surfaces of a plurality of first semiconductor layers 112 and a plurality of second semiconductor layers 114. The unetched portions of the plurality of first unit isolation insulating layers 132 and a plurality of second unit isolation insulating layers 134 can support the structure of the plurality of second semiconductor layers 114 during subsequent processes. Subsequently, a material having high etch selectivity for the first semiconductor layers 112 relative to the second semiconductor layers 114 can be used to selectively etch the plurality of first semiconductor layers 112 and the plurality of second semiconductor layers 114. The plurality of first semiconductor layers 112 can be removed by the etching process.

[0134] Subsequently, a thinning process can be performed on the plurality of second semiconductor layers 114 to form a plurality of semiconductor patterns SP. The thinning process reduces the thickness of each of the plurality of second semiconductor layers 114. Here, the thickness of the second semiconductor layer 114 can refer to its length in the third direction DR3. That is, the thickness of the plurality of semiconductor patterns SP can be thinner than the thickness of the plurality of second semiconductor layers 114.

[0135] Multiple semiconductor patterns SP can be spaced and stacked on a third direction DR3 perpendicular to the upper surface of the substrate 110. Multiple semiconductor patterns SP can be spaced and arranged on a second direction DR2 parallel to the upper surface of the substrate 110. Multiple semiconductor patterns SP can be spaced and arranged on a first direction DR1 parallel to the upper surface of the substrate 110 and intersecting the second direction DR2. Multiple semiconductor patterns SP can be located on two side surfaces of the preliminary intermediate insulating layer 120 along the first direction DR1. Multiple semiconductor patterns SP can be spaced and arranged between adjacent preliminary intermediate insulating layers 120 on the first direction DR1.

[0136] Subsequently, a cell isolation insulating layer 130 can be formed to surround a plurality of semiconductor patterns SP. The cell isolation insulating layer 130 may include, but is not limited to, the unetched remainders of a plurality of first cell isolation insulating layers 132 and a plurality of second cell isolation insulating layers 134. For example, the cell isolation insulating layer 130 may be reformed after the plurality of first cell isolation insulating layers 132 and the plurality of second cell isolation insulating layers 134 have been completely removed. In some implementations, the cell isolation insulating layer 130 may include a plurality of isolation insulating layers formed according to divided segments, such as a plurality of first cell isolation insulating layers 132 and a plurality of second cell isolation insulating layers 134. In this case, because the plurality of isolation insulating layers comprise the same insulating material, the boundaries between the plurality of isolation insulating layers may be unidentifiable. The cell isolation insulating layer 130 may include, for example, silicon oxide, but is not limited to.

[0137] The unit isolation insulating layer 130 may cover one side surface of each of the plurality of semiconductor patterns SP in the first direction DR1, two side surfaces of each of the plurality of semiconductor patterns SP in the second direction DR2, and two side surfaces of each of the plurality of semiconductor patterns SP in the third direction DR3. The other side surface of each of the plurality of semiconductor patterns SP in the first direction DR1 may be covered by the preliminary intermediate insulating layer 120.

[0138] refer to Figures 22 to 25 A portion of the preliminary intermediate insulating layer 120 can be etched to form the first hole H1. For example, the preliminary intermediate insulating layer 120 can be selectively etched using a material that has high etch selectivity for the preliminary intermediate insulating layer 120 relative to the semiconductor pattern SP and the cell isolation insulating layer 130. The upper portion of the preliminary intermediate insulating layer 120 is etched, and the lower portion of the preliminary intermediate insulating layer 120 adjacent to the upper surface of the substrate 110 can be retained; this lower portion can be referred to as the remaining intermediate insulating layer 120p. The remaining intermediate insulating layer 120p can cover a portion of the upper surface and side surface of the substrate 110, as well as a portion of the side surface of the cell isolation insulating layer 130 adjacent to the upper surface of the substrate 110.

[0139] The bottom surface of the first hole H1 can be formed by the upper surface of the remaining intermediate insulating layer 120p. The sidewalls of the first hole H1 can be formed by the side surfaces of multiple semiconductor pattern SPs and the side surfaces of the cell isolation insulating layer 130. The side surfaces of the multiple semiconductor pattern SPs and the side surfaces of the cell isolation insulating layer 130 can be exposed through the first hole H1. The side surfaces of the multiple semiconductor pattern SPs exposed through the first hole H1 can be side surfaces in the first direction DR1. Two semiconductor pattern SPs located on opposite sides of the first hole H1 can face each other in the first direction DR1.

[0140] In some implementations, a plurality of first holes H1 may be formed to be spaced apart in a first direction DR1. Each of the plurality of first holes H1 may extend in a third direction DR3 and a second direction DR2, and each of the plurality of first holes H1 may have a wall shape extending in the third direction DR3 and the second direction DR2. The portion of the unit isolation insulating layer 130 located between adjacent first holes H1 may be referred to as an intermediate unit isolation insulating layer 130m. The portion of the unit isolation insulating layer 130 located on the other side surface of the intermediate unit isolation insulating layer 130m based on the first hole H1 may be referred to as a side unit isolation insulating layer 130s. The intermediate unit isolation insulating layer 130m and the side unit isolation insulating layer 130s located on both sides of the first hole H1 may face each other in the first direction DR1.

[0141] exist Figure 24In the implementation shown, with Figure 23 The implementation shown differs in that, after etching a portion of the initial intermediate insulating layer 120, a portion of the cell isolation insulating layer 130 can be etched. As a result, portions of the two side surfaces of the plurality of semiconductor patterns SP on the third direction DR3 and a portion of the upper surface of the substrate 110 can be further exposed. Although not shown, the two side surfaces of the plurality of semiconductor patterns SP on the second direction DR2 can also be exposed.

[0142] refer to Figures 26 to 29 Sacrificial metal silicide patterns SSC can be formed on the side surfaces of multiple semiconductor patterns SP in the first direction DR1. The sacrificial metal silicide patterns SSC can be formed, for example, by a region selective deposition (ASD) process. The sacrificial metal silicide patterns SSC are formed only on the surface of the semiconductor patterns SP and not on the surface of the cell isolation insulating layer 130 and the remaining intermediate insulating layer 120p.

[0143] The sacrificial metal silicide pattern SSC can cover the facing sides of two semiconductor patterns SP located on both sides of the first hole H1 in the first direction DR1. The sacrificial metal silicide pattern SSC can be connected between the two semiconductor patterns SP located on both sides of the first hole H1.

[0144] In some implementations, multiple sacrificial metal silicide patterns SSC can be formed corresponding to multiple semiconductor patterns SP. The multiple sacrificial metal silicide patterns SSC can be formed to be spaced apart in a first aperture H1 along a second direction DR2 and a third direction DR3. Multiple sacrificial metal silicide patterns SSC located in corresponding adjacent first apertures H1 can be spaced apart from each other along a first direction DR1.

[0145] Sacrificial metal silicide patterned SSCs may include metal silicide materials. For example, sacrificial metal silicide patterned SSCs may include cobalt silicide, titanium silicide, nickel silicide, or titanium silicon nitride, but are not limited to these.

[0146] exist Figure 28 In the implementation shown, with Figure 27 The implementation shown differs in that the sacrificial metal silicide pattern SSC can further cover a portion of the two side surfaces of the multiple semiconductor patterns SP on the third direction DR3 and a portion of the upper surface of the substrate 110. Although not shown, the sacrificial metal silicide pattern SSC can also cover a portion of the two side surfaces of the multiple semiconductor patterns SP on the second direction DR2.

[0147] like Figure 24 and Figure 28 As shown, as a portion of the cell isolation insulating layer 130 is further etched, Figure 28The sacrificial metal silicide pattern (SSC) shown in the implementation can be formed more efficiently than... Figure 27 The sacrificial metal silicide pattern SSC in the illustrated implementation is thick. Here, thickness can refer to the maximum width in the first direction DR1, the second direction DR2, and the third direction DR3. In this case, even if the sacrificial metal silicide pattern SSC becomes thinner in subsequent processes due to partial loss, it can still cover one side surface of the semiconductor pattern SP in the first direction DR1. Because the sacrificial metal silicide pattern SSC covers one side surface of the semiconductor pattern SP in the first direction DR1, the sacrificial metal silicide pattern SSC can be selectively removed later, and only the area of ​​the contact capacitor CP of the semiconductor pattern SP can be accurately exposed, thereby preventing bridging defects between adjacent capacitor CPs. Furthermore, with the... Figure 28 The implementation shown executes the process described later, which can form according to, as... Figure 6 or Figure 7 The semiconductor device shown is an implementation method.

[0148] refer to Figures 30 to 33 An intermediate insulating layer ST can be formed. The intermediate insulating layer ST can be formed by filling the first hole H1 with an insulating material. The intermediate insulating layer ST may include an insulating material. The intermediate insulating layer ST may include a material different from the material of the cell isolation insulating layer 130 and the semiconductor pattern SP. The intermediate insulating layer ST may include an insulating material with etch selectivity relative to the material of the cell isolation insulating layer 130 and the semiconductor pattern SP. For example, the cell isolation insulating layer 130 may include silicon oxide, and the semiconductor pattern SP may include silicon. For example, the intermediate insulating layer ST may include silicon nitride, silicon boron nitride, silicon carbonitride, or combinations thereof, but is not limited thereto.

[0149] The intermediate insulating layer ST may comprise the same material as the initial intermediate insulating layer 120 and the remaining intermediate insulating layers 120p. Therefore, the interface between the intermediate insulating layer ST and the remaining intermediate insulating layers 120p may be unidentifiable.

[0150] The intermediate insulating layer ST can be located on both sides of the sacrificial metal silicide pattern SSC in the third direction DR3. The intermediate insulating layer ST can be located on both sides of the sacrificial metal silicide pattern SSC in the second direction DR2. The intermediate insulating layer ST can surround the sacrificial metal silicide pattern SSC in the second direction DR2 and the third direction DR3.

[0151] The intermediate insulating layer ST may overlap with the sacrificial metal silicide pattern SSC on the third-direction DR3. The intermediate insulating layer ST may cover both side surfaces of the sacrificial metal silicide pattern SSC along the third-direction DR3. The intermediate insulating layer ST may contact both side surfaces of the sacrificial metal silicide pattern SSC along the third-direction DR3.

[0152] The intermediate insulating layer ST may overlap with the sacrificial metal silicide pattern SSC in the second direction DR2. The intermediate insulating layer ST may cover the side surface of the sacrificial metal silicide pattern SSC in the second direction DR2. The intermediate insulating layer ST may contact the side surface of the sacrificial metal silicide pattern SSC in the second direction DR2.

[0153] exist Figure 32 In the implementation shown, with Figure 31 The implementation shown differs in that the sacrificial metal silicide pattern SSC can overlap with the semiconductor pattern SP on the third direction DR3. Although not shown, the sacrificial metal silicide pattern SSC can also overlap with the semiconductor pattern SP on the second direction DR2.

[0154] refer to Figures 34 to 36 The intermediate cell isolation insulating layer 130m can be removed to expose the portion of multiple semiconductor patterns SP that were covered by the intermediate cell isolation insulating layer 130m.

[0155] First, a photoresist pattern can be formed on the upper surface of the intermediate cell isolation insulating layer 130m and the upper surface of the side cell isolation insulating layer 130s using a photolithography process to define the region for forming the second hole H2. For example, the region corresponding to the opening of the photoresist pattern can be defined as the region for forming the second hole H2. The second hole H2 can be formed by etching the intermediate cell isolation insulating layer 130m exposed by the opening of the photoresist pattern. For example, the intermediate cell isolation insulating layer 130m can be etched until one side surface of the intermediate insulating layer ST in the first direction DR1 is exposed through the opening of the photoresist pattern.

[0156] For example, when the intermediate insulating layer ST is not formed, the intermediate cell isolation insulating layer 130m and the side cell isolation insulating layers 130s may be indistinguishable. In this case, during the process of etching the cell isolation insulating layer 130 along the first direction DR1, the portion of the cell isolation insulating layer 130 located between the plurality of semiconductor patterns SP stacked on the third direction DR3 may not be etched uniformly on the first direction DR1. For example, the portion of the cell isolation insulating layer 130 located between the plurality of semiconductor patterns SP stacked on the third direction DR3 may have a reduced amount of etching on the first direction DR1 because they are closer to the upper surface of the substrate 110. Therefore, the side surface of the portion of the cell isolation insulating layer 130 located between the plurality of semiconductor patterns SP corresponding to the first direction DR1 may have an inclination instead of being aligned on the third direction DR3. For example, the side surface of the portion of the cell isolation insulating layer 130 located between the plurality of semiconductor patterns SP on the first direction DR1 may become farther away from the central axis of the second hole H2 on the third direction DR3 as they become farther away from the upper surface of the substrate 110. Additionally, each of the side surfaces of the portion of the cell isolation insulating layer 130 located between the plurality of semiconductor patterns SP in the first direction DR1 may be non-planar and may have a recessed shape in the first direction DR1. When subsequent processes are performed in the example described above, the device characteristics may deteriorate and variations in characteristics between devices may occur.

[0157] In some implementations, the intermediate insulating layer ST can be used as an etch stop layer in the process of etching the cell isolation insulating layer 130 along the first direction DR1. The process can continue etching the cell isolation insulating layer 130 on the first direction DR1 until the intermediate insulating layer ST is exposed along the side surface of the first direction DR1. Therefore, multiple semiconductor patterns SP stacked on the third direction DR3 can be exposed to the same length on the first direction DR1. Furthermore, since the side surface of the intermediate insulating layer ST between the multiple semiconductor patterns SP is flat on the first direction DR1, the degradation of device characteristics and the dispersion between devices may be reduced with subsequent processing of the surface.

[0158] For example, with the removal of the cell isolation insulating layer 130, a semiconductor pattern SP located between a plurality of sacrificial metal silicide patterns SSC spaced apart in the first direction DR1 can be exposed. For example, a semiconductor pattern SP located on one side of a reference plane defined by a plurality of sacrificial metal silicide patterns SSC spaced apart and arranged along the third direction DR3 and the second direction DR2, and surrounded by an intermediate insulating layer ST, can be exposed. Semiconductor patterns SP located on opposite sides of the reference plane in the first direction DR1 can be covered by the side cell isolation insulating layer 130s.

[0159] In some implementations, the surfaces of the semiconductor pattern SP, except for the surface that contacts the sacrificial metal silicide pattern SSC, can be exposed. For example, one side surface of the semiconductor pattern SP along the first direction DR1, two side surfaces of the semiconductor pattern SP along the second direction DR2, and two side surfaces of the semiconductor pattern SP along the third direction DR3 can be exposed. The other side surface of the semiconductor pattern SP along the first direction DR1 can be covered by the sacrificial metal silicide pattern SSC.

[0160] refer to Figures 37 to 39 This can form word lines WL and bit lines BL.

[0161] First, a first interlayer dielectric layer 142, a second interlayer dielectric layer 144, and a third interlayer dielectric layer 146 can be formed on a substrate 110, two adjacent intermediate insulating layers ST, and multiple semiconductor patterns SP. The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 can be formed sequentially.

[0162] The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may cover two side surfaces of the other ends of the plurality of semiconductor patterns SP on the third direction DR3 and two side surfaces of the other ends of the plurality of semiconductor patterns SP on the second direction DR2. The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may cover one side surface of each of two adjacent intermediate insulating layers ST on the first direction DR1. The first interlayer dielectric layer 142 may further cover the upper surface and side surface of the substrate 110 located between the two adjacent intermediate insulating layers ST. The third interlayer dielectric layer 146 may extend along the first direction DR1 between the plurality of semiconductor patterns SP stacked to be spaced apart from each other on the third direction DR3.

[0163] The first interlayer dielectric layer 142, the second interlayer dielectric layer 144, and the third interlayer dielectric layer 146 may each comprise an insulating material. The second interlayer dielectric layer 144 may comprise a material that is etch-selective relative to the material of the first interlayer dielectric layer 142. The third interlayer dielectric layer 146 may comprise a material that is etch-selective relative to the material of the second interlayer dielectric layer 144. In some implementations, the first interlayer dielectric layer 142 and the third interlayer dielectric layer 146 may comprise the same material, but are not limited thereto. For example, the first interlayer dielectric layer 142 and the third interlayer dielectric layer 146 may comprise silicon oxide, and the second interlayer dielectric layer 144 may comprise silicon nitride, but are not limited thereto.

[0164] Subsequently, a gate insulating layer Gox, a word line WL, and a word line capping layer WLC can be formed. For example, the gate insulating layer Gox, the word line WL, and the word line capping layer WLC can be sequentially formed between multiple semiconductor patterns SP and multiple third interlayer dielectric layers 146.

[0165] The gate insulating layer Gox may cover the portion between the two ends of each of the plurality of semiconductor patterns SP in the first direction DR1. The gate insulating layer Gox may cover the two side surfaces of each of the plurality of semiconductor patterns SP in the third direction DR3 and the two side surfaces of each of the plurality of semiconductor patterns SP in the second direction DR2. The gate insulating layer Gox may cover the two side surfaces of each of the plurality of third interlayer dielectric layers 146 in the third direction DR3.

[0166] The gate insulating layer Gox may include at least one of a high-k material, silicon oxide, silicon nitride, or silicon oxynitride. The high-k material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0167] The gate insulating layer Gox and word lines WL formed between the plurality of semiconductor patterns SP and the plurality of third interlayer dielectric layers 146 can fill the remaining space. The word lines WL can cover the portion of each of the plurality of semiconductor patterns SP located between the two ends in the first direction DR1 on the second direction DR2 and the third direction DR3. The word lines WL can extend in the second direction DR2. The gate insulating layer Gox can be located between the word lines WL and the semiconductor patterns SP. The word lines WL can be spaced apart from the semiconductor patterns SP by the gate insulating layer Gox.

[0168] In the described implementation, the word line WL has been described as a peripheral surface centered on a first direction DR1 surrounding a specific region of the semiconductor pattern SP (e.g., two side surfaces on a third direction DR3 and two side surfaces on a second direction DR2), but the implementation is not limited to this. For example, two word lines WL may be positioned spaced apart from each other on two side surfaces of the semiconductor pattern SP on the third direction DR3. Alternatively, a word line WL may also be located on only one side surface of the semiconductor pattern SP on the third direction DR3.

[0169] In some implementations, multiple word lines WL can be formed and spaced apart and arranged on a third direction DR3. The multiple word lines WL can be further spaced apart and arranged on a first direction DR1. Each of the multiple word lines WL can extend across multiple semiconductor patterns SP spaced apart and arranged on a second direction DR2. The multiple semiconductor patterns SP spaced apart and arranged on the second direction DR2 can be electrically connected to a word line WL.

[0170] Word lines (WL) may include conductive materials. For example, word lines (WL) may include: doped semiconductor materials, such as doped silicon or doped germanium; conductive metal nitrides, such as titanium nitride or tantalum nitride; metals, such as tungsten, titanium, or tantalum; metal semiconductor compounds, such as tungsten silicide, cobalt silicide, or titanium silicide; or combinations thereof.

[0171] The word line overlay layer WLC can cover one side surface of the word line WL in the first direction DR1. The two side surfaces of the word line overlay layer WLC in the third direction DR3 and the two side surfaces of the word line overlay layer WLC in the second direction DR2 can be covered by the gate insulating layer Gox.

[0172] The word line overlay (WLC) may include an insulating material. For example, the word line overlay (WLC) may include silicon nitride, but is not limited to this.

[0173] Subsequently, a first insulating pad 152, a second insulating pad 154, and an isolation insulating layer 156 can be formed. First, the first insulating pad 152 and the second insulating pad 154 can be sequentially formed on a plurality of semiconductor patterns SP, a word line overlay layer WLC located between the plurality of semiconductor patterns SP, a gate insulating layer Gox, and a third interlayer dielectric layer 146. The first insulating pad 152 and the second insulating pad 154 can cover one end of each of the plurality of semiconductor patterns SP in the first direction DR1 and two side surfaces in the third direction DR3, and one end of each of the plurality of semiconductor patterns SP in the first direction DR1 and two side surfaces in the second direction DR2. The first insulating pad 152 and the second insulating pad 154 can cover a portion of one end of each of the plurality of semiconductor patterns SP in the first direction DR1 and a portion of one side surface in the first direction DR1. The first insulating pad 152 and the second insulating pad 154 can cover one side surface of the gate insulating layer Gox, the word line overlay layer WLC, and the third interlayer dielectric layer 146 located between the plurality of semiconductor patterns SP in the first direction DR1.

[0174] Subsequently, an insulating layer 156 can be formed to cover the first insulating pad 152 and the second insulating pad 154. After the first insulating pad 152 and the second insulating pad 154 are formed, the insulating layer 156 can fill the remaining space between the plurality of semiconductor patterns SP spaced apart in the first direction DR1 and between the plurality of word line overlay layers WLC spaced apart in the first direction DR1.

[0175] The first insulating pad 152, the second insulating pad 154, and the insulating layer 156 may comprise insulating materials. For example, the first insulating pad 152, the second insulating pad 154, and the insulating layer 156 may each comprise silicon oxide or silicon nitride, but are not limited thereto. The second insulating pad 154 may comprise a material that is etch-selective relative to the material of the first insulating pad 152. The insulating layer 156 may comprise a material that is etch-selective relative to the material of the second insulating pad 154. For example, the first insulating pad 152 and the insulating layer 156 may comprise silicon oxide, and the second insulating pad 154 may comprise silicon nitride, but are not limited thereto.

[0176] Subsequently, a lower insulating layer 158 and a bit line BL can be formed. The bit line BL can be formed on the lower insulating layer 158. The lower insulating layer 158 can be located between the first interlayer dielectric layer 142 covering the upper and side surfaces of the substrate 110 and the bit line BL. The bit line BL can be spaced apart from the substrate 110 by the lower insulating layer 158 and the first interlayer dielectric layer 142.

[0177] Bit lines BL can extend on the third direction DR3. Bit lines BL can be spaced apart on the third direction DR3 and connected to one end of each of the plurality of semiconductor patterns SP stacked on the first direction DR1. For example, bit lines BL can contact a side surface of a semiconductor pattern SP on the first direction DR1. The first insulating pad 152, the second insulating pad 154, and the isolation insulating layer 156 may not be provided between a side surface of a semiconductor pattern SP on the first direction DR1 and the bit lines BL.

[0178] Bit line BL can be located between two semiconductor patterns SP spaced apart along the first direction DR1. In some implementations, bit line BL can be connected to the two semiconductor patterns SP spaced apart along the first direction DR1, but this is not a limitation. For example, two bit lines BL can be formed between two semiconductor patterns SP spaced apart along the first direction DR1. In this case, the two semiconductor patterns SP spaced apart along the first direction DR1 can each be connected to a different bit line BL.

[0179] In some implementations, multiple bit lines BL spaced apart in the second direction DR2 can be formed. The insulating layer 156 can be located between the multiple bit lines BL spaced apart in the second direction DR2.

[0180] Bit lines BL can include conductive materials. For example, bit lines BL can include: doped semiconductor materials, such as doped silicon or doped germanium; conductive metal nitrides, such as titanium nitride or tantalum nitride; metals, such as tungsten, titanium or tantalum; metal semiconductor compounds, such as tungsten silicide, cobalt silicide or titanium silicide; or combinations thereof.

[0181] The lower insulating layer 158 may include an insulating material. For example, the lower insulating layer 158 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof, but is not limited thereto.

[0182] In the following text, the multiple semiconductor patterns SP, multiple bit lines BL, multiple sacrificial metal silicide patterns SSC, multiple intermediate insulating layers ST, multiple word lines WL, and various other insulating layers formed on the substrate 110 may be referred to as intermediate structures.

[0183] refer to Figures 40 to 42 The side cell isolation insulating layer 130s can be removed to expose a portion of the multiple semiconductor patterns SP covered by the side cell isolation insulating layer 130s.

[0184] First, a photoresist pattern can be formed on the upper surface of the intermediate structure on the substrate 110 using a photolithography process to define the region where the third hole H3 is formed. For example, the region corresponding to the opening of the photoresist pattern can be defined as the region where the third hole H3 is formed. The third hole H3 can be formed by etching the side cell isolation insulating layer 130s exposed by the opening of the photoresist pattern. For example, the etching of the side cell isolation insulating layer 130s can be performed until one side surface of the intermediate insulating layer ST in the first direction DR1 is exposed through the opening of the photoresist pattern.

[0185] For example, in the absence of an intermediate insulating layer ST, during the process of etching the side cell isolation insulating layer 130s along the first direction DR1, the portion of the side cell isolation insulating layer 130s located between multiple stacked semiconductor patterns SP on the third direction DR3 may not be etched uniformly on the first direction DR1. For example, the portion of the side cell isolation insulating layer 130s located between multiple stacked semiconductor patterns SP may have a reduced etching amount on the first direction DR1 as they become closer to the upper surface of the substrate 110. As a result, the side surfaces of the portion of the side cell isolation insulating layer 130s located between multiple semiconductor patterns SP on the first direction DR1 may be misaligned on the third direction DR3 and may have an angle. For example, as the side surfaces of the portion of the side cell isolation insulating layer 130s located between multiple semiconductor patterns SP on the first direction DR1 become farther from the upper surface of the substrate 110, they may become farther from the central axis of the third hole H3 on the third direction DR3. Furthermore, each of the side surfaces of the portion of the side cell isolation insulating layer 130s located between the plurality of semiconductor patterns SP in the first direction DR1 may be uneven and may have a recessed shape in the first direction DR1. If subsequent processes are performed in the aforementioned example, the device characteristics may deteriorate and differences in characteristics between devices may occur.

[0186] In some implementations, the intermediate insulating layer ST can be used as an etch stop layer in the process of etching the side cell isolation insulating layer 130s along the first direction DR1. In the process of etching the side cell isolation insulating layer 130s along the first direction DR1, the side cell isolation insulating layer 130s can be etched until the side surface of the intermediate insulating layer ST on the first direction DR1 is exposed. Therefore, multiple semiconductor patterns SP stacked on the third direction DR3 can be exposed to the same length on the first direction DR1. Since the intermediate insulating layer ST is flat along the side surface of the first direction DR1 between the multiple semiconductor patterns SP, subsequent surface processing can reduce device characteristic degradation and inter-device distribution.

[0187] In other words, the intermediate insulating layer ST can be Figures 34 to 36 The process and Figures 40 to 42 The process shown uses etch stop layers in both directions.

[0188] For example, as the side cell isolation insulating layer 130s is removed, the semiconductor pattern SP located on the opposite side of the bit line BL, which is situated on one of the multiple sacrificial metal silicide patterns SSC on the first direction DR1, can be exposed. For example, the semiconductor pattern SP located on the other side of the reference plane defined by the multiple sacrificial metal silicide patterns SSC spaced apart and arranged along the third direction DR3 and the second direction DR2, and the intermediate insulating layer ST surrounding them, can be exposed. The semiconductor pattern SP located on the other side of the reference plane on the first direction DR1 can be connected to the bit line BL.

[0189] In some implementations, the surfaces of the semiconductor pattern SP, except for the surface that contacts the sacrificial metal silicide pattern SSC, can be exposed. For example, one side surface of the semiconductor pattern SP in the first direction DR1, two side surfaces of the semiconductor pattern SP in the second direction DR2, and two side surfaces of the semiconductor pattern SP in the third direction DR3 can be exposed. The other side surface of the semiconductor pattern SP in the first direction DR1 can be covered by the sacrificial metal silicide pattern SSC.

[0190] refer to Figures 43 to 45 A capacitor molded part CM can be formed on the substrate 110 and the intermediate insulating layer ST.

[0191] In some implementations, the capacitor molding CM can be formed to be spaced apart from the surface of the semiconductor pattern SP. The capacitor molding CM may include a first molding layer 162, a second molding layer 164, a third molding layer 166, and a fourth molding layer 168. The first molding layer 162, the second molding layer 164, the third molding layer 166, and the fourth molding layer 168 may be formed sequentially on the substrate 110 and the intermediate insulating layer ST.

[0192] The first molding layer 162 may cover a portion of the other side surface of the intermediate insulating layer ST in the first direction DR1. The first molding layer 162 may not cover the portion of the other side surface of the intermediate insulating layer ST adjacent to the sacrificial metal silicide pattern SSC in the first direction DR1.

[0193] The second molding layer 164 may cover the first molding layer 162. The second molding layer 164 may include a vertical portion extending in the third direction DR3 and a horizontal portion extending from the vertical portion in the first direction DR1. The second molding layer 164 may extend in the first direction DR1 and may have a hollow cylindrical shape. The first molding layer 162 and the second molding layer 164 may further cover the upper surface and side surface of the substrate 110.

[0194] The third molding layer 166 may cover the second molding layer 164. The third molding layer 166 may fill the internal space surrounded by the second molding layer 164. The third molding layer 166 may be surrounded by the second molding layer 164.

[0195] The fourth molding layer 168 may cover the third molding layer 166. The fourth molding layer 168 may cover one side surface of the third molding layer 166 in the first direction DR1. The other side surface of the third molding layer 166 in the first direction DR1 may be covered by the second molding layer 164.

[0196] The first molding layer 162, the second molding layer 164, the third molding layer 166, and the fourth molding layer 168 may all comprise an insulating material. The second molding layer 164 may comprise a material that is etch-selective relative to the material of the first molding layer 162. The third molding layer 166 may comprise a material that is etch-selective relative to the material of the second molding layer 164. The fourth molding layer 168 may comprise a material that is etch-selective relative to the material of the third molding layer 166. In some implementations, the first molding layer 162 and the third molding layer 166 may comprise the same first material, and the second molding layer 164 and the fourth molding layer 168 may comprise the same second material. For example, the first material may comprise silicon nitride, and the second material may comprise silicon oxide, but is not limited thereto.

[0197] refer to Figures 46 to 48 The semiconductor pattern SP located on the opposite side of the bit line BL, which is one of the two sides of the sacrificial metal silicide pattern SSC on the first direction DR1, can be removed. For example, by using a material with high etch selectivity for the semiconductor pattern SP relative to the intermediate insulating layer ST, the sacrificial metal silicide pattern SSC, and the capacitor molding CM, the semiconductor pattern SP can be selectively removed only. Therefore, the opposite surface of the side surface of the sacrificial metal silicide pattern SSC that is covered by the semiconductor pattern SP connected to the bit line BL on the two side surfaces of the sacrificial metal silicide pattern SSC on the first direction DR1 can be exposed.

[0198] refer to Figures 49 to 51 This method can remove sacrificial metal silicide patterned SSCs. For example, materials with high etch selectivity for sacrificial metal silicide patterned SSCs relative to the intermediate insulating layer ST, semiconductor pattern SP, and capacitor molded component CM can be used to selectively remove sacrificial metal silicide patterned SSCs only. For example, low aluminum loss (LAL) etchants can be used to remove sacrificial metal silicide patterned SSCs, but this is not the only possibility, and the materials used to etch sacrificial metal silicide patterned SSCs can be varied.

[0199] As the sacrificial metal silicide pattern SSC is removed, the other end of multiple semiconductor patterns SP on the first direction DR1 can be exposed, thereby connecting one end of the multiple semiconductor patterns SP on the first direction DR1 to the bit line BL.

[0200] For example, when the sacrificial metal silicide pattern SSC is not formed, the other ends of multiple semiconductor patterns SP in the first direction DR1 can be covered by an intermediate insulating layer ST. In this case, during the process of opening the other ends of the multiple semiconductor patterns SP in the first direction DR1, it may be difficult to accurately etch and remove only the portion of the intermediate insulating layer ST covering the semiconductor pattern SP. For example, when etching and removing the portion extending to the intermediate insulating layer ST covering the first interlayer dielectric layer 142, bridging defects may occur where the capacitors CP of adjacent semiconductor patterns SP become electrically connected during subsequent capacitor CP formation processes. To prevent such bridging defects, the sacrificial metal silicide pattern SSC is formed to cover the other ends of the semiconductor patterns SP in the first direction DR1 so that it can be opened in subsequent processes, and by selectively removing the sacrificial metal silicide pattern SSC, it is possible to accurately open only the necessary portion (the other ends of the semiconductor patterns SP in the first direction DR1).

[0201] refer to Figures 52 to 54 A metal silicide pattern SC can be formed on the opposite surface of each of a plurality of semiconductor patterns SP in a first direction DR1. For example, the semiconductor pattern SP may include silicon. Initially, after depositing a metal layer to cover the plurality of semiconductor patterns SP, an intermediate insulating layer ST, and a capacitor molding CM, a silicide reaction can be initiated in the portion of the metal layer that contacts the semiconductor pattern SP by heat treatment. Subsequently, a metal silicide pattern SC can be formed on each semiconductor pattern SP by selectively removing the portions of the metal layer that have not yet undergone the silicide reaction.

[0202] In some implementations, multiple metal silicide patterns SC can be located on the opposite surface of multiple semiconductor patterns SP in the first direction DR1. The metal silicide patterns SC can cover the opposite surface of the semiconductor patterns SP in the first direction DR1. An intermediate insulating layer ST can be located on both sides of the metal silicide patterns SC in the third direction DR3 and on both sides of the metal silicide patterns SC in the second direction DR2. The two side surfaces of the metal silicide patterns SC in the third direction DR3 and the two side surfaces of the metal silicide patterns SC in the second direction DR2 can be covered by the intermediate insulating layer ST.

[0203] In some implementations, the two side surfaces of the metal silicide pattern SC on the third direction DR3 and the two side surfaces of the metal silicide pattern SC on the second direction DR2 can contact the intermediate insulating layer ST, but this is not limited to these embodiments. For example, as... Figure 6 As shown, the two side surfaces of the metal silicide pattern SC on the third direction DR3 and the two side surfaces of the metal silicide pattern SC on the second direction DR2 can be spaced apart from the intermediate insulating layer ST.

[0204] In some implementations, the width of the metal silicide pattern SC in the third direction DR3 can be the same as the width of the semiconductor pattern SP in the third direction DR3. The width of the metal silicide pattern SC in the second direction DR2 can also be the same as the width of the semiconductor pattern SP in the second direction DR2. However, the implementation is not limited to this. For example, as... Figure 6 and Figure 7 As shown, the metal silicide pattern SC can be formed to further cover the two side surfaces of the semiconductor pattern SP in the third direction DR3 and the two side surfaces of the semiconductor pattern SP in the second direction DR2. In this case, the width of the metal silicide pattern SC in the third direction DR3 can be greater than the width of the semiconductor pattern SP in the third direction DR3. The width of the metal silicide pattern SC in the second direction DR2 can be greater than the width of the semiconductor pattern SP in the second direction DR2.

[0205] In some implementations, the width of the metal silicide pattern SC in the first direction DR1 may be smaller than the width of the intermediate insulating layer ST in the first direction DR1, but it is not limited to this. For example, the width of the metal silicide pattern SC in the first direction DR1 may be the same as or greater than the width of the intermediate insulating layer ST in the first direction DR1.

[0206] The metal silicide pattern SC may include a metal silicide material. The work function of the metal silicide pattern SC may have a value between the work function of the material of the first electrode 171 and the work function of the material of the semiconductor pattern SP. The metal silicide pattern SC can reduce the work function difference between the material of the first electrode 171 and the material of the semiconductor pattern SP, thereby reducing the contact resistance between the semiconductor pattern SP and the capacitor CP. For example, the metal silicide pattern SC may include cobalt silicide, titanium silicide, nickel silicide, or titanium silicon nitride, but is not limited thereto.

[0207] refer to Figures 55 to 57 It can remove the capacitor molding part CM and form the capacitor CP.

[0208] First, a first electrode 171 can be formed. For example, after depositing a first electrode material layer on a metal silicide pattern SC, an intermediate insulating layer ST, and a capacitor molding CM, a portion of the first electrode material layer covering a side surface of the capacitor molding CM in a first direction DR1 can be removed by an etching process, thereby forming a plurality of first electrodes 171. The plurality of first electrodes 171 can be spaced apart by the capacitor molding CM in a second direction DR2 and a third direction DR3.

[0209] Each of the plurality of first electrodes 171 may contact one side surface of the metal silicide pattern SC in the first direction DR1. The other side surface of the metal silicide pattern SC in the first direction DR1 may contact the semiconductor pattern SP. The first electrode 171 may cover the portion of the intermediate insulating layer ST not covered by the capacitor molding CM. The first electrode 171 may cover a portion of one side surface of the intermediate insulating layer ST located on both sides of the metal silicide pattern SC in the first direction DR1.

[0210] The width of the metal silicide pattern SC in the first direction DR1 can be smaller than the width of the intermediate insulating layer ST in the first direction DR1, thereby exposing some portions of the surfaces of the intermediate insulating layers ST facing each other in the third direction DR3 on both sides of the metal silicide pattern SC, and some portions of the surfaces of the intermediate insulating layers ST facing each other in the second direction DR2. The first electrode 171 can cover some portions of the surfaces of the intermediate insulating layers ST facing each other in the third direction DR3 on both sides of the metal silicide pattern SC, and some portions of the surfaces of the intermediate insulating layers ST facing each other in the second direction DR2. Some portions of the first electrode 171 can be surrounded by the intermediate insulating layer ST in the third direction DR3 and the second direction DR2.

[0211] Subsequently, the capacitor molded part CM can be removed.

[0212] Subsequently, a dielectric layer 173 and a second electrode 175 can be formed sequentially. The dielectric layer 173 and the second electrode 175 can be formed to conformally cover a plurality of first electrodes 171. The dielectric layer 173 can cover one side surface of the plurality of first electrodes 171 in a first direction DR1, two side surfaces of the plurality of first electrodes 171 in a third direction DR3, and two side surfaces of the plurality of first electrodes 171 in a second direction DR2. The dielectric layer 173 can further cover one side surface of an intermediate insulating layer ST in the first direction DR1. The second electrode 175 can cover the dielectric layer 173. The second electrode 175 can be spaced apart from the plurality of first electrodes 171 by the dielectric layer 173.

[0213] The first electrode 171, the dielectric layer 173, and the second electrode 175 can form a capacitor CP. In some implementations, multiple capacitors CP, each including a plurality of first electrodes 171, can be formed. The multiple capacitors CP can be connected to multiple semiconductor patterns SP. Each first electrode 171 of the multiple capacitors CP can be connected to the semiconductor pattern SP via a metal silicide pattern SC.

[0214] Multiple capacitors CP can be arranged spaced apart on a third direction DR3 and a second direction DR2. The multiple capacitors CP may include multiple first electrodes 171 spaced apart on the third direction DR3 and the second direction DR2. The multiple first electrodes 171 spaced apart on the third direction DR3 and the second direction DR2 may be covered by a single dielectric layer 173 and a single second electrode 175. The dielectric layer 173 of each of the multiple capacitors CP spaced apart on the third direction DR3 and the second direction DR2 may be connected to each other. The second electrode 175 of each of the multiple capacitors CP spaced apart on the third direction DR3 and the second direction DR2 may be connected to each other.

[0215] Subsequently, a plate electrode PL can be formed. For example, in the case of forming a first electrode 171, a dielectric layer 173, and a second electrode 175, the plate electrode PL can fill the remaining space opposite to the side where the intermediate insulating layer ST is located and the bit line BL is located. The plate electrode PL can cover the second electrode 175 of a plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3. The plate electrode PL can be connected to the plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3.

[0216] In some implementations, the plate electrode PL may include a first portion PL_1 and a second portion PL_2, the first portion PL_1 extending in a third direction DR3 and a second direction DR2, and the second portion PL_2 extending from the first portion PL_1 in a first direction DR1. The first portion PL_1 may have a wall shape extending in the third direction DR3 and the second direction DR2. The second portion PL_2 may surround the first electrode 171 of a plurality of capacitors CP arranged along the second direction DR2 and the third direction DR3.

[0217] However, the implementation is not limited to this, and for example, such as Figure 8 and Figure 9 As shown, the structure and shape of the capacitor CP and the plate electrode PL can be modified in different ways.

[0218] The first electrode 171, the second electrode 175, and the plate electrode PL may all comprise conductive materials. Each of the first electrode 171, the second electrode 175, and the plate electrode PL may comprise at least one of the following: a metallic material, such as titanium, tantalum, tungsten, copper, or aluminum; a conductive metal nitride, such as titanium nitride or tantalum nitride; or a doped semiconductor material, such as doped silicon or doped germanium. The first electrode 171 and the second electrode 175 may comprise the same material, and the plate electrode PL may comprise a material different from the material of the first electrode 171 and the second electrode 175. For example, the first electrode 171 and the second electrode 175 may comprise titanium nitride, and the plate electrode 194 may comprise doped silicon-germanium.

[0219] The dielectric layer 173 may include at least one of a dielectric, a ferroelectric, or an antiferroelectric. The dielectric may include a high-k material. For example, the dielectric may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, scandium tantalum lead oxide, lead zinc niobate, or combinations thereof.

[0220] According to some implementations, the semiconductor device can have a symmetrical structure relative to the bit line BL extending in the third direction DR3. The two side surfaces of the bit line BL in the first direction DR1 can each be connected to one end of the semiconductor pattern SP in the first direction DR1. The other end of the semiconductor pattern SP in the first direction DR1 can be connected to the capacitor CP. A metal silicide pattern SC can be located between the other end of the semiconductor pattern SP in the first direction DR1 and the capacitor CP. An intermediate insulating layer ST can be located on both sides of the metal silicide pattern SC in the third direction DR3 and on both sides of the metal silicide pattern SC in the second direction DR2. Word lines WL can be located on both sides of each semiconductor pattern SP in the third direction DR3. Word lines WL can extend in the second direction DR2.

[0221] Figures 40 to 57 The description is based on one side of the bit line BL in the first direction DR1, but the same process can also be performed simultaneously on the other side of the bit line BL in the first direction DR1.

[0222] The implementation of this disclosure has been described in detail above, but the scope of this disclosure is not limited thereto. Alternatively, various modifications and improvements made by those skilled in the art using the basic concept of this disclosure as defined in the appended claims are also included within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; Multiple semiconductor patterns are stacked on the substrate and spaced apart from each other. Bit lines are connected to a first end of the plurality of semiconductor patterns in a first direction and extend in a direction perpendicular to the upper surface of the substrate; The word line overlaps with each of the plurality of semiconductor patterns in the direction perpendicular to the upper surface of the substrate, and extends in a second direction intersecting the first direction; A capacitor connected to a second end of each of the plurality of semiconductor patterns in the first direction; Metal silicide patterns are located between each semiconductor pattern and the capacitor; as well as An intermediate insulating layer overlaps the metal silicide pattern in a direction perpendicular to the upper surface of the substrate.

2. The semiconductor device according to claim 1, in, The metal silicide pattern contacts the second end of each semiconductor pattern in the first direction, and The intermediate insulating layer is located on the upper and lower surfaces of the metal silicide pattern.

3. The semiconductor device according to claim 2, wherein, The upper and lower surfaces of the metal silicide pattern are in contact with the intermediate insulating layer.

4. The semiconductor device according to claim 2, wherein, The capacitor includes portions located between the upper surface of the metal silicide pattern and the intermediate insulating layer, and between the lower surface of the metal silicide pattern and the intermediate insulating layer.

5. The semiconductor device according to claim 2, wherein, The first side surface of the metal silicide pattern that contacts each semiconductor pattern in the first direction is aligned with the first side surface of the intermediate insulating layer in the first direction in the direction perpendicular to the upper surface of the substrate.

6. The semiconductor device according to claim 2, wherein, Each semiconductor pattern includes a portion that overlaps with the intermediate insulating layer in the direction perpendicular to the upper surface of the substrate.

7. The semiconductor device according to claim 6, wherein, The metal silicide pattern includes a portion located between each semiconductor pattern and the intermediate insulating layer.

8. The semiconductor device of claim 1, further comprising a plate electrode, wherein the capacitor is provided as a plurality of capacitors, and the plate electrode is connected to the plurality of capacitors, wherein, Each of the plurality of capacitors is connected to a corresponding semiconductor pattern in the plurality of semiconductor patterns. Each of the plurality of capacitors includes a corresponding first electrode, a corresponding second electrode, and a corresponding dielectric layer. The corresponding first electrode contacts the metal silicide pattern, the corresponding second electrode is located on the corresponding first electrode, and the corresponding dielectric layer is located between the corresponding first electrode and the corresponding second electrode. The respective dielectric layers of the plurality of capacitors are connected together, and the respective second electrodes of the plurality of capacitors are connected together.

9. The semiconductor device according to claim 8, wherein, For each of the plurality of capacitors, the corresponding dielectric layer of the capacitor contacts a first side of the intermediate insulating layer in the first direction.

10. The semiconductor device according to claim 9, in, For each of the plurality of capacitors, the corresponding first electrode of the capacitor has a columnar shape extending in the first direction, and the corresponding first electrode is surrounded by the corresponding dielectric layer and the corresponding second electrode of the capacitor. The plate electrode includes a first portion and a second portion. The first portion extends on a first side of the respective first electrode of the plurality of capacitors in the first direction in a direction perpendicular to the upper surface of the substrate. The second portion extends from the first portion in the first direction and is located between the respective first electrodes.

11. The semiconductor device according to claim 9, wherein, For each of the plurality of capacitors, the corresponding first electrode has the shape of a hollow cylinder, and The corresponding dielectric layer and the corresponding second electrode of the capacitor cover the outer and inner surfaces of the corresponding first electrode.

12. The semiconductor device according to claim 8, wherein, For each of the plurality of capacitors, the corresponding dielectric layer is spaced apart from the first side of the intermediate insulating layer in the first direction.

13. The semiconductor device according to claim 12, wherein, For each of the plurality of capacitors, the corresponding first electrode has the shape of a hollow cylinder, and The corresponding dielectric layer and the corresponding second electrode of the capacitor cover the inner side of the corresponding first electrode.

14. The semiconductor device according to claim 1, wherein, The intermediate insulating layer comprises a first material that is different from the second material of each semiconductor pattern.

15. A semiconductor device, the semiconductor device comprising: Substrate; Multiple semiconductor patterns are stacked on the substrate and spaced apart from each other. Bit lines are connected to a first end of the plurality of semiconductor patterns in a first direction and extend in a direction perpendicular to the upper surface of the substrate; The word line overlaps with each of the plurality of semiconductor patterns in the direction perpendicular to the upper surface of the substrate, and extends in a second direction intersecting the first direction; A capacitor, the capacitor being connected to a second end of each of the plurality of semiconductor patterns in the first direction; Metal silicide patterns are located between each semiconductor pattern and the capacitor; as well as An intermediate insulating layer surrounds the metal silicide pattern.

16. The semiconductor device according to claim 15, wherein, The direction perpendicular to the upper surface of the substrate is a third direction, and The intermediate insulating layer is located on two opposite sides of the metal silicide pattern in the second direction and on two opposite sides of the metal silicide pattern in the third direction.

17. The semiconductor device according to claim 15, wherein, The metal silicide pattern contacts the intermediate insulating layer.

18. The semiconductor device according to claim 15, wherein, The capacitor includes a portion located between the metal silicide pattern and the intermediate insulating layer.

19. The semiconductor device according to claim 15, wherein, The metal silicide pattern contacts each semiconductor pattern in the first direction and in the direction perpendicular to the upper surface of the substrate.

20. A semiconductor device, the semiconductor device comprising: Substrate; An intermediate insulating layer extends in a direction perpendicular to the upper surface of the substrate; Multiple metal silicide patterns, the multiple metal silicide patterns being spaced apart by the intermediate insulating layer; Multiple semiconductor patterns, each of which is connected to a first side surface of a multiple metal silicide pattern in a first direction; Bit lines, the bit lines being connected to a first end of the plurality of semiconductor patterns in the first direction and extending in the direction perpendicular to the upper surface of the substrate; Multiple word lines, each word line being adjacent to the multiple semiconductor patterns and extending in a second direction intersecting the first direction; as well as Multiple capacitors, each connected to a second side surface of the multiple metal silicide patterns in the first direction, The intermediate insulating layer is located on two opposite sides of each of the plurality of metal silicide patterns in the second direction and on two opposite sides of each of the plurality of metal silicide patterns in the direction perpendicular to the upper surface of the substrate.

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