Semiconductor devices and semiconductor memory devices

Abstract

This invention relates to a semiconductor device and a semiconductor memory device. The semiconductor device includes: a first electrode; a second electrode; a first oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode opposing the first oxide semiconductor layer and extending in a first direction; a first gate insulating layer disposed between the gate electrode and the first oxide semiconductor layer, surrounding the first oxide semiconductor layer, and comprising at least one element combination selected from the group consisting of a combination of silicon (Si) and nitrogen (N), a combination of titanium (Ti) and oxygen (O), and a combination of aluminum (Al) and oxygen (O); and a first insulating layer comprising a first portion and a second portion in a first cross-section perpendicular to a second direction connecting the first electrode and the second electrode and including the gate electrode, wherein a gate electrode is disposed between the first portion and the second portion, the first portion being in contact with the first gate insulating layer, and the second portion being in contact with the gate electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and semiconductor memory devices. Background Technology

[0002] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess excellent characteristics such as extremely low channel leakage current during cutoff operation. Therefore, OSTs can be used, for example, as switching transistors in memory cells of Dynamic Random Access Memory (DRAM). Summary of the Invention

[0003] The problem to be solved by the present invention is to provide a semiconductor device with excellent transistor characteristics.

[0004] The semiconductor device of the embodiment includes: a first electrode; a second electrode; a first oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode opposing the first oxide semiconductor layer and extending in a first direction; a first gate insulating layer disposed between the gate electrode and the first oxide semiconductor layer, surrounding the first oxide semiconductor layer, and comprising at least one element combination selected from the group consisting of a combination of silicon (Si) and nitrogen (N), a combination of titanium (Ti) and oxygen (O), and a combination of aluminum (Al) and oxygen (O); and a first insulating layer comprising a first portion and a second portion in a first cross-section perpendicular to a second direction connecting the first electrode and the second electrode and including the gate electrode, wherein the gate electrode is disposed between the first portion and the second portion, the first portion being in contact with the first gate insulating layer, and the second portion being in contact with the gate electrode. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0006] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0007] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0008] Figure 4 This is an enlarged schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 5 This is an enlarged schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 6This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 7 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0012] Figure 8 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0013] Figure 9 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0014] Figure 10 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0015] Figure 11 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0016] Figure 12 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figure 13 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0018] Figure 14 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0019] Figure 15 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0020] Figure 16 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0021] Figure 17 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0022] Figure 18 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0023] Figure 19 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0024] Figure 20 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0025] Figure 21 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0026] Figure 22 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0027] Figure 23 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0028] Figure 24 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0029] Figure 25 This is an enlarged schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0030] Figure 26 This is an enlarged schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0031] Figure 27 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0032] Figure 28 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0033] Figure 29 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0034] Figure 30 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0035] Figure 31 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0036] Figure 32 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0037] Figure 33 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0038] Figure 34 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0039] Figure 35 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0040] Figure 36This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0041] Figure 37 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0042] Figure 38 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0043] Figure 39 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0044] Figure 40 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0045] Figure 41 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0046] Figure 42 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0047] Figure 43 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0048] Figure 44 This is an equivalent circuit diagram of the semiconductor memory device according to the fifth embodiment.

[0049] Figure 45 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment.

[0050] Explanation of symbols 12: Lower electrode (first electrode); 14: Upper electrode (second electrode); 16: Oxide semiconductor layer; 16a: First oxide semiconductor layer; 16b: Second oxide semiconductor layer; 16c: Third oxide semiconductor layer; 18: Gate electrode; 20: Gate insulating layer; 20a: First gate insulating layer; 20b: Second gate insulating layer; 20c: Third gate insulating layer; 20x: First film; 20y: Second film; 22: Interlayer insulating layer (first insulating layer); 22a: First part; 22b: Second part; 100: Transistor (semiconductor device); 200: Transistor (semiconductor device); 300: Transistor (semiconductor device); 400: Transistor (semiconductor device); 500: Semiconductor memory (semiconductor storage device); CA: Capacitor. Detailed Implementation

[0051] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have been described once before will sometimes be omitted.

[0052] In addition, for convenience, terms such as "upper," "lower," "upper part," or "lower part" are sometimes used in this specification. "Upper," "lower," "upper part," or "lower part" are merely terms indicating relative positional relationships within the accompanying drawings, and do not specify positional relationships relative to gravity.

[0053] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device and semiconductor memory device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness of the components constituting the semiconductor device and semiconductor memory device, the distance between components, and the crystal grain size can be performed, for example, by using a transmission electron microscope (TEM). Furthermore, in the identification of constituent materials of components constituting semiconductor devices and semiconductor memory devices, and in the measurement of the proportion of constituent materials, X-ray photoelectron spectroscopy (XPS), hard X-ray photoelectron spectroscopy (HAXPES), and electron energy loss spectroscopy (EELS) can be used, for example.

[0054] In this specification, "metal" is a general term for substances that exhibit metallic properties. For example, metal compounds that exhibit metallic properties, such as metal nitrides and metal carbides, are also included in the scope of "metal".

[0055] (First Implementation) The semiconductor device according to the first embodiment includes: a first electrode; a second electrode; a first oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode opposing the first oxide semiconductor layer and extending in a first direction; a first gate insulating layer disposed between the gate electrode and the first oxide semiconductor layer, surrounding the first oxide semiconductor layer, and comprising at least one element combination selected from the group consisting of a combination of silicon (Si) and nitrogen (N), a combination of titanium (Ti) and oxygen (O), and a combination of aluminum (Al) and oxygen (O); and a first insulating layer comprising a first portion and a second portion in a first cross-section perpendicular to a second direction connecting the first electrode and the second electrode and including the gate electrode, wherein a gate electrode is disposed between the first portion and the second portion, the first portion being in contact with the first gate insulating layer, and the second portion being in contact with the gate electrode.

[0056] Figure 1 , Figure 2 and Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 yes Figure 1 AA' section. Figure 1 yes Figure 3 BB' section. Figure 2 yes Figure 3 The CC' section.

[0057] exist Figure 1 In this context, the up-down direction is referred to as the second direction. Figure 1 In this context, the left and right directions are referred to as the third direction. Figure 2 In this context, the up-down direction is referred to as the second direction. Figure 2 In this context, the left and right directions are referred to as the first direction. Figure 3 In this context, the up-down direction is referred to as the first direction. Figure 3 In this context, the left and right directions are referred to as the third direction.

[0058] The second and third directions are perpendicular to the first direction. The third direction is perpendicular to the second direction. The second direction is the direction connecting the lower electrode 12 and the upper electrode 14.

[0059] Figure 1 and Figure 2 It is a cross section parallel to the second direction. Figure 3 It is a cross section perpendicular to the second direction. Figure 3 This is an example of the first section.

[0060] The semiconductor device in the first embodiment is a transistor 100. Transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. Transistor 100 is a so-called vertical transistor. Transistor 100 includes a plurality of transistors.

[0061] Transistor 100 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first wiring layer 21, and an interlayer insulating layer 22. The oxide semiconductor layer 16 includes a first oxide semiconductor layer 16a and a second oxide semiconductor layer 16b. The gate insulating layer 20 includes a first gate insulating layer 20a and a second gate insulating layer 20b. The interlayer insulating layer 22 includes a first portion 22a and a second portion 22b.

[0062] The lower electrode 12 is an example of the first electrode. The upper electrode 14 is an example of the second electrode. The interlayer insulating layer 22 is an example of the first insulating layer.

[0063] A transistor is composed of a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, and a gate insulating layer 20. Multiple transistors may have the same structure. Hereinafter, the configuration of a transistor will sometimes be described using a transistor that includes a first oxide semiconductor layer 16a or a second oxide semiconductor layer 16b as an example.

[0064] The lower electrode 12 is disposed below the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. For example, the lower electrode 12 is connected to the oxide semiconductor layer 16. The lower electrode 12 functions as the source electrode or drain electrode of the transistor 100.

[0065] The lower electrode 12 is a conductor. The lower electrode 12 may contain, for example, an oxide conductor. The lower electrode 12 may be, for example, an oxide conductor layer.

[0066] The lower electrode 12 may contain, for example, indium (In), tin (Sn), and oxygen (O). The lower electrode 12 may contain, for example, indium tin oxide. The lower electrode 12 may be, for example, an indium tin oxide layer.

[0067] The lower electrode 12 may contain, for example, tin (Sn) and oxygen (O). The lower electrode 12 may contain, for example, tin oxide. The lower electrode 12 may be, for example, a tin oxide layer.

[0068] The lower electrode 12 may contain metal, for example. The lower electrode 12 may be a metal layer.

[0069] The lower electrode 12 may contain, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The lower electrode 12 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0070] The lower electrode 12 may also have a stacked structure of multiple conductors. For example, the lower electrode 12 is a stacked structure of an oxide conductor layer and a metal layer. For example, the surface of the lower electrode 12 on the oxide semiconductor layer 16 side is an oxide conductor layer.

[0071] The upper electrode 14 is disposed on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. For example, the upper electrode 14 is connected to the oxide semiconductor layer 16. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0072] The upper electrode 14 is a conductor. The upper electrode 14 may contain, for example, an oxide conductor. The upper electrode 14 may be, for example, an oxide conductor layer.

[0073] The upper electrode 14 may contain, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 may contain, for example, indium tin oxide. The upper electrode 14 may be, for example, an indium tin oxide layer.

[0074] The upper electrode 14 may contain, for example, tin (Sn) and oxygen (O). The upper electrode 14 may contain, for example, tin oxide. The upper electrode 14 may be, for example, a tin oxide layer.

[0075] The upper electrode 14 may contain metal, for example. The upper electrode 14 may be a metal layer.

[0076] The upper electrode 14 may contain, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The upper electrode 14 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0077] The upper electrode 14 may also have a stacked structure of multiple conductors. For example, the upper electrode 14 may be a stacked structure of an oxide conductor layer and a metal layer. For instance, the surface of the upper electrode 14 on the oxide semiconductor layer 16 side may be an oxide conductor layer. The upper electrode 14 may also contain titanium oxide.

[0078] The lower electrode 12 and the upper electrode 14 are formed of the same material, for example. The lower electrode 12 and the upper electrode 14 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide layers.

[0079] A first oxide semiconductor layer 16a is disposed between the lower electrode 12 and the upper electrode 14. The first oxide semiconductor layer 16a is, for example, connected to the lower electrode 12. The first oxide semiconductor layer 16a is, for example, connected to the upper electrode 14.

[0080] The second oxide semiconductor layer 16b is disposed in the first direction of the first oxide semiconductor layer 16a.

[0081] like Figure 3 As shown, the first oxide semiconductor layer 16a is circular in a cross-section perpendicular to the second direction and containing the gate electrode 18.

[0082] A channel is formed on the first oxide semiconductor layer 16a, which becomes a current path when the transistor 100 is turned on.

[0083] The first oxide semiconductor layer 16a is an oxide semiconductor. The first oxide semiconductor layer 16a is, for example, amorphous.

[0084] The first oxide semiconductor layer 16a may contain, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The first oxide semiconductor layer 16a may contain, for example, indium gallium zinc oxide. The first oxide semiconductor layer 16a may be, for example, an indium gallium zinc oxide layer.

[0085] The first oxide semiconductor layer 16a may contain, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The first oxide semiconductor layer 16a may contain, for example, titanium oxide, zinc oxide, or tungsten oxide. The first oxide semiconductor layer 16a may be, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0086] The first oxide semiconductor layer 16a, for example, has a chemical composition different from that of the lower electrode 12 and the upper electrode 14.

[0087] The first oxide semiconductor layer 16a contains oxygen vacancies. The oxygen vacancies in the first oxide semiconductor layer 16a function as donors.

[0088] The length of the first oxide semiconductor layer 16a in the first direction is, for example, 15 nm or more and 200 nm or less. The length of the first oxide semiconductor layer 16a in the second direction is, for example, 10 nm or more and 100 nm or less.

[0089] The gate electrode 18 is opposite to the first oxide semiconductor layer 16a. The gate electrode 18 is opposite to the second oxide semiconductor layer 16b.

[0090] The gate electrode 18 extends in the first direction.

[0091] The gate electrode 18 is configured such that its position coordinates in the second direction are between the position coordinates of the lower electrode 12 and the upper electrode 14 in the second direction.

[0092] Gate electrode 18 is a conductor. Gate electrode 18 may be, for example, a metal, a metal compound, or a semiconductor. Gate electrode 18 may contain, for example, tungsten (W).

[0093] The third-direction length of the gate electrode 18 is, for example, 10 nm or more and 100 nm or less.

[0094] A first gate insulating layer 20a is disposed between the first oxide semiconductor layer 16a and the gate electrode 18. The first gate insulating layer 20a surrounds the first oxide semiconductor layer 16a. The first gate insulating layer 20a is in contact with the first oxide semiconductor layer 16a.

[0095] The second gate insulating layer 20b is disposed between the second oxide semiconductor layer 16b and the gate electrode 18. The second gate insulating layer 20b surrounds the second oxide semiconductor layer 16b. The second gate insulating layer 20b is in contact with the second oxide semiconductor layer 16b.

[0096] In a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the first gate insulating layer 20a is in contact with the gate electrode 18. In a cross-section perpendicular to the second direction and including the gate electrode 18, another portion of the first gate insulating layer 20a is in contact with a first portion 22a of the interlayer insulating layer 22. The first gate insulating layer 20a is, for example, in contact with the lower electrode 12. The first gate insulating layer 20a is, for example, in contact with the upper electrode 14.

[0097] In a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the second gate insulating layer 20b is in contact with the gate electrode 18. In a cross-section perpendicular to the second direction and including the gate electrode 18, another portion of the second gate insulating layer 20b is in contact with the first portion 22a of the interlayer insulating layer 22.

[0098] The first gate insulating layer 20a comprises at least one element combination selected from the group consisting of combinations of silicon (Si) and nitrogen (N), combinations of titanium (Ti) and oxygen (O), and combinations of aluminum (Al) and oxygen (O). The first gate insulating layer 20a may, for example, comprise at least one compound selected from the group consisting of silicon nitride, titanium oxide, and aluminum oxide. The first gate insulating layer 20a may, for example, comprise a silicon nitride film, a titanium oxide film, or an aluminum oxide film.

[0099] The second gate insulating layer 20b comprises at least one element combination selected from the group consisting of combinations of silicon (Si) and nitrogen (N), combinations of titanium (Ti) and oxygen (O), and combinations of aluminum (Al) and oxygen (O).

[0100] The first gate insulating layer 20a may also have a stacked structure, for example. The thickness of the first gate insulating layer 20a is, for example, 2 nm or more and 10 nm or less.

[0101] The first wiring layer 21 extends upward in a third direction. The first wiring layer 21 is repeated, for example, in a first direction. The first wiring layer 21 is electrically connected to the upper electrode 14. The first wiring layer 21 is disposed, for example, on the upper electrode 14.

[0102] The first wiring layer 21 is, for example, metal.

[0103] Interlayer insulating layer 22, for example, surrounds the lower electrode 12, the upper electrode 14, the oxide semiconductor layer 16, the gate insulating layer 20, and the first wiring layer 21. Interlayer insulating layer 22, for example, is disposed between the lower electrode 12 and the gate electrode 18. Interlayer insulating layer 22, for example, is disposed between the upper electrode 14 and the gate electrode 18.

[0104] The interlayer insulation layer 22 includes a first portion 22a and a second portion 22b. For example... Figure 3 As shown, in a cross section perpendicular to the second direction, a gate electrode 18 is disposed between the first portion 22a and the second portion 22b.

[0105] A first gate insulating layer 20a is disposed between the first portion 22a and the first oxide semiconductor layer 16a. The first portion 22a is connected to the first gate insulating layer 20a. The second portion 22b is connected to the gate electrode 18.

[0106] A second gate insulating layer 20b is disposed between the first portion 22a and the second oxide semiconductor layer 16b. The first portion 22a is in contact with the second gate insulating layer 20b.

[0107] Interlayer insulating layer 22 is an insulator. Interlayer insulating layer 22 may be, for example, an oxide, nitride, or oxynitride. Interlayer insulating layer 22 may contain, for example, silicon (Si) and oxygen (O). Interlayer insulating layer 22 may contain, for example, silicon oxide. Interlayer insulating layer 22 may be, for example, a silicon oxide layer.

[0108] Interlayer insulation layer 22 is, for example, an air gap containing gas.

[0109] Figure 4 and Figure 5 This is an enlarged schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 yes Figure 1 An enlarged section of a portion. Figure 5 yes Figure 3 An enlarged section of a portion. Figure 5 yes Figure 4 The DD' section.

[0110] like Figure 4 and Figure 5As shown, the first gate insulating layer 20a includes a first film 20x and a second film 20y. The first gate insulating layer 20a has a stacked structure of the first film 20x and the second film 20y. The second film 20y is disposed between the first film 20x and the first oxide semiconductor layer 16a.

[0111] The first film 20x may, for example, comprise at least one element combination selected from the group consisting of combinations of silicon (Si) and nitrogen (N), combinations of titanium (Ti) and oxygen (O), and combinations of aluminum (Al) and oxygen (O). The first film 20x may, for example, comprise at least one compound selected from the group consisting of silicon nitride, titanium oxide, and aluminum oxide. The first film 20x may, for example, be a silicon nitride film, a titanium oxide film, or an aluminum oxide film.

[0112] The chemical composition of the second membrane 20y differs from that of the first membrane 20x. The second membrane 20y may contain, for example, silicon (Si) and oxygen (O). The second membrane 20y may contain, for example, silicon oxide. The second membrane 20y may be, for example, a silicon oxide membrane.

[0113] like Figure 5 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the first oxide semiconductor layer 16a has a circular shape. A portion of the first oxide semiconductor layer 16a protrudes in a third direction relative to the gate electrode 18. Additionally, a portion of the first gate insulating layer 20a protrudes in a third direction relative to the gate electrode 18.

[0114] like Figure 5 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the maximum distance in a third direction perpendicular to the first direction between the end of the first portion 22a side of the first oxide semiconductor layer 16a and the end of the second portion 22b side of the gate electrode 18 is ( Figure 5 d1) is greater than the maximum width of the third direction of the gate electrode 18. Figure 5 w in the middle.

[0115] like Figure 5 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the minimum distance in a third direction perpendicular to the first direction between the first gate insulating layer 20a and the end of the second portion 22b side of the gate electrode 18 is ( Figure 5 d2 in the figure is, for example, the maximum width of the third direction of the gate electrode 18. Figure 5 More than one-third of the w in the middle.

[0116] like Figure 5 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the first gate insulating layer 20a is in contact with the gate electrode 18. Another portion of the first gate insulating layer 20a is in contact with a first portion 22a of the interlayer insulating layer 22.

[0117] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0118] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 6-19 Respectively represent and Figure 1 The corresponding cross section. Figures 6-19 This is a diagram illustrating an example of a manufacturing method for transistor 100.

[0119] The following description will be based on the following case: the lower electrode 12 of the transistor 100 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a stacked structure of silicon nitride film and silicon oxide film, the first wiring layer 21 is a tungsten layer, and the interlayer insulating layer 22 is a silicon oxide layer.

[0120] First, a first indium tin oxide layer 31 is formed in the first silicon oxide layer 30. Figure 6 The first silicon oxide layer 30 ultimately becomes the interlayer insulating layer 22. The first indium tin oxide layer 31 ultimately becomes the lower electrode 12.

[0121] Next, a first silicon oxide film 32, a tungsten film 33, and a second silicon oxide film 34 are formed on the first silicon oxide layer 30. Figure 7 The first silicon oxide film 32, the tungsten film 33, and the second silicon oxide film 34 are formed, for example, by chemical vapor deposition (CVD).

[0122] A portion of the first silicon oxide film 32 and a portion of the second silicon oxide film 34 ultimately become the interlayer insulating layer 22. A portion of the tungsten film 33 ultimately becomes the gate electrode 18.

[0123] Next, a first mask material 35 is formed on the second silicon oxide film 34. Figure 8 The first mask material 35 is, for example, a photoresist.

[0124] Next, using the first mask material 35 as a mask, the second silicon oxide film 34, the tungsten film 33, and the first silicon oxide film 32 are etched to form the first opening 36 reaching the first indium tin oxide layer 31. Figure 9 Etching can be performed, for example, using reactive ion etching (RIE).

[0125] Next, the first mask material 35 is peeled off, and the first opening 36 is filled with an amorphous silicon film 37. Figure 10 The amorphous silicon film 37 is formed, for example, by CVD-based deposition and planarization using chemical mechanical polishing (CMP).

[0126] Next, a second mask material 38 is formed on the second silicon oxide film 34. Figure 11 The second mask material 38 is, for example, a photoresist. The second mask material 38 is formed such that a portion of the amorphous silicon film 37 is exposed, while another portion is covered.

[0127] Next, using the second mask material 38 as a mask, the second silicon oxide film 34, the tungsten film 33, and the first silicon oxide film 32 are etched to form the second opening 39. Figure 12 Etching can be performed, for example, using the RIE method.

[0128] During etching, etching conditions are selected that ensure an etch selectivity ratio between silicon oxide and amorphous silicon. By ensuring an etch selectivity ratio between silicon oxide and amorphous silicon, the etching of the amorphous silicon film 37 can be suppressed.

[0129] Next, the second mask material 38 is removed, and the second opening 39 is filled with a third silicon oxide film 40. Figure 13 The third silicon oxide film 40 is formed, for example, by CVD-based deposition and planarization using CMP. The third silicon oxide film 40 ultimately becomes the interlayer insulating layer 22.

[0130] Next, the amorphous silicon film 37 that filled the first opening 36 was removed. Figure 14 The amorphous silicon film 37 is removed, for example, by wet etching.

[0131] Next, a laminated film 41 of silicon oxide film and silicon nitride film is formed at the first opening 36. Figure 15 The laminated film 41 is formed, for example, by CVD. A portion of the laminated film 41 eventually becomes the gate insulating layer 20.

[0132] Next, the laminated film 41 at the bottom of the first opening 36 is removed, exposing the first indium tin oxide layer 31. Figure 16 The laminated film 41 at the bottom of the first opening 36 is removed, for example, using the RIE method.

[0133] Next, the first opening 36 is filled with an indium gallium zinc oxide film 42. Figure 17 The indium gallium zinc oxide film 42, for example, is planarized using CMP after being formed by CVD.

[0134] Next, a second indium tin oxide layer 43 and a second silicon oxide layer 44 are formed using known manufacturing methods. Figure 18 The second indium tin oxide layer 43 ultimately becomes the upper electrode 14. The second silicon oxide layer 44 ultimately becomes the interlayer insulating layer 22.

[0135] Next, a tungsten layer 45 and a third silicon oxide layer 46 are formed using known manufacturing methods. Figure 19 The tungsten layer 45 ultimately becomes the first wiring layer 21. The third silicon oxide layer 46 ultimately becomes the interlayer insulating layer 22.

[0136] Using the above manufacturing methods, the following products are manufactured: Figures 1 to 5 The transistor 100 shown.

[0137] Next, the function and effects of the semiconductor device in the first embodiment will be explained.

[0138] Figure 20 and Figure 21 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 21 yes Figure 20 AA' section. Figure 20 yes Figure 21 BB' section. Figure 20 It is the same as the first embodiment. Figure 1 The corresponding diagram. Figure 21 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0139] The comparative example semiconductor device is transistor 900. Transistor 900 differs from transistor 100 of the first embodiment in that, in a cross-section perpendicular to the second direction and including the gate electrode 18, the gate insulating layer 20 is not connected to the interlayer insulating layer 22. Transistor 900 also differs from transistor 100 of the first embodiment in that, in a cross-section perpendicular to the second direction and including the gate electrode 18, the gate insulating layer 20 is surrounded by the gate electrode 18.

[0140] In the comparative example transistor 900, an oxide semiconductor layer 16 is disposed through the gate electrode 18. Because the oxide semiconductor layer 16 extends through the gate electrode 18, the effective third-direction width of the gate electrode 18 at the portion where the oxide semiconductor layer 16 is present becomes smaller. Therefore, the resistance of the gate electrode 18 at the portion where the oxide semiconductor layer 16 is present becomes higher.

[0141] When the resistance of the gate electrode 18 at the portion where the oxide semiconductor layer 16 exists becomes high, the wiring resistance of the gate electrode 18 in the first direction also becomes high. When the wiring resistance of the gate electrode 18 in the first direction becomes high, for example, the operation of the transistor 900 is delayed. Therefore, for example, it is difficult to make the transistor 900 operate at high speed.

[0142] For example, the effective width of the gate electrode 18 in the third direction at the portion where the oxide semiconductor layer 16 exists can be increased by reducing the width of the third direction of the oxide semiconductor layer 16. However, regarding reducing the width of the third direction of the oxide semiconductor layer 16, for example, in the case of miniaturization to improve the integration density of the transistor 900, it may be difficult to form a pattern of the oxide semiconductor layer 16 with a small width. In addition, by reducing the width of the third direction of the oxide semiconductor layer 16, the cross-sectional area of ​​the channel of the transistor 900 becomes smaller, and the on-resistance of the transistor 900 may increase.

[0143] The transistor 100 of the first embodiment is formed such that a portion of the oxide semiconductor layer 16 protrudes in a third direction relative to the gate electrode 18. Furthermore, a portion of the gate insulating layer 20 protrudes in a third direction relative to the gate electrode 18.

[0144] Therefore, compared with the transistor 900 of the comparative example, the transistor 100 of the first embodiment can increase the effective third-direction width of the gate electrode 18 in the portion where the oxide semiconductor layer 16 exists. Therefore, the effective third-direction width of the gate electrode 18 in the portion where the oxide semiconductor layer 16 exists can be increased. Therefore, for example, high-speed operation of the transistor 100 can be achieved.

[0145] Furthermore, in the transistor 100 of the first embodiment, a gate insulating layer 20 is disposed between a first portion 22a of the interlayer insulating layer 22 and the oxide semiconductor layer 16. Moreover, the gate insulating layer 20 comprises at least one element combination selected from the group consisting of a combination of silicon (Si) and nitrogen (N), a combination of titanium (Ti) and oxygen (O), and a combination of aluminum (Al) and oxygen (O). By comprising the above-mentioned element combinations, the gate insulating layer 20 can improve its barrier properties against hydrogen. For example, compared to a gate insulating layer formed of silicon oxide, the gate insulating layer 20, by comprising the above-mentioned element combinations, can improve its barrier properties against hydrogen.

[0146] Consider the case where there is no gate insulating layer 20 between the first portion 22a of the interlayer insulating layer 22 and the oxide semiconductor layer 16, or where the gate insulating layer 20 does not contain the aforementioned combination of elements. In this case, it is difficult to prevent hydrogen from penetrating from the interlayer insulating layer 22 into the oxide semiconductor layer 16.

[0147] Hydrogen acts as a donor in the oxide semiconductor layer 16. Therefore, the intrusion of hydrogen into the oxide semiconductor layer 16 may reduce the threshold voltage of the transistor or degrade the transistor's cutoff characteristics.

[0148] The transistor 100 of the first embodiment provides a gate insulating layer 20 between the first portion 22a of the interlayer insulating layer 22 and the oxide semiconductor layer 16, and the gate insulating layer 20 contains the aforementioned element combination, thereby suppressing hydrogen intrusion from the interlayer insulating layer 22 into the oxide semiconductor layer 16. Therefore, it is possible to suppress the decrease in threshold voltage and the deterioration of cutoff characteristics of the transistor 100.

[0149] From the viewpoint of reducing the resistance of the gate electrode 18 at the portion where the oxide semiconductor layer 16 is present, the minimum third-dimensional distance between the first gate insulating layer 20a and the end of the second portion 22b side of the gate electrode 18 ( Figure 5 d2) is preferably the maximum width in the third direction of the gate electrode 18. Figure 5 More than one-third of w), preferably more than one-half.

[0150] According to the semiconductor device of the first embodiment, the resistance of the gate electrode is reduced, and the intrusion of hydrogen into the oxide semiconductor layer is suppressed. Therefore, for example, high-speed operation can be achieved, and threshold voltage reduction and deterioration of cutoff characteristics can be suppressed. Thus, a semiconductor device with excellent transistor characteristics can be realized.

[0151] (Second Implementation) The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that, in the first cross-section, the maximum distance in a third direction perpendicular to the first direction between the end of the first portion side of the first oxide semiconductor layer and the end of the second portion side of the gate electrode is less than the maximum width of the gate electrode in a third direction. Hereinafter, some details that are repeated in the first embodiment will be omitted.

[0152] Figure 22 , Figure 23 and Figure 24 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 24 yes Figure 22 AA' section. Figure 22 yes Figure 24 BB' section. Figure 23 yes Figure 24 The CC' section.

[0153] Figure 22 , Figure 23 and Figure 24 These are respectively the first embodiment. Figure 1 , Figure 2 and Figure 3 The corresponding diagram.

[0154] The semiconductor device in the second embodiment is a transistor 200.

[0155] Transistor 200 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first wiring layer 21, and an interlayer insulating layer 22. The oxide semiconductor layer 16 includes a first oxide semiconductor layer 16a and a second oxide semiconductor layer 16b. The gate insulating layer 20 includes a first gate insulating layer 20a and a second gate insulating layer 20b. The interlayer insulating layer 22 includes a first portion 22a and a second portion 22b.

[0156] like Figure 24 As shown, the oxide semiconductor layer 16 is semi-circular in a cross-section perpendicular to the second direction and including the gate electrode 18. The first oxide semiconductor layer 16a and the second oxide semiconductor layer 16b are semi-circular in a cross-section perpendicular to the second direction and including the gate electrode 18.

[0157] Figure 25 and Figure 26 This is an enlarged schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 25 yes Figure 22 An enlarged section of a portion. Figure 26 yes Figure 24 An enlarged section of a portion. Figure 26 yes Figure 25 The DD' section.

[0158] Figure 25 and Figure 26 These are respectively the first embodiment. Figure 4 and Figure 5 The corresponding diagram.

[0159] like Figure 25 As shown, the third-dimensional width of the portion between the first portion 22a and the second portion 22b of the first oxide semiconductor layer 16a ( Figure 25 The width of w1 in the third direction is smaller than the portion of the first oxide semiconductor layer 16a that is in contact with the lower electrode 12. Figure 25 (w2 in the text). The third-direction width w1 of the portion between the first portion 22a and the second portion 22b of the first oxide semiconductor layer 16a is, for example, less than two-thirds of the third-direction width w2 of the portion of the first oxide semiconductor layer 16a that is in contact with the lower electrode 12.

[0160] like Figure 25 As shown, the third-direction center position of the portion between the first portion 22a and the second portion 22b of the first oxide semiconductor layer 16a (as shown). Figure 25 P1 in the middle, is the third-direction center position relative to the portion of the first oxide semiconductor layer 16a that is in contact with the lower electrode 12. Figure 25 P2 in the middle is offset to a third direction.

[0161] like Figure 26 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the first oxide semiconductor layer 16a has a semi-circular shape. The first oxide semiconductor layer 16a does not protrude in a third direction relative to the gate electrode 18. Additionally, a portion of the first gate insulating layer 20a also does not protrude in a third direction relative to the gate electrode 18.

[0162] like Figure 26 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the maximum distance in a third direction between the end of the first portion 22a side of the first oxide semiconductor layer 16a and the end of the second portion 22b side of the gate electrode 18 is ( Figure 26 d1 in the figure is smaller than the maximum width of the third direction of the gate electrode 18. Figure 26 w in the middle.

[0163] like Figure 26 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the minimum distance in a third direction between the first gate insulating layer 20a and the end of the second portion 22b side of the gate electrode 18 is ( Figure 26 d2 in the figure, for example, is the maximum width of the third direction of the gate electrode 18. Figure 26 More than one-third of the w in the middle.

[0164] like Figure 26 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the first gate insulating layer 20a is in contact with the gate electrode 18. Another portion of the first gate insulating layer 20a is in contact with a first portion 22a of the interlayer insulating layer 22.

[0165] Next, an example of the manufacturing method of the semiconductor device according to the second embodiment will be described.

[0166] Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 , Figure 32 , Figure 33 , Figure 34 and Figure 35 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second embodiment. Figures 27-35 Respectively represent and Figure 22 The corresponding cross section. Figures 27-35This is a diagram illustrating an example of a manufacturing method for transistor 200.

[0167] The following explanation will be based on the following case: the lower electrode 12 of the transistor 200 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a stacked structure of silicon nitride film and silicon oxide film, the first wiring layer 21 is a tungsten layer, and the interlayer insulating layer 22 is a silicon oxide layer.

[0168] The manufacturing process is the same as that in the first embodiment, up to the formation of the second mask material 38 on the second silicon oxide film 34. Figure 27 The second mask material 38 is, for example, a photoresist. The second mask material 38 is formed such that a portion of the amorphous silicon film 37 is exposed and another portion is covered.

[0169] Next, using the second mask material 38 as a mask, the second silicon oxide film 34, the tungsten film 33, the first silicon oxide film 32, and the amorphous silicon film 37 are etched to form the second opening 39. Figure 28 Etching can be performed, for example, using the RIE method.

[0170] During etching, an etching condition with a smaller etching selectivity is selected between silicon oxide and amorphous silicon. Because the etching selectivity between silicon oxide and amorphous silicon is relatively small, the amorphous silicon film 37 is etched.

[0171] Next, the second mask material 38 is peeled off, and the second opening 39 is filled with a third silicon oxide film 40. Figure 29 The third silicon oxide film 40 is formed, for example, by CVD-based deposition and planarization using CMP. The third silicon oxide film 40 ultimately becomes the interlayer insulating layer 22.

[0172] Next, the amorphous silicon film 37 filling the first opening 36 is removed. Figure 30 The amorphous silicon film 37 is removed, for example, by wet etching.

[0173] Next, a laminated film 41 of silicon oxide film and silicon nitride film is formed at the first opening 36. Figure 31 A portion of the laminated film 41 eventually becomes the gate insulating layer 20.

[0174] Next, the laminated film 41 at the bottom of the first opening 36 is removed, exposing the first indium tin oxide layer 31. Figure 32 ).

[0175] Next, the first opening 36 is filled with an indium gallium zinc oxide film 42. Figure 33 The indium gallium zinc oxide film 42, for example, is planarized using CMP after being formed by CVD.

[0176] Next, a second indium tin oxide layer 43 and a second silicon oxide layer 44 are formed using known manufacturing methods. Figure 34 The second indium tin oxide layer 43 ultimately becomes the upper electrode 14. The second silicon oxide layer 44 ultimately becomes the interlayer insulating layer 22.

[0177] Next, a tungsten layer 45 and a third silicon oxide layer 46 are formed using known manufacturing methods. Figure 35 The tungsten layer 45 ultimately becomes the first wiring layer 21. The third silicon oxide layer 46 ultimately becomes the interlayer insulating layer 22.

[0178] Using the above manufacturing methods, the following products are manufactured: Figures 22 to 26 The transistor 200 shown.

[0179] Like the transistor 100 in the first embodiment, the transistor 200 in the second embodiment can increase the effective width of the gate electrode 18 in the third direction at the portion where the oxide semiconductor layer 16 is present. Therefore, for example, high-speed operation of the transistor 200 can be achieved.

[0180] Furthermore, similarly to the transistor 100 of the first embodiment, the transistor 200 of the second embodiment also includes a gate insulating layer 20 disposed between the first portion 22a of the interlayer insulating layer 22 and the oxide semiconductor layer 16, and the gate insulating layer 20 contains the aforementioned element combination. This suppresses hydrogen intrusion from the interlayer insulating layer 22 into the oxide semiconductor layer 16. Therefore, it is possible to suppress the decrease in threshold voltage and the deterioration of cutoff characteristics of the transistor 200.

[0181] In addition, such as Figure 26 As shown, in the transistor 200 of the second embodiment, the first oxide semiconductor layer 16a does not protrude in a third direction relative to the gate electrode 18. Therefore, compared with the transistor 100 of the first embodiment, the gate electrode 18 has improved control over the electric field in the first oxide semiconductor layer 16a. Therefore, for example, it is possible to further suppress threshold voltage reduction and deterioration of cutoff characteristics.

[0182] From the viewpoint of reducing the resistance of the gate electrode 18 at the portion where the oxide semiconductor layer 16 is present, the minimum third-dimensional distance between the first gate insulating layer 20a and the end of the second portion 22b side of the gate electrode 18 ( Figure 26 d2) is preferably the maximum width in the third direction of the gate electrode 18. Figure 26 More than one-third of w), preferably more than one-half.

[0183] According to the semiconductor device of the second embodiment, the resistance of the gate electrode is reduced, and the intrusion of hydrogen into the oxide semiconductor layer is suppressed. Therefore, for example, high-speed operation can be achieved, and threshold voltage reduction and deterioration of cutoff characteristics can be suppressed. Thus, a semiconductor device with excellent transistor characteristics can be realized.

[0184] (Third Implementation) The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that it further comprises: a third oxide semiconductor layer, positioned in a first direction between the first oxide semiconductor layer and the second oxide semiconductor layer; and a third gate insulating layer, disposed between the gate electrode and the third oxide semiconductor layer, surrounding the third oxide semiconductor layer, comprising at least one element combination, and connected to the second portion in a first cross-section. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0185] Figure 36 , Figure 37 , Figure 38 and Figure 39 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 39 yes Figure 36 and Figure 37 AA' section. Figure 36 yes Figure 39 BB' section. Figure 37 yes Figure 39 The CC' section. Figure 38 yes Figure 39 The DD' section.

[0186] Figure 36 , Figure 38 and Figure 39 These are respectively the first embodiment. Figure 1 , Figure 2 and Figure 3 The corresponding diagram.

[0187] The semiconductor device in the third embodiment is a transistor 300.

[0188] Transistor 300 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first wiring layer 21, and an interlayer insulating layer 22. The oxide semiconductor layer 16 includes a first oxide semiconductor layer 16a, a second oxide semiconductor layer 16b, and a third oxide semiconductor layer 16c. The gate insulating layer 20 includes a first gate insulating layer 20a, a second gate insulating layer 20b, and a third gate insulating layer 20c. The interlayer insulating layer 22 includes a first portion 22a and a second portion 22b.

[0189] like Figure 39As shown, the second oxide semiconductor layer 16b is disposed in a first direction of the first oxide semiconductor layer 16a. Figure 39 As shown, the position of the third oxide semiconductor layer 16c in the first direction is between the position of the first oxide semiconductor layer 16a in the first direction and the position of the second oxide semiconductor layer 16b in the first direction.

[0190] A first oxide semiconductor layer 16a and a second oxide semiconductor layer 16b are disposed on the first portion 22a side of the gate electrode 18. A third oxide semiconductor layer 16c is disposed on the second portion 22b side of the gate electrode 18.

[0191] A first gate insulating layer 20a is disposed between the first oxide semiconductor layer 16a and the gate electrode 18. The first gate insulating layer 20a surrounds the first oxide semiconductor layer 16a. A second gate insulating layer 20b is disposed between the second oxide semiconductor layer 16b and the gate electrode 18. The second gate insulating layer 20b surrounds the second oxide semiconductor layer 16b. A third gate insulating layer 20c is disposed between the third oxide semiconductor layer 16c and the gate electrode 18. The third gate insulating layer 20c surrounds the third oxide semiconductor layer 16c.

[0192] In a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the first gate insulating layer 20a is in contact with the gate electrode 18. In a cross-section perpendicular to the second direction and including the gate electrode 18, another portion of the first gate insulating layer 20a is in contact with a first portion 22a of the interlayer insulating layer 22.

[0193] In a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the second gate insulating layer 20b is in contact with the gate electrode 18. In a cross-section perpendicular to the second direction and including the gate electrode 18, another portion of the second gate insulating layer 20b is in contact with the first portion 22a of the interlayer insulating layer 22.

[0194] In a cross-section perpendicular to the second direction and including the gate electrode 18, a portion of the third gate insulating layer 20c is in contact with the gate electrode 18. In a cross-section perpendicular to the second direction and including the gate electrode 18, another portion of the third gate insulating layer 20c is in contact with the second portion 22b of the interlayer insulating layer 22.

[0195] like Figure 39As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the first oxide semiconductor layer 16a has a circular shape. A portion of the first oxide semiconductor layer 16a protrudes in a third direction relative to the gate electrode 18. A portion of the first oxide semiconductor layer 16a also protrudes towards the first portion 22a relative to the gate electrode 18. Additionally, a portion of the first gate insulating layer 20a protrudes towards the first portion 22a relative to the gate electrode 18.

[0196] like Figure 39 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the third oxide semiconductor layer 16c has a circular shape. A portion of the third oxide semiconductor layer 16c protrudes in a third direction relative to the gate electrode 18. A portion of the third oxide semiconductor layer 16c also protrudes towards the second portion 22b side relative to the gate electrode 18. Additionally, a portion of the third gate insulating layer 20c protrudes towards the second portion 22b side relative to the gate electrode 18.

[0197] The transistor 300 of the third embodiment has an oxide semiconductor layer 16 disposed on both sides of the gate electrode 18. By disposing the oxide semiconductor layer 16 on both sides of the gate electrode 18, the repeating spacing in the third direction of the gate electrode 18 can be, for example, twice that of the transistor 100 of the first embodiment. Therefore, the width in the third direction of the gate electrode 18 is increased, and the wiring resistance in the first direction of the gate electrode 18 can be further reduced. Therefore, for example, high-speed operation of the transistor 300 can be achieved.

[0198] According to the semiconductor device of the third embodiment, the resistance of the gate electrode is reduced, and hydrogen intrusion into the oxide semiconductor layer is suppressed. Therefore, for example, high-speed operation can be achieved, and threshold voltage reduction and deterioration of cutoff characteristics can be suppressed. Thus, a semiconductor device with excellent transistor characteristics can be realized.

[0199] (Fourth Implementation) The semiconductor device of the fourth embodiment differs from that of the semiconductor device of the third embodiment in that the oxide semiconductor layer in the first cross-section is semi-circular. Hereinafter, some details that are repeated in the first embodiment will be omitted.

[0200] Figure 40 , Figure 41 , Figure 42 and Figure 43 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 43 yes Figure 40 and Figure 41 AA' section. Figure 40 yes Figure 43 BB' section. Figure 41 yes Figure 43The CC' section. Figure 42 yes Figure 43 The DD' section.

[0201] Figure 40 , Figure 41 , Figure 42 and Figure 43 These are respectively compared with the third embodiment. Figure 36 , Figure 37 , Figure 38 and Figure 39 The corresponding diagram.

[0202] The semiconductor device in the fourth embodiment is a transistor 400.

[0203] Transistor 400 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first wiring layer 21, and an interlayer insulating layer 22. The oxide semiconductor layer 16 includes a first oxide semiconductor layer 16a, a second oxide semiconductor layer 16b, and a third oxide semiconductor layer 16c. The gate insulating layer 20 includes a first gate insulating layer 20a, a second gate insulating layer 20b, and a third gate insulating layer 20c. The interlayer insulating layer 22 includes a first portion 22a and a second portion 22b.

[0204] like Figure 43 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the first oxide semiconductor layer 16a has a semi-circular shape. The first oxide semiconductor layer 16a does not protrude in a third direction relative to the gate electrode 18. Additionally, a portion of the first gate insulating layer 20a also does not protrude in a third direction relative to the gate electrode 18.

[0205] like Figure 43 As shown, in a cross-section perpendicular to the second direction and including the gate electrode 18, the third oxide semiconductor layer 16c has a semi-circular shape. The third oxide semiconductor layer 16c does not protrude in a third direction relative to the gate electrode 18. Additionally, a portion of the third gate insulating layer 20c also does not protrude in a third direction relative to the gate electrode 18.

[0206] According to the semiconductor device of the fourth embodiment, the resistance of the gate electrode is reduced, and hydrogen intrusion into the oxide semiconductor layer is suppressed. Therefore, for example, high-speed operation can be achieved, and threshold voltage reduction and deterioration of cutoff characteristics can be suppressed. Thus, a semiconductor device with excellent transistor characteristics can be realized.

[0207] (Fifth Implementation) The semiconductor memory device of the fifth embodiment includes the semiconductor device of the first embodiment and a capacitor electrically connected to either the first electrode or the second electrode.

[0208] The semiconductor memory device of the fifth embodiment is a semiconductor memory 500. The semiconductor memory device of the fifth embodiment is a DRAM. The semiconductor memory 500 uses the transistor 100 of the first embodiment as a switching transistor for a memory cell of the DRAM.

[0209] Hereinafter, some content that is repeated in the first embodiment will be omitted.

[0210] Figure 44 This is an equivalent circuit diagram of the semiconductor memory device according to the fifth embodiment. Figure 44 The example illustrates a case with 6 memory cells (MC), but there can also be 7 or more memory cells (MC).

[0211] The semiconductor memory 500 includes memory cells MC, word lines WL, bit lines BL, and board lines PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 44 In the diagram, the area enclosed by the dashed line is the memory cell MC.

[0212] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source or drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source or drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to plate line PL.

[0213] The storage cell MC stores data by accumulating charge in the capacitor CA. Data is written to and read from the storage cell MC by turning on the switching transistor TR.

[0214] For example, when the desired voltage is applied to the bit line BL, the switching transistor TR is turned on to write data to the memory cell MC.

[0215] Alternatively, for example, the switching transistor TR is turned on to detect the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor, and the data of the memory cell MC is read out.

[0216] Figure 45 This is a schematic cross-sectional view of the semiconductor memory device according to the fifth embodiment. Figure 45 This represents a cross-section of the memory cell MC of the semiconductor memory 500. Figure 45 Indicates and Figure 44 The cross-section of two switching transistors TR connected by the same bit line BL, which is surrounded by a dashed line.

[0217] The semiconductor memory 500 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, and an interlayer insulating layer 22.

[0218] The switching transistor TR has a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, and a gate insulating layer 20.

[0219] The switching transistor TR has the same construction as the transistor 100 in the first embodiment.

[0220] Capacitor CA is disposed between silicon substrate 10 and switching transistor TR. Capacitor CA is disposed between silicon substrate 10 and lower electrode 12. Capacitor CA is electrically connected to lower electrode 12.

[0221] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. For example, the unit electrode 71 is connected to the lower electrode 12.

[0222] Unit electrode 71 and plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a stacked structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0223] Gate electrode 18 is the word line WL. Upper electrode 14 is electrically connected to the first wiring layer 21. First wiring layer 21 is the bit line BL. Board electrode 72 is connected to board line PL.

[0224] The semiconductor memory 500 utilizes an oxide semiconductor transistor with extremely low channel leakage current during cutoff operation in the switching transistor TR. Therefore, it achieves DRAM with excellent charge retention characteristics.

[0225] In the fifth embodiment, the case where the capacitor CA is electrically connected to the lower electrode 12 is described as an example, but the capacitor CA can also be electrically connected to the upper electrode 14.

[0226] In the fifth embodiment, a semiconductor memory using the transistor of the first embodiment was described as an example, but the semiconductor memory of the embodiments of the present invention may also be a semiconductor memory using the transistor of the second to fourth embodiments.

[0227] The switching transistor TR in the semiconductor memory 500 has a reduced gate electrode resistance and suppresses hydrogen intrusion into the oxide semiconductor layer. Therefore, for example, high-speed operation of the switching transistor TR can be achieved, and threshold voltage reduction and deterioration of cutoff characteristics can be suppressed. Therefore, the semiconductor memory device according to the fifth embodiment can realize a semiconductor memory device with excellent transistor characteristics.

[0228] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, an element of one embodiment may be substituted or modified with elements of another embodiment. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: First electrode; Second electrode; A first oxide semiconductor layer is disposed between the first electrode and the second electrode; A gate electrode is opposite to the first oxide semiconductor layer and extends in a first direction; A first gate insulating layer is disposed between the gate electrode and the first oxide semiconductor layer, surrounding the first oxide semiconductor layer, and comprising at least one element combination selected from the group consisting of combinations of silicon (Si) and nitrogen (N), titanium (Ti) and oxygen (O), and aluminum (Al) and oxygen (O); and The first insulating layer, in a first cross section perpendicular to the second direction connecting the first electrode and the second electrode and including the gate electrode, includes a first portion and a second portion, and the gate electrode is disposed between the first portion and the second portion. The first portion is connected to the first gate insulating layer, and the second portion is connected to the gate electrode.

2. The semiconductor device according to claim 1, wherein, In the first cross-section, the maximum distance in a third direction perpendicular to the first direction between the end of the first portion side of the first oxide semiconductor layer and the end of the second portion side of the gate electrode is greater than the maximum width of the third direction of the gate electrode.

3. The semiconductor device according to claim 1, wherein, In the first cross-section, the maximum distance in a third direction perpendicular to the first direction between the end of the first portion side of the first oxide semiconductor layer and the end of the second portion side of the gate electrode is less than the maximum width of the third direction of the gate electrode.

4. The semiconductor device according to claim 3, wherein, The third-direction width of the portion between the first portion and the second portion of the first oxide semiconductor layer is smaller than the third-direction width of the portion of the first oxide semiconductor layer that is in contact with the first electrode.

5. The semiconductor device according to claim 4, wherein, The third-direction center position of the portion between the first portion and the second portion of the first oxide semiconductor layer is offset in the third direction relative to the third-direction center position of the portion of the first oxide semiconductor layer in contact with the first electrode.

6. The semiconductor device according to claim 1, wherein, In the first cross-section, the minimum distance in a third direction perpendicular to the first direction between the first gate insulating layer and the end of the second portion side of the gate electrode is more than one-third of the maximum width of the third direction of the gate electrode.

7. The semiconductor device according to claim 1, wherein, The first gate insulating layer has a stacked structure of a first film and a second film with a chemical composition different from that of the first film, wherein the first film contains the at least one element combination.

8. The semiconductor device according to claim 7, wherein, A second film is disposed between the first film and the first oxide semiconductor layer.

9. The semiconductor device according to claim 8, wherein, The second film contains silicon (Si) and oxygen (O).

10. The semiconductor device according to claim 1, further comprising: A second oxide semiconductor layer is disposed in the first direction of the first oxide semiconductor layer; and A second gate insulating layer is disposed between the gate electrode and the second oxide semiconductor layer, surrounds the second oxide semiconductor layer, contains the at least one element combination, and is connected to the first portion in the first cross-section.

11. The semiconductor device according to claim 10, further comprising: A third oxide semiconductor layer, wherein the position in the first direction is located between the first oxide semiconductor layer and the second oxide semiconductor layer; and A third gate insulating layer is disposed between the gate electrode and the third oxide semiconductor layer, surrounds the third oxide semiconductor layer, contains the at least one element combination, and is connected to the second portion in the first cross-section.

12. A semiconductor memory device comprising: The semiconductor device of claim 1; and A capacitor is electrically connected to either the first electrode or the second electrode.

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