Semiconductor structure and method of manufacturing the same, electronic device

Abstract

This application provides a semiconductor structure, its fabrication method, and an electronic device. The fabrication method includes: forming a read transistor above a substrate, comprising a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode stacked from bottom to top; using a deposition process, growing a first dielectric material based on a weakly oxidizing precursor to form a passivation layer; forming an insulating layer above the passivation layer, the passivation layer and the insulating layer constituting an interlayer isolation medium; forming a write transistor above the interlayer isolation medium, comprising a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top; the method further includes: forming a vertical interconnect via, one end of which is connected to the first gate electrode, and the other end extending in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and connected to a second source electrode or a second drain electrode in the second source / drain electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] With the growing demand for artificial intelligence and high-performance computing, traditional silicon-based dynamic random access memory (DRAM) technology is facing the dual challenges of the physical limits of process miniaturization and the "memory wall" bottleneck.

[0003] To address this challenge, novel DRAM technology with a three-dimensional stacked architecture (hereinafter referred to as "3D DRAM") has become a focus of industry attention. Among them, the 2T0C (dual transistor capacitorless) or 2T1C (dual transistor single capacitor) memory cell structure based on oxide semiconductor (OS) is highly favored due to its extremely low off-state current and compatibility with complementary metal-oxide-semiconductor (CMOS) back-end processes.

[0004] However, while oxide semiconductor transistors in 3D DRAM allow for monolithic 3D stacking at low temperatures, their metal electrodes are prone to unintended oxidation during the stacking process, forming a high-resistivity interface oxide layer. This interface oxide layer affects the performance of 3D DRAM. Therefore, a technical solution is needed to obtain high-performance 3D DRAM by preventing metal electrode oxidation. Summary of the Invention

[0005] This application provides a semiconductor structure and its fabrication method, as well as an electronic device, which can effectively prevent the oxidation of metal electrodes during the three-dimensional stacking process while ensuring the performance of oxide semiconductor devices and the quality of each film layer, thereby preparing high-performance 3D DRAM.

[0006] The technical solution of this application embodiment is implemented as follows:

[0007] This application provides a method for fabricating a semiconductor structure, comprising: forming a read transistor above a substrate, wherein the read transistor includes a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode stacked from bottom to top; using a deposition process, growing a first dielectric material based on a weakly oxidizing precursor above the first source / drain electrode to form a passivation layer, wherein the passivation layer is used to protect the first source / drain electrode from oxidation in subsequent processes; forming an insulating layer above the passivation layer, wherein the passivation layer and the insulating layer together constitute an interlayer isolation medium; forming a write transistor above the interlayer isolation medium, wherein the write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top; wherein the method further comprises: forming a vertical interconnect via, wherein one end of the vertical interconnect via is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to a second source electrode or a second drain electrode in the second source / drain electrode.

[0008] This application provides a semiconductor structure that can be fabricated using the above-described method. The semiconductor structure may include: a read transistor and a write transistor stacked from bottom to top, wherein the read transistor includes a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode stacked from bottom to top; the write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top; an interlayer isolation medium located between the read transistor and the write transistor; the interlayer isolation medium includes a passivation layer and an insulating layer stacked from bottom to top; the passivation layer is formed by growing a first dielectric material based on a weakly oxidizing precursor using a deposition process; and a vertical interconnect via, wherein one end of the vertical interconnect via is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to a second source electrode or a second drain electrode in the second source / drain electrode.

[0009] This application provides an electronic device, including: a circuit board and the semiconductor structure described above.

[0010] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0011] In this embodiment, after forming the read transistor using a back-gate planar transistor architecture, the first source / drain electrode faces upwards. A passivation layer covering the first source / drain electrode is formed by growing a first dielectric material on top of the first source / drain electrode using a deposition process based on a weakly oxidizing precursor. Then, an insulating layer is formed by depositing dielectric material on top of the passivation layer using a deposition process. The thickness of the insulating layer in the vertical direction is much greater than the thickness of the passivation layer in the vertical direction. Thus, the passivation layer and the insulating layer together form the interlayer isolation medium between the upper and lower transistor layers. On one hand, the thickness of this interlayer isolation medium meets the requirements for fabricating 3D DRAM, enabling three-dimensional stacking of the DRAM. On the other hand, the passivation layer in this interlayer isolation medium can protect the first source / drain electrode from oxidation in subsequent processes, eliminating the presence of a high-resistivity metal oxide interface layer on the surface of the first source / drain electrode, thereby ensuring high-speed read / write and high reliability of the 3D DRAM.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0013] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0014] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application.

[0015] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application.

[0016] Figures 3 to 21 This is a schematic diagram illustrating the fabrication process of a semiconductor structure provided in an embodiment of this application.

[0017] Figure 22 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 .

[0018] Figure 23 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 .

[0019] Figure 24 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 3 .

[0020] Figure 25 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 4 .

[0021] Figure 26 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 5 .

[0022] The reference numerals and names in the figure are as follows:

[0023] Tw, write transistor; Tr, read transistor; WWL, write word line; WBL, write bit line; RBL, read bit line; RWL, read word line; SN, memory node;

[0024] 1. Silicon substrate; 2. First gate electrode; 3. First gate dielectric layer; 4. First oxide semiconductor material layer; 5. First oxide semiconductor channel layer; 6. First source / drain electrode; 7. Passivation layer; 8. Initial insulating layer; 9. Insulating layer; 10. Initial first trench; 11. First trench; 12. Metal material layer; 13. Vertical interconnect via; 14. Second gate electrode; 15. Second gate dielectric layer; 16. Second oxide semiconductor material layer; 17. Second oxide semiconductor channel layer; 18. Second source / drain electrode; 19. Intermediate dielectric layer; 20. First gate dielectric sublayer; 21. Second gate dielectric sublayer; 22. Third gate dielectric sublayer; 23. Fourth gate dielectric sublayer; 24. Metal oxide interface. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0028] In 3D DRAM manufacturing processes, to achieve high-performance, low-resistance metal interconnects, active metal materials such as titanium nitride (TiN) and tungsten (W) can be used for the metal electrodes. Simultaneously, to achieve high-quality electrical isolation between the upper and lower transistor layers, atomic layer deposition (ALD) technology can be used to prepare high-k interlayer isolation media. ALD technology often uses ozone (O3) as a strong oxidizing precursor to enhance the density of the interlayer isolation media. While O3 oxidation helps repair oxygen vacancy defects in oxide semiconductor channels and improves device performance, its extremely strong oxidizing ability can lead to severe unintended oxidation on the surface of titanium nitride (TiN) or tungsten (W) electrodes, forming a high-resistance metal-oxide interface layer. This metal-oxide interface layer can cause various negative effects, such as increased contact resistance of the 2T0C DRAM interconnect layer, reduced read / write speed, and decreased reliability.

[0029] Therefore, how to effectively prevent the oxidation of active metal electrodes during the dielectric deposition process while ensuring the performance of oxide semiconductor devices and the quality of the dielectric layer has become a key technical challenge that needs to be solved in the preparation of high-performance 3D DRAM.

[0030] This application proposes a semiconductor structure and its fabrication method, as well as an electronic device, which can effectively solve the problem of oxidation of metal electrodes during the fabrication of interlayer isolation media in 3D DRAM while ensuring the performance of 2T0C DRAM devices and the quality of each film layer.

[0031] In a first aspect, embodiments of this application provide a method for preparing a semiconductor structure.

[0032] Figure 1 This is a schematic diagram of a circuit structure for a semiconductor structure provided in an embodiment of this application. See also... Figure 1 As shown, the 2T0C DRAM includes a write transistor Tw and a read transistor Tr, forming a memory node SN between them. The gate of the write transistor Tw is connected to the write word line WWL. One source / drain electrode (i.e., the source or drain electrode) of the write transistor Tw is connected to the write bit line WBL, and the other source / drain electrode is connected to the gate of the read transistor Tr. One source / drain electrode of the read transistor Tr is connected to the read bit line RBL, and the other source / drain electrode is connected to the read word line RWL.

[0033] Figure 2 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. See also... Figure 2 As shown, having Figure 1The method for fabricating the semiconductor structure of the circuit shown may include steps 101 to 105.

[0034] Step 201: Form a read transistor above the substrate, wherein the read transistor includes a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer and a first source drain electrode stacked from bottom to top.

[0035] Step 202: Using a deposition process, a first dielectric material is grown on top of the first source / drain electrode based on a weakly oxidizing precursor to form a passivation layer, wherein the passivation layer is used to protect the first source / drain electrode from oxidation in subsequent processes.

[0036] Step 203: An insulating layer is formed above the passivation layer, wherein the passivation layer and the insulating layer together constitute an interlayer isolation medium.

[0037] Step 204: Form a write transistor over the interlayer isolation medium, wherein the write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top.

[0038] The method also includes:

[0039] Step 205: Form a vertical interconnect via, wherein one end of the vertical interconnect via is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to the second source electrode or the second drain electrode in the second source-drain electrode.

[0040] In this embodiment, after forming the read transistor with a back-gate planar transistor architecture, the first source / drain electrode faces upwards. A passivation layer covering the first source / drain electrode can be formed by growing a first dielectric material based on a weakly oxidizing precursor using a deposition process. Then, an insulating layer can be formed by depositing dielectric material on top of the passivation layer using a deposition process. The thickness of the insulating layer in the vertical direction is much greater than the thickness of the passivation layer in the vertical direction. Thus, the passivation layer and the insulating layer together form the interlayer isolation medium between the upper and lower transistor layers. On the one hand, the thickness of this interlayer isolation medium meets the requirements for fabricating 3D DRAM; on the other hand, the passivation layer in the interlayer isolation medium can be used to protect the first source / drain electrode from oxidation in subsequent processes. For example, the passivation layer can protect the first source / drain electrode from oxidation during the formation of the insulating layer. After forming the interlayer isolation medium, a write transistor with a back-gate planar transistor architecture can be formed on top of the interlayer isolation medium, and vertical interconnect vias connecting the read transistor and the write transistor can also be formed, ultimately obtaining a 2T0C DRAM with a three-dimensional stacked configuration. Furthermore, the 2T0C DRAM does not have a high-resistivity metal oxide interface layer on the surface of the first source and drain electrode, thus ensuring high-speed read and write and high reliability of the high-density 3D DRAM.

[0041] It should be noted that, Figure 2 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 2 The steps shown can be adjusted in order according to actual needs. For example, the step of forming vertical interconnect vias can be performed simultaneously with the step of forming the various film layers (such as the second gate electrode and the second gate dielectric layer) in the write transistor, or it can be performed before the step of forming the write transistor.

[0042] Figures 3 to 21 This is a schematic diagram illustrating the fabrication process of a semiconductor structure provided in an embodiment of this application. Figures 3 to 21 All images show cross-sectional views of the semiconductor structure along the same direction. The following will combine... Figures 1 to 21 The method for preparing the semiconductor structure and the semiconductor structure obtained by the present application are described by way of example.

[0043] In step 201, a readout transistor is formed over the substrate.

[0044] Understandably, by providing a substrate and then sequentially fabricating a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode on the substrate, a readout transistor employing a back-gate planar transistor architecture can be formed.

[0045] In some embodiments, by providing a substrate, a gate electrode material can be deposited on the surface of the substrate using a deposition process to form an initial gate electrode thin film layer. The initial gate electrode thin film layer is then processed using a patterning process to obtain a first gate electrode. After forming the first gate electrode, a gate dielectric material can be deposited over the first gate electrode using a deposition process to form a first gate dielectric layer. After forming the first gate dielectric layer, an oxide semiconductor material can be deposited over the first gate dielectric layer using a deposition process to form a first oxide semiconductor material layer. Here, the first oxide semiconductor material layer is subsequently used to fabricate a first oxide semiconductor channel layer in a read transistor. After forming the first oxide semiconductor material layer, the first oxide semiconductor material layer can be processed using a patterning process to form a first oxide semiconductor channel layer. After forming the first oxide semiconductor channel layer, a metal material can be deposited over the first oxide semiconductor channel layer using a deposition process to form a first source / drain metal layer. The first source / drain metal layer is then processed using a patterning process to form the first source / drain electrode.

[0046] In some embodiments, the substrate can be any semiconductor substrate such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, silicon-on-insulator substrate, etc., and the embodiments of this application do not limit this.

[0047] In some embodiments, the first gate electrode serves as a memory node in a 2T0C DRAM. The first gate electrode corresponds to Figure 1 The storage node SN is shown.

[0048] In some embodiments, the first source / drain electrode includes a first source electrode and a first drain electrode. The first source electrode is patterned as a read bit line (RBL) extending continuously along a second direction, and the first drain electrode is patterned as a read word line (RWL) extending continuously along a first direction. The first and second directions are perpendicular to each other, and both the first and second directions are parallel to the upper surface of the substrate. By providing word lines and bit lines extending along the first and second directions respectively, an interleaved addressing memory array is constructed.

[0049] In some embodiments, read word lines and read bit lines are used to sense the charge state of internal memory nodes during read operations.

[0050] It should be noted that, unless otherwise specified, in the embodiments of this application, the deposition process may include ALD, physical vapor deposition (PVD), chemical vapor deposition (CVD), and metal-organic chemical vapor deposition (MOCVD). PVD may include direct current magnetron sputtering (DCMS) and electron beam evaporation (EBE).

[0051] In some embodiments, the metal material forming the first gate electrode may be a metal or alloy of tantalum nitride (TiN), tungsten (W), molybdenum (Mo), palladium (Pd), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), tantalum (Ta), or copper (Cu).

[0052] In some embodiments, after forming the first gate electrode, a first gate dielectric layer can be formed by growing a gate dielectric material on top of the first gate electrode using a deposition process based on a weakly oxidizing precursor. The first gate dielectric layer is used to protect the first gate electrode from oxidation in subsequent processes.

[0053] In some embodiments, the gate dielectric material forming the first gate dielectric layer may be a High-k dielectric material.

[0054] In some embodiments, the gate dielectric material forming the first gate dielectric layer may be one or a combination of silicon dioxide (SiO2), hafnium dioxide (HfO2), hafnium silicate (HfSiOx), hafnium lanthanum oxide (HfLaOx), hafnium aluminum oxide (HfAlOx) and other high dielectric constant dielectrics.

[0055] In some embodiments, the oxide semiconductor material forming the first oxide semiconductor channel layer may include indium trioxide (In2O3), tin dioxide (SnO2), gallium trioxide (Ga2O3), zinc oxide (ZnO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin zinc oxide (ITZO), indium tungsten oxide (IWO), indium tin tungsten oxide (ITWO), and all oxide semiconductor thin films and composite thin films of various doping components and proportions.

[0056] In some embodiments, the metal forming the first source / drain electrode can be an active metal material, such as tantalum nitride (TiN) or tungsten (W), to achieve high-performance, low-resistance metal interconnects.

[0057] In some embodiments, patterning can be a core technology in semiconductor fabrication that precisely transfers circuit design patterns to the wafer surface, achieving nanometer-level precision in device structure definition through the synergy of photolithography and etching.

[0058] See Figure 3 As shown, a single-crystal silicon substrate 1 with a resistivity much higher than that of a standard silicon wafer (i.e., resistivity > 1000 Ω·cm, which can reach 1000 to 10000 Ω·cm or even higher) can be obtained first.

[0059] In some embodiments, a silicon dioxide thin film layer with a thickness of 100 nanometers (i.e., 100 nm SiO2) may be attached to the surface of the silicon substrate. After obtaining the silicon substrate, it can be subjected to standard RCA cleaning.

[0060] See Figure 4 As shown, after obtaining the silicon substrate 1, a gate electrode material can be deposited on the upper surface of the silicon substrate 1 using ALD, DCMS, or EBE processes to form an initial gate electrode thin film layer. Then, a photolithography process can be used to etch the initial gate electrode thin film layer to obtain the first gate electrode 2.

[0061] In some embodiments, after obtaining the silicon substrate, a photolithography process can be used to form a photoresist mask over the silicon substrate. Then, a deposition process is used to deposit gate electrode material to form an initial gate electrode film covering the photoresist and the exposed area. The photoresist is then stripped away, and the initial gate electrode film over the photoresist is removed; the retained initial gate electrode film forms the first gate electrode. Here, the deposition process may include an EBE process.

[0062] See Figure 5 As shown, after obtaining the first gate electrode 2, an atomic layer deposition process can be used to deposit a gate dielectric material on top of the first gate electrode 2 based on a weakly oxidizing precursor, forming the first gate dielectric layer 3. It is understandable that if a strong oxidizing precursor atomic layer deposition process is used to grow the gate dielectric material, the metal surface of the first gate electrode 2 is easily oxidized, forming a high-resistivity metal oxide interface layer. Therefore, this step abandons the traditional ozone as the oxygen source precursor and instead uses a weakly oxidizing precursor to grow the first gate dielectric layer 3 without oxidizing the first gate electrode 2.

[0063] In some embodiments, if a non-atomic layer deposition process (such as reactive co-sputtering (non-oxidizing environment)) is used to deposit the first gate dielectric layer, the first gate electrode may not be oxidized. Therefore, depositing a weakly oxidizing precursor above the first gate electrode to form the first gate dielectric layer is only an optional solution. Those skilled in the art should understand that the scope of protection of this application is not limited thereto. Similarly, the implementation of the second gate dielectric layer is similar to that of the first gate dielectric layer.

[0064] See Figure 6 As shown, after forming the first gate dielectric layer 3, an oxide semiconductor material can be deposited on top of the first gate dielectric layer 3 using DCMS or ALD processes to form the first oxide semiconductor material layer 4.

[0065] See Figure 7 As shown, after the first oxide semiconductor material layer 4 is formed, wet etching or dry etching processes can be used to pattern the first oxide semiconductor material layer 4 to form the first oxide semiconductor channel layer 5.

[0066] See Figure 8 As shown, after forming the first oxide semiconductor channel layer 5, a metal material can be deposited on top of the first oxide semiconductor channel layer using a deposition process to form the first source / drain metal layer. Then, the first source / drain metal layer is patterned using a dry etching process to form the first source / drain electrode 6, thus obtaining the readout transistor Tr.

[0067] In some embodiments, after obtaining the first oxide semiconductor channel layer, a photolithography process can be used to form a photoresist mask over the first oxide semiconductor channel layer. Then, a deposition process is used to deposit a metal material to form a first source / drain metal layer covering the photoresist and the exposed area. The photoresist is then stripped away, and the first source / drain metal layer over the photoresist is removed, leaving the retained first source / drain metal layer to form the first source / drain electrodes. Here, the deposition process may include an EBE process.

[0068] After step 201 is completed, the first gate electrode, the first gate dielectric layer, the first oxide semiconductor channel layer and the first source / drain electrode are stacked from bottom to top, and the upper surface of the first source / drain electrode is exposed.

[0069] In step 202, a passivation layer is formed over the read transistor.

[0070] Understandably, a first dielectric material can be grown on top of the first source / drain electrodes using a deposition process, forming a passivation layer. This passivation layer protects the first source / drain electrodes from oxidation in subsequent processes. Since this step requires the use of a vapor-phase precursor for thin film deposition, the deposition process can include ALD, CVD, or MOCVD processes.

[0071] In some embodiments, the weak oxidizing precursor may be an organic alcohol oxygen source precursor.

[0072] In some embodiments, the organic alcohol oxygen source precursor may include one or a combination of weak oxidizing materials such as methanol, ethanol, ethylene glycol, isopropanol, and tert-butanol.

[0073] In some embodiments, the first dielectric material forming the passivation layer may be one or a combination of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium lanthanum oxide (HfLaOx), and hafnium silicon oxide (HfSiOx).

[0074] See Figure 9 As shown, after forming the read transistor, an atomic layer deposition process can be used to alternately introduce a metal source precursor and an organic alcohol-based weak oxidizing oxygen source precursor into the reaction chamber. Utilizing the nucleation selectivity of the metal source precursor and the organic alcohol-based weak oxidizing oxygen source precursor on different material surfaces, the deposition rate of the first dielectric material on the surface of the first source / drain electrode 6 is significantly higher than the deposition rate on the surface of the first oxide semiconductor channel layer 5. A passivation layer 7 is preferentially and selectively grown on the surface of the first source / drain electrode 5. The passivation layer 7 also serves to passivate the first source / drain electrode 6 and protect the surface of the first oxide semiconductor channel layer 5 from damage by subsequent strong oxidation processes.

[0075] In some embodiments, the metal source precursor comprises hafnium (Hf), zirconium (Zr), or aluminum (Al).

[0076] Understandably, the deposition rate of the first dielectric material on the surface of the first source / drain electrode is significantly higher than that on the surface of the first oxide semiconductor channel layer, enabling selective regional deposition of the dielectric material and eliminating the need for additional photolithography patterning steps. Therefore, in step 202, by using a weakly oxidizing precursor, a dielectric layer can be grown in situ as a passivation layer without oxidizing the first source / drain electrode.

[0077] In step 203, an insulating layer is formed over the passivation layer.

[0078] Understandably, after forming the passivation layer, a third dielectric material can be deposited on top of the passivation layer to form an insulating layer covering the passivation layer. The thickness of the insulating layer in the vertical direction is greater than the thickness of the passivation layer in the vertical direction. The passivation layer and the insulating layer together form an interlayer isolation dielectric. Here, the interlayer isolation dielectric is used to electrically isolate the upper and lower transistor layers to realize 3D DRAM.

[0079] Here, the third dielectric material forming the insulating layer can be a silicon-containing dielectric material. Silicon-containing dielectric materials can include one or a combination of insulating dielectrics such as silicon oxide (SiO2), silicon nitride (Si3N4), or doped silicon oxide.

[0080] See Figure 10 As shown, after the passivation layer 7 is formed, a deposition process can be used to deposit a third dielectric material on top of the passivation layer 7 to form the initial insulating layer 8.

[0081] See Figure 11 As shown, after the initial insulating layer 8 is formed, a chemical mechanical polishing process can be used to planarize the surface of the initial insulating layer 8 until a predetermined thickness is reached, forming the insulating layer 9. Here, the thickness of the passivation layer 7 and the insulating layer 9 in the vertical direction is equal to the predetermined interlayer isolation thickness.

[0082] Understandably, since the first source and drain electrodes have been sealed and protected by the passivation layer, step 203 can employ deposition processes such as plasma enhanced chemical vapor deposition (PECVD) and ion beam deposition (IBD), or other deposition processes. This application embodiment does not limit this to any particular process.

[0083] In step 205, vertical interconnect vias are formed.

[0084] Understandably, after the interlayer isolation dielectric is fabricated, vertical interconnect vias can be formed that penetrate the interlayer isolation dielectric and the dielectric structures (such as the first gate dielectric layer) in the upper and lower transistors. These vertical interconnect vias extend perpendicular to the substrate and are used for electrical connection between the first gate electrode in the read transistor and the second source / drain electrode in the subsequently fabricated write transistor. Specifically, the vertical interconnect vias can connect the second source electrode or the second drain electrode in the second source / drain electrode to the first gate electrode, thereby achieving electrical connection.

[0085] In some embodiments, the vertical interconnect via is fabricated before the write transistor is fabricated. In this case, the vertical interconnect via can simultaneously penetrate both the interlayer isolation medium and the first gate dielectric layer. Thus, step 205 may include: after forming the insulating layer, sequentially etching the interlayer isolation medium and the first gate dielectric layer to form a first trench, and depositing metal material within the first trench to form the vertical interconnect via.

[0086] See Figure 12 As shown, the via location is defined using photolithography, and this via location corresponds to the first gate electrode 2 of the read transistor. Then, the insulating layer 9 is etched using an etching process to form the initial first trench 10.

[0087] See Figure 13 As shown, the passivation layer 7 and the first gate dielectric layer 3 at the bottom of the initial first trench 10 are etched until the first gate electrode 2 is exposed, thus forming the first trench 11.

[0088] See Figure 14 As shown, after the first trench 11 is formed, a metal material can be deposited using a deposition process to obtain a metal material layer 12. Here, the metal material can at least fill the first trench 11.

[0089] See Figure 15 As shown, after the metal material layer 12 is formed, the metal material layer 12 can be planarized by a chemical mechanical polishing process until a vertical interconnecting via 13 filling the first trench 11 is formed.

[0090] In some embodiments, step 205 may include: after forming the second gate dielectric layer, sequentially etching the second gate dielectric layer, the insulating layer and the first gate dielectric layer to form a second trench, and depositing metal material in the second trench to form a vertical interconnect via.

[0091] Understandable. Figures 12 to 15 This illustrates a method for fabricating vertical interconnect vias (VIVs) prior to the fabrication of the write transistor. In other fabrication methods, VIVs can be fabricated simultaneously during the fabrication of the write transistor. In this case, the VIV can simultaneously penetrate the interlayer isolation medium, the first gate dielectric layer, and the second gate dielectric layer. Step 205 can be fabricated after the formation of the second gate dielectric layer in step 204. By sequentially etching the second gate dielectric layer, the interlayer isolation medium, and the first gate dielectric layer, a second trench can be formed. Subsequently, metal material is deposited within the second trench to form the VIV.

[0092] In step 204, a write transistor is formed over the interlayer isolation medium.

[0093] Understandably, by sequentially fabricating a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode over an interlayer isolation medium, a write transistor employing a back-gate planar transistor architecture can be formed.

[0094] In some embodiments, after forming vertical interconnect vias, a deposition process can be used to deposit gate electrode material on the surface of the interlayer isolation dielectric to form an initial gate electrode thin film layer. A patterning process is then used to process the initial gate electrode thin film layer to obtain a second gate electrode. After forming the second gate electrode, a deposition process can be used to deposit gate dielectric material over the second gate electrode to form a second gate dielectric layer. After forming the second gate dielectric layer, a deposition process can be used to deposit oxide semiconductor material over the second gate dielectric layer to form a second oxide semiconductor material layer. Here, the second oxide semiconductor material layer is subsequently used to fabricate a second oxide semiconductor channel layer in the read transistor. After forming the second oxide semiconductor material layer, a patterning process can be used to process the second oxide semiconductor material layer to form a second oxide semiconductor channel layer. After forming the second oxide semiconductor channel layer, a deposition process can be used to deposit metal material over the second oxide semiconductor channel layer to form a second source / drain metal layer. A patterning process is then used to process the second source / drain metal layer to form the second source / drain electrodes.

[0095] In some embodiments, the second gate electrode can be patterned as a write word line (WWL) extending along a first direction. The write word line is used to control the on and off states of the write transistor. Simultaneously, the orthographic projection of the second gate electrode toward the substrate does not coincide with the orthographic projection of the vertical interconnect via toward the substrate. Thus, the second gate electrode can avoid the location of the vertical interconnect via to prevent unintended short circuits.

[0096] In some embodiments, the orthographic projection of the second oxide semiconductor channel layer toward the substrate does not coincide with the orthographic projection of the vertical interconnect via toward the substrate. Thus, the second oxide semiconductor channel layer can avoid the location of the vertical interconnect via, preventing unintended short circuits.

[0097] In some embodiments, the second source / drain electrode includes a second source electrode and a second drain electrode. One electrode of the second source / drain electrode (such as the second source electrode) covers an interconnect via structure, thereby enabling an electrical interconnect between the source of the write transistor and the gate of the read transistor through a vertical interconnect via. The other electrode of the second source / drain electrode (such as the second drain electrode) can be patterned as a write bit line (WBL) extending continuously along a second direction. The second drain electrode is parallel to the read bit line in the read transistor and spatially orthogonally intersects the read word line in the read transistor.

[0098] In some embodiments, the second gate electrode of the top-level write transistor extends along a first direction to form a write word line, and the second drain electrode extends along a second direction to form a write bit line. The first drain electrode of the bottom-level read transistor extends along the first direction to form a read word line, and the first source electrode extends along the second direction to form a read bit line. Data writing, holding, and reading are accomplished by applying voltage pulses to the write word line, write bit line, read bit line, and read word line.

[0099] In some embodiments, the metal material forming the second gate electrode may be tantalum nitride (TiN), tungsten (W), molybdenum (Mo), palladium (Pd), nickel (Ni), gold (Au), platinum (Pt), aluminum (Al), tantalum (Ta), or copper (Cu) and their alloys.

[0100] In some embodiments, after forming the second gate electrode, a second gate dielectric layer can be formed by growing a gate dielectric material based on a weakly oxidizing precursor over the second gate electrode using a deposition process. The second gate dielectric layer is used to protect the second gate electrode from oxidation in subsequent processes.

[0101] In some embodiments, the gate dielectric material forming the second gate dielectric layer may be a High-k dielectric material.

[0102] In some embodiments, the gate dielectric material forming the second gate dielectric layer may be one or a combination of silicon dioxide (SiO2), hafnium dioxide (HfO2), hafnium silicate (HfSiOx), hafnium lanthanum oxide (HfLaOx), hafnium aluminum oxide (HfAlOx) and other high dielectric constant dielectrics.

[0103] In some embodiments, the oxide semiconductor material forming the second oxide semiconductor channel layer may include indium trioxide (In2O3), tin dioxide (SnO2), gallium trioxide (Ga2O3), zinc oxide (ZnO), indium tin oxide (ITO), indium gallium oxide (IGO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), indium tin zinc oxide (ITZO), indium tungsten oxide (IWO), indium tin tungsten oxide (ITWO), and all oxide semiconductor thin films and composite thin films of various doping components and proportions.

[0104] In some embodiments, the metal forming the second source / drain electrode can be an active metal material, such as tantalum nitride (TiN) or tungsten (W), to achieve high-performance, low-resistance metal interconnects.

[0105] See Figure 16As shown, after forming the vertical interconnect vias, gate electrode material can be deposited on the surface of the interlayer isolation dielectric using ALD, DCMS, or EBE processes to form an initial gate electrode thin film. Subsequently, photolithography can be used to etch the initial gate electrode thin film to obtain the second gate electrode 14.

[0106] In some embodiments, after forming the vertical interconnect vias, a photolithography process can be used to form a photoresist mask over a silicon substrate. Then, a deposition process is used to deposit gate electrode material to form an initial gate electrode film covering the photoresist and the exposed areas. The photoresist is then stripped away, and the initial gate electrode film over the photoresist is removed; the retained initial gate electrode film forms the second gate electrode. Here, the deposition process may include an EBE process.

[0107] See Figure 17 As shown, after forming the second gate electrode 14, an atomic layer deposition process can be used to deposit a gate dielectric material on top of the second gate electrode 14 based on a weakly oxidizing precursor, forming the second gate dielectric layer 15. It is understandable that if a strong oxidizing precursor atomic layer deposition process is used to grow the gate dielectric material, the metal surface of the second gate electrode 14 is easily oxidized, forming a high-resistivity metal oxide interface layer. Therefore, this step abandons the traditional ozone as an oxygen source and instead uses a weakly oxidizing precursor to grow the second gate dielectric layer 15 without oxidizing the second gate electrode 14.

[0108] See Figure 18 As shown, after obtaining the second gate dielectric layer 15, an oxide semiconductor material can be deposited on the second gate dielectric layer 15 using DCMS or ALD processes to form a second oxide semiconductor material layer 16.

[0109] See Figure 19 As shown, after obtaining the second oxide semiconductor material layer 16, the second oxide semiconductor material layer 16 can be patterned by wet etching or dry etching process to form the second oxide semiconductor channel layer 17.

[0110] See Figure 20 As shown, after forming the second oxide semiconductor channel layer 17, the second gate dielectric layer 15 above the vertical interconnect via 13 can be removed to expose the vertical interconnect via 13, so that the second source electrode or the second drain electrode formed in the subsequent process of fabricating the second source and drain electrodes can be directly connected to the vertical interconnect via 13.

[0111] See Figure 21As shown, after forming the second oxide semiconductor channel layer 17, a metal material can be deposited on top of the second oxide semiconductor channel layer 17 using a deposition process to form a second source / drain metal layer. Then, the second source / drain metal layer is patterned using a dry etching process to form the second source / drain electrodes 18, resulting in the write transistor Tw.

[0112] In some embodiments, after forming the second oxide semiconductor channel layer, a photolithography process can be used to form a photoresist mask over the second oxide semiconductor channel layer. Then, a deposition process is used to deposit a metal material to form a second source / drain metal layer covering the photoresist and the exposed areas. The photoresist is then stripped away, and the second source / drain metal layer over the photoresist is removed, leaving the retained second source / drain metal layer to form the second source / drain electrodes. Here, the deposition process may include an EBE process.

[0113] After step 204 is completed, the second gate electrode, the second gate dielectric layer, the second oxide semiconductor channel layer, and the second source / drain electrode are stacked from bottom to top to form the top-layer write transistor. The complete 2T0C DRAM cross-addressing array cell is fabricated. Understandably, since the bottom first source / drain electrode has been perfectly passivated by the high-dielectric-constant interface passivation layer grown from the weak oxide precursor, the bottom first source / drain electrode can be protected from secondary damage when the top-layer write transistor involves high-temperature or plasma processes, ensuring the low interconnect delay of the 3D cross array.

[0114] In this embodiment, the passivation layer in the interlayer isolation medium can be used to protect the first source / drain electrodes from oxidation in subsequent processes, ensuring that there is no high-resistivity metal oxide interface layer on the surface of the first source / drain electrodes, thereby guaranteeing high-speed read / write and high reliability of the 3D DRAM. Simultaneously, by employing atomic layer deposition (ALD) technology, a gate dielectric material is deposited above the gate electrode based on a weakly oxidizing precursor to form the gate dielectric in the top and bottom transistor layers. This effectively prevents the surface of the internal metal structure of the transistor from being oxidized and forming a high-resistivity metal oxide interface layer, ensuring low contact resistance within the transistor at the physical structure level, thereby further optimizing the performance of the 3D DRAM.

[0115] In some embodiments, the interlayer isolation medium further includes an intermediate dielectric layer. The intermediate dielectric layer is located between the passivation layer and the insulating layer. The step of forming the intermediate dielectric layer may include: using a deposition process to grow a second dielectric material on top of the passivation layer based on a strongly oxidizing precursor to form the intermediate dielectric layer.

[0116] Here, the intermediate dielectric layer is used to improve the film quality of the interlayer insulating medium. The film quality of the interlayer insulating medium can be measured by multiple parameters, including compactness, interface quality, barrier properties, and adhesion. In other words, the intermediate dielectric layer is at least used to improve the insulation performance of the interlayer insulating medium. The intermediate dielectric layer can improve the insulation performance of the interlayer insulating medium by enhancing the interface compactness between the passivation layer and the insulating layer, suppressing interdiffusion of interlayer elements, and reducing the interface state density.

[0117] In some embodiments, the second dielectric material forming the intermediate dielectric layer may be one or a combination of zirconium dioxide (ZrO2), aluminum oxide (Al2O3), silicon oxynitride (SiON).

[0118] In some embodiments, the strong oxidizing precursor may include ozone, oxygen, or nitrous oxide.

[0119] For example, Figure 22 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 1 , Figure 23 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 2 See also Figure 22 and Figure 23 As shown, the interlayer isolation medium may include: a passivation layer 7, an insulating layer 9, and an intermediate dielectric layer 19. The intermediate dielectric layer 19 is located between the passivation layer 7 and the insulating layer 9. Wherein, Figure 22 The intermediate medium layer 19 is formed by a deposition process, and the morphology of the intermediate medium layer 19 is consistent with that of the passivation layer. Figure 23 The intermediate dielectric layer is formed using a deposition process combined with a chemical mechanical planarization process. The lower surface of the intermediate dielectric layer 19 is in contact with the passivation layer 7, and the upper surface is flush with the substrate surface. It is evident that intermediate dielectric layers 19 with different morphologies can meet the usage requirements of 3D DRAM in different application scenarios.

[0120] In one example, the passivation layer was prepared using hafnium dioxide (HfO2), the intermediate dielectric layer was prepared using aluminum oxide (Al2O3), and the insulating layer was prepared using silicon dioxide (SiO2).

[0121] In the embodiments of this application, by providing an intermediate dielectric layer between the passivation layer and the insulating layer, defects that may exist at the interface between the passivation layer and the insulating layer can be mitigated, and the overall reliability of the interlayer isolation dielectric can be improved.

[0122] In some embodiments, the first gate dielectric layer may be a stacked structure. In this case, step 201 may include: after forming the first gate electrode, using a deposition process, first growing a gate dielectric material on top of the first gate electrode based on a weakly oxidizing precursor to form a first gate dielectric sublayer, and then growing a gate dielectric material on top of the first gate dielectric sublayer based on a strongly oxidizing precursor to form a second gate dielectric sublayer. The first and second gate dielectric sublayers are contained within the first gate dielectric layer.

[0123] Understandably, by sequentially depositing a first gate dielectric sublayer using a weakly oxidizing precursor and a second gate dielectric sublayer using a strongly oxidizing precursor above the first gate electrode, a gate dielectric stack structure with an oxygen concentration gradient distribution can be constructed. This gate dielectric stack structure ensures that a high-resistance metal-oxide interface is not generated on the surface of the first gate electrode during the fabrication of the first gate dielectric sublayer, reducing the contact resistance of the 3D DRAM. Simultaneously, the dense oxidation of the second gate dielectric sublayer guarantees high-k dielectric properties and insulation reliability. This synergistically optimizes key electrical parameters such as interface state density, equivalent oxide layer thickness, leakage current, and carrier mobility, effectively improving the long-term reliability of the device.

[0124] In some embodiments, the gate dielectric materials forming the first gate dielectric sublayer and the second gate dielectric sublayer may be different, or the gate dielectric materials forming the first gate dielectric sublayer and the second gate dielectric sublayer may be the same. This application does not limit this.

[0125] In one example, the gate dielectric material forming the first gate dielectric sublayer can be aluminum oxide (Al2O3), and the gate dielectric material forming the second gate dielectric sublayer can be hafnium dioxide (HfO2).

[0126] For example, Figure 24 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 3 See also Figure 24 As shown, the first gate dielectric layer 3 may include a first gate dielectric sublayer 20 and a second gate dielectric sublayer 21. The first gate dielectric sublayer 20 is formed by deposition of a weakly oxidizing precursor and is in contact with the surface of the first gate electrode 2, effectively preventing the formation of a high-resistance metal-oxide interface on the surface of the first gate electrode 2. The second gate dielectric sublayer 21 is formed by deposition of a strong oxidizing precursor and is located above the first gate dielectric sublayer 20.

[0127] In this embodiment, by setting a first gate dielectric layer of a stacked structure, the low contact resistance of the 3D DRAM can be guaranteed.

[0128] In some embodiments, the second gate dielectric layer may be a stacked structure. In this case, step 204 may include: after forming the second gate electrode, using a deposition process, first growing a gate dielectric material over the first gate electrode based on a weakly oxidizing precursor to form a third gate dielectric sublayer, and then growing a gate dielectric material over the third gate dielectric sublayer based on a strongly oxidizing precursor to form a fourth gate dielectric sublayer. The third and fourth gate dielectric sublayers are contained within the second gate dielectric layer.

[0129] As can be understood, referring to the description when the first gate dielectric layer is a multilayer structure, the second gate dielectric layer can have a similar structure and bring the same beneficial effects. For the sake of brevity, it will not be elaborated further here.

[0130] For example, Figure 25 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 4 See also Figure 25 As shown, the second gate dielectric layer 15 may include a third gate dielectric sublayer 22 and a fourth gate dielectric sublayer 23. The third gate dielectric sublayer 22 is formed by deposition of a weakly oxidizing precursor and is in contact with the surface of the second gate electrode 14, effectively preventing the formation of a high-resistance metal-oxide interface on the surface of the second gate electrode 14. The fourth gate dielectric sublayer 23 is formed by deposition of a strong oxidizing precursor and is located above the third gate dielectric sublayer 22.

[0131] In this embodiment of the application, by setting a second gate dielectric layer in a stacked structure, the low contact resistance of the 3D DRAM can be guaranteed.

[0132] Secondly, embodiments of this application provide a semiconductor structure.

[0133] See Figure 21 As shown, the semiconductor structure provided in this application embodiment can be fabricated using the fabrication method in any of the embodiments of the first aspect. The semiconductor structure may include: a read transistor and a write transistor stacked from bottom to top, wherein the read transistor includes a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode stacked from bottom to top; the write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top; an interlayer isolation medium located between the read transistor and the write transistor; the interlayer isolation medium includes a passivation layer and an insulating layer stacked from bottom to top; the passivation layer is formed by growing a first dielectric material based on a weakly oxidizing precursor using a deposition process; and a vertical interconnect via, wherein one end of the vertical interconnect via is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to a second source electrode or a second drain electrode in the second source / drain electrode.

[0134] In the embodiments of this application, the specific structure of each part in the semiconductor structure can be referred to the description in any embodiment of the first aspect, and will not be repeated here for the sake of brevity.

[0135] In some embodiments, the first gate dielectric layer may be a stacked structure, including a first gate dielectric sublayer and a second gate dielectric sublayer.

[0136] In some embodiments, the second gate dielectric layer may be a stacked structure, including a third gate dielectric sublayer and a fourth gate dielectric sublayer.

[0137] In some embodiments, one end of the vertical interconnect via is connected to the first gate electrode, and the other end passes through the interlayer isolation medium and the first gate dielectric layer and is connected to one end of the second source / drain electrode. The other end of the second source / drain electrode passes through the second gate dielectric and is connected to the second oxide semiconductor channel layer.

[0138] or,

[0139] One end of the vertical interconnect via is connected to the first gate electrode, and the other end passes through the second gate dielectric layer, the interlayer isolation dielectric and the first gate dielectric layer, and is connected to one end of the second source / drain electrode. The other end of the second source / drain electrode is connected to the second oxide semiconductor channel layer.

[0140] In some embodiments, the orthographic projection of the second gate electrode and the second oxide semiconductor channel layer toward the substrate does not coincide with the orthographic projection of the vertical interconnect via toward the substrate.

[0141] In some embodiments, the interlayer isolation medium further includes an intermediate dielectric layer located between the passivation layer and the insulating layer. The intermediate dielectric layer is formed using a deposition process to grow a second dielectric material on top of the passivation layer based on a strongly oxidizing precursor.

[0142] Figure 26 A schematic diagram of a semiconductor structure provided in this application embodiment. Figure 5 See also Figure 26 As shown, if the 3D DRAM is not fabricated using the method provided in this application embodiment, a high-resistivity metal-oxide interface 24 will be generated on the surfaces of the first gate electrode 2, the first source / drain electrode 6, the second gate electrode 14, and the vertical interconnect via 13. See also the embodiments in this application. Figure 21 As shown, a direct contact interface is formed between the metal structure and the high dielectric constant dielectric layer in 3D DRAM, eliminating the metal oxide layer that is inevitably associated with traditional strong oxide atomic layer deposition processes, thus ensuring low contact resistance from a physical structure perspective.

[0143] Thirdly, embodiments of this application provide an electronic device. It includes a circuit board and a semiconductor structure as described in the above embodiments, the semiconductor structure being disposed on the circuit board. The specific structure of the semiconductor structure can be found in the description of any embodiment of the first aspect; for the sake of brevity, it will not be repeated here.

[0144] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A read transistor is formed above the substrate, the read transistor comprising a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer, and a first source / drain electrode stacked from bottom to top; Using a deposition process, a first dielectric material is grown on top of the first source / drain electrode based on a weakly oxidizing precursor to form a passivation layer, wherein the passivation layer is used to protect the first source / drain electrode from oxidation in subsequent processes. An insulating layer is formed above the passivation layer, wherein the passivation layer and the insulating layer together constitute an interlayer isolation medium; A write transistor is formed over the interlayer isolation medium. The write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer, and a second source / drain electrode stacked from bottom to top. The method further includes: A vertical interconnect via is formed, one end of which is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to the second source electrode or the second drain electrode in the second source-drain electrode.

2. The method according to claim 1, characterized in that, The formation of the readout transistor over the substrate includes: After the first gate electrode is formed, a gate dielectric material is grown on the first gate electrode using a deposition process based on a weakly oxidizing precursor to form the first gate dielectric layer. or, After the first gate electrode is formed, a gate dielectric material is first grown on the first gate electrode based on a weakly oxidizing precursor to form a first gate dielectric sublayer, and then a gate dielectric material is grown on the first gate dielectric sublayer based on a strongly oxidizing precursor to form a second gate dielectric sublayer; the first gate dielectric sublayer and the second gate dielectric sublayer are contained in the first gate dielectric layer. The first gate dielectric layer is used to protect the first gate electrode from oxidation in subsequent processes.

3. The method according to claim 1, characterized in that, The formation of a write transistor over the interlayer isolation medium includes: After the second gate electrode is formed, a gate dielectric material is grown on top of the second gate electrode using a deposition process based on a weakly oxidizing precursor to form the second gate dielectric layer. or, After the second gate electrode is formed, a gate dielectric material is first grown on the first gate electrode based on a weakly oxidizing precursor to form a third gate dielectric sublayer, and then a gate dielectric material is grown on the third gate dielectric sublayer based on a strongly oxidizing precursor to form a fourth gate dielectric sublayer; the third gate dielectric sublayer and the fourth gate dielectric sublayer are contained in the second gate dielectric layer. The second gate dielectric layer is used to protect the second gate electrode from oxidation in subsequent processes.

4. The method according to any one of claims 1 to 3, characterized in that, The formation of vertical interconnect vias includes: After forming the insulating layer, the interlayer isolation medium and the first gate dielectric layer are etched sequentially to form a first trench, and metal material is deposited in the first trench to form the vertical interconnect via. or, After forming the second gate dielectric layer, the second gate dielectric layer, the interlayer isolation dielectric and the first gate dielectric layer are etched sequentially to form a second trench, and metal material is deposited in the second trench to form the vertical interconnect via.

5. The method according to claim 4, characterized in that, The formation of a write transistor over the interlayer isolation medium includes: Above the interlayer isolation medium, a second gate electrode, a second gate dielectric layer, and a second oxide semiconductor channel layer are sequentially formed, wherein the orthogonal projections of the second gate electrode and the second oxide semiconductor channel layer toward the substrate do not coincide with the orthogonal projections of the vertical interconnect vias toward the substrate; Above the second oxide semiconductor channel layer, a second source / drain electrode connecting the vertical interconnect via is formed using a patterning process.

6. The method according to claim 1, characterized in that, The deposition process includes: atomic layer deposition, chemical vapor deposition, or metal-organic chemical vapor deposition; The weakly oxidizing precursors include: organic alcohol precursors; The first dielectric material includes one or a combination of hafnium dioxide, zirconium dioxide, aluminum oxide, hafnium lanthanum oxide, and hafnium silicon oxide.

7. The method according to claim 1, characterized in that, After the method utilizes a deposition process to grow a first dielectric material on top of the first source / drain electrode based on a weakly oxidizing precursor to form a passivation layer, the method further includes: Using a deposition process, a second dielectric material is grown on top of the passivation layer based on a strong oxidizing precursor to form the intermediate dielectric layer, wherein the intermediate dielectric layer is contained within the interlayer isolation dielectric and is used to at least improve the insulation performance of the interlayer isolation dielectric.

8. The method according to claim 7, characterized in that, The strong oxidizing precursors include: ozone, oxygen, or nitrous oxide; The second dielectric material includes one or a combination of zirconium dioxide, aluminum oxide, and silicon oxynitride.

9. A semiconductor structure, characterized in that, Prepared by the method according to any one of claims 1 to 8, comprising: The read transistor and write transistor are stacked from bottom to top, wherein the read transistor includes a first gate electrode, a first gate dielectric layer, a first oxide semiconductor channel layer and a first source drain electrode stacked from bottom to top; the write transistor includes a second gate electrode, a second gate dielectric layer, a second oxide semiconductor channel layer and a second source drain electrode stacked from bottom to top. An interlayer isolation medium is located between the read transistor and the write transistor; the interlayer isolation medium includes a passivation layer and an insulating layer stacked from bottom to top; the passivation layer is formed by growing a first dielectric material on top of the first source and drain electrodes using a deposition process based on a weakly oxidizing precursor; A vertical interconnect via, wherein one end of the vertical interconnect via is connected to the first gate electrode, and the other end extends in a direction perpendicular to the substrate, at least penetrating the interlayer isolation medium, and is connected to the second source electrode or the second drain electrode in the second source-drain electrode.

10. An electronic device, characterized in that, include: A circuit board and the semiconductor structure as described in claim 9; the semiconductor structure is disposed on the circuit board.

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