Flash memory device and method of manufacturing the same

Abstract

This application provides a flash memory device and its fabrication method. In the fabrication method, the hard mask layer removal process is divided into two steps. The first step removes a certain thickness of hard mask layer so that the upper surface of the hard mask layer is lower than the upper surface of the first protective layer. The second step uses APC feedback to select an appropriate etching scheme based on the measurement results of the actual remaining thickness of the hard mask layer after the first step etching. On the one hand, through APC feedback, the etching process window of the hard mask layer can be adjusted in real time to completely remove the remaining thickness of the hard mask layer and ensure that the control gate layer is not mistakenly etched. On the other hand, the two-step hard mask layer etching process can first form steps in the right-angle regions on both sides of the first protective layer, and finally form a slope after the control gate layer and floating gate etching process, thereby increasing the top opening angle of the second trench and avoiding the situation where the high aspect ratio of the second trench leads to void defects in the subsequent interlayer dielectric layer filling.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a flash memory device and its fabrication method. Background Technology

[0002] In NORD flash memory devices, after sequentially forming a pad oxide layer, floating gate polysilicon, ONO film layer, and control gate polysilicon on the substrate surface, a silicon nitride layer is formed on the control gate surface. Subsequently, using this silicon nitride layer as a hard mask layer, the first trench of the flash memory cell structure is formed using a self-aligned process. After the word line polysilicon and word line guard layer are deposited, the silicon nitride layer on the flash memory cell side needs to be removed.

[0003] On the one hand, fluctuations in the fabrication process of the multilayer film of the flash memory cell will increase the changes in the silicon nitride layer (hard mask layer). During the removal of the silicon nitride layer (hard mask layer), excessive acid will erode the control gate polysilicon at the bottom of the silicon nitride layer, and may even form hole defects in the control gate polysilicon. In subsequent processes, dielectric material will inevitably be filled into the holes, which will easily lead to polysilicon residue on the bottom wall of the second trench when the control gate polysilicon, ONO film layer, floating gate polysilicon and pad oxide layer on both sides of the flash memory cell are removed to form the second trench.

[0004] On the other hand, the outline of the flash cell sidewall (the sidewall of the second trench) is inherited to some extent from the sidewall after the silicon nitride layer is removed. As the process node advances, the sidewall spacing on the floating gate side surface is small, which makes the filling of the subsequent interlayer dielectric layer more challenging. The second trench between the flash cell sidewalls has a high aspect ratio, and the filling of the subsequent interlayer dielectric layer is prone to void defects. Summary of the Invention

[0005] This application provides a flash memory device and its fabrication method, which can solve the problems that, during the removal process of the silicon nitride layer (hard mask layer) on the surface of the control gate, on the one hand, drill holes are formed in the polysilicon of the control gate, resulting in polysilicon residue on the bottom wall of the second trench, and on the other hand, the high aspect ratio of the second trench between the sidewalls of the flash memory cells leads to void defects in the filling of the subsequent interlayer dielectric layer.

[0006] On one hand, embodiments of this application provide a method for fabricating a flash memory device, including: A substrate is provided, on which a pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, a first sidewall, a second sidewall, a third sidewall, word line polysilicon, and a hard mask layer are formed, wherein the pad oxide layer, the floating gate layer, the ONO layer, the control gate layer, and the hard mask layer are sequentially formed on the substrate, and a plurality of spaced first trenches are formed in the hard mask layer, the control gate layer, the ONO layer, and the floating gate layer, and the first sidewall, the second sidewall, and the third sidewall are sequentially formed on the sidewalls of the first trenches, and the remaining space of the first trenches is filled with the word line polysilicon; The surface of the word line polysilicon is planarized using a chemical mechanical polishing process. A first protective layer is formed, which covers the word line polysilicon; A second protective layer is formed, which covers the hard mask layer and the first protective layer; The second protective layer and the hard mask layer of a certain thickness are etched away, wherein the upper surface of the remaining thickness of the hard mask layer is lower than the upper surface of the first protective layer; The actual remaining thickness of the hard mask layer is measured; Based on the actual remaining thickness of the hard mask layer, the remaining thickness of the hard mask layer is etched away and stopped on the surface of the control gate layer to form a second trench, wherein, during the removal of the remaining thickness of the hard mask layer, the top of the first sidewall on both sides of the word line polysilicon at the end of the first protective layer is over-etched to form a step. The control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer on the outer side of the first sidewall are removed. At the same time, the top of the first sidewall on both sides of the word line polysilicon at the end of the first protective layer is further over-etched, and a slope is formed on the remaining top surface of the first sidewall.

[0007] Optionally, in the method for fabricating the flash memory device, the hard mask layer is made of silicon nitride.

[0008] Optionally, in the method for fabricating the flash memory device, a wet etching process is used to etch away the second protective layer and the hard mask layer of a certain thickness.

[0009] Optionally, in the method for fabricating the flash memory device, a wet etching process is used to etch away the remaining thickness of the hard mask layer, as well as the end of the first protective layer and the top of the first sidewall on both sides of the word line polysilicon, based on the actual remaining thickness of the hard mask layer.

[0010] Optionally, in the method for fabricating the flash memory device, the first protective layer is made of silicon dioxide.

[0011] Optionally, in the method for fabricating the flash memory device, the material of the second protective layer is silicon nitride.

[0012] Optionally, in the method for fabricating the flash memory device, the first sidewall is made of silicon dioxide; the second sidewall is made of silicon nitride; and the third sidewall is made of silicon dioxide.

[0013] Optionally, in the method for fabricating the flash memory device, after removing the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer outside the first sidewall, and forming a slope on the end side surface of the remaining first protective layer and the top side surface of the first sidewall, the method for fabricating the flash memory device further includes: A fourth sidewall is formed, which covers the side surfaces of the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer at the bottom of the slope and a portion of the substrate surface.

[0014] Optionally, in the method for fabricating the flash memory device, the fourth sidewall includes: a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The first silicon oxide layer covers the side surfaces of the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer at the bottom of the ramp and the surface of a portion of the substrate. The silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers a portion of the surface of the silicon nitride layer near the bottom of the substrate.

[0015] On the other hand, embodiments of this application also provide a flash memory device, including: A substrate having a pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, a first sidewall, a second sidewall, a third sidewall, and word line polysilicon formed thereon, wherein the pad oxide layer, the floating gate layer, the ONO layer, the control gate layer, and the hard mask layer are sequentially formed on the substrate, and a plurality of spaced first trenches are formed in the hard mask layer, the control gate layer, the ONO layer, and the floating gate layer, and the first sidewall, the second sidewall, and the third sidewall are sequentially formed on the sidewalls of the first trenches, and the remaining space of the first trenches is filled with word line polysilicon; The second trench and the first trench are arranged alternately in the hard mask layer, the control gate layer, the ONO layer, the floating gate layer and the pad oxide layer; A first protective layer covers the word line polysilicon, wherein a slope is formed on the top surface of the first sidewall at the end of the first protective layer.

[0016] The technical solution of this application has at least the following advantages: This application provides a flash memory device and its fabrication method. In the fabrication method, the removal process of the hard mask layer is divided into two steps. The first step removes a certain thickness of the hard mask layer, making its upper surface lower than the upper surface of the first protective layer. The second step uses APC feedback based on the measurement results of the actual remaining thickness of the hard mask layer after the first etching step to select an appropriate etching scheme. On the one hand, through APC feedback, the etching process window of the hard mask layer can be adjusted in real time, thoroughly removing the remaining thickness of the hard mask layer while ensuring that the control gate layer is not mistakenly etched, thus avoiding… This avoids the problems of excessive etching leading to control gate pit defects or insufficient etching failing to completely remove the hard mask layer. On the other hand, the two-stage hard mask layer etching process can first form steps in the right-angled areas on both sides of the first protective layer, and finally form a slope after the control gate layer and floating gate etching process. This increases the top opening angle of the second trench, which is beneficial for the filling of the interlayer dielectric layer in the subsequent second trench. It also avoids the situation where the aspect ratio of the second trench between the flash memory cells is high, which would easily lead to void defects in the filling of the subsequent interlayer dielectric layer. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention; Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 100-Substrate, 110-Pad oxide layer, 120-Floating gate layer, 130-ONO layer, 140-Control gate layer, 150-Hard mask layer, 161-First sidewall, 162-Second sidewall, 163-Third sidewall, 164-First trench, 165-Step, 166-Second trench, 167-Bevel, 170-Word line polysilicon, 180-First protective layer, 190-Second protective layer, 201-First silicon oxide layer, 202-Silicon nitride layer, 203-Second silicon oxide layer. Detailed Implementation

[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] This application provides a method for fabricating a flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention. The method for fabricating the flash memory device includes: First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of a semiconductor after the formation of the first protective layer according to an embodiment of this application. A substrate 100 is provided, on which a pad oxide layer 110, a floating gate layer 120, an ONO layer 130, a control gate layer 140, a first sidewall 161, a second sidewall 162, a third sidewall 163, a word line polysilicon 170, and a hard mask layer 150 are formed. The pad oxide layer 110, the floating gate layer 120, the ONO layer 130, the control gate layer 140, the first sidewall 161, the second sidewall 162, the third sidewall 163, the word line polysilicon 170, and the hard mask layer 150 are formed. The hard mask layer 150 and the hard mask layer 150 are sequentially formed on the substrate 100. A plurality of spaced first trenches 164 are formed in the hard mask layer 150, the control gate layer 140, the ONO layer 130 and the floating gate layer 120. A first sidewall 161, a second sidewall 162 and a third sidewall 163 are sequentially formed on the sidewalls of the first trenches 164. The remaining space of the first trenches 164 is filled with word line polysilicon 170.

[0024] In this embodiment, the ONO layer 130 comprises, from bottom to top, a silicon oxide layer one, a silicon nitride layer and a silicon oxide layer two.

[0025] Preferably, the hard mask layer 150 is made of silicon nitride.

[0026] In this embodiment, the thickness of the hard mask layer 150 is 1500 angstroms to 2200 angstroms.

[0027] In this embodiment, the first sidewall 161 is made of silicon dioxide; the second sidewall 162 is made of silicon nitride; and the third sidewall 163 is made of silicon dioxide.

[0028] Then, proceed to step S2: Continue to refer to Figure 2 The surface of the word line polysilicon 170 is planarized by chemical mechanical polishing.

[0029] Next, proceed to step S3: Continue to refer to Figure 2 A first protective layer 180 is formed by using a high-temperature furnace tube oxidation process, and the first protective layer 180 covers the word line polycrystalline silicon 170.

[0030] In this embodiment, the first protective layer 180 is made of silicon dioxide.

[0031] Preferably, the thickness of the first protective layer 180 is 550 angstroms to 650 angstroms.

[0032] Further, proceed to step S4: (Refer to...) Figure 3 , Figure 3This is a schematic diagram of a semiconductor after the formation of the second protective layer according to an embodiment of this application. The second protective layer 190 is formed, and the second protective layer 190 covers the hard mask layer 150, the first sidewall 161 and the first protective layer 180.

[0033] In this embodiment, the second protective layer 190 is made of silicon nitride.

[0034] Preferably, the thickness of the second protective layer 190 is 500 angstroms to 580 angstroms.

[0035] Next, proceed to step S5: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of a semiconductor after etching away the second protective layer and the hard mask layer of a certain thickness according to an embodiment of this application. The second protective layer 190 and the hard mask layer 150 of a certain thickness are etched away, wherein the upper surface of the remaining thickness of the hard mask layer 150 is lower than the upper surface of the first protective layer 180.

[0036] Preferably, a wet etching process is used to etch away the second protective layer 190 and the hard mask layer 150 of a certain thickness.

[0037] In this embodiment, in step S5, the thickness of the hard mask layer 150 removed by etching is 900 angstroms to 1100 angstroms.

[0038] Further, step S6 is performed: the actual remaining thickness of the hard mask layer 150 is measured.

[0039] Next, proceed to step S7: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor after the formation of the second trench and step according to an embodiment of this application. Based on the actual remaining thickness of the hard mask layer 150, APC feedback is performed to etch away the remaining thickness of the hard mask layer 150 and stop on the surface of the control gate layer 140 to form the second trench 166. During the removal of the remaining thickness of the hard mask layer 150, the tops of the first sidewalls 161 on both sides of the word line polysilicon 170 at the end of the first protective layer 180 are over-etched to form a step 165.

[0040] Preferably, a wet etching process is used, and APC feedback is performed based on the actual remaining thickness of the hard mask layer 150, to etch away the remaining thickness of the hard mask layer 150, as well as the top of the first sidewall 161 on both sides of the word line polysilicon 170 over the end of the first protective layer 180.

[0041] Finally, proceed to step S8: (Refer to...) Figure 6 , Figure 6This is a schematic diagram of a semiconductor after removing the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer on the outer side of the first sidewall 161, and forming a slope, according to an embodiment of this application. The control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 on the outer side of the first sidewall 161 are removed. At the same time, the top of the first sidewall 161 on both sides of the word line polysilicon 170 at the end of the first protective layer 180 is further over-etched, and a slope 167 is formed on the remaining top surface of the first sidewall 161.

[0042] Further reference Figure 7 , Figure 7 This is a schematic diagram of a semiconductor after the formation of the fourth sidewall in an embodiment of this application. After removing the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 outside the first sidewall 161, and forming a ramp 167 on the top side surface of the remaining first sidewall 161, the method for fabricating the flash memory device may further include: forming a fourth sidewall, the fourth sidewall covering the ramp 167 and the side surfaces of the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 at the bottom of the ramp 167 and the surface of a portion of the substrate 100.

[0043] Preferably, the fourth sidewall includes: a first silicon oxide layer 201, a silicon nitride layer 202, and a second silicon oxide layer 203. The first silicon oxide layer 201 covers the slope 167 and the side surfaces of the control gate layer 140, the ONO layer 130, the floating gate layer 120, and the pad oxide layer 110 at the bottom of the slope 167, as well as a portion of the surface of the substrate 100. The silicon nitride layer 202 covers the first silicon oxide layer 201, and the second silicon oxide layer 203 covers a portion of the surface of the silicon nitride layer 202 near the bottom of the substrate 100.

[0044] In this application, the etching process of the hard mask layer is split into two steps. The first step removes a certain thickness of the hard mask layer, making the upper surface of the hard mask layer lower than the upper surface of the first protective layer. The second step uses APC feedback based on the measurement results of the actual remaining thickness of the hard mask layer after the first step to select an appropriate etching scheme. On the one hand, through APC feedback, the etching process window of the hard mask layer can be adjusted in real time to completely remove the remaining thickness of the hard mask layer and ensure that the control gate layer is not mistakenly etched. This avoids the situation where excessive etching leads to control gate hole (Pits) defects, or insufficient etching fails to completely remove the hard mask layer. On the other hand, the two-step hard mask layer etching process can first form steps in the right-angle areas on both sides of the first protective layer, and finally form a slope after the control gate layer and floating gate etching process. This increases the top opening angle of the second trench, which is beneficial to the filling of the interlayer dielectric layer in the subsequent second trench. This avoids the situation where the aspect ratio of the second trench between the flash memory cells is high, which would easily lead to void defects in the filling of the subsequent interlayer dielectric layer.

[0045] Based on the same inventive concept, embodiments of this application also provide a flash memory device, including: A substrate 100 has a pad oxide layer 110, a floating gate layer 120, an ONO layer 130, a control gate layer 140, a first sidewall 161, a second sidewall 162, a third sidewall 163, and word line polysilicon 170 formed on it. The pad oxide layer 110, the floating gate layer 120, the ONO layer 130, the control gate layer 140, and the hard mask layer 150 are sequentially formed on the substrate 100. A plurality of spaced first trenches 164 are formed in the hard mask layer 150, the control gate layer 140, the ONO layer 130, and the floating gate layer 120. The first sidewall 161, the second sidewall 162, and the third sidewall 163 are sequentially formed on the sidewalls of the first trenches 164. The remaining space of the first trenches 164 is filled with the word line polysilicon 170. The second trench 166 and the first trench 164 are arranged alternately in the hard mask layer 150, the control gate layer 140, the ONO layer 130, the floating gate layer 120 and the pad oxide layer 110. A first protective layer 180 covers the word line polysilicon 170, wherein a slope 167 is formed on the top surface of the first sidewall 161 at the end of the first protective layer 180.

[0046] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided, on which a pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, a first sidewall, a second sidewall, a third sidewall, word line polysilicon, and a hard mask layer are formed, wherein the pad oxide layer, the floating gate layer, the ONO layer, the control gate layer, and the hard mask layer are sequentially formed on the substrate, and a plurality of spaced first trenches are formed in the hard mask layer, the control gate layer, the ONO layer, and the floating gate layer, and the first sidewall, the second sidewall, and the third sidewall are sequentially formed on the sidewalls of the first trenches, and the remaining space of the first trenches is filled with the word line polysilicon; The surface of the word line polysilicon is planarized using a chemical mechanical polishing process. A first protective layer is formed, which covers the word line polysilicon; A second protective layer is formed, which covers the hard mask layer and the first protective layer; The second protective layer and the hard mask layer of a certain thickness are etched away, wherein the upper surface of the remaining thickness of the hard mask layer is lower than the upper surface of the first protective layer; The actual remaining thickness of the hard mask layer is measured; Based on the actual remaining thickness of the hard mask layer, the remaining thickness of the hard mask layer is etched away and stopped on the surface of the control gate layer to form a second trench, wherein, during the removal of the remaining thickness of the hard mask layer, the top of the first sidewall on both sides of the word line polysilicon at the end of the first protective layer is over-etched to form a step. The control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer on the outer side of the first sidewall are removed. At the same time, the top of the first sidewall on both sides of the word line polysilicon at the end of the first protective layer is further over-etched, and a slope is formed on the remaining top surface of the first sidewall.

2. The method of claim 1, wherein the method further comprises: The hard mask layer is made of silicon nitride.

3. The method of claim 1, wherein the method further comprises: A wet etching process is used to etch away the second protective layer and the hard mask layer of a certain thickness.

4. The method of claim 1, wherein the method further comprises: Using a wet etching process, the remaining thickness of the hard mask layer is etched away based on the actual remaining thickness of the hard mask layer, as well as the end of the first protective layer and the top of the first sidewall on both sides of the word line polysilicon.

5. The method of claim 1, wherein the method further comprises: The first protective layer is made of silicon dioxide.

6. The method of claim 1, wherein the method further comprises: The second protective layer is made of silicon nitride.

7. The method of claim 1, wherein the method further comprises: The first sidewall is made of silicon dioxide; the second sidewall is made of silicon nitride; and the third sidewall is made of silicon dioxide.

8. The method of claim 1, wherein the method further comprises: After removing the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer outside the first sidewall, and forming a slope on the end side surface of the remaining first protective layer and the top side surface of the first sidewall, the method for fabricating the flash memory device further includes: A fourth sidewall is formed, which covers the side surfaces of the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer at the bottom of the slope and a portion of the substrate surface.

9. The method of claim 8, wherein the method further comprises: The fourth sidewall includes: a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The first silicon oxide layer covers the side surfaces of the control gate layer, the ONO layer, the floating gate layer, and the pad oxide layer at the bottom of the slope and a portion of the substrate surface. The silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers a portion of the surface of the silicon nitride layer near the bottom of the substrate.

10. A flash memory device, comprising: include: A substrate having a pad oxide layer, a floating gate layer, an ONO layer, a control gate layer, a first sidewall, a second sidewall, a third sidewall, and word line polysilicon formed thereon, wherein the pad oxide layer, the floating gate layer, the ONO layer, the control gate layer, and the hard mask layer are sequentially formed on the substrate, and a plurality of spaced first trenches are formed in the hard mask layer, the control gate layer, the ONO layer, and the floating gate layer, and the first sidewall, the second sidewall, and the third sidewall are sequentially formed on the sidewalls of the first trenches, and the remaining space of the first trenches is filled with word line polysilicon; The second trench and the first trench are arranged alternately in the hard mask layer, the control gate layer, the ONO layer, the floating gate layer and the pad oxide layer; A first protective layer covers the word line polysilicon, wherein a slope is formed on the top surface of the first sidewall at the end of the first protective layer.

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