Semiconductor device and method of manufacturing semiconductor device

Abstract

This application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device includes: a gate structure comprising alternately stacked conductive and insulating layers; a single-crystal channel layer; and a source layer. The single-crystal channel layer includes a through-hole portion and an extended portion, the through-hole portion extending through the gate structure, the extended portion protruding from the gate structure, and at the junction of the through-hole portion and the extended portion, the extended portion having a width greater than that of the through-hole portion. The source layer is located above the gate structure and surrounds the extended portion.

Description

Technical Field

[0001] Embodiments of this disclosure relate to electronic devices, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration density of semiconductor devices with memory cells formed on a single layer on a substrate have approached their limits, three-dimensional semiconductor devices with memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of these semiconductor devices. Summary of the Invention

[0003] The embodiments of this disclosure are intended to provide a semiconductor device with a highly stable structure and improved reliability.

[0004] In one embodiment, a semiconductor device may include: a gate structure comprising alternating conductive and insulating layers; a single-crystal channel layer; and a source layer. The single-crystal channel layer includes a through-hole portion extending through the gate structure and an enlarged portion protruding from the gate structure, wherein at the junction of the through-hole portion and the enlarged portion, the enlarged portion has a width greater than that of the through-hole portion. The source layer is located above the gate structure and surrounds the enlarged portion.

[0005] In one embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a first opening in a substrate; forming a stack on the substrate; forming a second opening extending through the stack and connected to the first opening; forming a single-crystal channel layer in the first and second openings; etching the substrate; and forming a source layer by doping the etched substrate with impurities.

[0006] In one embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a first wafer including a substrate, a stack formed on the substrate, and a single-crystal channel layer extending through the stack into the substrate; forming a second wafer including peripheral circuitry; bonding the first wafer and the second wafer to each other; etching the substrate; and forming a source layer by doping the etched substrate with impurities. Attached Figure Description

[0007] Figure 1A and Figure 1B This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figures 3A to 3HThis is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4A and Figure 4B This is a diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0011] Figures 5A to 5D This is a diagram illustrating a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0012] Figure 6 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0014] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The drawings are schematic diagrams of various embodiments and intermediate structures. Therefore, due to factors such as manufacturing techniques and / or tolerances, variations from the illustrated configurations and shapes are expected. Consequently, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configuration and shape without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0015] Embodiments of this disclosure are described herein with reference to cross-sectional and / or plan views of the embodiments. However, the embodiments of this disclosure should not be construed as limiting the inventive concept. Although some embodiments of this disclosure will be shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and scope of this disclosure.

[0016] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element described below may also be referred to as the second element or the third element without departing from the principles and scope of this disclosure.

[0017] It will also be understood that when a component is referred to as being "connected to" or "attached to" another component, it may be directly on the other component, connected to or attached to the other component, or there may be one or more intermediate components. Furthermore, connection / attachment may not be limited to physical connections, but may also include non-physical connections, such as wireless connections.

[0018] Additionally, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements.

[0019] When the first element is referred to as being "above" the second element, it refers not only to the case where the first element is directly formed on the second element, but also to the case where a third element exists between the first and second elements. When the first element is referred to as being "on" the second element, it refers to the case where the first element is formed directly or indirectly on the second element or substrate.

[0020] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, or may have one or more layers on, above, and / or below it.

[0021] It should be understood that the accompanying drawings are simplified schematic diagrams of the described apparatus and may not include well-known details to avoid obscuring the features of the implementation.

[0022] It should also be noted that, without departing from the scope of this disclosure, a feature present in one embodiment may be used in conjunction with one or more features in another embodiment.

[0023] It should also be noted that in various accompanying drawings, similar reference numerals refer to similar elements.

[0024] The embodiments of this disclosure provide a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0025] The embodiments disclosed herein improve the integration density of semiconductor devices through three-dimensional stacked memory cells as described herein. These embodiments provide a semiconductor device with a stable structure and improved reliability.

[0026] Hereinafter, embodiments based on the technical concept of this disclosure will be described with reference to the accompanying drawings.

[0027] Figure 1A and Figure 1B This is a cross-sectional view showing the structure of a semiconductor device according to an embodiment.

[0028] Reference Figure 1AThe semiconductor device may include a gate structure GST, a single-crystal channel layer 13, a source layer 15, and a memory layer 14. The gate structure GST may include alternately stacked conductive layers 11 and insulating layers 12. The conductive layers 11 may be gate lines such as source select lines, word lines, or drain select lines. Each conductive layer 11 may comprise a conductive material such as polysilicon, tungsten, or molybdenum. The insulating layers 12 may be used to insulate the stacked conductive layers 11 from each other. Each insulating layer 12 may comprise oxides, nitrides, air gaps, etc.

[0029] A single-crystal channel layer 13 extends through the gate structure GST into the source layer 15. The single-crystal channel layer 13 may include a through-hole portion 13A and an extended portion 13B connected to the through-hole portion 13A. The through-hole portion 13A may extend through the gate structure GST and may have a tapered cross-section (or an arcuate shape with a width greater than the widths at the top and bottom). At the junction of the through-hole portion 13A and the extended portion 13B, the extended portion 13B may have a width greater than that of the through-hole portion 13A. The extended portion 13B may protrude from the upper surface of the gate structure GST. The extended portion 13B may contact the upper surface of the gate structure GST and may include a curved surface protruding from the upper surface of the gate structure GST. As an example, the extended portion 13B may have a hemispherical shape (or a semi-elliptical shape) and may have a uniform single-crystal structure.

[0030] The through-hole portion 13A and the extended portion 13B may have substantially the same doping concentration or different doping concentrations. As an example, the doping concentration of the extended portion 13B may be greater than that of the through-hole portion 13A. In this case, the through-hole portion 13A may be implemented as a channel layer, and the extended portion 13B may be implemented as a source layer.

[0031] The memory layer 14 may include at least one of a barrier layer 14A, a data storage layer 14B, and a tunneling layer 14C. The memory layer 14 may partially surround the single-crystal channel layer 13 (e.g., surround a portion of the single-crystal channel layer 13). As an example, the memory layer 14 may surround the sidewall of the penetration portion 13A of the single-crystal channel layer 13, but may not surround the extended portion 13B of the single-crystal channel layer 13.

[0032] Source-select transistors, memory cells, or drain-select transistors may be located in the region where the single-crystal channel layer 13 and the conductive layer 11 intersect. At least one drain-select transistor, a plurality of memory cells, and at least one source-select transistor stacked sequentially can constitute a memory string and may share the single-crystal channel layer 13. As an example, the source-select transistors, memory cells, and drain-select transistors may use a single-crystal silicon layer as the channel layer. By forming a single-crystal channel layer 13 instead of a polycrystalline channel layer, the disclosed embodiments can improve cell current.

[0033] The source layer 15 may be located on the gate structure GST and may surround the enlargement portion 13B. The source layer 15 may fill the spaces between adjacent enlargements 13B. As an example, the source layer 15 may be a substrate doped with impurities.

[0034] Reference Figure 1A (c) The upper surface of the source layer 15 may be located at substantially the same height as the upper surface of the single-crystal channel layer 13. However, the height of the source layer 15 is not limited to this. See [reference] Figure 1A In (a), the upper surface of the source layer 15 may be located at a height higher than the upper surface of the single-crystal channel layer 13. The entire surface of the enlarged portion 13B may be surrounded by the source layer 15. (See reference...) Figure 1A (b) The single-crystal channel layer 13 may have a flat upper surface F. The upper surface of the source layer 15 and the flat upper surface of the single-crystal channel layer 13 may be located at substantially the same height.

[0035] Reference Figure 1B The semiconductor device may include a gate structure GST, a single-crystal channel layer 13, a polycrystalline channel layer 16, and a source layer 15. The semiconductor device may also include a memory layer 14 and an insulating core 17. The gate structure GST may include alternately stacked conductive layers 11 and insulating layers 12. The single-crystal channel layer 13 may extend through the gate structure GST into the source layer 15. The source layer 15 may be located on the gate structure GST and may surround the enlarged portion 13B.

[0036] The single-crystal channel layer 13 may include a through-hole portion 13A extending through the gate structure GST and an extended portion 13B protruding into the source layer 15. A polycrystalline channel layer 16 may extend through the gate structure GST and may be connected to the single-crystal channel layer 13. The polycrystalline channel layer 16 and the through-hole portion 13A may be connected to each other. A memory layer 14 may surround the through-hole portion 13A of the single-crystal channel layer 13 and the polycrystalline channel layer 16. An insulating core 17 may be located in the polycrystalline channel layer 16. As an example, the polycrystalline channel layer 16 may surround the sidewall of the insulating core 17, and the insulating core 17 and the single-crystal channel layer 13 may be in contact with each other. Alternatively, the polycrystalline channel layer 16 may be located between the single-crystal channel layer 13 and the insulating core 17, and may have (e.g., as...) Figure 1B As shown, the cross-section is an inverted U-shape. The polycrystalline channel layer 16 may include polycrystalline silicon, and the insulating core 17 may include oxides, nitrides, air gaps, etc.

[0037] At least one drain-select transistor, a plurality of memory cells, and at least one source-select transistor may be stacked along interconnected polycrystalline channel layers 16 and monocrystalline channel layers 13. At least one drain-select transistor, a plurality of memory cells, and at least one source-select transistor may constitute a memory string. Each of the at least one drain-select transistor, memory cell, and at least one source-select transistor included in a memory string may include a monocrystalline channel layer 13 or a polycrystalline channel layer 16. According to one embodiment, the source-select transistor may include a monocrystalline channel layer 13, and the plurality of memory cells and the drain-select transistor may include a polycrystalline channel layer 16. According to another embodiment, the source-select transistor and at least one memory cell (among the plurality of memory cells) adjacent to the source-select transistor may include a monocrystalline channel layer 13, and the remaining memory cells (among the plurality of memory cells) and the drain-select transistor may include a polycrystalline channel layer 16. Based on the structure of this embodiment, the transistors included in a memory string may include different types of channel layers. Cell current can be improved by including a source selection transistor with a single-crystal channel layer 13, and cell distribution can be improved by including a memory cell with a polycrystalline channel layer 16 and a drain selection transistor.

[0038] According to the above structure, at least one of the source selection transistor, memory cell, and drain selection transistor may include a single-crystal channel layer 13. Therefore, the cell current of the semiconductor device can be improved, and the memory window can be ensured.

[0039] Figure 2 This is a diagram illustrating the structure of a semiconductor device according to an embodiment. In the following text, content repeated from the previous description may be omitted.

[0040] Reference Figure 2 The semiconductor device may include a first semiconductor structure S1, a second semiconductor structure S2, and a bonding structure BS. In some embodiments, the first semiconductor structure S1 may include a memory cell array CA, and the second semiconductor structure S2 may include peripheral circuitry PC.

[0041] The first semiconductor structure S1 may include a gate structure GST, a channel structure CH, a source layer 29, a second interlayer insulating layer IL2, a second interconnect structure IC2, a third interlayer insulating layer IL3, and a third interconnect structure IC3. The gate structure GST may include an alternately stacked conductive layer 23 and an insulating layer 24.

[0042] The source layer 29 may be located above the gate structure GST, and the second interlayer insulating layer IL2 may be located below the gate structure GST. The third interlayer insulating layer IL3 may be located above the source layer 29. The second interconnect structure IC2 may be located in the second interlayer insulating layer IL2. The second interconnect structure IC2 may include bit lines that can be connected to the polysilicon channel layer 27. The third interconnect structure IC3 may be located in the third interlayer insulating layer IL3 and may be electrically connected to the source layer 29.

[0043] The channel structure CH may be connected between the source layer 29 and the bit line. The channel structure CH may include a single-crystal channel layer 26, or a single-crystal channel layer 26 and a polycrystalline channel layer 27. The channel structure CH may also include at least one of an insulating core 28 and a memory layer 25. The memory layer 25 may include at least one of a barrier layer 25A, a data storage layer 25B, and a tunneling layer 25C.

[0044] The second semiconductor structure S2 may include a substrate 20, a transistor TR, a first interlayer insulating layer IL1, and a first interconnect structure IC1. The transistor TR may be part of a peripheral circuit PC (e.g., included in the peripheral circuit PC). As an example, the peripheral circuit PC may include a page buffer, a line decoder, logic circuits, input and output (input / output) circuits, etc. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1 and may be electrically connected to the peripheral circuit PC.

[0045] The bonding structure BS may be located between the first semiconductor structure S1 and the second semiconductor structure S2, and may bond the first semiconductor structure S1 and the second semiconductor structure S2 to each other. The bonding structure BS may include a first bonding layer BL1, a second bonding layer BL2, a first bonding pad BP1, and a second bonding pad BP2.

[0046] The peripheral circuit PC and the memory cell array CA can be physically bonded to each other through a first bonding layer BL1 and a second bonding layer BL2. The first bonding layer BL1 and the second bonding layer BL2 can each include silicon carbonitride (SiCN), tetraethyl orthosilicate (TEOS), etc. The first bonding pad BP1 and the second bonding pad BP2 can be electrically connected to each other at the interface between the first bonding layer BL1 and the second bonding layer BL2. The first bonding pad BP1 can be electrically connected to the memory cell array CA through a second interconnect structure IC2. The second bonding pad BP2 can be electrically connected to the peripheral circuit PC through the first interconnect structure IC1. Therefore, the peripheral circuit PC and the memory cell array CA can be electrically connected to each other through the first bonding pad BP1 and the second bonding pad BP2.

[0047] According to the above structure, the first semiconductor structure S1 and the second semiconductor structure S2, formed using separate manufacturing processes, can be electrically connected to each other via a bonding structure BS. The first semiconductor structure S1 may include a memory cell array CA, and each memory string of the memory cell array CA may include a single-crystal channel layer 26 or include a single-crystal channel layer 26 and a polycrystalline channel layer 27.

[0048] Figures 3A to 3H This is a diagram illustrating a method of manufacturing a semiconductor device according to embodiments of the present disclosure. In the following text, content repeated from the previous description may be omitted.

[0049] Reference Figure 3A and Figure 3B A first opening OP1 can be formed in the substrate 30. First, refer to... Figure 3A An initial opening OP can be formed in the substrate 30. The initial opening OP can be formed using a shallow trench isolation (STI) process that forms device isolation trenches. As an example, multiple initial opening OPs can be formed arranged in a first direction I and a second direction II intersecting the first direction I. Considering the expected width to be expanded in subsequent processes, the initial opening OPs can be arranged at sufficient intervals. Subsequently, referring to… Figure 3B The first opening OP1 can be formed by enlarging the initial opening OP. As an example, the substrate 30 can be etched using an isotropic etching process (e.g., a wet etching process). Through this etching process, the initial opening OP can be enlarged into a hemispherical or oval (or other semi-elliptical cross-section) shape.

[0050] Reference Figure 3C A curing process can be performed. The curing process can be a process that treats the surface of the substrate 30 exposed through the first opening OP1. As an example, the curing process may include at least one of a cleaning process, an injection process, and an annealing process. Alternatively, in an additional embodiment, the curing process can be performed on the surface of the substrate 30 exposed through the opening OP without enlarging the opening OP.

[0051] Initially, in the cleaning process, chemicals, etching byproducts, etc., present on the inner surface of the first opening OP1 can be removed. Deionized water can be used to perform the cleaning process. NH3, H2O2, citric acid, etc., can be added to the deionized water.

[0052] The doping concentration of the single-crystal channel layer can then be adjusted by performing an implantation process. As an example, P-type impurities such as boron (B), aluminum (Al), and gallium (Ga) can be doped, or N-type impurities such as phosphorus (P), arsenic (As), and antimony (Sb) can be doped. The doping concentration of the impurities can be determined by considering the threshold voltage of the source-select transistor.

[0053] Subsequently, an annealing process can be performed. Dopant impurities can be activated by the annealing process. In addition, damage present on the surface of substrate 30 can be cured and a protective layer 31 can be formed. The protective layer 31 can be used to protect the surface of substrate 30 from the chemicals used to deposit etch stop layer 32 or deposition byproducts in subsequent processes. As an example, the protective layer 31 can be an oxide layer.

[0054] By performing the curing process as described above, the embodiment provides the ability to remove chemicals, byproducts, etc. from the surface of the substrate 30. When the first opening OP1 has a hemispherical shape, the surface of the substrate 30 includes a curved surface, thus chemicals, byproducts, etc. can be effectively removed during the curing process.

[0055] Subsequently, an etch stop layer 32 may be formed in the first opening OP1. The etch stop layer 32 may include a material layer relative to that formed in subsequent processes (e.g., in...). Figure 3D The first material layer 33 and the second material layer 34 formed in the process are materials with high etch selectivity. As an example, the etch stop layer 32 may include carbon.

[0056] Reference Figure 3D A stack ST can be formed on substrate 30. The stack ST may include alternating layers of first material 33 and second material 34. In the illustrated example of the stack ST, a second material layer 34 is formed on substrate 30, and then a first material layer 33 is formed on this second material layer 34. Each of the first material layers 33 may include a material with high etch selectivity relative to the second material layer 34. The first material layer 33 is used to form gate lines and may each include a sacrificial material such as a nitride or a conductive material such as polysilicon or metal. The second material layer 34 is used to insulate the stacked gate lines from each other and may each include an insulating material such as an oxide or nitride.

[0057] Subsequently, a second opening OP2 can be formed in the laminate ST. As an example, the second opening OP2 extending through the laminate ST can be formed by etching the laminate ST using an etch stop layer 32. The etch stop layer 32 can be exposed through the second opening OP2. A plurality of first openings OP1 and a plurality of second openings OP2 can be connected to each other respectively. The second opening OP2 can have a tapered or arcuate cross-section. At the portion where the first openings OP1 and second openings OP2 connect to each other, the second opening OP2 can have a width smaller than that of the first opening OP1.

[0058] Subsequently, a memory layer 35 can be formed in the second opening OP2. The memory layer 35 can be conformally formed along the inner surface of the second opening OP2. As an example, a barrier layer 35A can be formed along the surface of the laminate ST and the surface of the etch stop layer 32, a data storage layer 35B can be formed on the barrier layer 35A, and a tunneling layer 35C can be formed on the data storage layer 35B. The data storage layer 35B may include a floating gate, polysilicon, charge trapping material, nitride, variable resistance material, etc.

[0059] Reference Figure 3E The etch stop layer 32 can be exposed by etching the memory layer 35. The portion of the memory layer 35 formed on the surface of the etch stop layer 32 can be etched, and the memory layer 35 can remain on the inner wall of the second opening OP2.

[0060] Subsequently, the etch stop layer 32 can be removed. As an example, the etch stop layer 32 can be selectively etched, thereby exposing the protective layer 31. The protective layer 31 can then be removed. As an example, the substrate 30 can be exposed by etching the protective layer 31. After the protective layer 31 is removed, unwanted materials present on the surface of the substrate 30 can be removed by performing a cleaning process. Additionally, the substrate 30 can be surface-treated. As an example, oxygen atoms present on the surface of the substrate 30 can be removed by surface treatment of the substrate 30 using methods such as plasma activation or liquid activation.

[0061] Reference Figure 3F A single-crystal channel layer 36 can be formed in the first opening OP1 and the second opening OP2. As an example, the single-crystal channel layer 36 can be formed by growing single-crystal silicon from the substrate 30 using an epitaxial growth method. The single-crystal channel layer 36 may include an enlarged portion 36B in the first opening OP1 and a penetrating portion 36A in the second opening OP2. The enlarged portion 36B can be grown using the substrate 30 as a seed. Because the first opening OP1 has a hemispherical shape, the enlarged portion 36B can be grown in a uniform single-crystal structure. Additionally, the penetrating portion 36A can be grown using the enlarged portion 36B as a seed.

[0062] The enlarged portion 36B may have a shape that transitions from the first opening OP1 (which may be hemispherical). The penetrating portion 36A may have a shape that transitions from the second opening OP2 (which may be pillar-shaped). According to an alternative embodiment, when the initial opening OP is not enlarged, monocrystalline silicon may be grown from the substrate 30 exposed through the opening OP, and the enlarged portion may have a shape that transitions from the opening OP.

[0063] Because monocrystalline silicon is grown with the surface of the substrate 30 optimized through processes such as curing, cleaning, and surface treatment, it can grow uniformly from the substrate 30. Furthermore, monocrystalline silicon can be grown without voids in the first opening OP1 and the second opening OP2.

[0064] Subsequently, the first material layer 33 can be replaced with a third material layer 39. As an example, a slit extending through the stack ST can be formed, through which the first material layer 33 can be removed. The third material layer 39 can then be formed in the region where the first material layer 33 has been removed. The third material layer 39 can be used to form gate lines and can each comprise a metal such as tungsten or molybdenum. Thus, a gate structure GST comprising alternately stacked second material layers 34 and third material layers 39 can be formed.

[0065] According to alternative embodiments, when each of the first material layers 33 comprises a conductive material, the process of replacing the first material layer 33 with a third material layer 39 can be omitted. In these cases, the first material layer 33 can be used as a gate line, and the stack ST can be used as a gate structure GST.

[0066] Reference Figure 3G The substrate 30 can be etched. As an example, the substrate 30 can be etched after the wafer is flipped so that the substrate 30 is above the gate structure GST. The substrate 30 can be polished using a planarization process, and a chemical mechanical polishing (CMP) method can be used in the planarization process.

[0067] The height of the etched upper surface of the substrate 30 can be adjusted according to the degree of polishing of the substrate 30. (Refer to...) Figure 3G (c) The upper surface of the etched substrate 30 and the top of the single-crystal channel layer 36 may be at substantially the same height. However, this disclosure is not limited thereto, and the planarization height of the substrate 30 may be adjusted differently. (See also...) Figure 3G (a) The upper surface of the substrate 30 may be located at a height higher than the top of the single-crystal channel layer 36. On the upper surface of the single-crystal channel layer 36, the substrate 30 may have a third thickness T3. (Refer to...) Figure 3G (b) The single-crystal channel layer 36 can be etched together with the substrate 30 during the etching process. The enlarged portion 36B can be partially etched, and the single-crystal channel layer 36 can have a flat upper surface F. The flat upper surface of the single-crystal channel layer 36 can be exposed through the upper surface of the substrate 30.

[0068] Reference Figure 3H A buffer layer 37 can be formed on the substrate 30. As an example, the buffer layer 37 can be formed by oxidizing the surface of the substrate 30 using an oxidation process. The buffer layer 37 can be an oxide layer.

[0069] Subsequently, the source layer 30A can be formed by doping the substrate 30 with impurities via the buffer layer 37. As an example, the substrate 30 can be doped with N-type or P-type impurities. Because the impurities are doped via the buffer layer 37, the embodiments disclosed herein prevent or reduce damage to the surface of the substrate 30 during the impurity doping process. Alternatively, in the impurity doping process, the enlarged portion 36B and the substrate 30 can be doped with impurities. The impurity-doped enlarged portion 36B can be used as the source layer.

[0070] Subsequently, the doped impurities can be activated by performing an annealing process. Then, the buffer layer 37 can be removed. As an example, the source layer 30A can be exposed by selectively etching the buffer layer 37. Because the buffer layer 37 may be damaged during the aforementioned impurity doping process, an interlayer insulating layer can be formed after removing the damaged buffer layer 37.

[0071] According to the above method, before forming the laminate ST, openings OP and / or the first opening OP1 can be formed, and a curing process can be performed. Therefore, the surface of substrate 30 can be optimized for growing single-crystal silicon, and the optimized surface can be protected by the etch stop layer 32. Because the single-crystal channel layer 36 is formed from the optimized surface of substrate 30, the single-crystal channel layer 36 can be formed without voids. Furthermore, because the source layer 30A is formed by doping the remaining substrate 30 with impurities, it is not necessary to completely remove substrate 30, and it is not necessary to deposit an additional conductive layer to form the source layer 30A.

[0072] Figure 4A and Figure 4B This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. In the following text, content repeated from the previous description may be omitted.

[0073] Reference Figure 4A A first opening OP1 can be formed in the substrate 40, and a stack ST can be formed on the substrate 40. The stack ST may include alternating layers of first material 43 and second material 44. In the illustrated example of the stack ST, a second material layer 44 is formed on the substrate 40, and then a first material layer 43 is formed on this second material layer 44. Subsequently, a second opening OP2 extending through the stack ST and connected to the first opening OP1 can be formed. Subsequently, a memory layer 45 can be formed on the inner wall of the second opening OP2. The memory layer 45 may include at least one of a barrier layer 45A, a data storage layer 45B, and a tunneling layer 45C.

[0074] Subsequently, a monocrystalline channel layer 46 can be formed in the first opening OP1 and the second opening OP2. The monocrystalline channel layer 46 can completely fill the first opening OP1 and partially fill the second opening OP2. As an example, the monocrystalline channel layer 46 that only partially fills the second opening OP2 can be formed by adjusting the growth time of the monocrystalline silicon. The monocrystalline channel layer 46 may include an enlarged portion 46B, or may include an enlarged portion 46B and a through portion 46A.

[0075] Subsequently, a polycrystalline layer 47 can be formed in the second opening OP2. The polycrystalline layer 47 can be conformally formed along the inner surface of the second opening OP2. As an example, the polycrystalline layer 47 can be deposited along the surface of the memory layer 45 and the surface of the single-crystal channel layer 46. The polycrystalline layer 47 can have a U-shaped cross-section. As an example, the polycrystalline layer 47 can be formed by forming a polycrystalline silicon layer in the second opening OP2 and performing an annealing process. The polycrystalline layer 47 can be a polycrystalline silicon layer with a first thickness T1.

[0076] Reference Figure 4B A polycrystalline channel layer 47A can be formed by etching the polycrystalline layer 47. Subsequently, an insulating core 48 can be formed in the polycrystalline channel layer 47A. The polycrystalline channel layer 47A may have a second thickness T2 less than the first thickness T1. By reducing the thickness of the polycrystalline channel layer 47A to the second thickness T2, the embodiments disclosed herein can improve the cell current. In the process of etching the polycrystalline layer 47, the portion of the polycrystalline layer 47 formed on the surface of the single-crystal channel layer 46 can be completely removed, and the polycrystalline channel layer 47A can be formed in a spacer shape on the inner wall of the second opening OP2. In the process of etching the polycrystalline layer 47, the portion of the polycrystalline layer 47 formed on the surface of the single-crystal channel layer 46 can be partially removed, and a polycrystalline channel layer 47A with a U-shaped cross-section can be formed.

[0077] Subsequently, despite Figure 4B The substrate 40, which is not shown in the figure, can be etched, and the source layer can be formed by doping the remaining substrate 40 with impurities.

[0078] According to the above method, a monocrystalline channel layer 46 and a polycrystalline channel layer 47A can be formed in the second opening OP2. Since the polycrystalline channel layer 47A is formed after the lower part of the second opening OP2 is filled with the monocrystalline channel layer 46, the aspect ratio of the second opening OP2 with the polycrystalline channel layer 47A can be reduced, and the difficulty of the etching process for reducing the thickness of the polycrystalline channel layer 47A can be reduced.

[0079] Figures 5A to 5D This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment. In the following text, content repeated from the preceding description may be omitted.

[0080] Reference Figure 5AA first wafer W1 comprising a memory cell array CA can be formed. The first wafer W1 may include a substrate 50, a gate structure GST, a channel structure CH, an interlayer insulating layer 59, an interconnect structure 60, a bonding layer 61, and bonding pads 62. The gate structure GST may include alternately stacked conductive layers 53 and insulating layers 54. In the illustrated example of the gate structure GST, an insulating layer 54 is located on the substrate 50, and a conductive layer 53 is located on this insulating layer 54.

[0081] The channel structure CH may include a single-crystal channel layer 56, or may include a single-crystal channel layer 56 and a polycrystalline channel layer 57. The single-crystal channel layer 56 may be a single-crystal silicon layer grown from the substrate 50 by an epitaxial method. The single-crystal channel layer 56 may include a through-hole portion extending through the gate structure GST and an enlarged portion located in the substrate 50. The channel structure CH may also include at least one of an insulating core 58 and a memory layer 55. The memory layer 55 may include at least one of a barrier layer 55A, a data storage layer 55B, and a tunneling layer 55C.

[0082] Reference Figure 5B A second wafer W2, including peripheral circuitry PC, can be formed. The second wafer W2 may include a substrate 70, a device isolation layer 4, a transistor TR, an interlayer insulating layer 71, an interconnect structure 72, a bonding layer 73, and bonding pads 74. The device isolation layer 4 may be located in the substrate 70 and may define an active region. The transistor TR may be located in the active region of the substrate 70 and may include a gate insulating layer 1, a gate electrode 2, and a junction 3.

[0083] Reference Figure 5C The first wafer W1 and the second wafer W2 can be bonded to each other. The first wafer W1 can be flipped so that the substrate 50 is located on the gate structure GST and bonded to the second wafer W2. The bonding layer 61 of the first wafer W1 and the bonding layer 73 of the second wafer W2 can be bonded to each other. The bonding pads 62 of the first wafer W1 and the bonding pads 74 of the second wafer W2 can be electrically connected to each other.

[0084] Subsequently, the substrate 50 can be etched, and the source layer 50A can be formed by doping the etched substrate 50 with impurities. When the substrate 50 is etched, the single-crystal channel layer 56 can be partially etched. When the substrate 50 is doped with impurities, the extended portion of the single-crystal channel layer 56 can also be doped with impurities.

[0085] Reference Figure 5DAn interconnect structure 76, an interlayer insulating layer 75, and a passivation layer 77 can be formed on the source layer 50A. The interconnect structure 76 may be located in the interlayer insulating layer 75 and / or the passivation layer 77, and may be electrically connected to the source layer 50A, etc. Thus, a semiconductor device can be manufactured, comprising: a first semiconductor structure S1 including a memory cell array CA, a second semiconductor structure S2 including peripheral circuitry PC, and a bonding structure BS connecting the first semiconductor structure S1 and the second semiconductor structure S2 to each other.

[0086] According to the above method, the first wafer W1 and the second wafer W2 can be formed separately and then bonded together. After the first wafer W1 and the second wafer W2 are bonded together, the source layer 50A can be formed by doping the substrate 50 with impurities. Therefore, the source layer 50A can be formed using the substrate 50 without removing the substrate 50 or depositing an additional conductive layer.

[0087] The structure and manufacturing method according to the above embodiments can be applied to semiconductor devices with various structures. Figure 6 and Figure 7 A schematic configuration of a semiconductor device to which the above embodiments are applicable is shown.

[0088] Figure 6 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0089] Reference Figure 6 The semiconductor device may include a substrate SUB, peripheral circuitry PC, and memory cell array CA. In some embodiments, the peripheral circuitry PC and memory cell array CA may be formed on the same substrate.

[0090] The substrate SUB may be made of or comprise a semiconductor material. In embodiments, the semiconductor material may include at least one of group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors. Group IV semiconductors may include single-crystal silicon (Si), polycrystalline silicon, germanium (Ge), or silicon-germanium-SiGe. Group III-V compound semiconductors may include gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), indium gallium arsenide phosphide (GaInAsP), aluminum arsenide (AlAs), aluminum gallium (AlGa), indium phosphide (InP), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI compound semiconductors may include zinc sulfide (ZnS), zinc oxide (ZnO), or cadmium sulfide (CdS).

[0091] The substrate SUB may include a dielectric layer. The substrate SUB may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, or a glass substrate. The substrate SUB may include organic materials. In one embodiment, the substrate SUB may include graphene.

[0092] The substrate SUB can be a bulk wafer or an epitaxial layer grown using a selective epitaxial growth (SEG) method. The substrate SUB can be a layer formed using a metal-induced lateral crystallization (MILC) method and may partially comprise a metal. The substrate SUB can be monocrystalline, polycrystalline, or amorphous. The substrate SUB may include group II, III, IV, V, or VI impurities. In an embodiment, the substrate SUB may include an n-well region doped with n-type impurities and / or a p-well region doped with p-type impurities.

[0093] The peripheral circuitry PC can be disposed between the substrate SUB and the memory cell array CA. The peripheral circuitry PC may include row decoders, column decoders, page buffers, logic circuits, control circuits, sense amplifiers, input / output circuits, etc. In some embodiments, the peripheral circuitry PC may include NMOS transistors, PMOS transistors, resistors, capacitors, etc. The peripheral circuitry PC may also include interconnect structures. These interconnect structures can serve as paths for transmitting operating voltages and may include contact plugs, wires, etc.

[0094] A memory cell array (CA) may include memory cells. In one embodiment, the memory cell array (CA) may include memory strings connected between source lines and bit lines, each memory string comprising stacked memory cells. In another embodiment, the memory cell array (CA) may include memory cells connected between word lines and bit lines. The memory cell array (CA) may also include interconnect structures.

[0095] Figure 7 This is a configuration diagram of a semiconductor device according to an embodiment of the present disclosure.

[0096] Reference Figure 7 The semiconductor device may include a substrate SUB, peripheral circuitry PC, bonding structure BS, and memory cell array CA. In some embodiments, the peripheral circuitry PC and memory cell array CA may be formed on separate substrates and then bonded. The semiconductor device may also include a support base SP_B.

[0097] The substrate SUB can be used as a support in the process of forming the peripheral circuit PC. The support base SP_B can be used as a support in the process of forming the memory cell array CA. In an embodiment, after fabricating a first wafer including the memory cell array CA and a second wafer including the peripheral circuit PC, the first wafer and the second wafer can be electrically connected via a bonding structure BS. After bonding, at least a portion of the support base SP_B of the first wafer can be removed. The support base SP_B can be completely removed or can be partially retained on the memory cell array CA.

[0098] The support substrate SP_B can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The support substrate SP_B can be a bulk wafer, an epitaxial layer grown using selective epitaxial growth (SEG), or a layer formed using metal-induced lateral crystallization (MILC). The support substrate SP_B can be monocrystalline, polycrystalline, or amorphous. The support substrate SP_B can include group II, III, IV, V, or VI impurities.

[0099] The bonding structure BS can be used to connect the memory cell array CA and the peripheral circuit PC. In embodiments, the memory cell array CA and the peripheral circuit PC can be bonded according to wafer-to-wafer bonding methods, chip-to-wafer bonding methods, chip-to-chip bonding methods, etc. The bonding structure BS may include bonding pads, bonding layers, bonding interfaces, etc. The bonding pads may include metals and / or alloys such as copper and aluminum. The bonding interfaces may include non-metal-to-non-metal interfaces, metal-to-metal interfaces, etc. The memory cell array CA and the peripheral circuit PC can be electrically connected through the bonding structure BS.

[0100] In an alternative embodiment, the interconnect structures included in the memory cell array (CA) and / or the peripheral circuitry (PC) can be directly connected without bonding pads. In this embodiment, the bonding layers included in the memory cell array (CA) and the bonding layers included in the peripheral circuitry (PC) can be bonded to form a bonding interface, allowing the interconnect structures included in the memory cell array (CA) and the interconnect structures included in the peripheral circuitry (PC) to be directly connected. Thus, contact plugs, wires, etc., formed on different wafers can be electrically connected without separate bonding pads.

[0101] Other configurations of the semiconductor device can be referenced above. Figure 6 The descriptions are in the same or similar ways.

[0102] In addition, the semiconductor device may have the above reference. Figure 6 and Figure 7 The described implementation method is a combination of structures, or may have partially modified structures. (Refer to...) Figure 6 and Figure 7 In the described implementation, the positions of the memory cell array CA and the peripheral circuit PC can be changed. At least one memory cell array CA and / or at least one peripheral circuit PC can be additionally coupled to a reference. Figure 6 and Figure 7 The described implementation method. In this implementation method, a portion of the peripheral circuitry PC may be located in the memory cell array CA.

[0103] Although embodiments based on the technical concept of this disclosure have been described above with reference to the accompanying drawings, this is merely for illustrating embodiments according to the concept of this disclosure, and this disclosure is not limited to the above embodiments. Various substitutions, modifications, alterations, and combinations of various types can be made to the embodiments by those skilled in the art to which this disclosure pertains without departing from the technical concept of this disclosure as defined in the following claims, and such substitutions, modifications, alterations, and combinations should be interpreted as falling within the scope of this disclosure.

[0104] Cross-references to related applications

[0105] This application claims priority to Korean Patent Application No. 10-2025-0012211, filed on January 31, 2025, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; Single-crystal channel layer; as well as Source layer, The single-crystal channel layer includes: The penetrating portion extends through the gate structure, and An enlarged portion protrudes from the gate structure and has a width greater than that of the through portion at the junction of the through portion and the enlarged portion. The source layer is located above the gate structure and surrounds the enlarged portion.

2. The semiconductor device according to claim 1, wherein, The enlarged portion has a hemispherical shape.

3. The semiconductor device according to claim 1, wherein, The enlarged portion contacts the upper surface of the gate structure and includes a curved surface protruding from the upper surface of the gate structure.

4. The semiconductor device of claim 1, further comprising a memory layer surrounding the sidewalls of the penetrated portion.

5. The semiconductor device of claim 1, further comprising a polycrystalline channel layer extending through the gate structure and connected to the single-crystal channel layer.

6. The semiconductor device of claim 5, further comprising an insulating core located in the polycrystalline channel layer.

7. The semiconductor device of claim 5, further comprising a memory layer surrounding the penetration portion and the polycrystalline channel layer.

8. The semiconductor device according to claim 1, in, The gate structure, the single-crystal channel layer, and the source layer form a unit array, and The semiconductor device further includes: Peripheral circuits; A first bonding pad, electrically connected to the cell array; and A second bonding pad is bonded to the first bonding pad and electrically connected to the peripheral circuit.

9. A method for manufacturing a semiconductor device, the method comprising the following steps: A first opening is formed in the substrate; A laminate is formed on the substrate; A second opening is formed that extends through the laminate and connects to the first opening; A monocrystalline channel layer is formed in the first opening and the second opening; Etch the substrate; as well as The source layer is formed by doping the etched substrate with impurities.

10. The method according to claim 9, wherein, The first opening includes a portion at the junction of the first opening and the second opening that has a width greater than that of the second opening.

11. The method according to claim 9, wherein, The steps to form the first opening include the following: An initial opening is formed in the substrate; and The first opening is formed by enlarging the initial opening.

12. The method according to claim 9, further comprising the step of: A cleaning process is performed on the substrate having the first opening.

13. The method of claim 9, further comprising the step of: The substrate is doped with the impurities through the first opening.

14. The method of claim 9, further comprising the step of: A protective layer is formed in the first opening; and An etch stop layer is formed on the protective layer.

15. The method according to claim 14, wherein, The protective layer comprises an oxide, and the etch stop layer comprises carbon.

16. The method of claim 14, further comprising the step of: The etch stop layer is removed through the second opening; as well as Remove the protective layer.

17. The method of claim 9, further comprising the step of: A memory layer is formed on the inner wall of the second opening.

18. The method according to claim 9, wherein, The step of forming the single-crystal channel layer includes the following steps: growing single-crystal silicon from the substrate exposed through the first opening using an epitaxial growth method.

19. The method of claim 9, further comprising the step of: A polycrystalline channel layer is formed in the second opening, which is connected to the monocrystalline channel layer.

20. The method of claim 19, further comprising the step of: An insulating core is formed in the polycrystalline channel layer.

21. The method according to claim 9, further comprising the step of: A first wafer and a second wafer are bonded together, the first wafer including the substrate, the stack and the single-crystal channel layer, and the second wafer including peripheral circuitry.

22. The method of claim 9, further comprising the step of: A buffer layer is formed by oxidizing the substrate. The substrate being etched is doped with the impurities through the buffer layer.

23. A method for manufacturing a semiconductor device, the method comprising the following steps: A first wafer is formed, the first wafer including a substrate, a stack formed on the substrate, and a single-crystal channel layer extending through the stack into the substrate; Forming a second wafer including peripheral circuitry; The first wafer and the second wafer are joined together; Etch the substrate; as well as The source layer is formed by doping the etched substrate with impurities.

24. The method according to claim 23, wherein, The steps for forming the first wafer include the following: A first opening is formed in the substrate; The laminate is formed on the substrate; Forming a second opening that extends through the laminate and connects to the first opening; and The monocrystalline channel layer is formed in the first opening and the second opening.

25. The method according to claim 24, wherein, The step of forming the single-crystal channel layer includes the following steps: growing a single-crystal silicon layer from the substrate exposed through the first opening.

26. The method of claim 24, further comprising the step of: A polycrystalline channel layer is formed in the second opening, which is connected to the monocrystalline channel layer.

27. The method of claim 23, further comprising the step of: A buffer layer is formed by oxidizing the surface of the etched substrate. The substrate being etched is doped with the impurities through the buffer layer.

Images