Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate, semiconductor patterns stacked on the substrate in a first direction, word lines surrounding the semiconductor patterns, bit lines on a first side of each semiconductor pattern, and capacitor structures on a second side of each semiconductor pattern. Each semiconductor pattern includes a first source / drain region adjacent to the bit line, a second source / drain region adjacent to the capacitor structure, and a channel region between the first source / drain region and the second source / drain region. The first source / drain region includes a first portion extending from the channel region in a third direction and a second portion surrounding the first portion.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device. Background Technology

[0002] As used herein, a semiconductor device refers to a core component in an electronic device used to control or amplify electrical signals, and various types of semiconductor devices can be manufactured. For example, semiconductor memory devices are primarily used to store and retrieve data. Semiconductor memory devices are an important component of electronic devices such as computers, communication equipment, and consumer electronics.

[0003] With industrial development, the demands for the performance and functionality of electronic devices are increasing. Therefore, high performance of semiconductor memory devices is crucial, and the integration density of semiconductor memory devices is constantly improving to meet this demand. During this development, new transistor structures have been proposed, such as transistors with vertical channels and vertically stacked transistors.

[0004] The above information is provided only to facilitate understanding of the background of this disclosure and may include information that does not constitute prior art. Summary of the Invention

[0005] Technical problems to be solved

[0006] This disclosure relates to providing a semiconductor memory device with improved electrical characteristics and / or reliability.

[0007] Technical solution

[0008] According to an aspect of this disclosure, a semiconductor memory device includes: a substrate; a plurality of semiconductor patterns stacked on the substrate and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; a plurality of word lines, each surrounding one of the plurality of semiconductor patterns and extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a bit line on a first side of each of the plurality of semiconductor patterns and extending longitudinally in the first direction; and a capacitor structure on a second side of each of the plurality of semiconductor patterns, the second side being opposite to the first side in a third direction parallel to the upper surface of the substrate and intersecting the first and second directions, and each of the plurality of semiconductor patterns extending longitudinally in a third direction. Each of the plurality of semiconductor patterns includes a first source / drain region adjacent to the bit line, a second source / drain region adjacent to the capacitor structure, and a channel region between the first source / drain region and the second source / drain region. The first source / drain region, the channel region, and the second source / drain region are arranged along a third direction. The first source / drain region includes a first portion extending from the channel region in a third direction and a second portion surrounding the first portion.

[0009] According to an aspect of this disclosure, a semiconductor memory device includes: a substrate; a plurality of semiconductor patterns stacked on the substrate in a first direction perpendicular to an upper surface of the substrate; a plurality of word lines, each surrounding one of the semiconductor patterns and extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; a bit line on a first side of each of the plurality of semiconductor patterns and extending longitudinally in the first direction; and a capacitor structure on a second side of each of the plurality of semiconductor patterns, the second side being opposite to the first side in a third direction parallel to the upper surface of the substrate and intersecting the first and second directions, and each of the plurality of semiconductor patterns extending longitudinally in the third direction. Each of the plurality of semiconductor patterns includes a first source / drain region adjacent to the bit line, a second source / drain region adjacent to the capacitor structure, and a channel region between the first source / drain region and the second source / drain region. The material of the first source / drain region is different from the material of each of the channel region and the second source / drain region.

[0010] According to an aspect of this disclosure, a semiconductor memory device includes: a substrate; a plurality of semiconductor patterns stacked on the substrate in a first direction perpendicular to an upper surface of the substrate; a plurality of word lines, each surrounding the plurality of semiconductor patterns and extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; an interlayer insulating layer between two adjacent word lines of the plurality of word lines; a bit line on a first side of each of the plurality of semiconductor patterns and extending longitudinally in the first direction; a capacitor structure on a second side of each of the plurality of semiconductor patterns, the second side being opposite to the first side in a third direction parallel to the upper surface of the substrate and intersecting the first and second directions, wherein each of the plurality of semiconductor patterns includes: a first source / drain region adjacent to the bit line; a second source / drain region adjacent to the capacitor structure; and a channel region between the first source / drain region and the second source / drain region, wherein the first source / drain region extends from the channel region in a third direction; and a hole collection layer configured to collect holes in a corresponding semiconductor pattern of the plurality of semiconductor patterns and surrounding the first source / drain region. The hole collection layer is positioned between the bit line and the corresponding word line of the corresponding semiconductor pattern among multiple word lines. The band gap of the first source / drain region is larger than the band gap of the hole collection layer.

[0011] According to some embodiments of this disclosure, a method of manufacturing a semiconductor memory device may include: providing a preliminary stacked structure on a substrate, the preliminary stacked structure including a plurality of interlayer insulating layers and a plurality of molded sacrificial layers alternately stacked along a first direction; forming a trench by partially patterning the plurality of molded sacrificial layers along the first direction through the preliminary stacked structure and along a second direction intersecting the first direction; forming an interlayer sacrificial pattern inside the trench along the exposed side surfaces of the patterned molded sacrificial layers between the plurality of interlayer insulating layers; forming a semiconductor pattern between the formed interlayer sacrificial patterns; partially patterning the interlayer sacrificial patterns along the second direction; forming a gate insulating film on the inner wall of the trench defined by the lower and upper surfaces of each of the plurality of interlayer insulating layers and the side surfaces of the patterned interlayer sacrificial patterns; forming word lines on the gate insulating film; forming a first portion of a first source / drain region by partially removing the gate insulating film to expose a portion of the semiconductor pattern outward; and forming a second portion of the first source / drain region on the surface of the first portion, wherein the semiconductor pattern may include a channel region surrounded by word lines.

[0012] Beneficial effects

[0013] According to some embodiments of this disclosure, the band gap of the material included in the first source / drain region adjacent to the bit line is larger than the band gap of the material included in the channel region, such that the first source / drain region is configured to collect excess holes accumulated in the channel region. Therefore, the buoyancy effect can be improved.

[0014] The effects that can be obtained from this disclosure are not limited to those described above. Those skilled in the art will clearly understand, based on the following description of this disclosure, the technical effects not mentioned herein. Attached Figure Description

[0015] Figure 1 A cell array of semiconductor memory devices according to some embodiments of the present disclosure is shown.

[0016] Figure 2 This is a plan view illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0017] Figure 3 It shows Figure 2 Semiconductor memory devices along Figure 2 The cross-sectional view taken from line AA.

[0018] Figure 4 It shows Figure 2 Semiconductor memory devices along Figure 2 The cross-sectional view of line BB.

[0019] Figure 5 It shows Figure 2 Semiconductor memory devices along Figure 2The cross-sectional view taken from line CC.

[0020] Figure 6 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0021] Figure 7 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0022] Figure 8 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0023] Figure 9 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0024] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0025] Figure 11 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0026] Figure 12 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0027] Figure 13 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0028] Figure 14 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure.

[0029] Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0030] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings. Throughout this specification, the same reference numerals refer to the same components.

[0031] Figure 1 A cell array of semiconductor memory devices according to some embodiments of the present disclosure is shown.

[0032] refer to Figure 1Some embodiments of semiconductor memory devices may include a plurality of memory cells MC arranged along a first direction D1 and a third direction D3. Each memory cell MC may include a data storage element DS and a memory cell transistor arranged together along the third direction D3.

[0033] Multiple bit lines BL can be conductive patterns (e.g., conductive metal lines) extending longitudinally in a direction perpendicular to the upper surface of the substrate (e.g., a first direction D1). Multiple bit lines BL can be arranged along a third direction D3. Adjacent bit lines BL can be spaced apart in the third direction D3.

[0034] In some embodiments, some bit lines among the multiple bit lines BL can be interconnected via bit lines trapping lines (BLS). For example, the bit lines trapping lines (BLS) can be interconnected with some bit lines BL arranged along a third direction D3 among the multiple bit lines BL.

[0035] Multiple word lines WL can be conductive patterns (e.g., conductive metal lines) stacked on a substrate along a first direction D1. Each word line WL can extend longitudinally in a second direction D2. Adjacent word lines WL can be spaced apart in the first direction D1.

[0036] The data storage element DS can be connected together to a plate electrode PLAT extending in a first direction D1 and a second direction D2. In some embodiments, the plate electrode PLAT arranged along the second direction D2 can be integrally formed.

[0037] The data storage element DS and the storage cell transistor arranged along the third direction D3 can be arranged symmetrically about a plane extending in the first direction D1 and the second direction D2 on which the plate electrode PLAT is disposed.

[0038] The gate electrode of the memory cell transistor can be connected to the word line WL. The first source / drain of the memory cell transistor can be connected to the bit line BL. The second source / drain of the memory cell transistor can be connected to the data storage element DS. For example, the data storage element DS can be a capacitor structure. The second source / drain of the memory cell transistor can be connected to the storage electrode of the capacitor.

[0039] Figure 2 This is a plan view illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 3 It shows Figure 2 Semiconductor memory devices along Figure 2 The cross-sectional view taken from line AA. Figure 4 It shows Figure 2 Semiconductor memory devices along Figure 2 The cross-sectional view of line BB. Figure 5 It shows Figure 2 Semiconductor memory devices along Figure 2 The cross-sectional view taken from line CC.

[0040] refer to Figures 2 to 5 According to some embodiments of the present disclosure, a semiconductor memory device may include a substrate 100 and a plurality of semiconductor patterns SP, a plurality of word lines WL, bit lines BL and a capacitor structure CAP disposed on the substrate 100.

[0041] Substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Substrate 100 may include silicon (Si) or other materials, such as silicon-germanium, silicon-germanium-on-insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe), indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GA-As), or gallium antimonide (GaSb), but this disclosure is not limited thereto. For ease of description, substrate 100 is described below as comprising silicon. Furthermore, peripheral circuitry and wiring layers connected to said peripheral circuitry may be formed on certain regions of substrate 100.

[0042] In this disclosure, the direction perpendicular to the surface (e.g., the upper surface) of the substrate 100 may be referred to as the first direction D1. Additionally, the direction parallel to the surface (e.g., the upper surface) of the substrate 100 may be referred to as the second direction D2 or the third direction D3. The second direction D2 and the third direction D3 may intersect each other (e.g., be orthogonal).

[0043] Multiple semiconductor patterns SP can be spaced apart and stacked on substrate 100 along a first direction D1. Each of the multiple semiconductor patterns SP can have a strip shape with its long axis along a third direction D3. Each of the multiple semiconductor patterns SP may include a first source / drain region 152 adjacent to a bit line BL, a second source / drain region 154 adjacent to a capacitor structure CAP, and a channel region 140 disposed between the first source / drain region 152 and the second source / drain region 154. The first source / drain region 152 can be connected to the bit line BL, and the second source / drain region 154 can be connected to the capacitor structure CAP.

[0044] Semiconductor patterns SP may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, semiconductor patterns SP may include two-dimensional semiconductor materials (e.g., MoS2 or WSe2) in the channel.

[0045] The first source / drain region 152 and the second source / drain region 154 may have a first conductivity type (e.g., n-type). The channel region 140 may be undoped or may have a second conductivity type different from the first conductivity type (e.g., p-type). However, this disclosure is not limited thereto.

[0046] According to an embodiment, the first source / drain region 152 may include a first portion 152a extending longitudinally from the channel region 140 in a third direction D3 and a second portion 152b surrounding the first portion 152a. (See reference...) Figure 3 and Figure 5 The second portion 152b may surround the upper surface of the first portion 152a, the lower surface of the first portion 152a, and the two side surfaces of the first portion 152a facing in the second direction D2. For example, the second portion 152b may surround the side surfaces of the first portion 152a.

[0047] According to an embodiment, the first portion 152a may include a first material, and the second portion 152b may include a second material. The band gap of the first material included in the first portion 152a may be larger than the band gap of the second material included in the second portion 152b. For example, the first material may include silicon (Si), and the second material may include silicon-germanium (SiGe). In one embodiment, the material of the first portion 152a may be Si, and the material of the second portion 152b may be SiGe. The second portion 152b may act as a hole collection layer that collects unused negatively biased holes accumulated in the semiconductor pattern. In an embodiment, the second portion 152b may be part of the first source / drain region 152. This disclosure is not limited thereto. For example, the second portion 152b may be a layer formed separately on the first portion 152a of the first source / drain region 152. The first portion 152a may act as a source / drain region, and the second portion 152b may act as a hole collection layer. In an embodiment, the second portion 152b may not be formed on the second source / drain region 154.

[0048] Because the first and second materials have different conduction band and valence band positions, a band offset can be formed between the channel region 140 and the second portion 152b of the first source / drain region 152 during the band alignment process. Therefore, the second portion 152b of the first source / drain region 152 can act as an excess channel hole collector, collecting excess holes accumulated in the channel region 140, thereby improving the floating body effect (FBE). The floating body effect can occur when the transistor body (e.g., the semiconductor pattern SP) is electrically isolated (not biased to a negative voltage when the transistor is an n-type transistor), allowing it to accumulate charge during operation. This dynamically modulates transistor behavior, and this collection of excess holes by the second portion 152b can reduce the body charge of excess holes in the semiconductor pattern SP other than the second portion 152b.

[0049] According to an embodiment, the first thickness H1 of the first source / drain region 152 may be greater than the second thickness H2 of the channel region 140. In an embodiment, the channel region 140 may have the same thickness as the second source / drain region 152. In this disclosure, "thickness" may refer to the distance between the upper and lower surfaces of the component along a first direction D1. "Thickness" may represent the average distance between the upper and lower surfaces over the entire surface of the component, or it may represent the distance between the upper and lower surfaces at a specific point, such as the central portion of the component. For example, the distance between the upper and lower surfaces of the second portion 152b of the first source / drain region 152 may be greater than the distance between the upper and lower surfaces of the channel region 140.

[0050] Multiple word lines WL can surround each of multiple semiconductor patterns SP and can extend longitudinally in the second direction D2. The word lines WL can have a gate-around-a-ring (GA-A) structure that completely surrounds the channel region 140.

[0051] The word line WL may include conductive materials. For example, the word line WL may include at least one of the following: doped semiconductor materials (doped silicon, doped silicon-germanium, doped germanium, etc.), conductive metal nitrides (titanium nitride, tantalum nitride, etc.), metals (tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (tungsten silicide, cobalt silicide, titanium silicide), but this disclosure is not limited thereto.

[0052] A gate insulating film 130 may be disposed on the word line WL. The gate insulating film 130 may be positioned between the word line WL and an adjacent component. (Reference) Figure 3 and Figure 4 The gate insulating film 130 may be located between the channel region 140 and each word line WL, between the interlayer insulating layer ILD and the word line WL, and between the second spacer SS2 and the word line WL. Alternatively, the gate insulating film 130 may not be located between the first spacer SS1 and each word line WL. Therefore, the first side surface of the first spacer SS1 on the third direction D3 may contact the first side surface of each word line WL on the third direction D3. Unless the context otherwise requires, the term "contact" as used herein refers to a direct connection (i.e., physical touch).

[0053] The gate insulating film 130 may include a high-k insulating film, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The high-k insulating film may include, for example, at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0054] An interlayer insulating layer (ILD) may be located in the space between adjacent word lines among a plurality of word lines WL stacked along the first direction D1. The ILD electrically isolates adjacent word lines WL from each other. In an embodiment, a portion of the ILD may be disposed between adjacent capacitor structures CAP along the first direction D1. For example, the ILD may be located in the space between adjacent first electrodes among a plurality of first electrodes 182 disposed along the first direction D1.

[0055] The interlayer insulating layer (ILD) may include insulating materials. For example, the interlayer insulating layer (ILD) may be selected from the group consisting of silicon oxide film, silicon nitride film, silicon oxynitride film, carbon-containing silicon oxide film, carbon-containing silicon nitride film, and carbon-containing silicon oxynitride film.

[0056] Multiple bit lines BL can be disposed on the substrate 100. The multiple bit lines BL can be arranged along a second direction D2. The bit lines BL can be disposed on a first side of each of the multiple semiconductor patterns SP and extend longitudinally in the first direction D1. Each of the multiple semiconductor patterns SP can be connected to the bit lines BL. For example, the bit lines BL can be electrically connected to the first source / drain region 152 of each semiconductor pattern SP.

[0057] The first spacer SS1 may be located between the bit line BL and each of the multiple word lines WL. The first spacer SS1 may be disposed between vertically adjacent interlayer insulating layers (ILDs), and the first spacer SS1 may surround the first source / drain region 152 of the semiconductor pattern SP. In an embodiment, the first spacer SS1 may be disposed on the upper and lower surfaces of the second portion 152b of the first source / drain region 152 and on the two side surfaces of the second portion 152b facing in the second direction D2.

[0058] The first spacer SS1 may include an insulating material. For example, the first spacer SS1 may include a high-k insulating material, such as a silicon nitride film and a silicon oxynitride film. In embodiments, the first spacer SS1 may be formed of an oxide-based material (e.g., a silicon oxide film (SiO2)) or a multilayer structure based on a nitride material to enhance electrical insulation properties. However, this disclosure is not limited thereto.

[0059] The capacitor structure CAP can be disposed on a second side of each of a plurality of semiconductor patterns SP, the second side being opposite to the first side. The capacitor structure CAP may include a plurality of first electrodes 182, a capacitor dielectric film 184, and a second electrode 186.

[0060] Multiple first electrodes 182 may be disposed on the second side of each of multiple semiconductor patterns SP and may be stacked in a first direction D1. Each of the first electrodes 182 may be located between adjacent interlayer insulating layers (ILDs) in the first direction D1.

[0061] For example, each first electrode 182 may extend along the contour of the side surface of the second source / drain region 154 (e.g., the side surface in the third direction D3) in the first direction D1 and along the side surface of the second spacer SS2 surrounding the second source / drain region 154 (e.g., the side surface in the third direction D3), and may extend along the surface contour of portions of the upper and lower surfaces of adjacent interlayer insulating layers (ILD) in the third direction D3.

[0062] The first electrode 182 may include at least one of a metal, a metal nitride film, and a metal silicide. For example, the first electrode 182 may include a refractory metal film such as cobalt, titanium, nickel, tungsten, and molybdenum. The first electrode 182 may include a metal nitride film such as titanium nitride, silicon nitride, aluminum titanium nitride, tantalum nitride, silicon tantalum nitride, aluminum tantalum nitride, and tungsten nitride.

[0063] The second electrode 186 may be spaced apart from the first electrode 182. A capacitor dielectric film 184 may be disposed between the first electrode 182 and the second electrode 186. The second electrode 186 may extend along the capacitor dielectric film 184. The second electrode 186 may fill the internal space formed along the contour of the capacitor dielectric film 184. The second electrode 186 may extend in a first direction D1. The second electrode 186 may serve as a reference. Figure 1 The plate electrode PLATE is described.

[0064] The second electrode 186 may include, for example, at least one of doped silicon, metal, metal nitride film, and metal silicide. In some embodiments, the second electrode 186 may include a material substantially the same as that of the first electrode 182.

[0065] A capacitor dielectric film 184 may be disposed between a first electrode 182 and a second electrode 186. The capacitor dielectric film 184 may be disposed along the contour of the first electrode 182 and along the side surface contour of the interlayer insulating layer (ILD) in a third direction (D3). The capacitor dielectric film 184 may include at least one of the following: metal oxides, such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide; and dielectric materials having a perovskite structure, such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT.

[0066] The second spacer SS2 may be located between the capacitor structure CAP and each word line in the plurality of word lines WL. The second spacer SS2 may be disposed between vertically adjacent interlayer insulating layers (ILDs), and the second spacer SS2 may surround the second source / drain region 154 of the semiconductor pattern SP. For example, the second spacer SS2 may be disposed on the upper and lower surfaces of the second source / drain region 154 and on the two side surfaces of the second source / drain region 154 facing in the second direction D2. The second spacer SS2 may include an insulating material. For example, the second spacer SS2 may include the same or similar material as the first spacer SS1.

[0067] The upper insulating layer (TIL) may cover a stacked structure in which multiple word lines (WL) and multiple interlayer insulating layers (ILD) are alternately stacked, with semiconductor patterns (SP) interspersed therebetween. Capacitor structures (CAP) and / or bit lines (BL) may extend through the upper insulating layer (TIL). The upper insulating layer (TIL) may comprise a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but this disclosure is not limited thereto.

[0068] Figures 6 to 9 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figures 6 to 9 Each of them can correspond to along Figure 2 The cross-sectional view taken from line AA. Besides the shape of the first source / drain region 152, Figures 6 to 9 The semiconductor memory device in the reference can be used with Figures 1 to 5 The semiconductor memory devices described are essentially the same. In the following text, for ease of description, the focus will be on [the specific semiconductor memory devices described]. Figures 1 to 5 The configurations described in the text are different from the configurations described in the text.

[0069] According to an embodiment, the third thickness H3 of the first portion 152a of the first source / drain region 152 may be less than the second thickness H2 of the channel region 140. (See reference...) Figure 6 The distance between the upper and lower surfaces of the first portion 152a can be less than the distance between the upper and lower surfaces of the channel region 140. In this case, the thickness of the first source / drain region 152 can be equal to or less than the second thickness H2 of the channel region 140. In an embodiment, the channel region 140 can have the same thickness as the second source / drain region 154. For example, the distance between the upper and lower surfaces of the second portion 152b of the first source / drain region 152 can be equal to or less than the distance between the upper and lower surfaces of the channel region 140.

[0070] According to an embodiment, the surface of the second portion 152b of the first source / drain region 152 may have a convex shape. (See reference...) Figure 7 The surface of the second part 152b can protrude outward, making the central part thicker than the ends.

[0071] According to an embodiment, the second portion 152b of the first source / drain region 152 may completely surround the entire surface of the first portion 152a except for the surface through which the first portion 152a connects to the channel region 140. (See reference...) Figure 8 The second portion 152b of the first source / drain region 152 can also be disposed between the first portion 152a and the bit line BL. For example, the second portion 152b can be disposed on the upper surface of the first portion 152a, the lower surface of the first portion 152a, the two side surfaces of the first portion 152a facing in the second direction D2, and the first surface of the first portion 152a adjacent to the bit line BL in the third direction D3.

[0072] According to an embodiment, the second portion 152b of the first source / drain region 152 may surround a portion of the upper surface of the first portion 152a, the lower surface of the first portion 152a, and a portion of each of the two side surfaces of the first portion 152a facing in the second direction D2. (See reference...) Figure 9 The first part 152a, in the third direction D3, has a first length L1 that is greater than the second part 152b, in the third direction D3, has a second length L2 that is also in the third direction D3. The second part 152b may be spaced apart from the word line WL in the third direction D3.

[0073] refer to Figures 6 to 9 The exemplary embodiments described are not mutually exclusive. For example, some exemplary embodiments may include Figures 6 to 9 Each of the features referenced in the figures is a combination of one or more features referenced in the figures and one or more other features referenced in the figures.

[0074] Figure 10 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 10 It can correspond to along Figure 2 A cross-sectional view taken from line AA. Besides the shape of the capacitor structure CAP, Figure 10 The semiconductor memory device in the reference can be used with Figures 1 to 9 The semiconductor memory devices described are essentially the same. In the following text, for ease of description, the focus will be on [the specific semiconductor memory devices described]. Figures 1 to 9 The configurations described in the text are different from the configurations described in the text.

[0075] According to an embodiment, each first electrode 182 may surround a portion of the semiconductor pattern SP. (See reference...) Figure 10 The first electrode 182 may be disposed on a portion of the second side of the semiconductor pattern SP connected to the capacitor structure CAP, and on a portion of the upper and lower surfaces of the semiconductor pattern SP connected to the second side. The first electrode 182 may not contact the interlayer insulating layer ILD. For example, the first electrode 182 may be spaced apart from the interlayer insulating layer ILD.

[0076] The capacitor dielectric film 184 may be located between the first electrode 182 and the second electrode 186. The capacitor dielectric film 184 may be disposed along the contour of the first electrode 182 and along the contour of the interlayer insulating layer ILD and the second spacer SS2 on the third-direction D3 side surface.

[0077] Figures 11 to 14 This is a diagram illustrating a semiconductor memory device according to some embodiments of the present disclosure. Figure 11 , Figure 13 and Figure 14 Each can correspond to along Figure 2 The cross-sectional view taken by line AA, and Figure 12 It can correspond to along Figure 2 A cross-sectional view taken from line CC. Apart from the shape of the first source / drain region 152, Figures 11 to 14 The semiconductor memory device in the reference can be used with Figures 1 to 10 The semiconductor memory devices described are essentially the same. In the following text, for ease of description, the focus will be on [the specific semiconductor memory devices described]. Figures 1 to 10 The configurations described in the text are different from the configurations described in the text.

[0078] refer to Figures 11 to 14 Each of the plurality of semiconductor patterns SP may include a first source / drain region 152 adjacent to the bit line BL, a second source / drain region 154 adjacent to the capacitor structure CAP, and a channel region 140 disposed between the first source / drain region 152 and the second source / drain region 154.

[0079] According to embodiments, the first source / drain region 152 and the channel region 140 may comprise different materials. For example, the channel region 140 may comprise a first material, and the first source / drain region 152 may comprise a second material. The band gap of the first material included in the channel region 140 may be larger than the band gap of the second material included in the first source / drain region 152. For example, the first material may comprise silicon (Si), and the second material may comprise silicon-germanium (SiGe). However, this disclosure is not limited thereto. In embodiments, the material of the first source / drain region 152 may be different from the material of the channel region 140. In embodiments, the material of the first source / drain region 152 may be different from the material of the second source / drain region 154, and the first source / drain region 152 and the second source / drain region 154 may be doped with the same dopant.

[0080] According to an embodiment, the fourth thickness H4 of the first source / drain region 152 can be greater than the second thickness H2 of the channel region 140. (See reference...) Figure 11 The distance between the upper and lower surfaces of the first source / drain region 152 can be greater than the distance between the upper and lower surfaces of the channel region 140.

[0081] According to an embodiment, the fourth thickness H4 of the first source / drain region 152 may be equal to the second thickness H2 of the channel region 140. In an embodiment, the channel region 140 may have the same thickness as the second source / drain region 154. (See reference...) Figure 13 The distance between the upper and lower surfaces of the first source / drain region 152 can be the same as or substantially the same as the distance between the upper and lower surfaces of the channel region 140.

[0082] According to an embodiment, the surface of the first source / drain region 152 may have a convex shape. (See reference...) Figure 14 The surface of the first source / drain region 152 can protrude outward, making the central portion thicker than the ends.

[0083] Figures 15 to 23 This is a diagram illustrating an intermediate stage of a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure. Figures 15 to 23 It can correspond to along Figure 2 The cross-sectional view taken from line AA.

[0084] refer to Figure 15 A preliminary stacked structure can be disposed on a substrate 100, in which multiple interlayer insulating layers (ILDs) and multiple molded sacrificial layers 210 are alternately stacked in a first direction D1. An upper insulating layer (TIL) can be formed on the top surface of the preliminary stacked structure, and a sacrificial pillar pattern 220 extending through the preliminary stacked structure and the upper insulating layer (TIL) in the first direction D1 can be formed. The molded sacrificial layers 210 and the sacrificial pillar pattern 220 can be formed of an insulating material having etch selectivity relative to the interlayer insulating layers (ILDs). For example, the molded sacrificial layers 210 and the sacrificial pillar pattern 220 can be silicon oxide. However, this disclosure is not limited thereto.

[0085] refer to Figure 16 The first trench T1 can be formed by patterning a sacrificial layer 210 in the first direction D1 through the initial stacked structure and the upper insulating layer TIL and in the third direction D3.

[0086] refer to Figure 17 Interlayer sacrificial patterns can be formed inside the first trench T1 along the exposed side surface of the patterned molded sacrificial layer 210, which is located between multiple interlayer insulating layers (ILDs). For example, the molded sacrificial layer 210 can be patterned on a third direction D3 to form an internal space, and interlayer sacrificial patterns 230 can be formed along the surface of each internal space. The interlayer sacrificial patterns 230 can be formed along the upper and lower surfaces of the interlayer insulating layers (ILDs) and along the exposed side surface of the molded sacrificial layer 210.

[0087] Subsequently, after forming the interlayer sacrificial pattern 230, a semiconductor pattern SP can be filled into the internal space. The semiconductor pattern SP can be formed in the space between the formed interlayer sacrificial patterns 230.

[0088] refer to Figure 18 and Figure 19 The interlayer sacrifice pattern 230 can be partially patterned on D3 by a third party. The patterned interlayer sacrifice pattern 230 can serve as a second source / drain region surrounding the semiconductor pattern SP (e.g., Figure 3 The second spacer in the second source / drain region 154. Thereafter, a gate insulating film 130 can be formed on the inner walls of the first trench T1, these inner walls being defined by the lower and upper surfaces of each of the plurality of interlayer insulating layers ILDs and the side surfaces of the patterned interlayer sacrificial pattern 230. Then, conductive material can be filled on the gate insulating film 130 formed between the interlayer insulating layer ILD and the semiconductor pattern SP, and between the uppermost semiconductor pattern SP and the upper insulating layer TIL, thereby forming the word line WL.

[0089] Subsequently, by partially removing the gate insulating film 130 formed on the inner wall of the first trench T1, a portion of the external semiconductor pattern SP and the first side surface of each word line WL on the third direction D3 can be exposed outward. The exposed portion of the semiconductor pattern SP can serve as the first source / drain region.

[0090] According to manufacturing references Figures 11 to 14 Some embodiments of the described method for a semiconductor memory device may partially remove the gate insulating film 130 formed on the inner wall of the first trench T1, may together remove the exposed portion of the semiconductor pattern SP, and may expose the first side surface of the semiconductor pattern SP aligned with the first side surface of the word line WL.

[0091] refer to Figure 20 The second portion 152b of the first source / drain region can be formed on the exposed surface of the semiconductor pattern SP. The second portion 152b of the first source / drain region can be formed by epitaxial growth.

[0092] refer to Figure 21 A first spacer SS1 can be formed around the second portion 152b of the first source / drain region. During the formation of the first spacer SS1, a portion of the second portion 152b formed on the side surface of the semiconductor pattern SP on the third-direction D3 can be partially removed. However, the scope of this disclosure is not limited thereto.

[0093] refer to Figure 22 Conductive material can fill the interior of the first trench T1, thereby forming a bit line BL extending longitudinally in the first direction D1.

[0094] refer to Figure 23 The sacrificial pillar pattern 220 and portions of the patterned molded sacrificial layer 210 can be removed, and then the patterned interlayer sacrificial pattern 230 can be partially removed to form the second trench T2. The remaining portions of the patterned interlayer sacrificial pattern 230 can correspond to the second spacer SS2. Capacitor structure (e.g., Figure 3 The capacitor structure (CAP) can be formed in the second trench T2. A reference can be provided by this manufacturing method or a similar manufacturing method. Figures 1 to 14 The semiconductor memory device described.

[0095] Although the present disclosure has been described above with reference to limited embodiments and accompanying drawings, the present disclosure is not limited thereto, and those skilled in the art will certainly make various modifications and variations within the technical spirit of the present disclosure and the equivalents of the appended claims.

[0096] Exemplary embodiments are not defined as mutually exclusive. For example, some exemplary embodiments may include one or more features referenced in any of the figures, and may also include one or more other features referenced in other figures.

Claims

1. A semiconductor memory device, comprising: Substrate; Multiple semiconductor patterns are stacked on the substrate in a first direction perpendicular to the upper surface of the substrate and spaced apart from each other; Multiple letter lines, each surrounding the multiple semiconductor patterns, extend longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; Bit lines are located on a first side of each of the plurality of semiconductor patterns and extend longitudinally in the first direction; as well as A capacitor structure is provided in which, on a second side of each of the plurality of semiconductor patterns, the second side faces the first side upward in a third direction parallel to the upper surface of the substrate and intersecting the first and second directions, and each of the plurality of semiconductor patterns extends longitudinally in this third direction. Each of the plurality of semiconductor patterns includes: The first source / drain region is adjacent to the bit line; The second source / drain region is adjacent to the capacitor structure; and The channel region is located between the first source / drain region and the second source / drain region. The first source / drain region, the channel region, and the second source / drain region are arranged along the third direction, and The first source / drain region includes: The first part extends upward from the trench region in the direction of the third party; and The second part revolves around the first part.

2. The semiconductor memory device according to claim 1, wherein, The band gap of the first material included in the first part is greater than the band gap of the second material included in the second part.

3. The semiconductor memory device according to claim 1, wherein The thickness of the first source / drain region is greater than the thickness of each of the channel region and the second source / drain region.

4. The semiconductor memory device according to claim 1, wherein The thickness of the first portion is less than the thickness of each of the second source / drain region and the channel region, and The material of the first part is the same as the material of the channel region.

5. The semiconductor memory device according to claim 1, wherein The surface of the second part protrudes outward, making the central portion of the second part thicker than the ends of the second part.

6. The semiconductor memory device according to claim 1, in, The second part is on the upper surface of the first part, the lower surface of the first part, the two side surfaces of the first part facing each other in the second direction, and the first surface of the first part adjacent to the bit line in the third direction.

7. The semiconductor memory device according to claim 1, in, The length of the first part in the third direction is greater than the length of the second part in the third direction.

8. The semiconductor memory device according to claim 1, in, The second part is spaced apart from the corresponding word line among the plurality of word lines in the third direction.

9. The semiconductor memory device according to claim 1, further comprising: A first spacer surrounds the first source / drain region and is disposed between the bit line and the corresponding word line among the plurality of word lines.

10. The semiconductor memory device according to claim 9, in, The first spacer and the corresponding word line are arranged along the third direction, wherein the first spacer contacts the corresponding word line.

11. The semiconductor memory device according to claim 1, in, The capacitor structure includes: A first electrode is connected to the second side of a corresponding semiconductor pattern in the plurality of semiconductor patterns that is adjacent to the first electrode in the third direction. The second electrode is spaced apart from the first electrode; and A capacitor dielectric film is located between the first electrode and the second electrode.

12. The semiconductor memory device of claim 11, further comprising: A second spacer surrounds the second source / drain region and is disposed between the capacitor structure and the corresponding word line among the plurality of word lines. The first electrode extends along the side surface of the second source / drain region and the side surface of the second spacer in the first direction.

13. The semiconductor memory device according to claim 11, in, The first electrode is located on a second side of the corresponding semiconductor pattern, a portion of the upper surface of the corresponding semiconductor pattern connected to the second side, and a portion of the lower surface of the corresponding semiconductor pattern connected to the second side.

14. A semiconductor memory device, comprising: Substrate; Multiple semiconductor patterns are stacked on the substrate in a first direction perpendicular to the upper surface of the substrate; Multiple letter lines surround the multiple semiconductor patterns and extend in a second direction that is parallel to the upper surface of the substrate and intersects the first direction; Bit lines are located on a first side of each of the plurality of semiconductor patterns and extend longitudinally in the first direction; as well as A capacitor structure is provided in which, on a second side of each of the plurality of semiconductor patterns, the second side faces the first side upward in a third direction parallel to the upper surface of the substrate and intersecting the first and second directions, and each of the plurality of semiconductor patterns extends longitudinally in this third direction. Each of the plurality of semiconductor patterns includes: The first source / drain region is adjacent to the bit line; The second source / drain region is adjacent to the capacitor structure; and The channel region is located between the first source / drain region and the second source / drain region, and The material of the first source / drain region is different from the material of each of the channel region and the second source / drain region.

15. The semiconductor memory device according to claim 14, in, The band gap of the first material included in the channel region is greater than the band gap of the second material included in the first source / drain region.

16. The semiconductor memory device according to claim 14, in, The thickness of the first source / drain region is greater than or equal to the thickness of each of the channel region and the second source / drain region.

17. The semiconductor memory device according to claim 14, in, The surface of the first source / drain region protrudes outward, making the central portion of the first source / drain region thicker than the ends of the first source / drain region.

18. The semiconductor memory device according to claim 14, in, The capacitor structure includes: A first electrode is connected to the second side of a corresponding semiconductor pattern in the plurality of semiconductor patterns that is adjacent to the first electrode in the third direction. The second electrode is spaced apart from the first electrode; and A capacitor dielectric film is located between the first electrode and the second electrode.

19. The semiconductor memory device according to claim 18, The first electrode is also located on a portion of the upper surface of the corresponding semiconductor pattern connected to the second side, and a portion of the lower surface of the corresponding semiconductor pattern connected to the second side.

20. A semiconductor memory device, comprising: Substrate; Multiple semiconductor patterns are stacked on the substrate in a first direction perpendicular to the upper surface of the substrate; Multiple letter lines, each surrounding the multiple semiconductor patterns, extend longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; An interlayer insulating layer is located between two adjacent word lines among the plurality of word lines; Bit lines are located on a first side of each of the plurality of semiconductor patterns and extend longitudinally in the first direction; A capacitor structure, on a second side of each of the plurality of semiconductor patterns, the second side being opposite to the first side on a third direction parallel to the upper surface of the substrate and intersecting the first and second directions. Each of the plurality of semiconductor patterns includes: The first source / drain region is adjacent to the bit line; The second source / drain region is adjacent to the capacitor structure; and The channel region is located between the first source / drain region and the second source / drain region, and Wherein, the first source / drain region extends from the channel region in the third direction; and A hole collection layer is configured to collect holes from corresponding semiconductor patterns in the plurality of semiconductor patterns and surround the first source / drain region. The hole collection layer is disposed between the bit line and the corresponding word line surrounding the corresponding semiconductor pattern among the plurality of word lines, and The band gap of the first source / drain region is larger than the band gap of the hole collection layer.

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