Semiconductor structure and method of fabricating the same

Abstract

This application provides a semiconductor structure and its fabrication method, applicable to the field of semiconductor technology. In this application, a silicon nitride dielectric layer is formed on the first dielectric layer using a polysilazane process, which has good filling performance and can eliminate voids that cause CT bridges. Secondly, the etchants commonly used in subsequent contact hole and Mo metal region etching processes have a slow etching rate on silicon nitride materials, thus effectively preventing lateral etching and avoiding CT and CT conduction in the middle of the selector tube.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] NAND flash, as an important flash memory device, has a very high cell density, which allows for high storage density. At the same time, its write and erase speeds are extremely fast, so it is widely used in various memory cards. For example, solid-state drives, which are gradually replacing mechanical hard drives, use this structure.

[0003] As device dimensions shrink, the word line spacing of NAND flash memory also decreases. This leads to severe inter-cell coupling interference in floating-gate memory, affecting cell threshold voltage and the programming and read speeds of the memory array. To address this issue, air-gap isolation technology has been introduced into NAND flash memory fabrication. By introducing air—the material with the lowest dielectric constant—between the floating gates, the capacitive coupling effect between the floating gates of the device word lines is improved.

[0004] However, in the process of forming air gaps in NAND flash, the dielectric material next to the select transistor is also etched during the etching process of removing the dielectric material between word lines. In order to form air gaps, a material with poor filling performance will be deposited. At the same time as the air gaps are formed between word lines, voids are also easily formed at the etched positions in the middle of the select transistor. The presence of such voids will cause the contact hole (CT) in the middle of the select transistor to become conductive, i.e., CTbridge. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor structure and its fabrication method, which solves the problem of CT and CT conduction in the middle of the NandFlash selector in the prior art.

[0006] To address the aforementioned technical problems, this application provides a method for fabricating a semiconductor structure, which may include at least the following steps:

[0007] A substrate is provided on which repeating word lines and selection tubes are formed, and the sidewalls of the word lines and selection tubes form a first sidewall.

[0008] An isolation layer is formed, which covers the substrate between adjacent selector tubes;

[0009] Remove part of the first sidewall and the isolation layer to expose the word line and the control gate head of the selector tube;

[0010] Remove the first sidewall;

[0011] A first dielectric layer is formed on the word lines, the select tubes, and the isolation layer to create an air gap between the word lines and a gap between adjacent select tubes;

[0012] A silicon nitride dielectric layer is formed on the first dielectric layer to fill the gap between adjacent selector tubes.

[0013] Furthermore, the process for forming the silicon nitride dielectric layer is a polysilazane filling process.

[0014] Furthermore, after forming the silicon nitride dielectric layer, the method further includes:

[0015] A second dielectric layer is formed on the silicon nitride dielectric layer;

[0016] A third dielectric layer is formed on the second dielectric layer.

[0017] Furthermore, prior to forming the isolation layer, the following is also included:

[0018] A barrier layer is formed, which covers the word line, the selection tube, the first sidewall, and the base.

[0019] Furthermore, after forming the barrier layer and before forming the isolation layer, the method further includes:

[0020] A contact hole etch stop layer is formed, which conformally covers the barrier layer.

[0021] Furthermore, the first sidewall is removed by wet etching.

[0022] Furthermore, the process of forming the isolation layer includes:

[0023] An insulating material layer is formed on the surfaces of the substrate, the letter lines, the selection tube, and the first sidewall;

[0024] The isolation material layer is subjected to chemical mechanical polishing to form an isolation layer, such that the top surface of the isolation layer is flush with the top surface of the selector tube.

[0025] Furthermore, after forming the third dielectric layer, the method further includes:

[0026] Contact hole regions are formed within the third dielectric layer, the second dielectric layer, the silicon nitride dielectric layer, the first dielectric layer, and the isolation layer.

[0027] Furthermore, after forming the contact hole area, the method further includes:

[0028] An M0 metal region is formed within the third dielectric layer.

[0029] To address the aforementioned technical problems, this application also provides a semiconductor structure, which is fabricated using the semiconductor structure fabrication method described above.

[0030] Compared with the prior art, the technical solution of this application has at least one of the following beneficial effects:

[0031] In the semiconductor structure and its fabrication method provided in this application, a silicon nitride dielectric layer is formed on the first dielectric layer by a polysilazane process, which has good filling performance and can eliminate voids that cause CT bridges. Secondly, the etching agents commonly used in the subsequent contact hole and Mo metal region etching processes have a slow etching rate on silicon nitride materials, thus effectively preventing lateral etching and avoiding CT and CT conduction in the middle of the selected tube. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0033] Figures 1-8 This is a schematic diagram of the fabrication process of a semiconductor structure in the prior art.

[0034] Figure 9 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;

[0035] Figures 10-11 A schematic diagram of the process of fabricating a semiconductor structure according to an embodiment of this application.

[0036] in, Figures 1-11 The specific reference numerals in the attached figures are as follows:

[0037] 100-Substrate; 101-Oxide layer; 102-Floating gate layer; 103-Inter-gate dielectric layer; 104-Control gate; 105-Hard mask layer; 106-First sidewall; 107-Second sidewall; 108-Barrier layer; 109-Contact hole etch stop layer; 110-Isolation layer; 111-Metal silicide; 112-First dielectric layer; 113-Fourth dielectric layer; 114-Fifth dielectric layer; 115-Sixth dielectric layer; 116-Contact hole region; 117-M0 metal region; 118-Silicon nitride dielectric layer; 119-Second dielectric layer; 120-Third dielectric layer;

[0038] 200 - Word line; 201 - Select tube; 202 - Hole.

[0039] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0040] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0041] The present application is described in more detail below with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.

[0042] As described in the background section, in the existing technology for forming air gaps in NAND flash, during the etching process to remove the inter-word line dielectric material, the dielectric material next to the select transistor is also etched. In subsequent processes, to form air gaps, a material with poor filling performance is deposited. While air gaps are formed between the word lines, voids are also easily formed at the etched locations in the middle of the select transistor. The main steps of this manufacturing method are as follows:

[0043] First, such as Figure 1 As shown, a substrate 100 is provided, on which an oxide layer 101, word lines 200 and select tubes 201 are formed. The word lines 200 and the select tubes 201 include floating gate layers 102, inter-gate dielectric layers 103, control gates 104 and hard mask layers 105 stacked from bottom to top.

[0044] Next, as Figure 2 As shown, a first sidewall 106 and a second sidewall 107 are formed on the sidewalls of the word line 200 and the selection tube 201.

[0045] Then, as Figure 3As shown, a barrier layer 108 is formed, which covers the word line 200, the select tube 201, the first sidewall 106, the second sidewall 107, and the substrate 100; a contact hole etch stop layer 109 is formed, which conformally covers the barrier layer 108; and an isolation layer 110 is formed, which covers the substrate 100 between adjacent select tubes 201.

[0046] Next, as Figure 4 As shown, the hard mask layer 105, part of the first sidewall 106, the second sidewall 107, the barrier layer 108, the contact hole etching stop layer 109, and the isolation layer 110 are removed to expose the head of the control gate 104 of the word line 200 and the select tube 201.

[0047] Then, as Figure 5 As shown, the first sidewall 106 and part of the contact hole etching stop layer 109 are removed.

[0048] Next, as Figure 6 As shown, a metal silicide 111 is formed on the top of the control gate 104; a first dielectric layer 112 with poor filling performance is formed on the word lines 200, the select tubes 201, the second sidewall 107, the barrier layer 108, the contact hole etching stop layer 109 and the isolation layer 110 to form air gaps between the word lines 200 and open gaps, i.e., voids, between adjacent select tubes 201.

[0049] Then, as Figure 7 As shown, a fourth dielectric layer 113 is formed on the first dielectric layer 112. The material of the fourth dielectric layer 113 is usually a silicon dioxide thin film formed by plasma-enhanced chemical vapor deposition, which has poor filling performance, so the voids 202 are retained. A fifth dielectric layer 114 and a sixth dielectric layer 115 are formed sequentially on the fourth dielectric layer 113.

[0050] Next, as Figure 8 As shown, contact hole regions 116 are formed within the sixth dielectric layer 115, the fifth dielectric layer 114, the third dielectric layer 113, the first dielectric layer 112, and the isolation layer 110. These contact hole regions 116 are distributed in all directions (front, back, left, and right). (For simplicity, the accompanying drawings are provided.) Figure 8 Only one contact hole area is drawn; an M0 metal area 117 is formed within the sixth dielectric layer 115. At this time, the contact hole area 116 is connected to the cavity 202. Since the cavity 202 is through, the contact hole areas 116 distributed front and back will be connected, causing subsequent contact holes to be connected, i.e., CT bridge.

[0051] To address the above issues, this application proposes an improvement: a silicon nitride dielectric layer is formed on the first dielectric layer using a polysilazane process, which has good filling performance and can eliminate voids that cause CT bridges. Secondly, the etchants commonly used in subsequent contact hole and M0 metal region etching processes have a slower etching rate on silicon nitride materials, thus effectively preventing lateral etching and avoiding CT and CT continuity in the middle of the selected tube.

[0052] refer to Figure 9 As shown, Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application; wherein, the method for fabricating the semiconductor structure may include the following steps:

[0053] Step S901: A substrate is provided, on which repeating word lines and selection tubes are formed, and the sidewalls of the word lines and the selection tubes are formed with a first sidewall and a second sidewall.

[0054] Step S902: Form a barrier layer that covers the word line, the selection tube, the first sidewall, the second sidewall, and the substrate;

[0055] Step S903: Form a contact hole etch stop layer, wherein the contact hole etch stop layer conformally covers the barrier layer.

[0056] Step S904: Form an isolation layer that covers the substrate between adjacent selector tubes;

[0057] Step S905: Remove part of the first sidewall and the isolation layer to expose the word line and the control gate head of the selection tube;

[0058] Step S906: Remove the first sidewall and part of the contact hole etching stop layer;

[0059] Step S907: A first dielectric layer is formed on the word lines, the select tubes, and the isolation layer to form an air gap between the word lines and a gap between adjacent select tubes;

[0060] Step S908: A silicon nitride dielectric layer is formed on the first dielectric layer to fill the gap between adjacent selector tubes.

[0061] The method for fabricating the semiconductor structure proposed in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application. Many specific details are set forth in the following description to provide a thorough understanding of this application; however, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.

[0062] See Figures 1-2 In step S901 above, a substrate 100 is first provided. The substrate 100 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. For example, in this embodiment, the substrate 100 is preferably a silicon wafer. An oxide layer 101 formed by natural oxidation, repeating word lines 200, and select tubes 201 are formed on the substrate 100. The word lines 200 and the select tubes 201 include a floating gate layer 102, an inter-gate dielectric layer 103, a control gate 104, and a hard mask layer 105 stacked from bottom to top. The sidewalls of the word lines 200 and the select tubes 201 are formed with a first sidewall 106 and a second sidewall 107. The second sidewall 107 is located between the word lines 200, the select tubes 201, and the first sidewall 106. The floating gate layer 102 and the control gate 104 are made of polycrystalline silicon or amorphous silicon; the inter-gate dielectric layer 103 may be a stacked structure of oxide-nitride-oxide. To simplify the drawings, the drawings in this embodiment only show the inter-gate dielectric layer 103 as a single film layer, but this is not a limitation; the hard mask layer 105 is made of silicon nitride; the first sidewall 106 is made of silicon nitride; and the second sidewall 107 is made of silicon oxide.

[0063] See Figure 3In step S902 above, a barrier layer 108 is formed by chemical vapor deposition process. The barrier layer 108 covers the word line 200, the select tube 201, the first sidewall 106, the second sidewall 107 and the substrate 100. The material of the barrier layer 108 includes silicon oxide.

[0064] Continue reading Figure 3 In step S903 above, a contact hole etch stop layer 109 is formed by chemical vapor deposition process, and the contact hole etch stop layer 109 conformally covers the barrier layer 108; the material of the contact hole etch stop layer 109 includes silicon nitride.

[0065] Continue reading Figure 3 In step S904 above, an isolation material layer is formed on the surfaces of the substrate 100, the word line 200, the select tube 201, and the first sidewall 106 by chemical vapor deposition. The isolation material layer is then subjected to chemical mechanical polishing to form an isolation layer 110, such that the top surface of the isolation layer 110 is flush with the top surface of the contact hole etch stop layer 109 above the select tube 201. The isolation layer 110 covers the contact hole etch stop layer 109 and the substrate 100 between adjacent select tubes 201. The material of the isolation layer 110 includes silicon oxide.

[0066] See Figure 4 In step S905 above, the hard mask layer 105 is removed by dry etching, and then a portion of the first sidewall 106, the second sidewall 107, the barrier layer 108, the contact hole etching stop layer 109 and the isolation layer 110 are removed by back etching to expose the head of the control gate 104 of the word line 200 and the select tube 201.

[0067] See Figure 5 In step S906 above, the first sidewall 106 and part of the contact hole etching stop layer 109 are removed by wet etching.

[0068] See Figure 6 In step S907 above, a metal silicide 111 is formed on the top of the control gate 104 by a self-aligned silicide process; a first dielectric layer 112 with poor filling performance is formed on the word line 200, the select tube 201, the second sidewall 107, the barrier layer 108, the contact hole etch stop layer 109 and the isolation layer 110 by a chemical vapor deposition process, so as to form an air gap between the word lines 200 and a top-open gap, i.e., a void, between adjacent select tubes 201.

[0069] See Figure 10In step S908 above, a silicon nitride dielectric layer 118 is formed on the first dielectric layer 112 by a polysilazane filling process. The filling performance is good and can eliminate voids that cause CT bridge.

[0070] Continue reading Figure 10 The method for fabricating the semiconductor structure provided in this application embodiment further includes:

[0071] Step S908.1: A second dielectric layer 119 and a third dielectric layer 120 are sequentially formed on the silicon nitride dielectric layer 118 by chemical vapor deposition process; the materials of the second dielectric layer 119 and the third dielectric layer 120 include silicon oxide.

[0072] Step S908.2, see Figure 11 The process involves etching contact holes to form contact hole regions 116. This etching process sequentially passes through the third dielectric layer 120 and the second dielectric layer 119. When etching the silicon nitride dielectric layer 118, the etching parameters are adjusted to ensure vertical penetration of the silicon nitride dielectric layer 118 into the target contact hole region, allowing further etching down to the first dielectric layer 112 and the isolation layer 110. Etching of the third dielectric layer 120 forms the MO metal region 117. During the etching of contact hole regions 116 and MO metal regions 117, the gaps between adjacent selector tubes 201 are completely filled by the silicon nitride dielectric layer 118. Since the main etchant used for etching contact hole regions 116 and MO metal regions 117 (such as fluorine-containing plasma) has a relatively slow etching rate on the silicon nitride material, lateral etching is effectively prevented, avoiding subsequent CT and CT conduction in the middle of the selector tube.

[0073] In other embodiments, a semiconductor structure is also provided, wherein the semiconductor structure can be fabricated using the methods described above, as detailed above, and will not be repeated here.

[0074] In summary, since the semiconductor structure and its fabrication method provided in this application form a silicon nitride dielectric layer on the first dielectric layer through a polysilazane process, the filling performance is good and the voids that cause CT bridges can be eliminated; secondly, the etchants commonly used in the subsequent contact hole and Mo metal region etching processes have a slow etching rate on silicon nitride materials, thus effectively preventing lateral etching and avoiding CT and CT conduction in the middle of the selected tube.

[0075] It should be noted that although preferred embodiments have been disclosed above in this application, these embodiments are not intended to limit this application. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of this application based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

Claims

1. A method of fabricating a semiconductor structure, comprising: include: A substrate is provided on which repeating word lines and selection tubes are formed, and the sidewalls of the word lines and selection tubes form a first sidewall. An isolation layer is formed, which covers the substrate between adjacent selector tubes; Remove part of the first sidewall and the isolation layer to expose the word line and the control gate head of the selector tube; Remove the first sidewall; A first dielectric layer is formed on the word lines, the select tubes, and the isolation layer to create an air gap between the word lines and a gap between adjacent select tubes; A silicon nitride dielectric layer is formed on the first dielectric layer to fill the gap between adjacent selector tubes.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The process for forming the silicon nitride dielectric layer is a polysilazane filling process.

3. The method of fabricating a semiconductor structure of claim 1, wherein, After forming the silicon nitride dielectric layer, the method further includes: A second dielectric layer is formed on the silicon nitride dielectric layer; A third dielectric layer is formed on the second dielectric layer.

4. The method of producing a semiconductor structure according to claim 1 or 3, wherein Before forming the isolation layer, the following are also included: A barrier layer is formed, which covers the word line, the selection tube, the first sidewall, and the base.

5. The method of fabricating a semiconductor structure of claim 4, wherein, After the barrier layer is formed, and before the isolation layer is formed, the method further includes: A contact hole etch stop layer is formed, which conformally covers the barrier layer.

6. The method of fabricating a semiconductor structure of claim 1, wherein, The first sidewall was removed by wet etching.

7. The method of fabricating a semiconductor structure of claim 1, wherein, The process of forming the isolation layer includes: An insulating material layer is formed on the surfaces of the substrate, the letter lines, the selection tube, and the first sidewall; The isolation material layer is subjected to chemical mechanical polishing to form an isolation layer, such that the top surface of the isolation layer is flush with the top surface of the selector tube.

8. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, After forming the third dielectric layer, the method further includes: Contact hole regions are formed within the third dielectric layer, the second dielectric layer, the silicon nitride dielectric layer, the first dielectric layer, and the isolation layer.

9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, After forming the contact hole area, the method further includes: An M0 metal region is formed within the third dielectric layer.

10. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the method described in any one of claims 1-9.

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