Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system including the semiconductor device are provided. The semiconductor device includes: a substrate; a gate stack structure including an interlayer insulating layer and a gate electrode alternately stacked on the substrate; a channel structure extending through the gate stack structure; and gate contacts, each of the gate contacts penetrating a portion of the gate stack structure to be electrically connected to the gate electrode, wherein the gate stack structure includes a first gate stack structure, a second gate stack structure, and a first upper insulating layer sequentially stacked on the substrate between the first gate stack structure and the second gate stack structure. Each gate contact electrically connected to the gate electrode of the first gate stack structure includes a stepped portion and a bent portion, wherein the width of each gate contact portion varies discontinuously, and the stepped portion and the bent portion are located within the first upper insulating layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more particularly to semiconductor devices and electronic systems including such semiconductor devices. Background Technology

[0002] In electronic systems that require data storage, semiconductor devices capable of storing high-capacity data are needed. Therefore, methods to increase the data storage capacity of semiconductor devices are being researched. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising memory cells arranged in three dimensions rather than two dimensions are being proposed. Summary of the Invention

[0003] Embodiments of this disclosure provide semiconductor devices and electronic systems including the semiconductor devices that can improve productivity and reliability.

[0004] One aspect of this disclosure provides a semiconductor device comprising: a substrate; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure extending through the gate stack structure; and a plurality of gate contacts, each of the plurality of gate contacts penetrating a portion of the gate stack structure for electrical connection to the plurality of gate electrodes, wherein the gate stack structure includes a first gate stack structure, a second gate stack structure, and a first upper insulating layer sequentially stacked on the substrate, and the gate contacts electrically connected to the gate electrodes of the first gate stack structure each including a stepped portion and a bent portion, wherein the width of each gate contact varies discontinuously, and the stepped portion and the bent portion are located within the first upper insulating layer.

[0005] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure extending through the gate stack structure; and a plurality of gate contacts, each of the plurality of gate contacts penetrating a portion of the gate stack structure to be electrically connected to the plurality of gate electrodes, wherein the gate stack structure includes a first gate stack structure, a second gate stack structure, and a third gate stack structure sequentially stacked from the substrate, a first upper insulating layer being located between the first gate stack structure and the second gate stack structure, a second upper insulating layer being located between the second gate stack structure and the third gate stack structure, a gate contact electrically connected to a gate electrode located in the first gate stack structure including a bend and a step located in the first upper insulating layer and a bend and a step located in the second upper insulating layer, a gate contact electrically connected to a gate electrode located in the second gate stack structure including a bend and a step located in the second upper insulating layer, and a gate contact electrically connected to a gate electrode located in the third gate stack structure penetrating a portion of the third gate stack structure.

[0006] Another aspect of this disclosure provides an electronic system comprising: a main substrate; a semiconductor device located on the main substrate; and a controller connected to the semiconductor device on the main substrate, wherein the semiconductor device comprises: a substrate; a gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on the substrate; a channel structure extending through the gate stack structure; and a plurality of gate contacts, each of the plurality of gate contacts penetrating a portion of the gate stack structure to be electrically connected to the plurality of gate electrodes, the gate stack structure including a first gate stack structure and a second gate stack structure being stacked with a first upper insulating layer located between the first gate stack structure and the second gate stack structure, and the gate contact electrically connected to the gate electrode of the first gate stack structure including a stepped portion and a bent portion, the stepped portion and the bent portion being located within the first upper insulating layer, and the width of the gate contact portion varying discontinuously.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. The method includes: forming a first sacrificial stack by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial insulating layers on a substrate, wherein the first sacrificial stack includes a connection region and a cell array region; forming a first channel through-portion penetrating the first sacrificial stack in the cell array region; forming a first upper insulating layer and a plurality of first etch stop patterns on the first sacrificial stack; forming a second sacrificial stack by alternately laminating a plurality of interlayer insulating layers and a plurality of sacrificial insulating layers on the first upper insulating layer; simultaneously forming a second channel through-portion penetrating the cell array region of the second sacrificial stack and a second gate through-portion penetrating the connection region of the second sacrificial stack; and forming a first gate through-portion contacting each sacrificial insulating layer of the first sacrificial stack through the second gate through-portion.

[0008] In some embodiments, when the first upper insulating layer and a plurality of first etch stop patterns are formed on the first sacrificial stack, the first etch stop patterns may be formed to contact the first channel through portion.

[0009] In some examples, when the second channel through portion and the second gate through portion through the connection region of the second sacrificial stack are formed simultaneously, the second gate through portion may be formed up to the upper surface of the first etch stop pattern.

[0010] In some embodiments, the first etch stop pattern may be formed within the first upper insulating layer.

[0011] In some embodiments, the first gate through portion and the second gate through portion may have the following shape: as the first gate through portion and the second gate through portion approach the substrate (e.g., toward the substrate), the width becomes narrower (or at least partially narrower), and due to the width difference between the first gate through portion and the second gate through portion, the first gate through portion and the second gate through portion may include a bend.

[0012] In some embodiments, the first etch stop pattern may have a shape that narrows (or at least partially narrows) in width as it approaches the substrate.

[0013] In some embodiments, in the formation of the first gate through portion that contacts each sacrificial insulating layer of the first sacrificial stack portion through the second gate through portion, the second gate through portion may be formed simultaneously to contact each sacrificial insulating layer of the second sacrificial stack portion.

[0014] In some embodiments, when the first upper insulating layer and the plurality of first etch stop patterns are formed on the first sacrificial stack, the number of the first etch stop patterns formed in the connection region may be equal to the number of the sacrificial insulating layers located on the first sacrificial stack.

[0015] In some embodiments, when the first upper insulating layer and the plurality of first etch stop patterns are formed on the first sacrificial stack, the thickness of the first upper insulating layer may be thicker than the thickness of the interlayer insulating layer.

[0016] In some implementations, semiconductor devices that can improve productivity and reliability, as well as electronic systems including such semiconductor devices, are provided. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view schematically illustrating an example of a semiconductor device.

[0018] Figure 2 yes Figure 1 An enlarged cross-sectional view of an example of the channel structure of the semiconductor device shown.

[0019] Figure 3 It is shown Figure 1 A cross-sectional view of an example of the connection region of a cell region included in a semiconductor device.

[0020] Figure 4 It is shown Figure 3 A cross-sectional view of an example of the first gate contact shown.

[0021] Figure 5 It is shown Figure 3 The cross-sectional view of the thirteenth to seventeenth gate contacts is shown.

[0022] Figure 6 It is shown Figure 3 The cross-sectional view of the twenty-fifth gate contact and the twenty-sixth gate contact is shown.

[0023] Figure 7 This illustrates the relationship according to some implementation methods. Figure 1 Views of the same area.

[0024] Figures 8 to 17 This is a partial cross-sectional view illustrating an example of a semiconductor device manufacturing method.

[0025] Figure 18 This is a schematic diagram of an example of an electronic system that includes semiconductor devices.

[0026] Figure 19This is a perspective view schematically illustrating an example of an electronic system including semiconductor devices.

[0027] Figure 20 This is a cross-sectional view schematically showing an example of a semiconductor package. Detailed Implementation

[0028] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements. Furthermore, in this specification, the terms "on" or "above" refer to being positioned on or below a target portion, and do not necessarily mean being positioned above the target portion based on the direction of gravity.

[0029] In the following text, see references Figures 1 to 20 A detailed description is provided of a semiconductor device according to some embodiments and a method for manufacturing the semiconductor device.

[0030] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to some embodiments. Figure 2 yes Figure 1 An enlarged cross-sectional view of an example of the channel structure CH included in the semiconductor device shown. Indicated for clarity. Figure 1 In A-A', B-B', and C-C', and Figure 1 A-A', B-B', and C-C' in the diagram conceptually show the positions of the source contact 186 and the input / output connection line 188.

[0031] refer to Figure 1 and Figure 2 A semiconductor device according to some embodiments may include: a cell region 100 having a memory cell structure and a circuit region 200 having a peripheral circuit structure, the peripheral circuit structure controlling the operation of the memory cell structure. For example, the circuit region 200 and the cell region 100 may be respectively connected to... Figure 18 The electronic system 1000 shown includes corresponding portions of the first structure 1100F and the second structure 1100S of the semiconductor device 1100. Alternatively, the circuit region 200 and the unit region 100 may each include... Figure 20 The semiconductor chip 2200 shown includes the first structure 3100 and the second structure 3200.

[0032] Here, the circuit region 200 may include peripheral circuit structures formed on the first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH formed on the second substrate 110 as a memory cell structure. Circuit line portions 280 may be disposed in the circuit region 200, and cell line portions 180 electrically connected to the memory cell structure may be disposed in the cell region 100.

[0033] In some embodiments, cell region 100 may be located on circuit region 200. Therefore, it is not necessary to fix the region corresponding to circuit region 200 separately from cell region 100, thus reducing the area of ​​the semiconductor device. In some embodiments, circuit region 200 may be located adjacent to cell region 100. Various other variations are possible.

[0034] Circuit region 200 may include a first substrate 210, circuit elements 220, and circuit line portion 280, the circuit line portion 280 being formed on one surface of the first substrate 210. Figure 1 On the upper surface.

[0035] The first substrate 210 may be a semiconductor substrate comprising semiconductor materials. For example, the first substrate 210 may be a semiconductor substrate made of semiconductor materials, or it may be a semiconductor substrate on which a semiconductor layer is formed. For example, the first substrate 210 may be composed of monocrystalline silicon or polycrystalline silicon, epitaxial silicon, germanium, silicon-germanium, silicon-on-insulator, or germanium-on-insulator.

[0036] The circuit element 220 formed on the first substrate 210 may include various circuit components for operating the memory cell structure disposed in the control unit region 100. For example, the circuit element 220 may be configured with peripheral circuit structures, such as decoder circuitry. Figure 18 Reference number 1110), page buffer ( Figure 18 (reference number 1120) and logic circuits ( Figure 18 (Reference number 1130).

[0037] Circuit element 220 may include, for example, multiple transistors, but is not limited thereto. Circuit element 220 may include not only active elements (such as transistors) but also passive elements (such as capacitors, resistors, and inductors).

[0038] The circuit line portion 280 located on the first substrate 210 can be electrically connected to the circuit element 220. In some embodiments, the circuit line portion 280 may include a plurality of wiring layers 286, which are spaced apart from each other by an insulating layer 282 and connected by contact passages 284 to form a desired path. The wiring layers 286 or contact passages 284 may include various conductive materials, and the insulating layer 282 may include various insulating materials. For example, the insulating layer 282 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0039] The cell region 100 may include a cell array region 102 and a connection region 104. A gate stack structure 120 and a channel structure CH may be formed in the cell array region 102 on the second substrate 110. Structures for connecting the gate stack structure 120 and / or the channel structure CH formed in the cell array region 102 to the circuit region 200 or external circuits may be located in the cell array region 102 and / or the connection region 104.

[0040] In some embodiments, the second substrate 110 may include a semiconductor layer comprising a semiconductor material. For example, the second substrate 110 may be a semiconductor substrate made of a semiconductor material, and the semiconductor layer may be formed on the substrate. For example, the second substrate 110 may be composed of silicon, germanium, silicon-germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Here, the semiconductor layer included in the second substrate 110 may be doped with p-type or n-type impurities. For example, p-type impurities may include boron (B), gallium (Ga), etc., and n-type impurities may include phosphorus (P), arsenic (As), etc. However, the embodiments are not limited to the material of the second substrate 110, the conductivity type of the impurities doped in the semiconductor layer, or the material.

[0041] In the cell array region 102, a gate stack structure 120 may be formed, comprising an interlayer insulating layer 132m and a gate electrode 130 alternately stacked on one surface (e.g., the upper surface) of the second substrate 110, and a channel structure CH extending through the gate stack structure 120 in the thickness direction (Z-axis direction in the figure) of the semiconductor device. Here, the thickness direction of the semiconductor device may be a direction that intersects (e.g., is perpendicular to) the second substrate 110 (e.g., a vertical direction).

[0042] In some embodiments, the cell array region 102 may include horizontal conductive layers 112 and 114 located between the second substrate 110 and the gate stack structure 120, and electrically connected (e.g., directly connected) to the channel structure CH and the second substrate 110. The horizontal conductive layers 112 and 114 may include a first horizontal conductive layer 112 and / or a second horizontal conductive layer 114 sequentially located on the second substrate 110. The first horizontal conductive layer 112 may serve as part of a common source line of a semiconductor device. For example, the first horizontal conductive layer 112 may be used together with the second substrate 110 as a common source line.

[0043] The first horizontal conductive layer 112 and the second horizontal conductive layer 114 may include semiconductor materials (e.g., polycrystalline silicon). For example, the first horizontal conductive layer 112 may include a polycrystalline silicon layer with impurities. The embodiments are not limited thereto, and the second horizontal conductive layer 114 may be composed of a different material than the first horizontal conductive layer 112 (e.g., an insulating material), or the second horizontal conductive layer 114 may not be provided.

[0044] The gate stack structure 120 may be located on the second substrate 110 (e.g., on the first horizontal conductive layer 112 and the second horizontal conductive layer 114 formed on the second substrate 110), in which unit insulating layers 132 (e.g., interlayer insulating layer 132m, first upper insulating layer 132a, second upper insulating layer 132b, and third upper insulating layer 132c) and gate electrode 130 are stacked alternately.

[0045] The gate electrode 130 may include a variety of conductive materials. For example, the gate electrode 130 may include metallic materials such as tungsten (W), copper (Cu), aluminum (Al), polycrystalline silicon, metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN)) or combinations thereof. Figure 2 As shown in the enlarged view, a portion of the barrier layer 156 (e.g., the first barrier layer 156a) composed of insulating material may be located outside the gate electrode 130. The interlayer insulating layer 132m may include various insulating materials. For example, the interlayer insulating layer 132m may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

[0046] refer to Figure 2In some embodiments, the channel structure CH may include a channel layer 140 and a gate dielectric layer 150 located on the channel layer 140 between the gate electrode 130 and the channel layer 140. The channel structure CH may also include a core insulating layer 142 located within the channel layer 140; however, as another example, the core insulating layer 142 may not be provided. The channel structure CH may also include channel pads 144 disposed on the channel layer 140 and / or the gate dielectric layer 150. The gate dielectric layer 150 located between the gate electrode 130 and the channel layer 140 may include a tunneling layer 152, a charge storage layer 154, and a barrier layer 156 sequentially formed on the channel layer 140.

[0047] Each channel structure CH can form a string of memory cells, and multiple channel structures CH can be arranged spaced apart from each other in rows and columns on a plane. For example, multiple channel structures CH can be arranged in various shapes on a plane, such as a grid shape or a zigzag shape. The channel structure CH can have a columnar shape. For example, the channel structure CH can have sloping side surfaces such that, when viewed in cross-section, its width narrows (or at least partially narrows) as it approaches the second substrate 110, depending on the aspect ratio. However, the implementation is not limited to this, and the arrangement, structure, shape, etc., of the channel structures CH can be modified differently.

[0048] The channel layer 140 may include a semiconductor material, such as polysilicon. The core insulating layer 142 may include various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0049] The tunneling layer 152 may include an insulating material (e.g., silicon oxide, silicon oxynitride, etc.) capable of charge tunneling. The charge storage layer 154 may serve as a data storage region and may include polysilicon, silicon nitride, etc. The barrier layer 156 may include an insulating material capable of preventing unwanted charge flow into the gate electrode 130. For example, the barrier layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In some embodiments, the barrier layer 156 may include a first barrier layer 156a and a second barrier layer 156b, the first barrier layer 156a including a portion extending horizontally along the gate electrode 130, and the second barrier layer 156b extending vertically between the first barrier layer 156a and the charge storage layer 154.

[0050] However, the materials, stacking structure, etc. of the channel layer 140, the core insulating layer 142, and the gate dielectric layer 150 can be modified in various ways, and the implementation is not limited thereto.

[0051] The channel pad 144 may be arranged to cover the upper surface of the core insulating layer 142 and be electrically connected to the channel layer 140. The channel pad 144 may include, but is not limited to, a conductive material, such as doped polysilicon.

[0052] In one embodiment, the gate stack structure 120 may include multiple stacked portions arranged in sequence. Accordingly, the number of stacked gate electrodes 130 can be increased, thereby increasing the number of memory cells with a stable structure.

[0053] Figure 1 An example of a gate stack structure 120 or more stack portions including a first gate stack portion 121, a second gate stack portion 122 and a third gate stack portion 123 is shown.

[0054] However, the implementation is not limited to this, and the gate stack structure 120 or more stack portions may include two, four or more gate stack portions.

[0055] The first gate stack portion 121 may include a plurality of gate electrodes 130 (e.g., a plurality of first electrodes) and a plurality of interlayer insulating layers 132m stacked alternately, and the second gate stack portion 122 may include a plurality of gate electrodes 130 (e.g., a plurality of first electrodes) and a plurality of interlayer insulating layers 132m stacked alternately. Furthermore, the third gate stack portion 123 may include a plurality of gate electrodes 130 (e.g., a plurality of second electrodes) and a plurality of interlayer insulating layers 132m stacked alternately with each other.

[0056] When multiple gate stack portions (e.g., first gate stack portion 121, second gate stack portion 122, and third gate stack portion 123) are provided as described above, the channel structure CH can have multiple channel portions (e.g., first channel portion CH1, second channel portion CH2, and third channel portion CH3) that are connected to each other and extend through the multiple gate stack portions (e.g., first gate stack portion 121, second gate stack portion 122, and third gate stack portion 123). Each of the multiple channel portions (e.g., first channel portion CH1, second channel portion CH2, and third channel portion CH3) can have inclined side surfaces such that, when viewed in cross-section, their widths become narrower (or at least partially narrower) as they approach the second substrate 110, depending on the aspect ratio, and channel bends CP1 and CP2 can be provided due to the width difference at the boundaries of the multiple channel portions (e.g., first channel portion CH1, second channel portion CH2, and third channel portion CH3). As another example, multiple channel sections may have continuously sloping side surfaces without channel bends. Figure 2An example is shown in which a gate dielectric layer 150, a channel layer 140, and a core insulating layer 142 of multiple channel portions extend from each other to form a monolithic structure. As another example, the gate dielectric layer 150, channel layer 140, and core insulating layer 142 of the multiple channel portions may be formed separately from each other and electrically connected to each other, or separate channel pads may be additionally provided at the boundaries of the multiple channel portions. Thus, the implementation is not limited to the form of multiple channel portions.

[0057] refer to Figure 2 In the semiconductor device according to this embodiment, the plurality of channel portions may include channel step portions CC1 and CC2, which are located between a first channel portion CH1, a second channel portion CH2, and a third channel portion CH3. That is, the first channel step portion CC1 may be located between the first channel portion CH1 and the second channel portion CH2, and the second channel step portion CC2 may be located between the second channel portion CH2 and the third channel portion CH3. The first channel step portion CC1 and the second channel step portion CC2 may have inclined side surfaces, such that the width of these side surfaces becomes narrower (or at least partially narrower) as they approach the second substrate 110. (Reference) Figure 1 and Figure 2 The first channel step portion CC1 and the second channel step portion CC2 can be formed within the first upper insulating layer 132a and the second upper insulating layer 132b, respectively. The first upper insulating layer 132a can be located on the first gate stack portion 121, and the second upper insulating layer 132b can be located on the second gate stack portion 122. In this case, the thickness of the upper insulating layers 132a and 132b can be greater than the thickness of the interlayer insulating layer 132m.

[0058] The first channel step portion CC1 and the second channel step portion CC2 can be located within the first upper insulating layer 132a and the second upper insulating layer 132b. (Reference) Figure 2 The bend in the channel CP1 and the step portion of the first channel CC1 can be located between the first channel portion CH1 and the second channel portion CH2. Similarly, the bend in the channel CP2 and the step portion of the second channel CC2 can be located between the second channel portion CH2 and the third channel portion CH3. Therefore, as Figure 2 As shown, the two protruding portions P1 and C1 can be located between the first channel portion CH1 and the second channel portion CH2. Similarly, the two protruding portions P2 and C2 can be located between the second channel portion CH2 and the third channel portion CH3. This will be explained separately later, but it is a structure obtained by simultaneously forming through portions in the unit array region 102 and the connecting region 104.

[0059] In some embodiments, the gate stack structure 120 can be divided into multiple portions in a plane by an isolation structure 146 extending in the thickness direction (Z-axis direction in the figures) of the semiconductor device and penetrating the gate stack structure 120. Furthermore, an upper isolation region 148 can be formed on the gate stack structure 120. In the plane, the number of isolation structures 146 and / or upper isolation regions 148 can be multiple, extending in the extension direction (X-axis direction in the figures) of the gate electrode 130 and spaced apart from each other by a predetermined distance in the direction intersecting the gate electrode 130 (Y-axis direction in the figures).

[0060] The isolation structure 146 or the upper isolation region 148 may be filled with various insulating materials. For example, the isolation structure 146 or the upper isolation region 148 may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. However, the embodiments are not limited to this, and the structure, shape, material, etc. of the isolation structure 146 or the upper isolation region 148 may be modified in various ways.

[0061] A connection region 104 and a cell line portion 180 may be provided to connect the gate stack structure 120 and the channel structure CH disposed in the cell array region 102 to the circuit region 200 or external circuitry. The connection region 104 may be arranged around the cell array region 102, and a portion of the cell line portion 180 may be located in the connection region 104.

[0062] Here, the cell line portion 180 may include all components that electrically connect the gate electrode 130, the channel structure CH, the horizontal conductive layers 112 and 114 and / or the second substrate 110 to the circuit region 200 or external circuitry. For example, the cell line portion 180 may include a bit line 182, a gate contact portion 190, a source contact portion 186, an input / output connection line 188, and a contact passage 180a and connection lines 180b respectively connected to the contact passage 180a.

[0063] refer to Figure 1 The gate contact 190 may include a first gate contact to a thirty-sixth gate contact, which are respectively connected to a first gate electrode to a thirty-sixth gate electrode. However, in Figure 1 Only a portion of the gate contact is shown in the image. Figure 1 A 36-layer gate electrode is shown, but this is only an example, and the number of stacked gate electrodes 130 can vary. Gate contacts 190 can be positioned in the same number as the gate electrodes 130 and can be electrically connected to the gate electrodes 130 located in each layer. The specific connection relationship between the gate electrodes 130 and the gate contacts 190 is described below.

[0064] Bit line 182 can extend in a cross direction (Y-axis direction in the figure) that intersects the extension direction (X-axis direction in the figure) of gate electrode 130. Bit line 182 can be electrically connected to channel structure CH (e.g., channel pad 144) through contact passage 180a (e.g., bit line contact passage through interlayer insulating layer 132m).

[0065] In this implementation, the gate stack structure 120 may be located together in the cell array region 102 and the connection region 104. For example, in the connection region 104, the extension lengths of the plurality of gate electrodes 130 may be substantially the same. Here, substantially the same includes cases where there are differences within process tolerances (e.g., within 10%). In the connection region 104, the plurality of gate contacts 190 may each extend through a portion of the gate stack structure 120 and be electrically connected to the plurality of gate electrodes 130.

[0066] In this embodiment, a portion of the gate stack structure 120 may be omitted (e.g., a stepped portion): at this portion, a part of the gate stack structure 120 is removed for electrical connection between the gate electrode 130 and the gate contact 190. The connection structure of the plurality of gate contacts 190 and the plurality of gate electrodes 130 will be described in more detail later.

[0067] In the connection region 104, the source contact 186 can penetrate the cell insulating layer 132 and be electrically connected to the horizontal conductive layers 112 and 114 and / or the second substrate 110, and the input / output connection line 188 can pass through the gate stack structure 120 or be disposed outside the gate stack structure 120 and electrically connected to the circuit line portion 280 of the circuit region 200. The cell insulating layer 132 may include an interlayer insulating layer 132m, a first upper insulating layer 132a, a second upper insulating layer 132b, a third upper insulating layer 132c, and an insulating layer formed on and / or around the gate stack structure 120.

[0068] Figure 1 An example is shown in which the source contact 186 and / or the input / output connection 188 have sloping side surfaces that, when viewed in cross-section, narrow with increasing aspect ratio as they approach the second substrate 110 and have bends at the boundaries of the plurality of gate stack portions. However, the implementation is not limited to this. The source contact 186 and / or the input / output connection 188 may also not have bends at the boundaries of the plurality of gate stack portions. Various other modifications are possible.

[0069] For clear understanding and simple explanation, Figure 1The diagram shows that the connection line 180b is configured as a single layer located in the same plane as the bit line 182, and a separate insulating layer 180c is located on the portion excluding the connection line 180b. However, the implementation is not limited to this. Therefore, the connection line 180b may include multiple wiring layers for electrical connection to the bit line 182, the gate contact 190, the source contact 186, and / or the input / output connection line 188, and may also include contact paths.

[0070] The unit line portion 180 can be electrically connected to the circuit line portion 280, so that the bit line 182, gate electrode 130, horizontal conductive layers 112 and 114 and / or the second substrate 110 electrically connected to the channel structure CH can be electrically connected to the circuit element 220 of the circuit region 200.

[0071] refer to Figures 3 to 7 as well as Figure 1 The connection structure of multiple gate contacts 190 and multiple gate electrodes 130 is described together.

[0072] Figure 3 It is shown in Figure 1 A cross-sectional view of the connection region 104 of the cell region 100 included in the semiconductor device shown. Figure 3 It shows the location Figure 1 The connection region 104 of the unit region 100 at the B-B' part. Figure 3 The diagram shows gate electrode 130 including first gate electrode 1301 to thirty-sixth gate electrode 1336, but this is merely an example and the invention is not limited thereto.

[0073] Figure 3 The diagram primarily shows a first gate contact 1901 electrically connected to the first gate electrode 1301, thirteenth gate contacts 1913 to seventeenth gate contacts 1917 electrically connected to the thirteenth to seventeenth gate electrodes 1313 to 17th gate electrodes 1317 respectively, and a twenty-fifth gate contact 1925 and a twenty-sixth gate contact 1926 electrically connected to the twenty-fifth and twenty-sixth gate electrodes. Although not shown, the first to thirty-sixth gate electrodes 1336 can be connected to the first to thirty-sixth gate contacts 1901 to 1936 respectively.

[0074] refer to Figure 1 and Figure 3 In one embodiment, multiple gate contacts 190 in the connection region 104 may extend through a portion of the gate stack structure 120 and be electrically connected to multiple gate electrodes 130 (e.g., in contact with multiple gate electrodes 130).

[0075] For example, each gate contact 190 may extend downward from the upper surface toward the bottom surface of the gate stack structure 120, thereby penetrating a portion of the gate stack structure 120 in the thickness direction (Z-axis direction in the figures) of the semiconductor device. Here, the thickness direction of the semiconductor device may be a direction intersecting (e.g., perpendicular to) the second substrate 110 (e.g., a vertical direction). The upper surface of the gate stack structure 120 may refer to the surface facing the cell line portion 180 or the surface opposite to the second substrate 110 in the thickness direction of the semiconductor device, and the bottom surface of the gate stack structure 120 may refer to the surface opposite to the cell line portion 180 or the surface facing the second substrate 110 in the thickness direction of the semiconductor device. Unless otherwise stated, with respect to the cell region 100, the upper portion or upper surface may refer to the portion or surface facing the cell line portion 180 or the portion or surface opposite to the second substrate 110, and the lower portion or bottom surface may refer to the portion or surface opposite to the cell line portion 180 or the portion or surface facing the second substrate 110.

[0076] Multiple gate contacts 190 can be provided to connect to multiple gate electrodes 130 respectively. Since the multiple gate electrodes 130 are located at different heights in the thickness direction (Z-axis direction in the figure) of the semiconductor device, the multiple gate contacts 190 can have different lengths or depths, so that they can each reach the multiple gate electrodes 130.

[0077] Each gate contact 190 may penetrate a portion of the gate stack structure 120, such that it has a depth that can reach the connection gate electrode 130c among the plurality of gate electrodes 130. For example, a first gate contact may be electrically connected to a first gate electrode. Moreover, an nth gate contact may be electrically connected to an nth gate electrode, and a kth gate contact may be connected to a kth gate electrode. Here, n may be a natural number greater than 1 and less than k, and k may correspond to the total number of the plurality of gate electrodes 130 or the total number of the plurality of gate contacts 190.

[0078] The accompanying drawing shows a gate electrode 130 including a first gate electrode to a thirty-sixth gate electrode. In this configuration, the first gate contact to the twelfth gate contact can be electrically connected to the first gate electrode to the twelfth gate electrode, respectively; the thirteenth gate contact to the twenty-fourth gate contact can be electrically connected to the thirteenth gate electrode to the twenty-fourth gate electrode, respectively; and the twenty-fifth gate contact to the thirty-sixth gate contact can be electrically connected to the twenty-fifth gate electrode to the thirty-sixth gate electrode, respectively. Thus, a plurality of gate contacts 190 can be electrically connected to a plurality of gate electrodes 130, respectively.

[0079] For clarity and simplicity, the accompanying drawings show that the depth of the plurality of gate contacts 190 is arranged to increase sequentially as they approach the cell array region 102; however, the implementation is not limited to this. The arrangement of the plurality of gate contacts 190 can vary in various ways.

[0080] Referring to a gate contact 190, a plurality of gate electrodes 130 may include a connecting gate electrode 130c electrically connected to a gate contact 190, and may include a through gate electrode 130p and / or a residual gate electrode 130r. The through gate electrode 130p may correspond to a gate electrode 130 located on the connecting gate electrode 130c, and is a gate electrode 130 that is penetrated by the gate contact 190 but electrically insulated from the gate contact 190 by a side insulating layer 190i. The residual gate electrode 130r may correspond to a gate electrode 130 located below the connecting gate electrode 130c, and is a gate electrode 130 that is not penetrated by the gate contact 190 and is electrically insulated from the gate contact 190.

[0081] In the first gate contact, the first gate electrode 1301 may correspond to the connecting gate electrode 130c, and the gate electrode 130 located above the connecting gate electrode 130c may correspond to the through gate electrode 130p. In the nth gate contact, the nth gate electrode may correspond to the connecting gate electrode 130c, the gate electrode 130 located on the connecting gate electrode 130c may correspond to the through gate electrode 130p, and the gate electrode 130 located below the connecting gate electrode 130c may correspond to the remaining gate electrode 130r.

[0082] To understand clearly, Figure 3 With the seventeenth gate contact 1917 as a reference, the connecting gate electrode 130c, the through gate electrode 130p, and the remaining gate electrode 130r are shown.

[0083] In one embodiment, each gate contact 190 may be electrically connected to the upper surface of the connecting gate electrode 130c (e.g., in contact with the upper surface of the connecting gate electrode 130c). However, the embodiment is not limited to this. Each gate contact 190 may be electrically connected to other portions (e.g., sides) of the connecting gate electrode 130c (e.g., in contact with other portions).

[0084] In an embodiment, each gate contact 190 may include a conductive portion 190e and a side insulating layer 190i located between the conductive portion 190e and the gate stack structure 120.

[0085] In each gate contact 190, a side insulating layer 190i may be located between at least the side surface of the conductive portion 190e and the side surface of the through gate electrode 130p, so as to electrically insulate the conductive portion 190e and the through gate electrode 130p. Furthermore, the side insulating layer 190i may not be located on the bottom surface of the conductive portion 190e and / or the upper surface of the connecting gate electrode 130c. That is, the side insulating layer 190i may not be located between the upper surface of the connecting gate electrode 130c and the bottom surface of the gate contact 190. For example, the bottom surface of the side insulating layer 190i may contact the connecting gate electrode 130c, or it may be located between the upper and bottom surfaces of the interlayer insulating layer 132m positioned on the connecting gate electrode 130c.

[0086] Accordingly, the side insulating layer 190i can surround the entire side of the gate contact 190 corresponding to the through gate electrode 130p, and can stably insulate between the gate contact 190 and the through gate electrode 130p. However, the implementation is not limited to this, and the position of the side insulating layer 190i, the connection position of the gate contact 190 and the connecting gate electrode 130c, etc., can be modified in various ways.

[0087] For example, the conductive portion 190e has a columnar shape (e.g., a columnar shape with a planar shape such as a circle, polygon, or ellipse), and the side insulating layer 190i may have various planar shapes surrounding the conductive portion 190e, such as a loop (ring) shape, annular shape, and frame shape.

[0088] In an embodiment, each gate contact 190 located within a gate through-portion PH can be electrically connected to the upper portion of the connecting gate electrode 130c. For example, a plurality of gate through-portions PH may be included, each penetrating the gate stack structure 120 individually and spaced apart with the gate stack structure 120 sandwiched between them. One gate contact 190 may be located within one gate through-portion PH, and the bottom surface of the conductive portion 190e of the gate contact 190 located within the gate through-portion PH may be located on the upper surface of the connecting gate electrode 130c (e.g., in contact with the upper surface of the connecting gate electrode 130c). For example, a plurality of gate contacts 190 may be located within a plurality of gate through-portions PH spaced apart from each other, having a one-to-one correspondence between the plurality of gate contacts 190. In an embodiment, the gate through-portion PH may have various planar shapes such as circular, polygonal, elliptical, etc., and the embodiment is not limited to the planar shape of the gate through-portion PH.

[0089] Therefore, the pad area (e.g., pad insulating layer) through which multiple gate contacts 190 pass together, or the portion of the gate stack structure 120 that is removed for the electrical connection of the gate contacts 190 (e.g., the stepped portion), can be omitted. In other words, multiple gate contacts 190 can be individually electrically connected to multiple gate electrodes 130 without a pad area or pad insulating layer. Therefore, the process of electrically connecting the gate contacts 190 and the gate electrodes 130 can be simplified, and the area of ​​the connection region 104 can be reduced.

[0090] On the other hand, in the comparative example including the pad region, processes must be performed for etching a portion of the gate stack structure (e.g., for forming a portion with a stepped shape), for forming a pad insulating layer covering the stepped shape of the gate stack structure, and for electrically connecting multiple gate contacts penetrating a pad insulating layer to multiple gate electrodes. Therefore, the processes for forming the pad region and forming the gate contacts can become complex. To prevent misalignment of the gate contacts in the pad region or pad insulating layer penetrated by the multiple gate contacts together, sufficient width between the multiple gate contacts must be ensured. Therefore, the area of ​​the connection region may increase. However, this embodiment does not include a separate pad region, which prevents these problems.

[0091] refer to Figure 3 Each gate contact 190 may have multiple connecting portions (e.g., a first connecting portion 190a, a second connecting portion 190b, and a third connecting portion 190c), which respectively penetrate multiple gate stack portions (e.g., a first gate stack portion 121, a second gate stack portion 122, and a third gate stack portion 123) and are connected to each other. Each of the multiple connecting portions (e.g., the first connecting portion 190a, the second connecting portion 190b, and the third connecting portion 190c) has a sloping side surface such that, when viewed in cross-section, the width of the sloping side surface narrows (or at least partially narrows) as it approaches the second substrate 110, depending on the aspect ratio, and bends P1 and P2 caused by the width difference may be provided at the boundaries of the multiple connecting portions (e.g., the first connecting portion 190a, the second connecting portion 190b, and the third connecting portion 190c).

[0092] refer to Figure 3In the semiconductor device according to this embodiment, the plurality of connection portions of each gate contact 190 may include step portions C1 and C2 located between the first connection portion 190a, the second connection portion 190b, and the third connection portion 190c. That is, the first step portion C1 may be located between the first connection portion 190a and the second connection portion 190b, and the second step portion C2 may be located between the second connection portion 190b and the third connection portion 190c.

[0093] The first step portion C1 and the second step portion C2 may have inclined side surfaces, such that the width of the inclined side surfaces becomes narrower (or at least partially narrower) as they approach the second substrate 110. (See reference) Figure 3 The first step portion C1 and the second step portion C2 can be formed within the first upper insulating layer 132a and the second upper insulating layer 132b, respectively. As mentioned above, the first upper insulating layer 132a and the second upper insulating layer 132b can have a thickness greater than that of the interlayer insulating layer 132m.

[0094] The first stepped portion C1 can be located within the first upper insulating layer 132a, and the second stepped portion C2 can be located within the second upper insulating layer 132b. (See reference) Figure 3 The curved portion P1 and the first stepped portion C1 can be located between the first connecting portion 190a and the second connecting portion 190b. Similarly, the curved portion P2 and the second stepped portion C2 can be located between the second connecting portion 190b and the third connecting portion 190c. Therefore, as Figure 3 As shown, the two protruding portions P1 and C1 can be located between the first connecting portion 190a and the second connecting portion 190b. Similarly, the two protruding portions P2 and C2 can be located between the second connecting portion 190b and the third connecting portion 190c. This will be explained separately later, but it is a structure derived from the manufacturing process.

[0095] The first step C1 and the second step C2 are stop patterns etched during the manufacturing process (reference). Figure 9 and Figure 11 The area where (310, 320) are located. The width of the upper surface of the first step portion C1 and the second step portion C2 (the surface located away from the second substrate 110, as described below) can be the same as or similar to the width of the upper surface of the first gate penetration portion PH1, the second gate penetration portion PH2 and the third gate penetration portion PH3, and the width of the lower surface of the first step portion C1 and the second step portion C2 (the surface located near the second substrate 110) can be narrower than the width of the upper surface of the first gate penetration portion PH1, the second gate penetration portion PH2 and the third gate penetration portion PH3. Therefore, a step can be formed between the first step portion C1 and the bent portion P1, and a step can be formed between the second step portion C2 and the bent portion P2.

[0096] In the manufacturing process, since the etching stop pattern is formed in the first upper insulating layer 132a and the second upper insulating layer 132b, the first step portion C1 and the second step portion C2 can also be formed in the first upper insulating layer 132a and the second upper insulating layer 132b.

[0097] In other words, such as Figure 3 As shown, the width of each gate contact can vary discontinuously. Figure 3 The stepped and curved portions shown are areas where the width of the gate contact changes discontinuously. (Reference) Figure 3 The width of the gate contact differs at the boundary between the second connecting portion 190b and the first stepped portion C1. Specifically, the width of the second connecting portion 190b narrows as it approaches the substrate and then increases at the boundary with the first stepped portion C1. At this point, the width of the upper surface of the first stepped portion C1 is wider than the width of the lower surface of the second connecting portion 190b, resulting in a discontinuous increase in the width of the gate contact. Similarly, at the boundary between the first stepped portion C1 and the first connecting portion 190a, the width of the first connecting portion 190a can vary discontinuously. The width of the first connecting portion 190a increases as it moves away from the substrate and then narrows at the boundary with the first stepped portion C1. At this point, the width of the lower surface of the first stepped portion C1 is narrower than the width of the upper surface of the first connecting portion 190b, resulting in a discontinuous change in the width of the gate contact.

[0098] In other words, the discontinuous variation in the width of the gate contact portion in this specification means that the inner side of the gate contact portion includes a curved portion (stepped portion, bend). Although this specification shows a configuration in which misalignment does not occur at the boundaries of the first connection portion 190a, the second connection portion 190b, and the third connection portion 190c, it may also include a configuration in which misalignment occurs at the boundaries of the first connection portion 190a, the second connection portion 190b, and the third connection portion 190c.

[0099] Furthermore, in this specification, the discontinuous variation in the width of the gate contact includes width variations within the first connection portion 190a, the second connection portion 190b, and the third connection portion 190c (e.g., Figure 3 (As shown) and the configuration with different width variations within the step portions C1 and C2. That is, the imaginary straight lines extending along the inner sides of the first connecting portion 190a, the second connecting portion 190b and the third connecting portion 190c, as well as the imaginary straight lines extending along the inner sides of the step portions C1 and C2, may not be parallel to each other.

[0100] Thus, the configuration in which the width variations within the first connecting portion 190a, the second connecting portion 190b, and the third connecting portion 190c, as well as the configuration in which the width variations within the step portions C1 and C2 are different, is also included in the configuration in which the width of the gate contact portion varies discontinuously.

[0101] refer to Figure 3 The number of steps included in the gate contact portion 190 at each of the gate stack portions 121, 122 and 123 may be different.

[0102] refer to Figure 3 The gate contact portion 190 connected to the gate electrode 130 located at the first gate stack portion 121 may include a first step portion C1 and a second step portion C2.

[0103] Figure 4 A first gate contact 1901, connected to the first gate electrode 1301, is shown in a gate contact 190 that is connected to the gate electrode 130 located at the first gate stack portion 121. (See reference) Figure 4 The first gate contact portion 1901 may include a first step portion C1 and a second step portion C2, and the first gate contact portion 1901 may include bent portions P1 and P2 located at the boundaries of the first connection portion 190a, the second connection portion 190b and the third connection portion 190c.

[0104] Therefore, as Figure 4 As shown, the first gate contact 1901 may include two protrusions, P1 and C1, located between the first connecting portion 1901a and the second connecting portion 1901b. Both protrusions P1 and C1 may be located within the first upper insulating layer 132a. Similarly, the first gate contact 1901 may include two protrusions, P2 and C2, located between the second connecting portion 1901b and the third connecting portion 1901c. Both protrusions P2 and C2 may be located within the second upper insulating layer 132b.

[0105] That is, the gate contact 190 connected to the first gate stack portion 121 may include four protruding portions P1, P2, C1, C2.

[0106] although Figure 4 Although not shown, the second gate electrode 1302 to the twelfth gate electrode 1312 can be connected to the second gate contact to the twelfth gate contact, respectively. The second gate contact to the twelfth gate contact may also include two protrusions C1 and P1 located in the first upper insulating layer 132a, and two protrusions C2 and P2 located in the second upper insulating layer 132b.

[0107] Figure 5The thirteenth gate contact 1913 to the seventeenth gate contact 1917 are shown, connected to the gate electrode 130 located in the second gate stack portion 122. (See reference) Figure 5 The gate contact 190 connected to the gate electrode 130 located at the second gate stack portion 122 may include a second stepped portion C2. Additionally, the gate contact 190 located at the second gate stack portion 122 may include a second connecting portion 190b and a third connecting portion 190c, and may include a bent portion P2 located at the boundary between the second connecting portion 190b and the third connecting portion 190c. That is, the gate contact 190 located at the second gate stack portion 122 may include two protruding portions C2 and P2 between the second connecting portion 190b and the third connecting portion 190c. (Comparison) Figure 4 and Figure 5 The gate contact 190 connected to the first gate stack portion 121 may include four protrusions P1, P2, C1 and C2, and the gate contact 190 connected to the second gate stack portion 122 may include two protrusions P2 and C2.

[0108] refer to Figure 5 The thirteenth gate contact 1913 can be connected to the thirteenth gate electrode 1313, the fourteenth gate contact 1914 can be connected to the fourteenth gate electrode 1314, the fifteenth gate contact 1915 can be connected to the fifteenth gate electrode 1315, the sixteenth gate contact 1916 can be connected to the sixteenth gate electrode 1316, and the seventeenth gate contact 1917 can be connected to the seventeenth gate electrode 1317. Although not shown, the eighteenth gate electrode 1318 to the twenty-fourth gate electrode 1324 can be connected to the eighteenth gate contact to the twenty-fourth gate contact, respectively.

[0109] Figure 6 A twenty-fifth gate contact 1925 and a twenty-sixth gate contact 1926 are shown, connected to the gate electrode 130 located at the third gate stack portion 123. (See reference) Figure 6 The gate contact 190 located at the third gate stack portion 123 may not include a bent portion or a stepped portion. That is, the gate contact 190 connected to the third gate stack portion 123 includes a third connecting portion 190c, but does not include the first connecting portion 190a and the second connecting portion 190b. Therefore, the gate contact 190 connected to the third gate stack portion 123 may not include a stepped portion or a bent portion. (Reference) Figure 6The twenty-fifth gate contact 1925 can be connected to the twenty-fifth gate electrode 1325, and the twenty-sixth gate contact 1926 can be connected to the twenty-sixth gate electrode 1326. Although not shown, the twenty-seventh gate electrode 1327 to the thirty-sixth gate electrode 1336 can be connected to the twenty-seventh gate contact to the thirty-sixth gate contact, respectively.

[0110] As described above, the semiconductor device according to this embodiment may include two protruding portions P1 and C1 located between the first gate stack portion 121 and the second gate stack portion 122, and two protruding portions P2 and C2 located between the second gate stack portion 122 and the third gate stack portion 123. Specifically, the bent portion P1 and the first stepped portion C1 may be located in the first upper insulating layer 132a, and the bent portion P2 and the second stepped portion C2 may be located in the second upper insulating layer 132b.

[0111] When the gate contact 190 is formed through a length penetrating the first upper insulating layer 132a and the second upper insulating layer 132b, the gate contact 190 may include four protrusions P1, P2, C1, and C2. When the gate contact 190 is formed through a length penetrating the second upper insulating layer 132b but not through the first upper insulating layer 132a, the gate contact 190 may include two protrusions P2 and C2. Alternatively, if the gate contact 190 is formed through a length not penetrating the first upper insulating layer 132a and the second upper insulating layer 132b, the protrusions may not be included.

[0112] As will be explained separately later, the step portions C1 and C2 may be structures derived from a process used to simultaneously form a channel through portion for forming the channel CH of the cell array region 102 and a gate through portion for forming the gate contact portion 190 of the connection region 104.

[0113] In a previous embodiment, the channel CH was disclosed to include channel step portions CC1 and CC2 located between multiple channel portions CH1, CH2, and CH3. However, in another embodiment, the channel CH may not include the channel step portions CC1 and CC2 located between the multiple channel portions CH1, CH2, and CH3. That is, the channel bends CP1 and CP2 may be located between channel portions CH1, CH2, and CH3, and may not include the channel step portions CC1 and CC2.

[0114] Figure 7 An example of another implementation is shown. Figure 1 The same area. Except for the channel CH, which does not include the channel steps CC1 and CC2 located between the multiple channel sections CH1, CH2 and CH3. Figure 7 and Figure 1The implementation method is the same. Detailed descriptions of identical components are omitted. See references. Figure 7 The gate contact 190 located in the connection region 104 may include bends P1 and P2 and steps C1 and C2 respectively located between the first gate stack portion 121, the second gate stack portion 122 and the third gate stack portion 123. However, with Figure 1 In contrast, the channel CH located in the cell array region 102 may not include the channel step portions located between the multiple channel portions CH1, CH2, and CH3, but may only include the channel bends CP1 and CP2. The step portions C1 and C2, as well as the channel step portions CC1 and CC2, are areas where the etch stop pattern is located to prevent etching of the lower portion during the manufacturing process. In the case of channel portions CH1, CH2, and CH3, lower etching prevention is not a necessary configuration, and therefore, when etching channel portions CH1, CH2, and CH3 in the manufacturing process, the formation of the etch stop pattern can be omitted, and in this case, the channel CH may not include the channel step portions CC1 and CC2 located between the multiple channel portions CH1, CH2, and CH3.

[0115] In the following text, see references Figures 8 to 17 A method for manufacturing a semiconductor device according to some embodiments is described in more detail. Detailed descriptions of parts already described are omitted, and detailed descriptions of parts not described are provided.

[0116] Figures 8 to 17 This is a partial cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments. Figures 8 to 17 It shows the location Figure 1 The cell array region and connection region at parts A-A' and parts B-B'. The following describes the semiconductor device manufacturing method, focusing primarily on the gate stack structure 120, the channel structure CH, the isolation structure 146, and the gate contact 190.

[0117] like Figure 8 As shown, a second substrate 110 and a first sacrificial stack portion 121s can be formed on the circuit region 200, and a first channel sacrificial portion 126a can be formed in the cell array region.

[0118] The first sacrifice stack portion 121s can be corresponding to Figure 1 The first gate stack portion 121.

[0119] More specifically, a second substrate 110 can be formed on the circuit region 200, and a horizontal insulating layer 116 and a second horizontal conductive layer 114 can be formed on the second substrate 110. Then, a first sacrificial stack portion 121s can be formed by alternately stacking interlayer insulating layers 132m and sacrificial insulating layers 130s. For example, the first sacrificial stack portion 121s can be formed in the cell array region and the connection region, and can include a plurality of sacrificial insulating layers 130s and a plurality of interlayer insulating layers 132m that are alternately included with each other. A first upper insulating layer 132a can be located on the first sacrificial stack portion 121s. The thickness of the first upper insulating layer 132a can be thicker than the thickness of the interlayer insulating layers 132m.

[0120] The sacrificial insulating layer 130s is obtained through subsequent processes using the gate electrode ( Figure 1 The reference numeral 130 (which applies hereinafter the same) replaces the layer and can be formed to correspond to the portion where the gate electrode 130 is to be formed. At least a portion of the horizontal insulating layer 116 can be formed by a subsequent process from the first horizontal conductive layer ( Figure 1 (Ref. 112, which applies hereinafter the same) replaces the layer such that the horizontal insulating layer 116 includes the portion to which the first horizontal conductive layer 112 is to be formed.

[0121] The horizontal insulating layer 116 and / or the sacrificial insulating layer 130s may be formed of a material different from the interlayer insulating layer 132m. For example, the interlayer insulating layer 132m may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material, etc., and the sacrificial insulating layer 130s may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, and may be made of a material different from the interlayer insulating layer 132m.

[0122] Furthermore, the first channel sacrificial portion 126a can be formed to extend through the first sacrificial stack portion 121s in the cell array region. More specifically, the first channel sacrificial portion 126a can be formed to extend through the first sacrificial stack portion 121s, the horizontal insulating layer 116, and the second horizontal conductive layer 114.

[0123] For example, a first channel penetration portion H1 can be formed, which penetrates the channel structure to be formed ( Figure 1 The reference symbol CH (which also applies below) corresponds to the first sacrificial stack portion 121s, and sacrificial material can be filled into the first channel through portion H1 to form the first channel sacrificial portion 126a.

[0124] The first channel through-portion H1 can be formed by various processes (e.g., etching processes, etc.), and the process of filling the first channel through-portion H1 with a sacrificial material can be performed by various processes (e.g., deposition processes, etc.). The first channel sacrificial portion 126a may include at least one of metallic or non-metallic materials, such as polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the first channel sacrificial portion 126a may include various materials.

[0125] Next, as Figure 9 As shown, a first upper insulating layer 132a is formed over the first channel penetration portion H1 and the connection region 104 of the cell array region 102. In this step, the first upper insulating layer 132a may include the same material as the first upper insulating layer 132a formed in a previous step, and its boundary with the first upper insulating layer 132a formed in a previous step may be invisible. Subsequently, a first etch stop pattern 310 is formed within the first upper insulating layer 132a. The first etch stop pattern 310 may include, but is not limited to, a TIN.

[0126] The first etch stop pattern 310 can be formed through the first channel through portion H1 of the overlapping cell array region 102, and the first etch stop pattern 310 can also be formed on the connection region 104. As will be explained separately later, the first etch stop pattern 310 can be formed in the region where the gate through portion will be formed in the connection region 104 later.

[0127] The first etch stop pattern 310 can be used as an etch stop layer to prevent the first sacrificial stack portion 121s from being etched during the formation of the gate through portion in subsequent processes. For example... Figure 9 As shown, the first etch stop pattern 310 may have sloping sidewalls that narrow as they approach the second substrate 110. The first etch stop pattern 310 may be formed within the first upper insulating layer 132a. The width of the upper surface of the first etch stop pattern 310 may be the same as or similar to the width of the upper surface of the first channel penetration portion H1, and the width of the lower surface of the first etch stop pattern 310 may be narrower than the width of the upper surface of the first channel penetration portion H1. The first etch stop pattern 310 may be formed to contact the first channel penetration portion H1.

[0128] Next, refer to Figure 10 A second sacrificial stack portion 122s can be formed on the first sacrificial stack portion 121s.

[0129] The second sacrifice stack portion 122s can correspond to Figure 1This is a portion of the second gate stack portion 122. The second sacrificial stack portion 122 can be formed using the same process as the first sacrificial stack portion 121s. Specific descriptions of the same components are omitted. (See reference...) Figure 10 Interlayer insulating layers 132m and sacrificial insulating layers 130s can be alternately stacked to form a second sacrificial stack portion 122s. For example, the second sacrificial stack portion 122s can be formed in the cell array region and the connection region, and can include a plurality of sacrificial insulating layers 130s and a plurality of interlayer insulating layers 132m that are alternately included with each other. A second upper insulating layer 132b can be located on the first sacrificial stack portion 121s. The thickness of the second upper insulating layer 132b can be thicker than the thickness of the interlayer insulating layers 132m.

[0130] Next, a second channel penetration portion H2 can be formed in the unit array region 102, penetrating the second sacrificial stack portion 122s, and sacrificial material can be filled into the second channel penetration portion H2 to form a second channel sacrificial portion 126b. At this time, the second channel penetration portion H2 can be formed to overlap with the first channel penetration portion H1 formed in the previous step in the third direction (z direction). The second channel sacrificial portion 126b formed in this step can be connected integrally with the first channel sacrificial portion 126a formed in the previous step.

[0131] Specifically, a second channel penetration portion H2 can be formed through the second sacrificial stack portion 122s, the second sacrificial stack portion 122s corresponding to the channel structure to be formed ( Figure 1 The reference symbol CH (which also applies hereinafter) is used for the portion. Next, the first etch stop pattern 310 formed in the previous step through the second channel through portion H2 can be removed. Next, sacrificial material can be filled into the portion where the first etch stop pattern 310 has been removed and the second channel through portion H2 to form the second channel sacrificial portion 126b.

[0132] The second channel through-portion H2 can be formed by various processes (e.g., etching processes, etc.), and the process of filling the second channel through-portion H2 with sacrificial material can be performed by various processes (e.g., deposition processes, etc.). The second channel sacrificial portion 126b can include at least one of metallic or non-metallic materials, such as polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the second channel sacrificial portion 126b can include various materials.

[0133] At this point, the second gate through-partition PH2 can be formed in the connection region 104 using the same process as that used to form the second channel through-partition H2. The second gate through-partition PH2 can be formed by penetrating the second sacrificial stack portion 122s, and can be formed using the first etch stop pattern 310 as an etch stop layer. That is, the second gate through-partition PH2 can be formed up to the top of the first etch stop pattern 310. The second gate through-partition PH2 can have a sloped side surface, such that the sloped side surface narrows (or at least partially narrows) as it approaches the second substrate 110. Next, the first etch stop pattern 310 can be removed through the second gate through-partition PH2, and sacrificial material can be filled in the area where the first etch stop pattern 310 was removed and in the second gate through-partition PH2 to form the second sacrificial gate contact portion 196b. The sacrificial material filled in the second gate through-partition PH2 can be the same as the sacrificial material filled in the second channel through-partition H2.

[0134] exist Figure 10 For ease of explanation, only one second gate through-hole portion PH2 is shown in this diagram. However, the number of second gate through-hole portions PH2 formed in this step can be equal to the number of sacrificial insulating layers 130s located at the first sacrificial stack portion 121s. That is, each second gate through-hole portion PH2 can be connected to the first gate stack portion (…) through subsequent process steps. Figure 1 Each gate electrode 130 at reference number 121.

[0135] Next, refer to Figure 11 A second upper insulating layer 132b is formed on the second channel penetration portion H2 and the connection region 104 of the cell array region 102. In this step, the second upper insulating layer 132b may include the same material as the second upper insulating layer 132b formed in the previous step, and therefore, the boundary with the second upper insulating layer 132b formed in the previous step may not be identifiable. Subsequently, a second etch stop pattern 320 is formed within the second upper insulating layer 132b. The second etch stop pattern 320 may include, but is not limited to, a TIN.

[0136] The second etch stop pattern 320 can be formed through the second channel through portion H2 of the overlapping cell array region 102, and can also be formed on the connection region 104. As will be explained separately later, the second etch stop pattern 320 can be formed in the region where the gate through portion will be formed later in the connection region 104.

[0137] The second etch stop pattern 320 can be used as an etch stop layer to prevent the second sacrificial stack portion 122s from being etched during the formation process of the gate through portion in subsequent processes. For example... Figure 11 As shown, the second etch stop pattern 320 may have angled side surfaces, such that the width of the side surfaces becomes narrower (or at least partially narrower) closer to the second substrate 110. The second etch stop pattern 320 may be formed within the second upper insulating layer 132b. The width of the upper surface of the second etch stop pattern 320 may be the same as or similar to the width of the upper surface of the second channel penetration portion H2, and the width of the lower surface of the second etch stop pattern 320 may be narrower than the width of the upper surface of the second channel penetration portion H2. The second etch stop pattern 320 may be formed to contact the second channel penetration portion H2.

[0138] Next, refer to Figure 12 A third sacrificial stack portion 123s is formed on the second sacrificial stack portion 122s. The third sacrificial stack portion 123s can be corresponding to... Figure 1 The third gate stack portion 123 is a portion thereof. The third sacrificial stack portion 123 can be formed using the same process as the first sacrificial stack portion 121s and the second sacrificial stack portion 122s. Detailed descriptions of the same components are omitted. Reference Figure 12 Interlayer insulating layers 132m and sacrificial insulating layers 130s can be alternately stacked to form a third sacrificial stack portion 123s. For example, the third sacrificial stack portion 123s can be formed in the cell array region 102 and the connection region 104, and can include a plurality of sacrificial insulating layers 130s and a plurality of interlayer insulating layers 132m formed alternately with each other. A third upper insulating layer 132c can be located on the third sacrificial stack portion 123s.

[0139] Next, a third channel penetration portion H3 can be formed through the third sacrificial stack portion 123s in the unit array region 102, and sacrificial material can be filled into the third channel penetration portion H3 to form a third channel sacrificial portion 126c. At this time, the third channel penetration portion H3 can be formed to overlap with the first channel penetration portion H1 and the second channel penetration portion H2 formed in the previous step in the third direction (z direction). The third channel sacrificial portion 126c formed in this step can be connected to the first channel sacrificial portion 126a and the second channel sacrificial portion 126b formed in the previous step.

[0140] Specifically, this can correspond to the channel structure that will be formed ( Figure 1The reference symbol CH (which also applies hereinafter) is used to form a third channel through portion 123s, through which a third channel through portion 123s is formed. Next, the second etch stop pattern 320 formed in the previous step can be removed through the third channel through portion H3. Next, sacrificial material can be filled into the removed portion of the second etch stop pattern 320 and the third channel through portion H3 to form the third channel sacrificial portion 126c.

[0141] The third channel through-portion H3 can be formed by various processes (e.g., etching processes, etc.), and the process of filling the third channel through-portion H3 with sacrificial material can be performed by various processes (e.g., deposition processes, etc.). The third channel sacrificial portion 126c can include at least one of metallic or non-metallic materials, such as polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the third channel sacrificial portion 126c can include various materials.

[0142] At this point, the third gate through-partition PH3 can be formed in the connection region 104 using the same process as that used to form the third channel through-partition H3. The third gate through-partition PH3 can be formed by penetrating the third sacrificial stack portion 123s, and the second etch stop pattern 320 can be used as an etch stop layer. That is, the third gate through-partition PH3 can be formed up to the top of the second etch stop pattern 320. The third gate through-partition PH3 can have a sloping side surface, such that the width of the side surface narrows (or at least partially narrows) as it approaches the second substrate 110. Next, the second etch stop pattern 320 can be removed through the third gate through-partition PH3, and sacrificial material can be filled in the area where the second etch stop pattern 320 has been removed and in the third gate through-partition PH3 to form the third sacrificial gate contact portion 196c. The sacrificial material filled in the third gate through-partition PH3 can be the same as the sacrificial material filled in the third channel through-partition H3.

[0143] exist Figure 12 For ease of explanation, only six third gate through-portions PH3 are shown in this diagram. However, the number of third gate through-portions PH3 formed in this step can be equal to the number of sacrificial insulating layers 130s located on the first sacrificial stack portion 121s and the second sacrificial stack portion 122s. That is, each third gate through-portion PH3 can be connected to the first gate stack portion (…) through subsequent process steps. Figure 1 Reference numeral 1211) and the second gate stack portion ( Figure 1 Each gate electrode 130 at reference number 122.

[0144] Next, refer to Figure 13 A third upper insulating layer 132c is formed on the third sacrificial stack portion 123s. The thickness of the third upper insulating layer 132c formed in this step can be thicker than the thickness of the interlayer insulating layer 132m. In this step, the third upper insulating layer 132c can cover the upper part of the third channel through portion H3 and the upper part of the third gate through portion PH3.

[0145] Next, refer to Figure 14 This can remove the sacrificial material that fills the second gate penetration portion PH2 and the third gate penetration portion PH3 formed in the previous step.

[0146] Next, multiple first gate through-portions PH1, contacting each sacrificial insulating layer 130s, can be formed in the first sacrificial stack portion 121s using the second gate through-portion PH2 and the third gate through-portion PH3. Using the same process, second gate through-portions PH2, contacting each sacrificial insulating layer 130s, can be formed in the second sacrificial stack portion 122s using the third gate through-portion PH3. Additionally, third gate through-portions PH3, contacting each sacrificial insulating layer 130s, can be formed in the third sacrificial stack portion 123s using the same process. That is, the first gate through-portions PH1, second gate through-portions PH2, and third gate through-portions PH3 formed in this step can have different lengths and are formed to contact the sacrificial insulating layers 130s located in different layers one by one. During this process, each sacrificial insulating layer 130s can contact each gate through-portion.

[0147] exist Figure 14 In the first sacrificial stack portion 121s, for ease of explanation, only one first gate through portion PH1 is shown. However, the number of first gate through portions PH1 formed in this step can be equal to the number of sacrificial insulating layers 130s located in the first sacrificial stack portion 121s. Thus, each first gate through portion PH1 can be formed up to the first gate stack portion ( Figure 1 The upper part of each gate electrode 130 at reference numeral 121.

[0148] In addition, refer to Figure 14 In the second sacrificial stack portion 122s, the second gate through-port portion PH2 is formed through the third gate through-port portion PH3. Figure 14For ease of explanation, only five second gate through-portions PH2 are shown in this diagram. However, the number of second gate through-portions PH2 formed in this step can be equal to the number of sacrificial insulating layers 130s located in the second sacrificial stack portion 122s. Each second gate through-portion PH2 can be formed above each sacrificial insulating layer 130s located in the second sacrificial stack portion 122s. That is, each second gate through-portion PH2 can be formed up to the second gate stack portion ( Figure 1 The upper part of each gate electrode 130 at reference numeral 122.

[0149] exist Figure 14 For ease of explanation, only two third gate through-portions PH3 are shown in this diagram. However, the number of third gate through-portions PH3 formed in this step can be equal to the number of sacrificial insulating layers 130s located in the third sacrificial stack portion 123s. Each third gate through-portion PH3 can be formed above each sacrificial insulating layer 130s located in the third sacrificial stack portion 123s. That is, each third gate through-portion PH3 can be formed up to the third gate stack portion ( Figure 1 The upper part of each gate electrode 130 at reference numeral 123.

[0150] In other words, Figure 14 In this process, the second gate through-portion PH2 and the third gate through-portion PH3 formed in the previous steps can be simultaneously formed in the first sacrificial stack portion 121s, the second sacrificial stack portion 122s, and the third sacrificial stack portion 123s. The multiple gate through-portions formed at this time can have different lengths and can be formed to contact different sacrificial insulating layers 130s.

[0151] This implementation simplifies the process compared to forming the gate through-port in each of the first sacrificial stack portion 121s, the second sacrificial stack portion 122s, and the third sacrificial stack portion 123s.

[0152] exist Figure 14 In this embodiment, the process of simultaneously forming gate penetrations in contact with different sacrificial insulating layers 130s in the first sacrificial stack portion 121s, the second sacrificial stack portion 122s, and the third sacrificial stack portion 123s can be performed using a binary method with multiple partial etching processes. That is, in the embodiment, the position (position or height in the vertical direction) of the sacrificial insulating layer 130s to be replaced by the gate electrode 130 can be converted to binary, and multiple partial etching processes (e.g., first partial etching process to fourth partial etching process) can be performed accordingly to form gate penetrations with different depths.

[0153] According to the manufacturing method of this embodiment, the gate through-portions PH1, PH2, and PH3 are formed simultaneously during the process of forming the channel through-portions H1, H2, and H3. Therefore, compared with manufacturing methods that do not pre-form the gate through-portions PH1, PH2, and PH3, the number of multiple part etching processes using the binary method can be reduced.

[0154] Use examples to illustrate the reduction effect of specific processes. For example, in... Figure 1 In the manufacturing method of the semiconductor device including 36 layers of sacrificial insulating layers 130s, in order to form the gate through portion located on the upper part of the sacrificial insulating layer 130s up to each different layer by using a binary method, the following processes are required: a process for etching one layer of interlayer insulating layer 132m (first part etching process), a process for etching two layers of interlayer insulating layer 132m (second part etching process), a process for etching four layers of interlayer insulating layer 132m (third part etching process), a process for etching eight layers of interlayer insulating layer 132m (fourth part etching process), a process for etching 16 layers of interlayer insulating layer 132m (fifth part etching process), and a process for etching 32 layers of interlayer insulating layer 132m (sixth part etching process).

[0155] For better understanding and ease of explanation, the etching depth is described as the number of layers of interlayer insulating layer 132m, but this etching depth includes the depth of the sacrificial insulating layer 130s located between the interlayer insulating layers 132m.

[0156] The number 32, when converted to binary, is 100100. Through a sixth-part etching process (32-layer etching) and a third-part etching process (4-layer etching), 36 layers can be etched to form the first gate electrode. Figure 1 The gate through-portion (reference symbol 1301) is in contact with the reference symbol. Using binary as the same method, multiple gate through-portions can be formed that contact each gate electrode from the second gate electrode 1302 to the thirty-sixth gate electrode 1336. In other words, the maximum number of layers that should be etched in this process is 36.

[0157] However, as in this embodiment, when a portion of the gate through portions PH2 and PH3 are simultaneously formed in the process of forming the channel through portions H1, H2, and H3, the maximum number of layers that must be etched to form the gate through portion contacting each gate electrode 130 is reduced to 12. This is because some layers have already been etched in the previous steps by forming the gate through portions PH2 and PH3. Therefore, the gate through portion located up to the top of the sacrificial insulating layer 130s located at different layers can be formed by the following processes: etching one interlayer insulating layer 132m (first part etching process), etching two interlayer insulating layers 132m (second part etching process), etching four interlayer insulating layers 132m (third part etching process), and etching eight interlayer insulating layers 132m (fourth part etching process).

[0158] The number 12, when converted to binary, is 1100. By etching 12 layers using a fourth-part etching process (8-layer etching) and a third-part etching process (4-layer etching), a connection can be formed with the first gate electrode (…). Figure 1 The gate through-port (reference symbol 1301) is in contact with the gate electrode. Using the same binary method, multiple gate through-ports can be formed that contact each gate electrode from the second gate electrode 1302 to the thirty-sixth gate electrode 1336. For the first gate contact 1911 that contacts the first gate electrode 1301, 36 layers of interlayer insulating layer 132m must be etched if the gate through-ports PH2 and PH3 were not pre-etched. However, since the gate through-ports PH2 and PH3 are formed by an etching process in a previous step, and 24 layers have already been etched, the number of layers to be etched is reduced to 12. Therefore, the process can be simplified.

[0159] In this embodiment, for better understanding and ease of description, each sacrificial stack portion includes 12 interlayer insulating layers 132m, and the structure with 36 interlayer insulating layers 132m located in the entire semiconductor device is described as an example, but this is only an example, and the present invention is not limited thereto.

[0160] Next, refer to Figure 15 A protective insulating layer 190t and a through-sacrificial layer 190s can be formed within the gate penetration portion PH. At this stage, a first sacrificial gate contact portion 196a can be formed by filling the first gate penetration portion PH1 with the protective insulating layer 190t and the through-sacrificial layer 190s.

[0161] A protective insulating layer 190t can be formed within multiple gate penetration portions PH. For example, the protective insulating layer 190t can be formed on the inner surface and the bottom surface of each of the multiple gate penetration portions PH. The process for forming the protective insulating layer 190t can be performed by various processes (e.g., deposition processes, etc.). However, the implementation is not limited to this.

[0162] After forming the protective insulating layer 190t, a through-sacrificial layer 190s can be formed on the protective insulating layer 190t within the plurality of gate penetration portions PH. The through-sacrificial layer 190s may include at least one of a metallic or non-metallic material, such as polysilicon, tungsten, titanium nitride, and carbon. However, the embodiments are not limited thereto, and the through-sacrificial layer 190s may include various materials.

[0163] Next, as Figure 16 As shown, a channel structure CH, a gate electrode 130, and an isolation structure 146 can be formed.

[0164] More specifically, the sacrificial material filling the first channel penetration portion H1, the second channel penetration portion H2, and the third channel penetration portion H3 can be removed, and the gate dielectric layer can be formed sequentially. Figure 2 Reference number 150, which also applies below), channel layer ( Figure 2 Reference number 140 (which also applies below) and core insulation layer ( Figure 2 Reference numeral 142, which also applies hereinafter, can be used to refer to the first channel penetration portion H1, the second channel penetration portion H2, and the third channel penetration portion H3, and can form channel pads ( Figure 2 Reference number 144, which also applies below.

[0165] The process of forming the gate dielectric layer 150, the channel layer 140, the core insulating layer 142, or the channel pad 144 can be performed by various processes (e.g., deposition processes).

[0166] An opening for the isolation structure can be formed in the region corresponding to the isolation structure 146 to penetrate the first sacrificial stack portion 121s, the second sacrificial stack portion 122s, and the third sacrificial stack portion 123s, and the sacrificial insulating layer can be replaced by a gate electrode 130. Figure 15 (Ref. 130s), and the openings for the isolation structure can be filled with insulating materials, etc., to form the isolation structure 146.

[0167] In some embodiments, openings for the isolation structure can be formed using various processes (e.g., etching processes). The sacrificial insulating layer 130s can be selectively removed using an etching process (e.g., wet etching) through the openings for the isolation structure. The gate electrode 130 can be formed by filling the area where the sacrificial insulating layer 130s has been removed with a conductive material. In this way, the area where the sacrificial insulating layer 130s is located can be replaced with the gate electrode 130. At this time, a barrier layer can be further formed before the process of filling the conductive material forming the gate electrode 130. Figure 2 A portion of (reference numeral 156) (e.g., the first barrier layer) Figure 2 The process described in reference numeral 156a) is applicable. However, the implementation is not limited to this. The process of filling the openings for the isolation structure can be performed by various processes (e.g., deposition processes, etc.).

[0168] According to an embodiment, an opening for the isolation structure can be formed to expose the horizontal insulating layer 116. In an etching process through the opening for the isolation structure, at least a portion of the horizontal insulating layer 116 and a portion of the gate dielectric layer 150 can be removed, and the material constituting the first horizontal conductive layer 112 can be filled to form the first horizontal conductive layer 112.

[0169] According to an embodiment, an upper isolation region 148 may be formed in a portion of the gate stack structure 120. The upper isolation region 148 may be formed by forming an opening for an isolation pattern using an etching process with a mask layer and filling at least a portion of the opening for the isolation pattern with an insulating material. The process for forming the opening for the isolation pattern may be performed using various processes (e.g., etching processes, etc.). The process for forming the insulating material within the opening for the isolation pattern may be performed using various processes (e.g., deposition processes, etc.). The process for forming the opening for the isolation pattern and the process for forming the insulating material within the opening for the isolation pattern may be performed using various steps.

[0170] Next, as Figure 17 As shown, remove the penetrating sacrificial layer ( Figure 15 Reference number 190s in the text, which also applies below, and the protective insulation layer can be removed ( Figure 15 The lower portion (located on the upper surface of the gate electrode 130) of the reference numeral 190t (which also applies hereinafter) is used to form a side insulating layer 190i. Furthermore, a conductive material can be used to fill the gate penetration portion PH to form a conductive portion. In this way, a gate contact portion 190 can be formed.

[0171] The process of removing the through-sacrificial layer 190s can be performed by various processes (e.g., etching process, etc.), the process of removing the lower portion of the protective insulating layer 190t can be performed by various processes (e.g., etching process, etc.), and the process of forming the conductive portion can be performed by various processes (e.g., deposition process, etc.).

[0172] Next, unit line portions such as those connected to the bit lines of the channel structure CH can be formed to form, for example, Figure 1 The semiconductor device shown.

[0173] As described above, in the semiconductor device manufacturing method according to this embodiment, the process of forming the first channel through portion H1, the second channel through portion H2 and the third channel through portion H3 of the cell array region 102 can be simplified by simultaneously forming a portion of the gate through portions PH2 and PH3 of the connection region 104.

[0174] In structures that do not remove portions of the gate stack structure 120 (e.g., portions with a stepped shape) for electrical connection between the gate electrode 130 and the gate contact 190, complex processes may be required to form the gate contact 190 reaching each gate electrode 130. However, in this embodiment, the process is simplified by pre-etching portions of the gate contacts using an etch stop pattern. Furthermore, for known manufacturing processes, the thicknesses of the first upper insulating layer 130a and the second upper insulating layer 130b need to be similar to the thickness of the interlayer insulating layer 130m. This is because in a process that simultaneously etches multiple insulating layers, the thickness of each insulating layer should be similar to form the gate contact up to the desired gate electrode. In this case, when the thicknesses of the first upper insulating layer 130a and the second upper insulating layer 130b are similar to the thickness of the interlayer insulating layer 130m, insufficient allowance may occur due to misalignment at the boundaries of the gate contacts formed by different processes. However, in this embodiment, the etch stop pattern is located on the first upper insulating layer 130a and the second upper insulating layer 130b. Therefore, the thickness of the first upper insulating layer 130a and the second upper insulating layer 130b can be thicker than the thickness of the interlayer insulating layer 130m. And thus, sufficient margin due to misalignment can be ensured at the boundary of each gate contact.

[0175] The following describes in detail an example of an electronic system that includes the semiconductor devices described above.

[0176] Figure 18 This is a schematic diagram of an electronic system including semiconductor devices according to an exemplary embodiment.

[0177] refer to Figure 18The electronic system 1000 according to the embodiments may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0178] Semiconductor device 1100 may be a non-volatile memory device and may be a NAND flash memory device, for example, as referenced. Figures 1 to 18 Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In some embodiments, the first structure 1100F may be placed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0179] In the second structure 1100S, each memory cell string CSTR may include: lower transistors LT1 and LT2 adjacent to the common source line CSL; upper transistors UT1 and UT2 adjacent to the bit line BL; and a plurality of memory cell transistors MCTs arranged between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the implementation.

[0180] In some implementations, lower transistors LT1 and LT2 may include ground select transistors, and upper transistors UT1 and UT2 may include string select transistors. A first lower gate line LL1 and a second lower gate line LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. A word line WL may be the gate electrode of a memory cell transistor MCT, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0181] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0182] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one memory cell transistor selected from a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0183] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (host I / F) 1230. According to some embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, in which case the controller 1200 may control the plurality of semiconductor devices 1100.

[0184] Processor 1210 can control the operation of the entire electronic system 1000 (including controller 1200). Processor 1210 can operate according to predetermined firmware and control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface (NAND I / F) 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When a control command is received from an external host through host interface 1230, processor 1210 can respond to the control command to control semiconductor device 1100.

[0185] Figure 19 This is a schematic perspective view of an electronic system including semiconductor devices according to some embodiments.

[0186] refer to Figure 19According to some embodiments, the electronic system 2000 may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be interconnected with the controller 2002 via wire patterns 2005 formed on the main substrate 2001.

[0187] The main board 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In some embodiments, the electronic system 2000 may communicate with the external host via any of the following interfaces: such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In some embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0188] The controller 2002 can write data to or read data from the semiconductor package 2003, and improve the operating speed of the electronic system 2000.

[0189] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 can also function as a high-speed cache memory and provide temporary data storage space during the control operation of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0190] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include: a package substrate 2100; semiconductor chips 2200 located on the package substrate 2100; an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200; a connection structure 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100; and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0191] The package substrate 2100 may be a printed circuit board (PCB) including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 18 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include a reference... Figures 1 to 18 The semiconductor device described.

[0192] In some embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to an embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including through-silicon vias (TSVs) instead of a bonding wire type connection structure 2400.

[0193] In some implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, separate from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via wires formed on the interposer substrate.

[0194] Figure 20This is a schematic cross-sectional view of a semiconductor package according to some embodiments. Figure 20 It shows Figure 19 An embodiment of the semiconductor package 2003 is conceptually illustrated along... Figure 19 The area cut by the cross-section line I-I' of the semiconductor package 2003.

[0195] refer to Figure 20 In the semiconductor package 2003, the package substrate 2100 can be a printed circuit board (PCB). The package substrate 2100 may include: a package substrate body portion 2120; an upper package pad 2130 disposed on the upper surface of the package substrate body portion 2120; a lower package pad 2125 disposed on or exposed through the bottom surface of the package substrate body portion 2120; and an internal conductor 2135 electrically connecting the upper package pad 2130 and the lower package pad 2125 within the package substrate body portion 2120. The upper package pad 2130 can be electrically connected to a connection structure 2400. The lower package pad 2125 can be connected via a conductive connection 2800 to, for example,... Figure 19 The wiring pattern 2005 of the main substrate 2001 of the electronic system 2000 shown.

[0196] Semiconductor chip 2200 may each include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, which includes a peripheral line 3110. The second structure 3200 may include: a common source line 3205; a gate stack structure 3210 located on the common source line 3205; a channel structure 3220 and an isolation structure 3230 extending through the gate stack structure 3210; a bit line 3240 electrically connected to the channel structure 3220; and a gate connection line electrically connected to the word line WL of the gate stack structure 3220.

[0197] In the semiconductor chip 2200 or semiconductor device according to the embodiment, a portion of the gate through-portion of the connection region is simultaneously formed during the formation process of the channel through-portion in the cell array region. Therefore, the manufacturing process can be simplified by reducing the number of partial etching processes used to etch the gate through-portion. Through this process, the gate through-portion can include a stepped portion by forming and removing an etch stop pattern.

[0198] Each of the semiconductor chips 2200 may include a through-line 3245 electrically connected to the peripheral line 3110 of the first structure 3100 and extending into the second structure 3200. The through-line 3245 may pass through the gate stack structure 3210 and may be further disposed on the outside of the gate stack structure 3210. Each of the semiconductor chips 2200 may also include an input / output connection line 3265 and an input / output pad 2210, the input / output connection line 3265 being electrically connected to the peripheral line 3110 of the first structure 3100 and extending into the second structure 3200, and the input / output pad 2210 being electrically connected to the input / output connection line 3265.

[0199] In some embodiments, a plurality of semiconductor chips 2200 in the semiconductor package 2003 may be electrically connected to each other via a connection structure 2400 in the form of bonding wires. As another example, a plurality of semiconductor chips 2200 or a plurality of portions constituting the semiconductor chips 2200 may be electrically connected via a connection structure including through electrodes.

[0200] Although the embodiments have been described in detail above, the scope of the invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the invention as defined in the claims may also fall within the scope of the invention.

[0201] While this specification contains details of numerous specific embodiments, these details should not be construed as limiting the scope of any invention or the scope claimed, but rather as descriptions of features specific to particular embodiments of the invention. Certain features described herein in the context of individual embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of individual embodiments can also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described foregoing as functioning in certain combinations, one or more features from a combination may, in some cases, be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor device, the semiconductor device comprising: substrate; A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of gate electrodes, wherein each of the plurality of interlayer insulating layers and each of the plurality of gate electrodes are alternately stacked on the substrate; A channel structure extending through the gate stack structure; and A plurality of gate contacts, each gate contact (i) extending into at least a portion of the gate stack structure and (ii) connected to a corresponding gate electrode among the plurality of gate electrodes. The gate stack structure includes a first gate stack structure, a second gate stack structure, and a first upper insulating layer, wherein the first upper insulating layer is located between the first gate stack structure and the second gate stack structure. The first gate stack structure, the first upper insulating layer, and the second gate stack structure are sequentially stacked on the substrate. Wherein, at least one of the plurality of gate contacts is a first gate contact connected to a corresponding first gate electrode of the first gate stack structure. Each of the at least one first gate contact portion includes a stepped portion and a bent portion. Wherein, the width of each of the at least one first gate contact portion varies discontinuously, and The stepped portion and the curved portion are located within the first upper insulating layer.

2. The semiconductor device according to claim 1, wherein, Each of the at least one first gate contact includes a first connection portion and a second connection portion, the first connection portion extending into the first gate stack structure, and the second connection portion extending into the second gate stack structure. The stepped portion is located between the first connecting portion and the second connecting portion.

3. The semiconductor device according to claim 2, wherein, The stepped portion has a width that decreases at least partially towards the substrate, and The lower surface of the stepped portion is located within the first upper insulating layer.

4. The semiconductor device according to claim 3, wherein, Each of the first connecting portion and the second connecting portion has a width that decreases at least partially towards the substrate, and The bent portion is located between the first connecting portion and the second connecting portion, and The width of the curved portion is different from the width of the upper surface of the first connecting portion and the lower surface of the second connecting portion.

5. The semiconductor device according to claim 4, wherein, The curved portion is closer to the substrate than the stepped portion.

6. The semiconductor device according to claim 1, wherein, The channel structure includes: (i) a first channel portion extending into the first gate stack structure, (ii) a second channel portion extending into the second gate stack structure, and (iii) a channel step portion located between the first channel portion and the second channel portion.

7. The semiconductor device according to claim 6, wherein, The width of the channel step portion decreases at least partially toward the substrate, and The lower surface of the channel step portion is located within the first upper insulating layer.

8. The semiconductor device according to claim 7, wherein, The width of each of the first channel portion and the second channel portion decreases at least partially toward the substrate. The curved section of the channel is located between the first channel portion and the second channel portion, and A portion of the curved section of the channel is defined at least based on the width difference between the upper surface of the first channel portion and the lower surface of the second channel portion.

9. The semiconductor device according to claim 8, wherein, The curved portion of the channel is closer to the substrate than the stepped portion of the channel.

10. The semiconductor device according to claim 1, wherein, The gate stack structure further includes a second upper insulating layer and a third gate stack structure, wherein the second upper insulating layer is located on the second gate stack structure, and the third gate stack structure is located on the second upper insulating layer. Each of the at least one first gate contact portion further includes a second step portion and a second bend portion located within the second upper insulating layer.

11. The semiconductor device according to claim 10, wherein, At least one of the plurality of gate contacts is connected to a corresponding second gate electrode of the second gate stack structure, and Wherein, at least one second gate contact extends into the second gate stack structure and the third gate stack structure. Each of the at least one second gate contact portion includes a stepped portion and a bent portion located within the second upper insulating layer, and The width of each of the at least one second gate contact varies discontinuously.

12. The semiconductor device according to claim 10, wherein, At least one of the plurality of gate contacts is a third gate contact connected to a corresponding third gate electrode of the third gate stack structure, and Each of the at least one third gate contact extends into at least a portion of the plurality of gate electrodes of the third gate stack structure.

13. The semiconductor device according to claim 1, wherein, The gate stack structure includes a second upper insulating layer located on the second gate stack structure, and The thickness of each of the first upper insulating layer and the second upper insulating layer is greater than the thickness of each of the interlayer insulating layers.

14. The semiconductor device according to claim 1, wherein, The gate stack structure includes a cell array region and a connection region, the channel structure is located in the cell array region, and the plurality of gate contacts are located in the connection region. Wherein, at least a portion of each of the plurality of gate contacts extends at the connection region into a corresponding second gate electrode located above the corresponding gate electrode connected to each gate contact.

15. A semiconductor device, the semiconductor device comprising: substrate; A gate stack structure, the gate stack structure including a plurality of interlayer insulating layers and a plurality of gate electrodes, wherein each of the plurality of interlayer insulating layers and each of the plurality of gate electrodes are alternately stacked on the substrate, wherein the gate stack structure includes a first gate stack structure, a second gate stack structure and a third gate stack structure sequentially stacked on the substrate; A channel structure that extends through the gate stack structure; A plurality of gate contacts, each gate contact (i) extending into a portion of the gate stack structure and (ii) connected to a corresponding gate electrode among the plurality of gate electrodes; A first upper insulating layer is located between the first gate stack structure and the second gate stack structure; and A second upper insulating layer is located between the second gate stack structure and the third gate stack structure. The first gate contact among the plurality of gate contacts is connected to the first gate electrode located in the first gate stack structure among the plurality of gate electrodes. The first gate contact portion includes: A first curved portion and a first stepped portion, the first curved portion and the first stepped portion being located within the first upper insulating layer; and The second curved portion and the second stepped portion are located within the second upper insulating layer. The second gate contact among the plurality of gate contacts is connected to the second gate electrode located in the second gate stack structure among the plurality of gate electrodes. The second gate contact portion includes: The third bend and the third step are located within the second upper insulating layer, and The third gate contact of the plurality of gate contacts (i) is connected to the third gate electrode of the plurality of gate electrodes located in the third gate stack structure, and (ii) extends into at least a portion of the third gate stack structure.

16. The semiconductor device according to claim 15, wherein, The width of each of the first step portion, the second step portion, and the third step portion decreases at least partially toward the substrate.

17. The semiconductor device according to claim 16, wherein, Each of the first bend, the second bend, and the third bend is closer to the substrate than the corresponding step portion of the first step, the second step, and the third step.

18. The semiconductor device of claim 15, wherein, The thickness of each of the first upper insulating layer and the second upper insulating layer is greater than the thickness of each interlayer insulating layer.

19. The semiconductor device according to claim 15, wherein, The gate stack structure includes a cell array region and a connection region, the channel structure is located in the cell array region, and the plurality of gate contacts are located in the connection region. Wherein, at least a portion of each of the plurality of gate contacts extends at the connection region into a fourth gate electrode located above the corresponding gate electrode connected to each gate contact.

20. An electronic system, the electronic system comprising: main substrate; A semiconductor device located on the main substrate; as well as A controller, which is connected to the semiconductor device on the main substrate, The semiconductor device includes: substrate, A gate stack structure comprising a plurality of interlayer insulating layers and a plurality of gate electrodes, wherein each of the plurality of interlayer insulating layers and each of the plurality of gate electrodes are alternately stacked on the substrate; A channel structure extending through the gate stack structure, and Multiple gate contacts, each gate contact (i) extending into a portion of the gate stack structure and (ii) connected to a corresponding gate electrode among the multiple gate electrodes. The gate stack structure includes a first gate stack structure and a second gate stack structure. With a first upper insulating layer located between the first gate stack structure and the second gate stack structure, the first gate stack structure and the second gate stack structure are stacked. At least one of the plurality of gate contacts is connected to the first gate electrode of the first gate stack structure. Each of the at least one first gate contact portion includes a stepped portion and a bent portion located within the first upper insulating layer, and The width of each of the at least one first gate contact varies discontinuously.

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