Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device capable of forming a more suitable stacked structure and a method for manufacturing the same are provided. The semiconductor memory device comprises a first columnar portion, a second columnar portion, and a separating portion, formed by alternating stacking of multiple first conductive layers and multiple first insulating layers in a first direction. The first columnar portion is disposed in a first region of the stack and includes a first semiconductor portion. The second columnar portion is disposed in a second region of the stack, extends within the stack along the first direction, and includes an insulator. The separating portion extends within the stack in the first direction and in a second direction intersecting the first direction, separating the first region and the second region. The number of layers in the first columnar portion is different from the number of layers in the second columnar portion and the separating portion. A first bridging portion is also provided at the joint of the separating portion between adjacent layers. The position of the first bridging portion in the first direction is the position of the middle portion between the upper and lower ends of the first columnar portion in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices and methods for manufacturing the same. Background Technology

[0002] In three-dimensional non-volatile memory, to improve the integration density of memory cells, it is known that the arrangement of memory cells in multiple columns is arranged relative to a pillar in the height direction. In this type of three-dimensional non-volatile memory, the word lines stacked in the height direction of the pillars must be finely subdivided without collapsing. Summary of the Invention

[0003] The present invention provides a semiconductor memory device capable of forming a more suitable stacked structure and a method thereof.

[0004] The semiconductor memory device of this embodiment includes a stack of multiple first conductive layers and multiple first insulating layers alternately stacked in a first direction. The stack has a first columnar portion, a second columnar portion, and a separating portion. The first columnar portion is disposed in a first region of the stack and includes a first semiconductor portion extending in the first direction within the stack and a first insulating portion disposed on the outer peripheral surface of the first semiconductor portion. The second columnar portion is disposed in a second region of the stack, extends in the first direction within the stack, and includes an insulator. The separating portion extends in the stack in the first direction and in a second direction intersecting the first direction, separating the first region and the second region. The number of layers in the first columnar portion is different from the number of layers in the second columnar portion and the separating portion. A first bridging portion is also provided at the joint of the separating portion between adjacent layers. The position of the first bridging portion in the first direction is the position of the middle portion between the upper and lower ends of the first columnar portion in the first direction. Attached Figure Description

[0005] Figure 1 This is a perspective view illustrating a semiconductor memory device according to the first embodiment.

[0006] Figure 2 This is a top view representing a stacked body.

[0007] Figure 3 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0008] Figure 4 This is a cross-sectional view representing an example of a three-dimensional storage unit.

[0009] Figure 5 This is a top view showing an example of a semiconductor memory device according to the first embodiment.

[0010] Figure 6 It is a top-down view showing the layout of the connection area and storage unit area.

[0011] Figure 7A It is a three-dimensional diagram representing the general connection area of ​​the block.

[0012] Figure 7B It is a three-dimensional diagram representing the general connection area of ​​the block.

[0013] Figure 8A It is a top view that shows the several conductive layers of the connection area in more detail.

[0014] Figure 8B It is a top view that shows the several conductive layers of the connection area in more detail.

[0015] Figure 9 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0016] Figure 10 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0017] Figure 11A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0018] Figure 11B It means to continue Figure 11A A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0019] Figure 11C It means to continue Figure 11B A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0020] Figure 11D It means to continue Figure 11C A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0021] Figure 11E It means to continue Figure 11D A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0022] Figure 11F It means to continue Figure 11E A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0023] Figure 12A This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the first embodiment.

[0024] Figure 12B It means to continue Figure 12A A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0025] Figure 12CIt means to continue Figure 12B A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0026] Figure 12D It means to continue Figure 12C A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0027] Figure 12E It means to continue Figure 12D A perspective view of an example of a method for manufacturing a semiconductor memory device.

[0028] Figure 13 This is a top view showing an example of the configuration of the semiconductor memory device according to the second embodiment.

[0029] Figure 14 This is a top view showing an example of the configuration of the semiconductor memory device according to the third embodiment.

[0030] Figure 15 This is a top view showing an example of the configuration of the semiconductor memory device according to the fourth embodiment.

[0031] Figure 16 This is a top view showing an example of the configuration of the semiconductor memory device according to the fifth embodiment.

[0032] Figure 17 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to the sixth embodiment. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts, etc., may not be the same as in reality. In the specification and drawings, elements identical to those described in previously seen drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0034] (First Implementation)

[0035] [First Configuration Example of a Semiconductor Storage Device]

[0036] Figure 1 This is a perspective view illustrating the semiconductor memory device 100 according to the first embodiment. Figure 2 This is a top view showing the laminate 2. In this specification, the lamination direction of the laminate 2 is defined as the Z-axis direction. A direction orthogonal to the Z-axis direction is defined as the Y-axis direction. A direction orthogonal to both the Z and Y axes is defined as the X-axis direction. Figure 3 and Figure 4 These are cross-sectional views representing an example of a three-dimensional storage unit. Figure 5This is a top view showing an example of the semiconductor memory device 100 according to the first embodiment. For example... Figures 1-5 As shown, the semiconductor memory device 100 of the first embodiment is a non-volatile memory having a three-dimensional memory cell array.

[0037] The semiconductor memory device 100 includes a substrate 1, a laminate 2, a plate-shaped portion 3, a plurality of columnar portions CL, and a plurality of insulating columns CLHR.

[0038] The substrate 1 includes a semiconductor wafer (substrate) 10, an insulating film 11, a conductive film 12, and a semiconductor portion 13. The insulating film 11 is disposed on the semiconductor wafer 10. The conductive film 12 is disposed on the insulating film 11. The semiconductor portion 13 is disposed on the conductive film 12. The semiconductor wafer 10 is, for example, a silicon wafer. The conductivity type of the semiconductor wafer 10 is, for example, p-type. A component separation region 10i is, for example, disposed on the surface region of the semiconductor wafer 10. The component separation region 10i is, for example, an insulating region containing a silicon oxide film. An active region AA is defined on the surface region of the semiconductor wafer 10. The source and drain regions of a transistor Tr are disposed in the active region AA. The transistor Tr constitutes a CMOS (Complementary Metal Oxide Semiconductor) circuit as a control circuit for non-volatile memory. The insulating film 11 contains, for example, a silicon oxide film, insulating the transistor Tr. A wiring 11a is disposed within the insulating film 11. The wiring 11a is electrically connected to the transistor Tr. The conductive film 12 contains a conductive metal, for example, tungsten (W). Semiconductor section 13 may, for example, contain n-type silicon. A portion of semiconductor section 13 may also contain undoped silicon.

[0039] The laminate 2 is positioned above the semiconductor section 13 in the Z-axis direction. The laminate 2 is constructed by alternately stacking multiple conductive layers 21 (as multiple first conductive layers) and multiple insulating layers 22 (as multiple first insulating layers) in the Z-axis direction. The multiple conductive layers 21 are stacked at intervals, separated from each other by insulating layers 22. The conductive layers 21 contain conductive metals, such as tungsten. The insulating layers 22 contain, for example, silicon oxide. The insulating layers 22 insulate the conductive layers 21 from each other. The number of stacked conductive layers 21 and insulating layers 22 is arbitrary. The insulating layers 22 can also be gaps, for example. An insulating film 2g is provided between the laminate 2 and the semiconductor section 13, for example. The insulating film 2g contains, for example, a silicon oxide film. The insulating film 2g can also contain a high dielectric material with a higher relative permittivity than silicon oxide. The high dielectric material can be, for example, an oxide such as hafnium oxide.

[0040] The conductive layer 21 includes at least one source-side selected gate (SGS), a plurality of word lines (WL), and at least one drain-side selected gate (SGD). The source-side selected gate (SGS) is the gate electrode of a source-side selected transistor (STS). The word lines (WL) are the gate electrodes of memory cells (MC). The drain-side selected gate (SGD) is the gate electrode of a drain-side selected transistor (STD). The source-side selected gate (SGS) is disposed in the lower region of the stack 2. The drain-side selected gate (SGD) is disposed in the upper region of the stack 2. The lower region refers to the region of the stack 2 closest to the substrate portion 1, and the upper region refers to the region of the stack 2 furthest from the substrate portion 1. The word lines (WL) are disposed between the source-side selected gate (SGS) and the drain-side selected gate (SGD).

[0041] The thickness of the insulating layer 22 that insulates the source-side select gate SGS from the word line WL in the Z-axis direction can, for example, be thicker than the thickness of the insulating layer 22 that insulates the word lines WL from each other in the Z-axis direction. Furthermore, a protective insulating film can be provided on the uppermost insulating layer 22, which is furthest from the substrate 1. The protective insulating film may, for example, comprise silicon oxide.

[0042] Semiconductor memory device 100 has multiple memory cells MC connected in series between a source-side selection transistor STS and a drain-side selection transistor STD. The structure in which the source-side selection transistor STS, memory cells MC, and drain-side selection transistor STD are connected in series is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a connector Cb. The bit line BL is positioned above the stack 2 and extends along the Y-axis.

[0043] Multiple deep slits (ST) and multiple shallow slits (SHE) are provided within the laminate 2. For example... Figure 2 As shown, the slit ST extends along the X-axis in the planar layout. In addition, in the cross-section of the Z-direction (stack direction), the slit ST penetrates the stacked body 2 from the upper end of the stacked body 2 to the base part 1 and is provided within the stacked body 2. Figure 2 A plate-shaped portion 3 is disposed within the slit ST. The plate-shaped portion 3 may be an insulating film, such as a silicon oxide film. Alternatively, the plate-shaped portion 3 may be made of a conductive metal, such as a conductive material (e.g., tungsten, copper), which is electrically connected to the semiconductor portion 13, and is electrically insulated from the laminate 2 by the insulating film. The slit SHE extends approximately parallel to the slit ST along the X-axis in a planar layout. Furthermore, in a cross-section along the Z-direction, the slit SHE extends from the top of the laminate 2 to the middle of the laminate 2. An insulator 4 is disposed within the slit SHE, for example. The insulator 4 may be an insulating film, such as a silicon oxide film.

[0044] like Figure 2As shown, the laminate 2 includes a stepped portion 2s and a memory cell array MCA. The stepped portion 2s is disposed at the edge of the laminate 2. The memory cell array MCA is held or surrounded by the stepped portion 2s. A slit ST is disposed from the stepped portion 2s at one end of the laminate 2 through the memory cell array MCA to the stepped portion 2s at the other end of the laminate 2. The slit ST is disposed at least in the memory cell array MCA.

[0045] The portion of the stack 2 sandwiched between two slits ST (plate-like portions 3) is called a block BLK. The block, for example, constitutes the smallest unit for data erasure. A slit SHE (insulator 4) is disposed within the block. The stack 2 between the slits ST and SHE is called a finger. The drain-side select gate SGD is divided for each finger. Therefore, during data writing and reading, one finger within the block can be selected via the drain-side select gate SGD.

[0046] like Figure 5 As shown, the memory cell array MCA includes cell regions and the area outside them. Within the cell region, multiple columnar sections CL are disposed within memory apertures MH. Outside the cell region, a tap region, a stepped area SSA, and a bridging area BRA are disposed. The tap region Tap is disposed in block BLK, which is adjacent to the stepped area SSA and the bridging area BRA in the Y direction, separated by a slit ST. Figure 6 As shown, the tap area (Tap) can also be positioned between the unit areas in the X direction. The stepped area (SSA) and bridging area (BRA) can also be positioned between the unit areas in the X direction. The stepped area (SSA) is for multiple contact plugs (CC). For example... Figure 6 As shown, the bridging region BRA is provided to electrically connect the word lines WL of adjacent blocks BLK in the X direction, separated by the step region SSA. The tap region Tap is the area for the contact plug C4. Contact plugs CC and C4 extend, for example, along the Z-axis direction. Contact plug CC is electrically connected to conductive layer 21, for example. Contact plug C4 is electrically connected to wiring 11a, for example, to supply power to transistor Tr. Contact plugs CC and C4 are made of low-resistance metals such as copper or tungsten.

[0047] An insulating film (not shown) is provided around each of the contact plugs CC and C4. This provides electrical insulation between the contact plugs CC and C4 and the laminate 2. Thus, while maintaining insulation from the laminate 2, the contact plugs CC and C4 can electrically connect wiring above the laminate 2 to wiring below the laminate 2. The insulating film may be, for example, a silicon oxide film.

[0048] Multiple columnar portions CL are respectively disposed within memory holes MH provided within the laminate 2. The memory holes MH extend from the top end of the laminate 2 along the lamination direction (Z-axis direction) and into the laminate 2 and the semiconductor portion 13. For example... Figure 3 and Figure 4 As shown, the plurality of columnar portions CL each include a semiconductor body 210, a memory film 220, and a core layer 230, which serve as semiconductor pillars. The semiconductor body 210 extends within the laminate 2 along its lamination direction (Z direction) and is electrically connected to the semiconductor portion 13. The memory film 220 has a charge trapping portion between the semiconductor body 210 and the conductive layer 21. The plurality of columnar portions CL, selected sequentially from each finger portion, are commonly connected to a bit line BL via a connector Cb. The columnar portions CL are respectively provided, for example... Figure 5 The cell region.

[0049] like Figure 3 and Figure 4 As shown, the shape of the memory aperture MH in the XY plane is, for example, a circle or an ellipse. A barrier insulating film 21a, forming part of the memory film 220, may also be provided between the conductive layer 21 and the insulating layer 22. The barrier insulating film 21a is, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 21b may also be provided between the conductive layer 21 and the insulating layer 22, and between the conductive layer 21 and the memory film 220. For example, if the conductive layer 21 is tungsten, the barrier film 21b may be a laminated structure of titanium nitride and titanium. The barrier insulating film 21a suppresses reverse tunneling of charge from the conductive layer 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the conductive layer 21 and the barrier insulating film 21a.

[0050] The semiconductor body 210 is, for example, cylindrical in shape. The semiconductor body 210 contains, for example, silicon. The silicon is, for example, polycrystalline silicon formed by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor (STD), the memory cell (MC), and the source-side selection transistor (STS).

[0051] The portion of the memory film 220 other than the barrier insulating film 21a is disposed between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical. A plurality of memory cells MC have storage regions between the semiconductor body 210 and the conductive layer 21, which forms the word line WL, and are stacked in the Z-axis direction. The memory film 220 includes, for example, a protective insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 each extend along the Z-axis direction.

[0052] A protective insulating film 221 is disposed between the insulating layer 22 and the charge trapping film 222. The protective insulating film 221 is, for example, made of silicon oxide. The protective insulating film 221 is provided to protect the charge trapping film 222 from etching when the sacrificial film disposed between the insulating layers 22 is replaced with the conductive layer 21 during the manufacturing process. The protective insulating film 221 can also be removed from between the conductive layer 21 and the memory film 220 during a replacement process. In this case, such as Figure 3 and Figure 4 As shown, a barrier insulating film 21a is provided, for example, between the conductive layer 21 and the charge trapping film 222. Alternatively, if the formation of the conductive layer 21 does not require a replacement process, the protective insulating film 221 may not be provided.

[0053] A charge trapping film 222 is disposed between the barrier insulating film 21a, the protective insulating film 221, and the tunnel insulating film 223. The charge trapping film 222 may contain, for example, silicon nitride and has trapping portions within the film for trapping charges. The portion of the charge trapping film 222 sandwiched between the conductive layer 21 (which forms the word line WL) and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trapping section. The threshold voltage of the memory cell MC varies depending on the presence or absence of charge in the charge trapping section, or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC is able to retain information.

[0054] A tunnel insulating film 223 is disposed between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 may be made of silicon oxide, or silicon oxide and silicon nitride, for example. The tunnel insulating film 223 acts as a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 into the charge trapping section (writing operation) and when holes are injected from the semiconductor body 210 into the charge trapping section (erasing operation), electrons and holes respectively pass through (tunnel) the barrier of the tunnel insulating film 223.

[0055] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 uses an insulating film such as silicon oxide film.

[0056] Figure 5Multiple insulating pillars CLHR shown are respectively disposed within holes HR provided in the laminate 2. The holes HR penetrate the laminate 2 from the top end along the Z-axis and are disposed within the laminate 2 and the semiconductor section 13. The insulating pillars CLHR are, for example, insulating materials such as silicon oxide films. In addition, the insulating pillars CLHR can each have the same structure as the columnar portion CL. The insulating pillars CLHR are respectively disposed in, for example, the tap region, the stepped region SSA, and the bridging region BRA. When the sacrificial film (not shown) is replaced with the conductive layer 21 (replacement process), the insulating pillars CLHR function as support members to retain the gaps formed in the stepped region and the tap region. The holes HR of the insulating pillars CLHR have a larger diameter (width in the X or Y direction) than the columnar portion CL.

[0057] like Figure 1 As shown, the semiconductor memory device 100 further includes a semiconductor section 14. The semiconductor section 14 is located between the laminate 2 and the semiconductor section 13. The semiconductor section 14 is disposed between the insulating layer 22 closest to the semiconductor section 13 and the insulating film 2g in the insulating layer 22. The conductivity type of the semiconductor section 14 is, for example, n-type. The semiconductor section 14 functions, for example, as a source-side select gate (SGS).

[0058] Figure 6 This is a schematic top view showing the layout of the connection area 101 and the memory cell area 100a. The memory cell area 100a includes a first memory cell area 100a_1 and a second memory cell area 100a_2 that are adjacent to each other. The first memory cell area 100a_1 and the second memory cell area 100a_2 each contain a plurality of blocks BLK. In the Y direction, the plurality of blocks BLK are respectively divided by slits ST extending along the X direction.

[0059] Both the first storage cell region 100a_1 and the second storage cell region 100a_2 have the plurality of columnar portions CL (memory holes MH) and have a plurality of storage cells arranged in three dimensions. The storage cells are formed at the intersections of a plurality of word lines WL and columnar portions CL.

[0060] For convenience, the block BLK belonging to the first storage cell region 100a_1 will be referred to as block BLK_1. Similarly, the block BLK belonging to the second storage cell region 100a_2 will be referred to as block BLK_2.

[0061] The connection region 101 is located in the X direction, which intersects the Z direction, between the first storage cell region 100a_1 and the second storage cell region 100a_2. For each block BLK, it has a tap region (Tap), a step region (SSA), and a bridging region (BRA). The step region (SSA) and the bridging region (BRA) are also referred to below as step regions (SSA), etc.

[0062] As described above, the tap area (Tap) and the stepped area (SSA), etc., are adjacent in the Y direction, separated by a slit (ST). Figure 6 As shown, the tap area and the step area SSA are alternately arranged in the Y direction. Furthermore, although not shown, the tap area and the step area SSA are also alternately arranged in the X direction. That is, the tap area and the step area SSA are alternately arranged in the Y direction separated by a slit ST, and alternately arranged in the X direction separated by memory areas (blocks BLK).

[0063] In the stepped region SSA, the select gate line (source-side select gate) SGS and multiple word lines WL each have a step difference in the X direction from the lower layer, forming a stepped shape. In other words, in the stepped region SSA, the select gate line SGS and multiple word lines WL each have a platform portion (also called a step, step section, or lead-out portion) at their ends that does not overlap with the lower wiring layer (conductive layer). A [missing information - likely a diagram or diagram] is formed on each platform portion. Figure 5 The contact plug CC. The select gate line SGS and multiple word lines WL can be energized separately via the contact plug CC. Thus, the stepped region SSA is provided as a platform region for connecting multiple connectors in each of the multiple conductive layers connected to the select gate line SGS and the multiple word lines WL.

[0064] In addition, the contact plug CC is electrically connected to the upper wiring (not shown) via the upper layer wiring. Figure 5 The contact plug C4 in the tap area is electrically connected to the line decoder located below the memory cell array via the contact plug C4. Thus, the line decoder can control the voltage of each conductive layer 21 (word line WL) via the contact plug CC. The diameters of the contact plugs CC and C4 are larger than the diameter of the insulator post CLHR.

[0065] In the bridging region BRA, multiple third conductive layers corresponding to the select gate line SGS and multiple word lines WL are stacked at intervals in the Z direction. These third conductive layers electrically connect the conductive layer 21 (select gate line SGS and multiple word lines WL) of the first memory cell region 100a_1 to the conductive layer 21 (select gate line SGS and multiple word lines WL) of the second memory cell region 100a_2. Therefore, the first and second memory cell regions 100a_1 and 100a_2 can function as a memory cell array (MCA).

[0066] In this way, the connection region 101 is positioned in the middle of the memory cell array MCA, so that the contact plug CC is located in the middle of the word line WL wiring, which shortens the distance from the contact plug CC to the end of the word line WL. Therefore, the semiconductor memory device 100 can quickly supply power to the end of the word line WL via the contact plug CC, making voltage control of the word line WL easier. Furthermore, since memory cell regions 100a_1 and 100a_2 can be arranged on both sides of a connection region 101, operating speed can be maintained and the size (memory capacity) of the memory cell array MCA can be increased.

[0067] The bridging region BRA has the same stacked structure as the first and second memory cell regions 100a_1 and 100a_2. Therefore, the stacked structure of the bridging region BRA is formed by alternately stacking multiple conductive layers 21 and multiple insulating layers 22 in the Z-axis direction. That is, multiple conductive layers 21, which are multiple third conductive layers, are stacked with insulating layers 22 spaced apart from each other. As described above, the insulating layer 22 can also be an air gap.

[0068] Figure 7A and Figure 7B This is a schematic perspective view of the connection area 101 of a certain BLK. The stepped area SSA of the connection area 101 is set in a stepped shape to connect multiple contact plugs CC to multiple conductive layers 21 (word lines WL). In the bridging area BRA, multiple conductive layers 21 electrically connect the conductive layers 21 (word lines WL) of the first and second memory cell areas 100a_1 and 100a_2.

[0069] The bridging region BRA is disposed adjacent to the stepped region SSA in the Y direction (a direction substantially perpendicular to the extension direction of the slit ST) in the connection region 101, and is not etched into a stepped shape. Therefore, the bridging region BRA has the same number of conductive layers 21 and the same number of insulating layers 22 as the stack 2 of the first and second memory cell regions 100a_1 and 100a_2.

[0070] Figure 8A and Figure 8B This is a top view showing in more detail the several conductive layers 21 of the connection region 101. Figure 8A This indicates a state where conductive layer 21 is stacked. Figure 8B These represent the various layers of conductive layer 21. Figure 8A and Figure 8B The image shows five conductive layers 21. Of course, the conductive layers 21 can be four or fewer, or six or more. Furthermore, in... Figure 8A and Figure 8B In the middle, it represents a block BLK portion, which is omitted. Figure 5The diagram shows the columnar section CL (memory hole MH), the insulator column CLHR, and the slit SHE.

[0071] like Figure 8A As shown, the stepped region SSA of the connection region 101 is formed in a stepped shape such that the surfaces (steps) of each conductive layer 21 are visible from the Z direction. The surface (step) of each conductive layer 21 has a width (area) allowing the contact plug CC to be connected from the Z direction. Figure 8A In this configuration, the stepped portion of the stepped area SSA is positioned opposite to both sides of the connecting area 101 in the X direction. For example... Figure 8A and Figure 8B As shown, one contact plug CC is disposed in each of the conductive layers 21 of the stepped region SSA, and is connected to the tread surface of the conductive layer 21. For example, in Figure 8A and Figure 8B In the example shown, the contact plug CC is alternately connected to the left and right steps of the stepped area SSA. More specifically, in the uppermost conductive layer 21, the contact plug CC is connected to the tread surface of the left step of the stepped area SSA. In the second conductive layer 21, the contact plug CC is connected to the tread surface of the right step of the stepped area SSA. In the third conductive layer 21, the contact plug CC is connected to the tread surface of the left step of the stepped area SSA. In the fourth conductive layer 21, the contact plug CC is connected to the tread surface of the right step of the stepped area SSA. In the fifth (lowest) conductive layer 21, the contact plug CC is connected to the tread surface of the left step of the stepped area SSA.

[0072] Alternatively, the stepped area SSA can be provided only on one side of the connecting area 101 in the X direction. In this case, the contact plug CC is connected to the tread of the stepped portion provided on one side of the connecting area 101.

[0073] One contact plug CC is provided on each conductive layer 21. Therefore, the conductive layer 21 of the memory cell region on the side not connected to the contact plug CC is electrically connected to the contact plug CC via the bridging region BRA. For example, no contact plug CC is provided on the uppermost conductive layer 21 of the second memory cell region 100a_2 on the right side. Therefore, the uppermost conductive layer 21 of the second memory cell region 100a_2 on the right side is electrically connected to the contact plug CC of the uppermost conductive layer 21 of the second memory cell region 100a_2 on the left side via the uppermost conductive layer 21 of the bridging region BRA. In addition, no contact plug CC is provided on the second conductive layer 21 of the second memory cell region 100a_2 on the left side. Therefore, the second conductive layer 21 of the second memory cell region 100a_2 on the left side is electrically connected to the contact plug CC of the second conductive layer 21 of the second conductive layer 21 of the second memory cell region 100a_2 on the right side via the second conductive layer 21 of the bridging region BRA. In this way, one of the storage cell regions 100a_1 and 100a_2 located on both sides of the connection region 101 is electrically connected to the contact plug CC provided on the other via the bridging region BRA.

[0074] in addition, Figure 4 and Figure 5 The structure shown is one example; the tap area and contact plug C4 may also be omitted.

[0075] [Structure of the bridging section]

[0076] Next, we will describe in detail the structure around the slits ST and SHE.

[0077] Figure 9 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 100 according to the first embodiment. Figure 10 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 100 according to the first embodiment. Figure 9 A sectional view representing a unit region. Figure 10 A sectional view showing the stepped area.

[0078] The laminate 2 has laminates 41, 42, and 43. Laminates 41, 42, and 43 are respectively the lower laminate 41, the middle laminate 42, and the upper laminate 43.

[0079] The laminate 42 has a lower layer 421 and an upper layer 422.

[0080] Figure 9 The memory hole MH and the columnar portion CL (not shown) disposed in the memory hole MH have a three-layer structure.

[0081] The memory hole MH has memory holes LMH, MMH, and UMH. The memory holes LMH, MMH, and UMH are memory holes MH corresponding to the lower layer stack 41, the middle layer stack 42, and the upper layer stack 43, respectively.

[0082] The columnar portion CL has columnar portions LCL, MCL, and UCL embedded in memory holes LMH, MMH, and UMH, respectively. The columnar portions LCL, MCL, and UCL correspond to the columnar portions CL of the lower layer stack 41, the middle layer stack 42, and the upper layer stack 43, respectively.

[0083] also, Figure 9 The memory holes LMH, MMH, and UMH shown have the same width along the Z-axis, but their widths can also be different. For example, the widths of the memory holes LMH, MMH, and UMH can decrease from the top to the bottom.

[0084] In addition, a bonding layer can be provided at the connection between memory holes LMH, MMH, and UMH.

[0085] Figure 9 and Figure 10 The slit ST shown is a two-layer structure.

[0086] The slit ST has slits LST and UST. Slits LST and UST are the lower and upper slits ST, respectively.

[0087] The slit ST is filled with a material not shown (plate-like part 3). The slit ST is filled, for example, with a metal film such as tungsten or an insulating film.

[0088] Figure 9 The semiconductor memory device 100 shown also includes an insulating layer 50 and a bridging portion STB.

[0089] An insulating layer 50 is disposed on the laminate 2. The insulating layer 50 is separated by a slit ST. The insulating layer 50 is, for example, a TEOS (Tetra-ethoxy silane)-SiO2 film.

[0090] A bridging section STB is provided within the slit ST (separation section). The bridging section STB prevents adjacent fingers from tilting (inking lines). Furthermore, the bridging section STB can suppress finger deformation. The bridging section STB may include, for example, an insulating film.

[0091] Figure 9 The bridge section STB shown has a lower bridge section LSTB and an upper bridge section USTB.

[0092] The bridging portion LSTB is located on the upper surface of the lower layer 421 (above the slit LST) in the Z-axis direction. The bridging portion USTB is located on the upper surface of the insulating layer 50 in the Z-axis direction.

[0093] Bridging components such as LSTB and USTB may contain insulators such as silicon oxide films.

[0094] The bridging section LSTB is located at the joint of the slit ST (slit LST, UST) of the adjacent layer. Furthermore, the Z-axis position of the bridging section LSTB is the Z-axis position of the middle part between the upper and lower ends of the memory hole MMH.

[0095] The bridging section USTB is located between the insulating layers 50 separated by the slit ST, i.e., above the slit ST.

[0096] Figure 10 The hole HR shown and the columnar part CLHR (not shown) buried in the hole HR are also two-layer structures, just like the slit ST.

[0097] The HR has two holes: LHR and UHR. LHR and UHR are the HR of the lower and upper layers, respectively.

[0098] The columnar portion CLHR has columnar portions LCLHR and UCLHR. The columnar portions LCLHR and UCLHR are the lower and upper columnar portions CLHR, respectively.

[0099] like Figure 9 and Figure 10 As shown, the number of levels of the memory hole MH (columnar portion CL) is different from the number of levels of the hole HR (columnar portion CLHR) and the slit ST.

[0100] in addition, Figure 10 The holes LHR and UHR shown have the same width along the Z-axis, but their widths can also be different. For example, the widths of holes LHR and UHR can decrease from the top to the bottom.

[0101] Next, the formation methods of the bridging section STB, memory hole MH, and hole HR will be explained.

[0102] Figures 11A to 11F This is a cross-sectional view illustrating an example of a manufacturing method of the semiconductor memory device 100 according to the first embodiment. Figures 11A to 11F The left side shows a cross-sectional view of the unit region of the 3-layer structure as viewed from the X-axis direction. Figures 11A to 11F The central section represents a cross-sectional view of the stepped area of ​​the two-story structure as viewed from the X-axis direction. Figures 11A to 11F The right side shows a sectional view of the unit area and the stepped area as viewed from the Y-axis direction.

[0103] First, such as Figure 11A As shown, a laminate 41 is formed to form a memory hole LMH. The laminate 41 comprises a laminate consisting of multiple sacrificial films 21c and multiple insulating layers 22 alternately stacked in the Z-axis direction. The memory hole LMH extends in the Z-axis direction within the laminate 41. Alternatively, the memory hole LMH can be filled using sacrificial films.

[0104] Next, as Figure 11B As shown, a lower layer 421 of a laminate 42 is formed on a laminate 41, forming a hole LHR, a slit LST, and a stepped portion 2s of a stepped region. The stepped portion 2s is planarized, for example, by an insulating film 52 (TEOS-SiO2 film). The lower layer 421 comprises a laminate formed by alternating layers of multiple sacrificial films 21c and multiple insulating layers 22 in the Z-axis direction. The hole LHR extends in the Z-axis direction within the laminate 41 and the lower layer 421. The slit LST extends in the X-axis direction within the laminate 41 and the lower layer 421, separating the cell regions and the stepped regions. Alternatively, the hole LHR can be filled with a sacrificial film.

[0105] Next, as Figure 11C As shown, a bridging portion LSTB is formed inside the slit LST along the lower layer 421 and the upper surface of the aperture LHR. The bridging portion LSTB is located in the upper part of the slit LST. Furthermore, the portion of the slit LST other than the bridging portion LSTB is filled with a sacrificial membrane 51.

[0106] Here, refer to Figures 12A-12E The details of the formation method of the bridging part LSTB are explained.

[0107] Figures 12A-12E This is a cross-sectional view illustrating an example of a manufacturing method of the semiconductor memory device 100 according to the first embodiment.

[0108] First, such as Figure 12A As shown, a lower layer 421 is formed. The lower layer 421 comprises a laminate consisting of multiple sacrificial films 21c and multiple insulating layers 22 alternately stacked in the Z-axis direction.

[0109] Next, as Figure 12B As shown, a slit LST is formed in the lower layer 421.

[0110] Next, as Figure 12C As shown, a sacrificial membrane 51 is buried in the slit LST.

[0111] Next, as Figure 12DAs shown, a portion of the sacrificial film 51 within the slit LST is removed. This creates a recess in the area where the sacrificial film 51 has been removed. The removal of a portion of the sacrificial film 51 is performed, for example, by RIE (Reactive Ion Etching).

[0112] Next, as Figure 12E As shown, the recess formed by removing the sacrificial film 51 is filled with an insulating film (e.g., a silicon oxide film). Thus, a bridging portion LSTB is formed inside the slit LST at a location along the upper surface of the lower layer 421.

[0113] In addition, a bridging portion USTB is also formed along the upper surface of the insulating layer 50.

[0114] Next, as Figure 11D As shown, an upper layer 422 is formed on a lower layer 421, and a memory hole MMH is formed on the memory hole LMH. The upper layer 422 comprises a laminate consisting of multiple sacrificial films 21c and multiple insulating layers 22 alternately stacked in the Z-axis direction. The memory hole MMH extends in the Z-axis direction within the lower layer 421 and the upper layer 422. Alternatively, the memory hole MMH can be filled with a sacrificial film.

[0115] Next, as Figure 11E As shown, a laminate 43 is formed on the upper layer 422, forming a memory hole UMH on the memory hole MMH, a hole UHR on the hole LHR, a stepped portion 2s in the stepped region, a slit UST, and a bridging portion USTB. The laminate 43 comprises a laminate formed by alternately stacking multiple sacrificial films 21c and multiple insulating layers 22 in the Z-axis direction. The bridging portion USTB is provided on the upper part of the slit UST. Furthermore, the portion of the slit UST other than the bridging portion USTB is filled with sacrificial film 51.

[0116] Next, as Figure 11F As shown, the sacrificial membrane 51 within the slits LST and UST is removed. Thus, the following is obtained: Figure 9 and Figure 10 The structure shown.

[0117] As described above, according to the first embodiment, the number of layers in the columnar portion CL is different from the number of layers in the columnar portion CLHR and the slit ST. The bridging portion LSTB is provided at the joint of the slit ST in adjacent layers. The Z-axis position of the bridging portion LSTB is the Z-axis position of the middle portion between the upper end and the lower end of the columnar portion CL.

[0118] In addition, the bridging section USTB is disposed between the insulating layers 50 separated by the slit ST.

[0119] By using the bridging sections LSTB and USTB, the tilting of the finger caused by the left-right asymmetry in the finger parting line BL direction (Y-axis direction) can be suppressed. This reduces the risk of leakage and other problems caused by the metal membrane embedded in the slit ST coming into contact with the connector Cb due to finger tilting.

[0120] Furthermore, the bridging section LSTB can suppress the arcuate deformation of the central portion (side of the slit ST) in the depth direction of the slit ST, which accompanies the layering of the word line WL. This reduces the risk of slit ST blockage.

[0121] In addition, the columnar portion CL consists of 3 layers, while the columnar portion CLHR and the slit ST consist of 2 layers. This combination allows for the placement of the bridging portion LSTB at the center of the laminate 2 in the Z-axis direction, making it easier to suppress bow-shaped deformation.

[0122] Furthermore, the number of levels is not limited to the examples described. It is acceptable as long as the number of levels of the columnar portion CL of the storage region is different from the number of levels of the columnar portion CLHR and the slit ST.

[0123] (Second Implementation)

[0124] Figure 13 This is a top view showing an example of the configuration of the semiconductor memory device 100 according to the second embodiment. The second embodiment shows an example of the configuration of the bridging section STB.

[0125] Multiple bridging STBs are intermittently installed along the X direction.

[0126] exist Figure 13 In the example shown, the bridging portion STB is positioned precisely between adjacent slits ST. This further suppresses the arcuate deformation of the central portion of the slit ST in the depth direction.

[0127] That is, between adjacent slits ST in the Y-axis direction, which intersects the Z-axis and X-axis directions, the bridging part STB (bridging part LSTB) is arranged at approximately the same position along the X-axis direction.

[0128] The bridging section STB can also be configured as in the second embodiment. The semiconductor memory device 100 of the second embodiment can achieve the same effect as the first embodiment.

[0129] (Third Implementation)

[0130] Figure 14 This is a top view showing an example of the configuration of the semiconductor memory device 100 according to the third embodiment. The third embodiment shows an example of the configuration of the bridge section STB.

[0131] Multiple bridging STBs are intermittently arranged along the X direction.

[0132] exist Figure 14 In the example shown, the bridging portions STB are configured in a staggered pattern. That is, the bridging portions STB are staggered by half a spacing in the X direction. This helps to suppress adverse process effects during the replacement step of the sacrificial film 21c with the conductive layer 21.

[0133] That is, between adjacent slits ST in the Y-axis direction, which intersects the Z-axis and X-axis directions, the bridging part STB (bridging part LSTB) is arranged at different positions along the X-axis direction.

[0134] The bridging section STB can also be configured as in the third embodiment. The semiconductor memory device 100 of the third embodiment can achieve the same effect as the first embodiment.

[0135] (Fourth Implementation)

[0136] Figure 15 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 100 according to the fourth embodiment. The fourth embodiment shows an example of the configuration of the bridging section STB.

[0137] exist Figure 15 In the example shown, the bridging portions LSTB and USTB, viewed from the Z-axis direction, are arranged in an overlapping manner. This further suppresses the bow-shaped deformation of the central portion of the slit ST in the depth direction.

[0138] That is, the bridging part LSTB and the bridging part USTB are arranged at approximately the same position along the X-axis. In addition, when the bridging part USTB is set to two or more layers, adjacent bridging parts USTB in the Z-axis direction can also be arranged at approximately the same position along the X-axis.

[0139] The bridging section STB can also be configured as in the fourth embodiment. The semiconductor memory device 100 of the fourth embodiment can achieve the same effect as the first embodiment.

[0140] (Fifth Implementation)

[0141] Figure 16 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 100 according to the fifth embodiment. The fifth embodiment shows an example of the configuration of the bridging section STB.

[0142] exist Figure 16 In the example shown, the bridging sections LSTB and USTB, viewed from the Z-axis direction, are configured in a way that they do not overlap.

[0143] That is, the bridging part LSTB and the bridging part USTB are arranged in different positions along the X-axis direction. In addition, when the bridging part USTB is set in two or more layers, adjacent bridging parts USTB in the Z-axis direction can also be arranged in different positions along the X-axis direction.

[0144] The bridging section STB can also be configured as in the fifth embodiment. The semiconductor memory device 100 of the fifth embodiment can achieve the same effects as the first embodiment.

[0145] (Sixth Implementation Method)

[0146] Figure 17 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 100 according to the sixth embodiment. The sixth embodiment shows an example of the configuration of the bridging section STB.

[0147] The bridging section LSTB is located in the Z-axis direction of the joint of the slit ST in some or all of the adjacent layers.

[0148] Figure 17 The hole HR, the corresponding columnar portion CLHR, and the slit ST shown constitute a 5-layer structure. That is, it is a 5-layer structure of a stepped region. Figure 17 (a)~ Figure 17 (g) represents seven examples of the configuration of the bridging STB.

[0149] To suppress defects caused by arcuate deformation of the central portion of the slit ST in the depth direction, it is preferable to have fewer areas without bridging sections STB. Furthermore, if the number of areas without bridging sections STB is the same, it is preferable to place them on the lower layer. Additionally, it is preferable that the areas without bridging sections STB are discontinuous. According to this viewpoint, defects caused by arcuate deformation of the central portion of the slit ST in the depth direction can be suppressed in the order (a) > (b) > (c) > (d) > (e) > (f) > (g).

[0150] The bridging section STB can also be configured as in the sixth embodiment. The semiconductor memory device 100 of the sixth embodiment can achieve the same effects as the first embodiment.

[0151] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0152] [Explanation of reference numerals in the attached figures]

[0153] 100 Semiconductor memory device, 2-layer stack, 21 conductive layer, 22 insulating layer, 41, 42, 43-layer stack, 421 lower layer, 422 upper layer, 50 insulating layer, Cell cell region, CL columnar portion, CLHR columnar portion, MH memory hole, hole HR, ST slit, STB bridging portion, SSA step region.

Claims

1. A semiconductor memory device comprising a laminate formed by alternately stacking a plurality of first conductive layers and a plurality of first insulating layers in a first direction. The laminate has: A first columnar portion is disposed in a first region of the laminate and includes a first semiconductor portion extending in the first direction and a first insulator portion disposed on the outer peripheral surface of the first semiconductor portion within the laminate. The second columnar portion is disposed in the second region of the laminate, extends in the first direction within the laminate, and includes an insulator; as well as The separating portion extends within the laminate in the first direction and in a second direction intersecting the first direction, separating the first region and the second region. The number of layers in the first columnar section is different from the number of layers in the second columnar section and the separating section. The semiconductor memory device further includes a first bridging portion, which is disposed at the connector of the separation portion in an adjacent layer. The position of the first bridging portion in the first direction is the position of the middle portion between the upper end and the lower end of the first columnar portion in the first direction.

2. The semiconductor memory device according to claim 1, further comprising: A second insulating layer is disposed on the laminate and separated from the separating portion; and The second bridging portion is disposed between the separated second insulating layers.

3. The semiconductor memory device according to claim 1, The first bridging portion is located in the first direction at the joint portion of the separation portion of some or all of the adjacent layers.

4. The semiconductor memory device according to claim 1, The first bridging portion includes an insulator.

5. The semiconductor memory device according to claim 1, Between the separating portions that are adjacent to each other on a third upward direction intersecting the first and second directions, the first bridging portions are arranged at approximately the same position along the second direction.

6. The semiconductor memory device according to claim 1, Between the separation portions that are adjacent to each other on a third upward direction intersecting the first and second directions, the first bridging portions are arranged at different positions along the second direction.

7. The semiconductor memory device according to claim 1, further comprising: A second insulating layer is disposed on the laminate and separated from the separating portion; and The second bridging portion is disposed between the separated second insulating layers. The first bridging portion and the second bridging portion are arranged at approximately the same position along the second direction.

8. The semiconductor memory device according to claim 1, further comprising: A second insulating layer is disposed on the laminate and separated from the separating portion; and The second bridging portion is disposed between the separated second insulating layers. The first bridging portion and the second bridging portion are arranged at different positions along the second direction.

9. The semiconductor memory device according to claim 1, It has a plurality of first bridging portions disposed discontinuously along the second direction.

10. The semiconductor memory device according to claim 1, The laminate in the second region has a stepped structure.

11. A method for manufacturing a semiconductor memory device, comprising the following steps: A first laminate is formed, which is formed by alternately stacking a plurality of first sacrificial layers and a plurality of first insulating layers in a first direction; A first hole extending in the first direction is formed in a first region of the first laminate; A second laminate is formed on the first laminate, the second laminate being formed by alternately stacking a plurality of first sacrificial layers and a plurality of first insulating layers in the first direction; In the second region of the first laminate and the second laminate, a second hole extending in the first direction is formed in the first laminate and the second laminate, and a first separation portion is formed, which extends in the first laminate and the second laminate in the first direction and in a second direction intersecting the first direction, separating the first region and the second region; A third bridging portion is formed at the upper part of the first separation portion; A third stack is formed on the second stack, the third stack being formed by alternately stacking a plurality of first sacrificial layers and a plurality of first insulating layers in the first direction; as well as A third hole extending in the first direction is formed on the first hole within the second and third stacks.

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