Ferroelectric field effect transistor integrated chip and method for manufacturing the same

Abstract

This application provides a ferroelectric field-effect transistor (FET) integrated chip and its fabrication method, relating to the field of electronic component technology. It aims to improve the integration flexibility of FETs with different threshold voltages and the manufacturing efficiency of the FET integrated chip. The integrated chip includes a substrate, and a back gate conductive layer, a ferroelectric layer, an oxide semiconductor layer, a source electrode, and a drain electrode sequentially stacked on the substrate. The FET integrated chip also includes a first FET and a second FET. The first FET includes a first gate located on the back gate conductive layer, and the material of the first gate includes at least two materials. The second FET includes a second gate located on the back gate conductive layer, and the material of the second gate includes at least two materials. The coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate.

Description

Technical Field

[0001] This application relates to the field of electronic components technology, and in particular to a ferroelectric field-effect transistor integrated chip and its fabrication method. Background Technology

[0002] With the rapid development of information technology and the explosive growth of generative artificial intelligence and big data applications, unprecedented demands have been placed on the density, energy efficiency, and reliability of memory. The market urgently needs a high-density, low-power, and high-endurance non-volatile memory solution to support the continuous evolution of data-intensive computing architectures. Ferroelectric field-effect transistors (FETs), as an emerging non-volatile memory device, have become a strong candidate for next-generation embedded memory and 3D stacked memory due to their low operating voltage, nanosecond-level read / write speeds, and high compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes.

[0003] Among them, ferroelectric field-effect transistors (FETs) using oxide semiconductors as the channel material exhibit significant advantages in improving reliability and integration density due to their higher durability and superior three-dimensional integration flexibility. Achieving flexible and precise threshold voltage control is a key technology for improving the performance of FET memory arrays, ensuring compatibility with peripheral circuit designs, and realizing voltage domain partitioning and power consumption optimization.

[0004] However, improving the integration flexibility of ferroelectric field-effect transistors with different threshold voltages and the manufacturing efficiency of ferroelectric field-effect transistor integrated chips have become problems to be solved in the field. Summary of the Invention

[0005] This application proposes a ferroelectric field-effect transistor integrated chip and its fabrication method, aiming to improve the integration flexibility of ferroelectric field-effect transistors with different threshold voltages in the ferroelectric field-effect transistor integrated chip, as well as the manufacturing efficiency of the ferroelectric field-effect transistor integrated chip.

[0006] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0007] On one hand, embodiments of this application provide a ferroelectric field-effect transistor integrated chip, which includes a substrate, a back gate conductive layer disposed on the substrate, a ferroelectric layer, an oxide semiconductor layer, a source, and a drain. The back gate conductive layer is made of at least two materials with different coefficients of thermal expansion. The ferroelectric layer is disposed on the side of the back gate conductive layer away from the substrate. The coefficient of thermal expansion of the ferroelectric layer material is different from that of the back gate conductive layer material. The oxide semiconductor layer is disposed on the side of the ferroelectric layer away from the substrate, and the oxide semiconductor layer includes a channel region. The source and drain are disposed on the side of the oxide semiconductor layer away from the substrate. The orthographic projection of the channel region onto the substrate lies between the orthographic projections of the source and drain onto the substrate.

[0008] The ferroelectric field-effect transistor integrated chip further includes multiple ferroelectric field-effect transistors, including a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor. The first ferroelectric field-effect transistor includes a first gate located on the back gate conductive layer, and the material of the first gate includes at least two materials. The thermal expansion coefficient of the material of the first gate is different from that of the material of the second gate.

[0009] The ferroelectric field-effect transistor integrated chip provided in the embodiments of this application includes a substrate, and a back gate conductive layer, a ferroelectric layer, an oxide semiconductor layer, and a source and a drain layer sequentially stacked on the substrate. A first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor are disposed on the substrate of the ferroelectric field-effect transistor integrated chip. The first gate of the first ferroelectric field-effect transistor and the second gate of the second ferroelectric field-effect transistor are each made of at least two materials. Furthermore, the coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate.

[0010] Understandably, during the formation of the ferroelectric field-effect transistor (FET) integrated chip, the first FET and the second FET are formed simultaneously. A thermal annealing process can be used to form a channel region in the oxide semiconductor layer, thereby enabling the regulation of the threshold voltage in both the first and second FETs. Since the back gate conductive layer comprises at least two materials with different coefficients of thermal expansion, and the coefficient of thermal expansion of the ferroelectric layer material differs from that of the back gate conductive layer material, the different materials in the back gate conductive layer undergo varying degrees of thermal expansion during the thermal annealing process. This allows for continuous regulation of the thermal expansion of the back gate conductive layer, thereby generating the necessary stress during the cooling phase and improving the threshold voltage control accuracy of both the first and second FETs.

[0011] Furthermore, because the coefficients of thermal expansion of the first gate material differ from those of the second gate material, the first and second gates will undergo different degrees of thermal expansion during the thermal annealing process. This results in the first and second ferroelectric field-effect transistors having different threshold voltages. In other words, ferroelectric field-effect transistors with different threshold voltages can be formed on the substrate through a single thermal annealing process. This allows for flexible control of the threshold voltage position of the ferroelectric field-effect transistors during the fabrication process, thereby improving the integration flexibility of ferroelectric field-effect transistors with different threshold voltages in ferroelectric field-effect transistor integrated chips and enhancing the manufacturing efficiency of ferroelectric field-effect transistor integrated chips.

[0012] In some embodiments, the back gate conductive layer includes a first back gate conductive layer and a second back gate conductive layer stacked together. The first gate includes a first sub-gate located in the first back gate conductive layer and a second sub-gate located in the second back gate conductive layer. The second gate includes a third sub-gate located in the first back gate conductive layer and a fourth sub-gate located in the second back gate conductive layer. Along a direction perpendicular to the substrate, the thickness of the first sub-gate is different from the thickness of the third sub-gate, or the thickness of the second sub-gate is different from the thickness of the fourth sub-gate, or the thickness of the first sub-gate is different from the thickness of the third sub-gate, and the thickness of the second sub-gate is also different from the thickness of the fourth sub-gate.

[0013] In some embodiments, the material of the first sub-gate is the same as the material of the third sub-gate, or the material of the second sub-gate is the same as the material of the fourth sub-gate, or the material of the first sub-gate is the same as the material of the third sub-gate and the material of the second sub-gate is the same as the material of the fourth sub-gate. The coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate.

[0014] In some embodiments, the material of the first gate includes a first alloy material, the material of the second gate includes a second alloy material, and the coefficient of thermal expansion of the first alloy material is different from that of the second alloy material.

[0015] In some embodiments, the difference between the thermal expansion coefficient of the first gate and the thermal expansion coefficient of the material of the second gate is greater than or equal to 4 × 10⁻⁶. -6 / K.

[0016] In some embodiments, the difference between the threshold voltage of the first ferroelectric field-effect transistor and the threshold voltage of the second ferroelectric field-effect transistor is greater than or equal to 0.5V.

[0017] On the other hand, embodiments of this application also provide a method for fabricating a ferroelectric field-effect transistor integrated chip, the method comprising: A first gate and a second gate are formed on a substrate. The material of the first gate includes at least two materials, and the material of the second gate includes at least two materials. The coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate. A ferroelectric layer and an oxide semiconductor layer are sequentially formed on the side of the first gate and the second gate away from the substrate. The thermal expansion coefficient of the ferroelectric layer material is different from that of the materials of the first gate and the second gate. The source and drain are formed on the side of the oxide semiconductor layer away from the substrate; A channel region is formed within an oxide semiconductor layer using a thermal annealing process to form a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor.

[0018] The fabrication method provided in the embodiments of this application includes sequentially forming a back gate conductive layer, a ferroelectric layer, an oxide semiconductor layer, and source and drain electrodes on a substrate. Furthermore, a channel region is formed within the oxide semiconductor layer through a thermal annealing process to form a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor. The materials of both the first and second gate electrodes comprise at least two materials, and the thermal expansion coefficients of the first and second gate electrodes are different. The thermal expansion coefficient of the ferroelectric layer material is different from that of both the materials of the first and second gate electrodes.

[0019] Understandably, during the formation of the ferroelectric field-effect transistor (FET) integrated chip, the first FET and the second FET are formed simultaneously. By employing a thermal annealing process to form a channel region in the oxide semiconductor layer, the threshold voltage of both the first and second FETs can be controlled. Since the back gate conductive layer comprises at least two materials with different coefficients of thermal expansion, and the coefficient of thermal expansion of the ferroelectric layer material differs from that of the back gate conductive layer material, the different materials in the back gate conductive layer undergo varying degrees of thermal expansion during the thermal annealing process. This allows for continuous control of the thermal expansion of the back gate conductive layer, thereby generating the necessary stress during the cooling phase and improving the threshold voltage control accuracy of both the first and second FETs.

[0020] Furthermore, because the coefficients of thermal expansion of the first gate material differ from those of the second gate material, the first and second gates will undergo different degrees of thermal expansion during the thermal annealing process. This results in the first and second ferroelectric field-effect transistors having different threshold voltages. In other words, ferroelectric field-effect transistors with different threshold voltages can be formed on the substrate through a single thermal annealing process. This allows for flexible control of the threshold voltage position of the ferroelectric field-effect transistors during the fabrication process, thereby improving the integration flexibility of ferroelectric field-effect transistors with different threshold voltages in ferroelectric field-effect transistor integrated chips and enhancing the manufacturing efficiency of ferroelectric field-effect transistor integrated chips.

[0021] In some embodiments, forming a first gate and a second gate on a substrate includes: forming a back gate conductive layer on the substrate, the back gate conductive layer including a first back gate conductive layer and a second back gate conductive layer sequentially stacked on the substrate, the material of the back gate conductive layer including at least two materials with different coefficients of thermal expansion; etching the back gate conductive layer to form the first gate and the second gate, the first gate including a first sub-gate located on the first back gate conductive layer and a second sub-gate located on the second back gate conductive layer, the second gate including a third sub-gate located on the first back gate conductive layer and a fourth sub-gate located on the second back gate conductive layer; and etching the second sub-gate of the first gate to thin the second sub-gate.

[0022] In some embodiments, forming a first gate and a second gate on a substrate includes: forming a first gate on a substrate, the first gate including a first sub-gate and a second sub-gate sequentially stacked on the substrate, the first sub-gate and the second sub-gate being made of different materials and having different coefficients of thermal expansion; forming a second gate on a substrate, the second gate including a third sub-gate and a fourth sub-gate sequentially stacked on the substrate, the third sub-gate and the fourth sub-gate being made of different materials and having different coefficients of thermal expansion.

[0023] The first gate and the second gate have different coefficients of thermal expansion. Along the direction perpendicular to the substrate, the thickness of the first sub-gate is different from the thickness of the third sub-gate, or the thickness of the second sub-gate is different from the thickness of the fourth sub-gate, or the thickness of the first sub-gate is different from the thickness of the third sub-gate, and the thickness of the second sub-gate is different from the thickness of the fourth sub-gate.

[0024] In some embodiments, forming a first gate and a second gate on a substrate includes: forming a first gate on the substrate, the first gate being made of a first alloy material; and forming a second gate on the substrate, the second gate being made of a second alloy material. The coefficient of thermal expansion of the first alloy material is different from that of the second alloy material. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0026] Figure 1 A schematic diagram of the structure of a ferroelectric field-effect transistor integrated chip provided for an embodiment of this application; Figure 2 A schematic diagram of another ferroelectric field-effect transistor integrated chip provided for an embodiment of this application; Figure 3 A schematic diagram of another ferroelectric field-effect transistor integrated chip provided for an embodiment of this application; Figure 4 The simulation results diagram provided in this application; Figure 5 A flowchart illustrating a method for fabricating a ferroelectric field-effect transistor integrated chip, provided as an embodiment of this application; Figures 6-10 for Figure 5 The preparation method shown in the diagrams illustrates each step. Figure 11 A flowchart illustrating another method for fabricating a ferroelectric field-effect transistor integrated chip provided for embodiments of this application; Figures 12-15 for Figure 11 The preparation method shown in the diagrams illustrates each step. Figure 16 A flowchart illustrating another method for fabricating a ferroelectric field-effect transistor integrated chip provided for embodiments of this application; Figures 17-20 for Figure 16 The preparation method is illustrated in the following diagrams. Detailed Implementation

[0027] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0030] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0031] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0032] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0033] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0034] In related technologies, the ferroelectric field-effect transistor (FeFET) is a novel semiconductor device formed by replacing the gate insulating layer of a traditional metal-oxide-semiconductor field-effect transistor (MOSFET) with a ferroelectric material with a high dielectric constant. Its core principle utilizes the spontaneous polarization characteristics of ferroelectric materials to control the resistance state of the semiconductor channel through gate voltage, combining non-volatile storage with field-effect modulation functions. It is primarily used in ultra-high-speed integrated circuits and novel memory fields.

[0035] Ferroelectric field-effect transistors (FETs) can serve as memory cells in ultra-high-speed integrated circuits and novel memories. In this case, FETs have a programming (PRG) state and an erased (ESR) state. The programming and erased states are two stable states of FETs based on the polarization reversal characteristics of the ferroelectric material in the ferroelectric layer. They correspond to different threshold voltages (Vth) and conductivity characteristics, and the states can be switched by applying electric fields in different directions.

[0036] In related technologies, oxide semiconductor channel materials cannot be used for threshold voltage regulation using the ion implantation process of traditional silicon-based devices. Their threshold voltage regulation can only rely on in-situ doping during thin film deposition or subsequent thermal treatment processes. In the process of forming multiple ferroelectric field-effect transistors on a wafer substrate, atomic layer deposition (ALD) or physical vapor deposition (PVD) processes are typically used.

[0037] However, since mainstream channel film deposition technologies such as atomic layer deposition or physical vapor deposition are all whole-wafer growth processes, they cannot achieve spatial selective control. As a result, all ferroelectric field-effect transistors on the same wafer have the same threshold voltage. This severely restricts the co-design of memory devices and circuits and reduces the flexibility of system and circuit design.

[0038] Furthermore, it is difficult to achieve a precise correspondence between process parameters and threshold voltage through operations such as doping and annealing. Modifying the work function of the gate alone results in a relatively small range of threshold voltage variation, thus reducing the flexibility of threshold voltage control in oxide semiconductor channel ferroelectric transistors. Moreover, forcibly achieving localized threshold voltage difference control through multiple deposition and patterning processes not only dramatically increases the number of process steps and reduces yield, but also significantly increases manufacturing costs and integration complexity, making it difficult to meet the reliability and cost requirements of memory chip manufacturing.

[0039] Faced with the aforementioned technical bottlenecks, there is an urgent need for an innovative control mechanism that offers low process integration costs, good process compatibility, and the ability to perform local Vth programming. In practical integrated circuit design, it is often necessary to integrate multiple devices with different threshold voltages on the same chip to optimize the read / write power consumption and static power consumption of the memory system. Finding a system-level solution based on the aforementioned stress control mechanism that efficiently and cost-effectively integrates multiple threshold voltage devices is crucial for advancing the frontier development of memory technology.

[0040] Therefore, on the one hand, embodiments of this application provide an integrated chip for a ferroelectric field-effect transistor. Figure 1This is a schematic diagram of the structure of a ferroelectric field-effect transistor integrated chip provided for an embodiment of this application.

[0041] See Figure 1 The integrated chip 10 includes a substrate 1, and a back gate conductive layer 2, a ferroelectric layer 3, an oxide semiconductor layer 4, a source electrode 5, and a drain electrode 6 disposed on the substrate 1.

[0042] For example, the integrated chip 10 may include a plurality of ferroelectric field-effect transistors 100, and at least two of the plurality of ferroelectric field-effect transistors 100 have different threshold voltages (Vth). The ferroelectric field-effect transistors 100 can be used as memory chips in the fields of ultra-high-speed integrated circuits and novel memory. The ferroelectric field-effect transistors 100 have a programmable state (PRG) and an eraser state (ESR), and the two different states of the ferroelectric field-effect transistors have different threshold voltages and conductivity characteristics.

[0043] The threshold voltage of the ferroelectric field-effect transistor 100 is a core parameter distinguishing its cutoff and conduction regions, playing a crucial role in the switching of the ferroelectric field-effect transistor 100's operating states, performance optimization, circuit design adaptation, and stability assurance. The threshold voltage is the critical voltage value that allows the ferroelectric field-effect transistor to switch from "off" to "on". When the gate voltage is below the threshold voltage, no conductive channel is formed within the oxide semiconductor layer 4, the ferroelectric field-effect transistor 100 is in the cutoff state, and the drain current 6 is extremely small. When the gate voltage reaches or exceeds the threshold voltage, strong inversion occurs within the oxide semiconductor layer 4, forming a conductive channel, the ferroelectric field-effect transistor 100 turns on, and the drain current 6 increases significantly.

[0044] For example, the material of substrate 1 can be silicon or other semiconductor materials, such as a wafer.

[0045] See also Figure 1 The material of the back gate conductive layer 2 includes at least two materials with different coefficients of thermal expansion (CTE).

[0046] For example, the material of the back gate conductive layer 2 can be at least two of the following metal materials: titanium nitride, tantalum nitride, molybdenum, titanium, tungsten, ruthenium, etc.

[0047] See also Figure 1 The ferroelectric layer 3 is disposed on the side of the back gate conductive layer 2 away from the substrate 1. The coefficient of thermal expansion (CTE) of the material of the ferroelectric layer 3 is different from that of the material of the back gate conductive layer 2.

[0048] For example, the ferroelectric layer 3 can serve as the gate insulating layer of the ferroelectric field-effect transistor 100, electrically isolating the back gate conductive layer 2 from the oxide semiconductor layer 4. Furthermore, the ferroelectric layer 3 can also enable the ferroelectric field-effect transistor 100 to possess key performance characteristics such as non-volatile storage, threshold voltage regulation, low power consumption operation, and high switching ratio through its unique ferroelectric properties, such as spontaneous polarization, polarization reversal, and hysteresis loop.

[0049] For example, the material of the ferroelectric layer 3 may include hafnium oxide. For instance, the material of the ferroelectric layer 3 may be a pure hafnium oxide thin film, or a hafnium oxide thin film doped with silicon, zirconium, aluminum, lanthanum, gallium, or yttrium. The embodiments of this application illustrate the use of hafnium oxide (HfO2) as the material of the ferroelectric layer 3.

[0050] See also Figure 1 The oxide semiconductor layer 4 is disposed on the side of the ferroelectric layer 3 away from the substrate 1, and the oxide semiconductor layer 4 includes a channel region 41.

[0051] For example, after forming the oxide semiconductor layer 4, a rapid thermal annealing (RTA) process can be used to form the channel region 41 in the oxide semiconductor layer 4. It is understood that during the thermal annealing process, a portion of the material in the oxide semiconductor layer 4 can be transformed from an amorphous state to a polycrystalline state under high temperature, and the portion transformed into the polycrystalline state is the channel region 41.

[0052] For example, the rapid thermal annealing stage includes a heating stage, a holding stage, and a cooling stage. During the heating and holding stages, partial crystallization reactions occur in the ferroelectric layer 3 and the oxide semiconductor layer 4, and the back gate conductive layer 2 simultaneously undergoes thermal expansion at high temperatures. During the cooling stage, the back gate conductive layer 2, the ferroelectric layer 3, and the oxide semiconductor layer 4 all undergo cooling contraction. Because the coefficient of thermal expansion of the material of the ferroelectric layer 3 is different from that of the material of the back gate conductive layer 2, the difference in the coefficient of thermal expansion between the two will generate a stress difference. This stress difference will be conducted through the ferroelectric layer 3 to the oxide semiconductor layer 4, resulting in the oxide semiconductor layer 4 being subjected to localized tensile stress. This stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 100.

[0053] For example, the material of the oxide semiconductor layer 4 includes an n-type semiconductor material. For instance, the material of the oxide semiconductor layer 4 can be a monolithic oxide semiconductor material, such as titanium oxide, tin oxide, zinc oxide, indium oxide, gallium oxide, or cerium oxide. Alternatively, the material of the oxide semiconductor layer 4 can also be a binary oxide or a multi-component oxide material composed of the aforementioned metal elements, such as indium-doped zinc oxide (binary oxide), indium gallium zinc oxide (ternary oxide), indium gallium zinc tin oxide (quaternary oxide), etc.

[0054] See also Figure 1 The source electrode 5 and the drain electrode 6 are disposed on the side of the oxide semiconductor layer 4 away from the substrate 1.

[0055] For example, the source 5 and the drain 6 are made of the same material, and the positions of the source 5 and the drain 6 can be interchanged. For instance, the source 5 and the drain 6 can be conductive materials such as titanium nitride, tantalum nitride, molybdenum, titanium, tungsten, ruthenium, or indium tin oxide, which form ohmic contacts with the oxide semiconductor layer 4 and are process-compatible.

[0056] The orthographic projection of the channel region 41 onto the substrate 1 lies between the orthographic projections of the source 5 and the drain 6 onto the substrate 1. It can be understood that, along the X direction, the source 5 and drain 6 are located on opposite sides of the channel region 41. The back gate conductive layer 2 can apply an electric field to the channel region 41 through the ferroelectric layer 3, thereby controlling the conductivity of the channel region 41 and thus controlling the switching state of the ferroelectric field-effect transistor 100.

[0057] For example, during the formation of the channel region 41 using a thermal annealing process, the thermal expansion coefficient of the ferroelectric layer 3 material is different from that of the back gate conductive layer 2 material. This difference in thermal expansion coefficients will cause a stress difference between the two materials. This stress difference will be conducted through the ferroelectric layer 3 to the oxide semiconductor layer 4, thereby causing the oxide semiconductor layer 4 to be subjected to localized tensile stress. This stress will affect the grain size and oxygen vacancy distribution of the channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus affecting the threshold voltage of the ferroelectric field-effect transistor 100.

[0058] See also Figure 1 The ferroelectric field-effect transistor integrated chip 10 also includes a first ferroelectric field-effect transistor 101 and a second ferroelectric field-effect transistor 102. The first ferroelectric field-effect transistor 101 includes a first gate 7 located in the back gate conductive layer 2, and the material of the first gate 7 includes at least two materials. The second ferroelectric field-effect transistor 102 includes a second gate 8 located in the back gate conductive layer 2, and the material of the second gate 8 includes at least two materials. The coefficient of thermal expansion of the material of the first gate 7 is different from that of the material of the second gate 8.

[0059] It is understandable that the thermal expansion coefficients of the first gate 7 of the first ferroelectric field-effect transistor 101 and the second gate 8 of the second ferroelectric field-effect transistor 102 are different. Therefore, in the thermal annealing process, the first gate 7 and the second gate 8 can undergo different degrees of thermal expansion during the heating and holding stages, thereby causing the first gate 7 and the second gate 8 to generate different stresses during the cooling stage. This results in the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 generating different threshold voltages, that is, forming multiple ferroelectric field-effect transistors 100 with differentiated threshold voltage distributions on the substrate 1.

[0060] For example, the materials of the first gate 7 and the second gate 8 may contain the same metal elements, but the composition of each metal may be different, thereby resulting in different coefficients of thermal expansion between the materials of the first gate 7 and the second gate 8. Alternatively, the materials of the first gate 7 and the second gate 8 may contain different metal elements, thereby resulting in different coefficients of thermal expansion between the materials of the first gate 7 and the second gate 8.

[0061] For example, the materials of the first gate 7 and the second gate 8 can be homogeneous monolayer alloy materials. For instance, the materials of both the first gate 7 and the second gate 8 can be Ti1- x W x Mo1- Ru Or W1- x Mo x One of them. Among them, Ti1- x W x It is a solid solution alloy formed by partially replacing titanium (Ti) atoms with tungsten (W) as the matrix. Mo1- Ru The alloy is a solid solution alloy formed by partially replacing molybdenum (Mo) atoms with ruthenium (Ru) as the matrix. W1- x Mo x It is a solid solution alloy formed by introducing molybdenum (Mo) element by partially replacing tungsten atoms, with tungsten (W) as the matrix.

[0062] By adjusting the alloy composition ratio of the materials of the first gate 7 and the second gate 8, the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 can be adjusted, thereby generating different stresses in the first gate 7 and the second gate 8 during the cooling stage.

[0063] Alternatively, both the first gate 7 and the second gate 8 can be stacks of at least two metal material layers. For example, both the first gate 7 and the second gate 8 can be stacked structures of three or more metal layers, in which at least two different metal materials are present. By adjusting the thickness of the different metal material layers, the composition of different metals can be changed, thereby adjusting the coefficient of thermal expansion of the materials of the first gate 7 and the second gate 8.

[0064] For example, the aforementioned stacked structure can be TiN / W / Ti, TaN / Al / TaN, or Ru / Mo / Ru. Among them, TiN / W / Ti refers to a three-layer metal stack of titanium nitride (TiN), tungsten (W), and titanium (Ti); TaN / Al / TaN refers to a three-layer metal stack of tantalum nitride (TaN), aluminum (Al), and tantalum nitride (TaN); and Ru / Mo / Ru refers to a three-layer metal stack of ruthenium (Ru), molybdenum (Mo), and ruthenium (Ru).

[0065] For example, by setting the first gate 7 and the second gate 8 to be a stacked structure of multiple metal material layers, the superposition of multi-interface thermal mismatch of the first gate 7 and the second gate 8, as well as the stress direction modulation, can be realized, thereby achieving a more complex and finer stress distribution, and thus enabling precise control of the threshold voltage of the first ferroelectric field effect transistor 101 and the second ferroelectric field effect transistor 102.

[0066] For example, along the direction X parallel to the substrate 1, the length of the first gate 7 ranges from 10 μm to 10 nm, and the length of the second gate 8 also ranges from 10 μm to 10 nm. By setting the length range of both the first gate 7 and the second gate 8 to be within the range of 10 μm to 10 nm, multiple first ferroelectric field-effect transistors 101 and multiple second ferroelectric field-effect transistors 102 can be integrated on the substrate 1, thereby achieving high-density integration of ferroelectric field-effect transistors 100 on the chip 1.

[0067] The ferroelectric field-effect transistor integrated chip 10 provided in the embodiments of this application includes a substrate 1, and a back gate conductive layer 2, a ferroelectric layer 3, an oxide semiconductor layer 4, a source electrode 5, and a drain electrode 6 sequentially stacked on the substrate 1. A first ferroelectric field-effect transistor 101 and a second ferroelectric field-effect transistor 102 are disposed on the substrate 1 of the ferroelectric field-effect transistor integrated chip 10. The first gate 7 of the first ferroelectric field-effect transistor 101 and the second gate 8 of the second ferroelectric field-effect transistor 102 are both made of at least two materials. Furthermore, the coefficient of thermal expansion of the material of the first gate 7 is different from that of the material of the second gate 8.

[0068] It is understandable that during the formation of the ferroelectric field-effect transistor integrated chip 10, the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 are formed simultaneously. A thermal annealing process can be used to form a channel region 41 in the oxide semiconductor layer 4, thereby enabling the regulation of the threshold voltage in the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102. Since the material of the back gate conductive layer 2 includes at least two materials with different coefficients of thermal expansion, and the coefficient of thermal expansion of the material of the ferroelectric layer 3 is different from that of the material of the back gate conductive layer 2, different materials in the back gate conductive layer 2 undergo different degrees of thermal expansion during the thermal annealing process. This allows for continuous regulation of the thermal expansion of the back gate conductive layer 2, thereby generating the required stress in the back gate conductive layer 2 during the cooling stage, improving the threshold voltage control accuracy of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102.

[0069] Furthermore, since the coefficient of thermal expansion of the material of the first gate 7 is different from that of the material of the second gate 8, the first gate 7 and the second gate 8 will undergo different degrees of thermal expansion during the thermal annealing process, thereby causing the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 to have different threshold voltages. In other words, ferroelectric field-effect transistors 100 with different threshold voltages can be formed on the substrate 1 through only one thermal annealing process. This allows for flexible control of the threshold voltage position of the ferroelectric field-effect transistors 100 during the fabrication process, thereby improving the integration flexibility of ferroelectric field-effect transistors 100 with different threshold voltages in the ferroelectric field-effect transistor integrated chip 10 and the manufacturing efficiency of the ferroelectric field-effect transistor integrated chip 10.

[0070] Figure 2 This is a schematic diagram of another ferroelectric field-effect transistor integrated chip provided as an embodiment of this application.

[0071] In some embodiments, see Figure 1 and Figure 2 The back gate conductive layer 2 includes a first back gate conductive layer 2 and a second back gate conductive layer 2 stacked together.

[0072] It is understood that the back gate conductive layer 2 can be configured as a stack of two metal material layers, namely a first back gate conductive layer 21 and a second back gate conductive layer 22. The back gate conductive layer 2 can be referred to as a "double-layer metal gate". In this embodiment, both the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 are double-layer metal gate devices.

[0073] Furthermore, the first back gate conductive layer 21 and the second back gate conductive layer 22 have different coefficients of thermal expansion. During the thermal annealing process, different materials in the back gate conductive layer 2 can undergo different degrees of thermal expansion, thereby achieving continuous control of the thermal expansion of the back gate conductive layer 2. This allows the back gate conductive layer 2 to generate the required stress during the cooling stage, thus improving the threshold voltage control accuracy.

[0074] For example, the difference Δα between the coefficient of thermal expansion of the material of the first back gate conductive layer 21 and the coefficient of thermal expansion of the material of the second back gate conductive layer 22 is greater than or equal to 2 × 10⁻⁶. -6 / K. Where " / K" refers to the coefficient of thermal expansion, which is measured in Kelvin.

[0075] See also Figure 1 and Figure 2 The first gate 7 includes a first sub-gate 71 located in the first back gate conductive layer 2 and a second sub-gate 72 located in the second back gate conductive layer 2. The second gate 8 includes a third sub-gate 83 located in the first back gate conductive layer 2 and a fourth sub-gate 84 located in the second back gate conductive layer 2.

[0076] It is understandable that the material of the first sub-gate 71 is different from that of the second sub-gate 72, and the material of the third sub-gate 83 is different from that of the fourth sub-gate 84.

[0077] Along the direction Z perpendicular to the substrate 1, the thickness of the first sub-gate 71 is different from the thickness of the third sub-gate 83, or the thickness of the second sub-gate 72 is different from the thickness of the fourth sub-gate 84, or the thickness of the first sub-gate 71 is different from the thickness of the third sub-gate 83, and the thickness of the second sub-gate 72 is also different from the thickness of the fourth sub-gate 84.

[0078] For example Figure 1 As shown, along the direction Z perpendicular to the substrate 1, the thickness of the first sub-gate 71 is the same as the thickness of the third sub-gate 83, and the thickness of the second sub-gate 72 is different from the thickness of the fourth sub-gate 84. Alternatively, for example... Figure 2 As shown, the thickness of the first sub-gate 71 is different from the thickness of the third sub-gate 83, and the thickness of the second sub-gate 72 is also different from the thickness of the fourth sub-gate 84.

[0079] It is understandable that when the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 are different, the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 can be further controlled by adjusting the thickness ratio of the different metal film layers in the first gate 7 and the second gate 8, thereby controlling the threshold voltage of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102, thereby further improving the integration flexibility of multi-threshold voltage devices.

[0080] In some embodiments, see Figure 1and Figure 2 The material of the first sub-gate 71 is the same as the material of the third sub-gate 83, or the material of the second sub-gate 72 is the same as the material of the fourth sub-gate 84, or the material of the first sub-gate 71 is the same as the material of the third sub-gate 83, and the material of the second sub-gate 72 is the same as the material of the fourth sub-gate 84. The coefficient of thermal expansion of the material of the first gate 7 is different from that of the material of the second gate 8.

[0081] For example, the material of the first sub-gate 71 can be the same as the material of the third sub-gate 83. In this case, the first sub-gate 71 and the third sub-gate 83 can be formed simultaneously during the fabrication of the ferroelectric field-effect transistor integrated chip 100, thereby simplifying the process steps and reducing the process cost. Alternatively, the material of the first sub-gate 71 can be different from the material of the third sub-gate 83. In this case, the first sub-gate 71 and the third sub-gate 83 can be formed separately during the fabrication of the ferroelectric field-effect transistor integrated chip 100.

[0082] For example, the material of the second sub-gate 72 can be the same as that of the fourth sub-gate 84. In this case, the second sub-gate 72 and the fourth sub-gate 84 can be formed simultaneously during the fabrication of the ferroelectric field-effect transistor integrated chip 100, thereby simplifying the process steps and reducing process costs. Alternatively, the material of the second sub-gate 72 can be different from that of the fourth sub-gate 84. In this case, the second sub-gate 72 and the fourth sub-gate 84 can be formed separately during the fabrication of the ferroelectric field-effect transistor integrated chip 100, thereby forming a first gate 7 and a second gate 8 with different coefficients of thermal expansion.

[0083] It is understandable that when the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 are different, the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 can be further controlled by adjusting the different metal materials included in the first gate 7 and the second gate 8, thereby controlling the threshold voltage of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102, thereby further improving the integration flexibility of multi-threshold voltage devices.

[0084] Figure 3 This is a schematic diagram of another ferroelectric field-effect transistor integrated chip provided as an embodiment of this application.

[0085] In some embodiments, see Figure 3 The first gate 7 is made of a first alloy material, and the second gate 8 is made of a second alloy material. The coefficient of thermal expansion of the first alloy material is different from that of the second alloy material.

[0086] It is understandable that the back gate conductive layer 2 can be a single-layer alloy material layer. Both the first alloy material and the second alloy material include at least two metal materials with different coefficients of thermal expansion. By setting both the first gate 7 and the second gate 8 to be single-layer material layers, the first gate 7 or the second gate 8 can be formed in only one deposition process during the fabrication of the ferroelectric field-effect transistor integrated chip 100, which simplifies the process steps and reduces the process cost.

[0087] For example, the metal materials included in the first alloy material may be the same as those included in the second alloy material, and the different metals may constitute different proportions in the first and second alloy materials, thereby resulting in different coefficients of thermal expansion of the materials of the first gate 7 and the second gate 8. Alternatively, the metal materials included in the first alloy material may be different from those included in the second alloy material, and the coefficients of thermal expansion of the materials of the first gate 7 and the second gate 8 may be controlled by using different alloy materials.

[0088] In some embodiments, see Figures 1-3 The difference Δα between the thermal expansion coefficient of the first gate 7 and the thermal expansion coefficient of the material of the second gate 8 is greater than or equal to 4 × 10⁻⁶. -6 / K. Here, " / K" refers to the coefficient of thermal expansion, measured in Kelvin. For example, the value of Δα could be 4 × 10⁻⁶. -6 / K、5×10 -6 / K、6×10 -6 / K、7×10 -6 / K or 8×10 -6 / K.

[0089] It is understandable that by setting the thermal expansion coefficient of the first gate 7 to be Δα ≥ 4 × 10⁻⁶, the difference between the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 can be achieved. -6 / K can ensure the threshold voltage difference between the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102, thereby improving the distribution difference of threshold voltage of different devices in the ferroelectric field-effect transistor integrated chip 10, which is beneficial to optimizing the read / write power consumption and static power consumption of the storage system.

[0090] In some embodiments, see Figures 1-3 The difference between the threshold voltage of the first ferroelectric field-effect transistor 101 and the threshold voltage of the second ferroelectric field-effect transistor 102 is greater than or equal to 0.5V.

[0091] It is understandable that by setting the threshold voltage of the first ferroelectric field-effect transistor 101 to be greater than or equal to 0.5V with the threshold voltage of the second ferroelectric field-effect transistor 102, the distribution difference of the threshold voltage of different devices in the ferroelectric field-effect transistor integrated chip 10 can be improved, thereby ensuring the functional differentiation of the ferroelectric field-effect transistor integrated chip 10 and further optimizing the read / write power consumption and static power consumption of the storage system.

[0092] This application also provides an experiment for controlling the threshold voltage of the ferroelectric field-effect transistor 100. Figure 4 The simulation results provided in this application are shown in the figure.

[0093] See Figure 4 , Figure 4 In (a), the back gate conductive layer 2 is a double-layer metal gate, and the double metal layers are a ruthenium (Ru) layer and a molybdenum (Mo) layer, with the Ru layer being the one closer to the substrate 1. The coefficients of thermal expansion (CTE) of ruthenium and molybdenum are 9.6 × 10⁻⁶ and 9.6 × 10⁻⁶, respectively. -6 / k and 4.8×10 -6 The Young's modulus (YM) of ruthenium and molybdenum are 447 GPa and 329 GPa, respectively. The Poisson's ratio (ν) of ruthenium and molybdenum are 0.34 and 0.31, respectively. Poisson's ratio is a dimensionless physical quantity that describes the relationship between transverse strain and axial strain when a material is subjected to stress. It is defined as the ratio of transverse strain to axial strain.

[0094] Total thickness of back gate conductive layer 2 (T) total ) is 40nm, "T Mo "Refers to the thickness of the molybdenum layer," "T" total -T Mo "This refers to the thickness of the ruthenium layer. The ferroelectric layer 3 is made of hafnium oxide (HfO2) and has a thickness of 8 nm. The oxide semiconductor layer 4 is made of titanium dioxide (TiO2) and has a thickness of 6 nm."

[0095] Figure 4 (a) shows five sets of simulation experimental parameters. The independent variable in the simulation experimental parameters is the proportion of different metals in the double-layer metal grid, while other parameters remain consistent. In the first set of sample parameters, the thickness of the ruthenium layer is 0 nm, and the thickness of the molybdenum layer is 40 nm. In the second set of sample parameters, the thickness of the ruthenium layer is 8 nm, and the thickness of the molybdenum layer is 32 nm. In the third set of sample parameters, the thickness of the ruthenium layer is 16 nm, and the thickness of the molybdenum layer is 24 nm. In the fourth set of sample parameters, the thickness of the ruthenium layer is 24 nm, and the thickness of the molybdenum layer is 16 nm. In the fifth set of sample parameters, the thickness of the ruthenium layer is 32 nm, and the thickness of the molybdenum layer is 8 nm.

[0096] Figure 4 (b) for Figure 4(a) shows the results obtained from the experiment using the five sets of simulation parameters. The horizontal axis represents the number of sample groups, and the vertical axis represents the tensile stress on the channel region 41. The unit of tensile stress is "GPa".

[0097] Depend on Figure 4 (a) shows that the thickness of the molybdenum layer gradually decreases in the five sets of simulation parameters. From Figure 4 (b) It can be seen that at an annealing temperature of 250°C, as the proportion of molybdenum layer in the back gate conductive layer 2 decreases, the tensile stress on the channel region 41 gradually increases. That is, in the back gate conductive layer 2, the lower the proportion of metal near the ferroelectric layer 3, the greater the tensile stress on the channel region 41, i.e., the greater the tensile stress generated by the back gate conductive layer 2, the greater the threshold voltage of the ferroelectric field-effect transistor 100.

[0098] Figure 4 (c) is for Figure 4 (a) Drain current (I) of ferroelectric field-effect transistor 100 under five sets of simulation experimental parameters D ) and gate voltage (V G The characteristic relationship curves of the ferroelectric field-effect transistor 100 are shown. The ferroelectric field-effect transistor 100 has a programmed state (PRG) and an erased state (ESR). The ferroelectric field-effect transistor 100 in the above two different states has different threshold voltages (Vth) and conductivity characteristics. Therefore, the ferroelectric field-effect transistor 100 corresponding to each set of sample parameters has two different characteristic curves.

[0099] Depend on Figure 4 (a) shows that the thickness of the molybdenum layer gradually decreases in the five sets of simulation parameters. From Figure 4 (c) It can be seen that as the proportion of molybdenum layer in back gate conductive layer 2 decreases, the tensile stress on channel region 4 gradually increases, and the threshold voltage of ferroelectric field effect transistor 100 becomes larger.

[0100] Figure 4 (d) is Figure 4 (c) shows a line graph depicting the relationship between the threshold voltages of the ferroelectric field-effect transistor 100 in the programmed state (PRG) and erased state (ESR) for the five sets of simulation experimental parameters. The horizontal axis represents the number of sample groups, and the vertical axis represents the threshold voltage (V). T The threshold voltage is measured in volts (V). T-PRG "V" refers to the threshold voltage corresponding to the programmed state. T-ESR "Refers to the threshold voltage corresponding to the erase state."

[0101] Depend on Figure 4(d) It can be seen that as the proportion of molybdenum layer in back gate conductive layer 2 decreases, the tensile stress on channel region 41 gradually increases, the threshold voltage of ferroelectric field effect transistor 100 in programming state gradually increases, and the threshold voltage of ferroelectric field effect transistor 100 in erase state also gradually increases.

[0102] In summary, see [link / reference] Figure 4 By adjusting the thickness of different metals in the back gate conductive layer 2, that is, by adjusting the thickness of different metals in the first gate 7 or the second gate 8, the composition of different metals can be changed, thereby changing the thermal expansion coefficient of the materials of the first gate 7 or the second gate 8. The different thermal expansion coefficients of the materials of the first gate 7 or the second gate 8 can cause different stresses to be conducted to the channel region 41 after the thermal annealing process, so that the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 generate different threshold voltages. Thus, the wafer-level integration of ferroelectric field-effect transistors 100 with different threshold voltages can be realized in the fabrication process, providing a new technical path for the design and manufacturing of next-generation high-density, low-power, multi-functional FeFET memories (such as 3D NAND) and multi-voltage domain logic circuits.

[0103] On the other hand, embodiments of this application also provide a method for fabricating a ferroelectric field-effect transistor integrated chip 10, for forming such a... Figure 1 The ferroelectric field-effect transistor integrated chip 10 is shown. Figure 5 A flowchart illustrating a method for fabricating a ferroelectric field-effect transistor integrated chip, provided as an embodiment of this application; Figures 6-10 for Figure 5 The preparation method is illustrated in the following diagrams.

[0104] See Figure 5 The preparation method includes the following steps S1 to S4: Step S1: See Figures 6-8 A first gate 7 and a second gate 8 are formed on a substrate 1. The material of the first gate 7 includes at least two materials, the material of the second gate 8 includes at least two materials, and the coefficient of thermal expansion of the material of the first gate 7 is different from that of the second gate 8.

[0105] Step S1 includes the following steps S101 to S103: Step S101: See Figure 6 A back gate conductive layer 2 is formed on a substrate 1. The back gate conductive layer 2 includes a first back gate conductive layer 21 and a second back gate conductive layer 22 that are sequentially stacked on the substrate 1. The material of the back gate conductive layer 2 includes at least two materials with different coefficients of thermal expansion.

[0106] It is understandable that the first back gate conductive layer 21 and the second back gate conductive layer 22 are made of different materials. By setting the first back gate conductive layer 21 and the second back gate conductive layer 22 with different coefficients of thermal expansion, the back gate conductive layer 2 can undergo different degrees of thermal expansion at high temperatures, thereby achieving continuous control of the thermal expansion of the back gate conductive layer 2. This allows the back gate conductive layer 2 to generate the required stress, thereby controlling the grain size and oxygen vacancy distribution of the subsequently formed channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus controlling the threshold voltage of the ferroelectric field-effect transistor 100.

[0107] For example, the first back gate conductive layer 21 and the second back gate conductive layer 22 can be formed sequentially by a deposition process. In the embodiments of this application, the deposition process can be physical vapor deposition, chemical vapor deposition, or any other film formation process.

[0108] Deposition processes are key technologies used in many fields, including semiconductor manufacturing, to form uniform thin films on substrate surfaces. Through specific physical or chemical means, the materials constituting the thin film migrate from the source material to the substrate surface in the form of atoms, molecules, or ions, gradually depositing and growing on the substrate to ultimately form a continuous thin film with specific thickness, composition, and properties. Common deposition processes include physical vapor deposition (PVD) and chemical vapor deposition (CVD). PVD uses physical methods such as high temperature and high-energy particle bombardment to evaporate or sublimate the source material before depositing it on the substrate. CVD utilizes gaseous chemicals to react on the substrate surface, generating solid thin film materials. These processes allow for precise control of the film's thickness, uniformity, and composition.

[0109] For example, the back gate conductive layer 2 can also be a stack of at least two metal material layers. The back gate conductive layer 2 can be formed by sequentially depositing each metal layer onto the substrate 1 through multiple deposition processes. The back gate conductive layer 2 can be a stacked structure of three or more metal layers, in which at least two different metal materials are present. The stacked structure can be TiN / W / Ti, TaN / Al / TaN, or Ru / Mo / Ru. For example, in the case where the back gate conductive layer 2 is a Ru / Mo / Ru stacked structure, a ruthenium (Ru) layer, a molybdenum (Mo) layer, and a ruthenium (Ru) layer can be sequentially deposited onto the substrate 1 through a deposition process to form the back gate conductive layer 2.

[0110] In this embodiment, the back gate conductive layer 2 is a stack of two different metal material layers as an example for illustration.

[0111] Step S102: See Figure 7The back gate conductive layer 2 is etched to form a first gate 7 and a second gate 8. The first gate 7 includes a first sub-gate 71 located in the first back gate conductive layer 2 and a second sub-gate 72 located in the second back gate conductive layer 2. The second gate 8 includes a third sub-gate 83 located in the first back gate conductive layer 2 and a fourth sub-gate 84 located in the second back gate conductive layer 2.

[0112] It is understandable that the back gate conductive layer 2 can be etched using photolithography to define the gate positions of different ferroelectric field-effect transistors, namely the positions of the first gate 7 and the second gate 8. In the above case, the material of the first sub-gate 71 is the same as the material of the third sub-gate 83, and the material of the second sub-gate 72 is also the same as the material of the fourth sub-gate 84.

[0113] Step S103: See Figure 8 The second sub-gate 72 of the first gate 7 is etched to thin the second sub-gate 72.

[0114] For example, the second sub-gate 72 can be etched by plasma etching process so that the proportion of the second sub-gate 72 in the first gate 7 is different from the proportion of the fourth sub-gate 84 in the second gate 8, thereby making the proportions of each material in the first gate 7 and the second gate 8 different, so as to form a first gate 7 and a second gate 8 with different coefficients of thermal expansion.

[0115] Step S2: See Figure 9 On the side of the first gate 7 and the second gate 8 away from the substrate 1, a ferroelectric layer 3 and an oxide semiconductor layer 4 are sequentially formed. The coefficient of thermal expansion of the material of the ferroelectric layer 3 is different from that of the materials of the first gate 7 and the second gate 8.

[0116] For example, an atomic layer deposition process can be used to deposit a ferroelectric material layer and an oxide semiconductor material layer on the entire surface in sequence. Then, a photolithography process can be used to etch the oxide semiconductor material layer to form an oxide semiconductor layer 4 and define the active region. Then, the ferroelectric material layer can be etched to form a ferroelectric layer 3.

[0117] For example, the atomic layer deposition process parameters can be: chamber growth temperature of 200°C to 300°C, and oxidant of ozone, water, or oxygen plasma. By setting the above process parameters, the oxide semiconductor layer 4 can be kept under low stress during growth, and the stack of oxide semiconductor layer 4 and ferroelectric layer 3 can generate mechanical stress with the back gate conductive layer 2 in the cooled state.

[0118] It is understandable that when the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 are different, the thickness ratio of different metal film layers in the first gate 7 and the second gate 8 can be adjusted by thinning the second sub-gate 72, thereby further adjusting the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8, and thus adjusting the threshold voltage of the subsequently formed first ferroelectric field-effect transistor 101 and second ferroelectric field-effect transistor 102, thereby further improving the integration flexibility of multi-threshold voltage devices.

[0119] Furthermore, by using only two deposition processes and two etching processes, a first gate 7 and a second gate 8 with different coefficients of thermal expansion can be formed, so that the first gate 7 and the second gate 8 will generate different stresses in the subsequent thermal annealing process, thereby improving the integration flexibility and manufacturing efficiency of multi-threshold voltage devices.

[0120] Step S3: See Figure 10 Source 5 and drain 6 are formed on the side of oxide semiconductor layer 4 away from substrate 1.

[0121] For example, the source and drain electrode layers can be deposited on the entire surface using a deposition process, and then the source and drain electrode layers can be etched using a photolithography process, thereby simultaneously forming the source 5 and drain 6.

[0122] Step S4: See Figure 1 A channel region 41 is formed in the oxide semiconductor layer 4 using a thermal annealing process to form the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102.

[0123] In the above-mentioned thermal annealing process, all regions of the ferroelectric field effect transistor integrated chip 10 undergo the same temperature curve. The first ferroelectric field effect transistor 101 and the second ferroelectric field effect transistor 102 with different threshold voltages can be formed by only one thermal annealing process. This achieves threshold voltage differentiation of the ferroelectric field effect transistor 100 in the integrated chip 10, simplifies process control, and improves the fabrication yield of the ferroelectric field effect transistor integrated chip 10.

[0124] It is understandable that the first gate 7 and the second gate 8 can generate different stresses in the above-mentioned thermal annealing process. The stresses are conducted to the channel region 41 through the ferroelectric layer 3, which can cause the channel region 41 to form different grain sizes and oxygen vacancy distributions, thereby making the carrier concentration and mobility of the two channel regions 41 different, thus forming ferroelectric field-effect transistors 100 with different threshold voltages.

[0125] Furthermore, the embodiments provided in this application, without increasing the additional thermal budget, do not require ion implantation and multiple channel depositions. They can apply controllable stress at a specified position in the oxide semiconductor layer 4 through only gate patterning, one channel film formation, and one thermal annealing process steps. This enables differentiated control of the threshold voltages of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102, thereby achieving device integration with multiple threshold voltages.

[0126] For example, the above-mentioned thermal annealing process parameters can be: peak temperature 400℃~600℃, holding time 10s~60s, temperature of the high-temperature region greater than 300℃, and cooling rate greater than 10℃ / s. By setting the above process parameters, the stress generated by the first gate 7 and the second gate 8 can be effectively transferred to the oxide semiconductor layer 4 without damaging the ferroelectricity and interface integrity of the ferroelectric layer 3.

[0127] The fabrication method provided in the embodiments of this application includes sequentially forming a back gate conductive layer 2, a ferroelectric layer 3, an oxide semiconductor layer 4, and a source electrode 5 and a drain electrode 6 on a substrate 1. Furthermore, a channel region 41 is formed within the oxide semiconductor layer 4 through a thermal annealing process to form a first ferroelectric field-effect transistor 101 and a second ferroelectric field-effect transistor 102. The materials of the first gate 7 and the second gate 8 each comprise at least two materials, and the thermal expansion coefficients of the first gate 7 and the second gate 8 are different. The thermal expansion coefficient of the material of the ferroelectric layer 3 is different from that of the materials of the first gate 7 and the second gate 8.

[0128] Understandably, during the formation of the ferroelectric field-effect transistor integrated chip 10, the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 are formed simultaneously. By employing a thermal annealing process to form a channel region 41 in the oxide semiconductor layer 4, the threshold voltage of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 can be controlled. Since the material of the back gate conductive layer 2 includes at least two materials with different coefficients of thermal expansion, and the coefficient of thermal expansion of the ferroelectric layer 3 is different from that of the back gate conductive layer 2, the different materials in the back gate conductive layer 2 undergo different degrees of thermal expansion during the thermal annealing process. This allows for continuous control of the thermal expansion of the back gate conductive layer 2, thereby generating the necessary stress in the back gate conductive layer 2 during the cooling stage and improving the threshold voltage control accuracy of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102.

[0129] Furthermore, since the coefficient of thermal expansion of the material of the first gate 7 is different from that of the material of the second gate 8, the first gate 7 and the second gate 8 will undergo different degrees of thermal expansion during the thermal annealing process, thereby causing the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102 to have different threshold voltages. In other words, ferroelectric field-effect transistors 100 with different threshold voltages can be formed on the substrate 1 through only one thermal annealing process. This allows for flexible control of the threshold voltage position of the ferroelectric field-effect transistors 100 during the fabrication process, thereby improving the integration flexibility of ferroelectric field-effect transistors 100 with different threshold voltages in the ferroelectric field-effect transistor integrated chip 10 and the manufacturing efficiency of the ferroelectric field-effect transistor integrated chip 10.

[0130] On the other hand, embodiments of this application also provide another method for fabricating a ferroelectric field-effect transistor integrated chip 10, for forming such a... Figure 2 The ferroelectric field-effect transistor integrated chip 10 is shown. Figure 11 A flowchart illustrating another method for fabricating a ferroelectric field-effect transistor integrated chip provided for embodiments of this application; Figures 12-15 for Figure 11 The preparation method is illustrated in the following diagrams.

[0131] See Figure 11 The preparation method includes the following steps S1 to S4: Step S1: See Figure 12 and Figure 13 A first gate 7 and a second gate 8 are formed on a substrate 1. The material of the first gate 7 includes at least two materials, the material of the second gate 8 includes at least two materials, and the coefficient of thermal expansion of the material of the first gate 7 is different from that of the second gate 8.

[0132] Step S1 includes the following steps S101 and S102: Step S101: See Figure 12 A first gate 7 is formed on a substrate 1. The first gate 7 includes a first sub-gate 71 and a second sub-gate 72 that are sequentially stacked on the substrate 1. The first sub-gate 71 and the second sub-gate 72 are made of different materials and have different coefficients of thermal expansion.

[0133] It is understandable that by setting the first sub-gate 71 and the second sub-gate 72 with different coefficients of thermal expansion, the first gate 7 can undergo different degrees of thermal expansion at high temperature, thereby achieving continuous control of the thermal expansion of the first gate 7. This allows the first gate 7 to generate the required stress, thereby controlling the grain size and oxygen vacancy distribution of the subsequently formed channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus controlling the threshold voltage of the first ferroelectric field-effect transistor 101.

[0134] For example, the first sub-gate 71 and the second sub-gate 72 can be formed sequentially by a deposition process and an etching process.

[0135] Step S102: See Figure 13 A second gate 8 is formed on the substrate 1. The second gate 8 includes a third sub-gate 83 and a fourth sub-gate 84 that are sequentially stacked on the substrate 1. The third sub-gate 83 and the fourth sub-gate 84 are made of different materials and have different coefficients of thermal expansion.

[0136] It is understandable that by setting the third sub-gate 83 and the fourth sub-gate 84 with different coefficients of thermal expansion, the second gate 8 can undergo different degrees of thermal expansion at high temperatures, thereby achieving continuous control of the thermal expansion of the second gate 8. This allows the second gate 8 to generate the required stress, thereby controlling the grain size and oxygen vacancy distribution of the subsequently formed channel region 41, thus changing the carrier concentration and mobility of the channel region 41, and thereby controlling the threshold voltage of the second ferroelectric field-effect transistor 102.

[0137] For example, the third sub-gate 83 and the fourth sub-gate 84 can be formed sequentially by deposition and etching processes.

[0138] The first gate 7 and the second gate 8 have different coefficients of thermal expansion. Along the direction Z perpendicular to the substrate 1, the thickness of the first sub-gate 71 is different from the thickness of the third sub-gate 83, or the thickness of the second sub-gate 72 is different from the thickness of the fourth sub-gate 84, or the thickness of the first sub-gate 71 is different from the thickness of the third sub-gate 83, and the thickness of the second sub-gate 72 is different from the thickness of the fourth sub-gate 84.

[0139] For example, the material of the first sub-gate 71 can be the same as the material of the third sub-gate 83, and the material of the second sub-gate 72 can be the same as the material of the fourth sub-gate 84. In this case, the thickness of the first sub-gate 71 can be different from the thickness of the third sub-gate 83, and the thickness of the second sub-gate 72 can be different from the thickness of the fourth sub-gate 84, so that the same metal has different proportions in the different gates, thereby forming a first gate 7 and a second gate 8 with different coefficients of thermal expansion.

[0140] For example, the materials of the first sub-gate 71 and the third sub-gate 83 may be different, or the materials of the second sub-gate 72 and the fourth sub-gate 84 may also be different. In this case, the proportion of the first sub-gate 71 in the first gate 7 and the proportion of the third sub-gate 83 in the second gate 8 can be adjusted by selectively adjusting the thicknesses of the first sub-gate 71, the second sub-gate 72, the third sub-gate 83 and the fourth sub-gate 84, thereby adjusting the coefficients of thermal expansion of the first gate 7 and the second gate 8.

[0141] It is understood that the fabrication method provided in this embodiment can improve the flexibility of threshold voltage regulation of different ferroelectric field-effect transistors 100 in the ferroelectric field-effect transistor integrated chip 10.

[0142] Step S2: See Figure 14 On the side of the first gate 7 and the second gate 8 away from the substrate 1, a ferroelectric layer 3 and an oxide semiconductor layer 4 are sequentially formed. The coefficient of thermal expansion of the material of the ferroelectric layer 3 is different from that of the materials of the first gate 7 and the second gate 8.

[0143] For example, an atomic layer deposition process can be used to deposit a ferroelectric material layer and an oxide semiconductor material layer on the entire surface in sequence. Then, a photolithography process can be used to etch the oxide semiconductor material layer to form an oxide semiconductor layer 4 and define the active region. Then, the ferroelectric material layer can be etched to form a ferroelectric layer 3.

[0144] For example, the atomic layer deposition process parameters can be: chamber growth temperature of 200°C to 300°C, and oxidant of ozone, water, or oxygen plasma. By setting the above process parameters, the oxide semiconductor layer 4 can be kept under low stress during growth, and the stack of oxide semiconductor layer 4 and ferroelectric layer 3 can generate mechanical stress with the back gate conductive layer 2 in the cooled state.

[0145] It is understandable that when the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 are different, the thickness ratio of different metal film layers in the first gate 7 and the second gate 8 can be adjusted by thinning the second sub-gate 72, thereby further adjusting the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8, and thus adjusting the threshold voltage of the subsequently formed first ferroelectric field-effect transistor 101 and second ferroelectric field-effect transistor 102, thereby further improving the integration flexibility of multi-threshold voltage devices.

[0146] Furthermore, by using only two deposition processes and two etching processes, a first gate 7 and a second gate 8 with different coefficients of thermal expansion can be formed, causing the first gate 7 and the second gate 8 to generate different stresses in the subsequent thermal annealing process. This enables differentiated control of the threshold voltages of the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102, thereby improving the integration flexibility and manufacturing efficiency of multi-threshold voltage devices.

[0147] Step S3: See Figure 15 Source 5 and drain 6 are formed on the side of oxide semiconductor layer 4 away from substrate 1.

[0148] For example, the source and drain electrode layers can be deposited on the entire surface using a deposition process, and then the source and drain electrode layers can be etched using a photolithography process, thereby simultaneously forming the source 5 and drain 6.

[0149] Step S4: See Figure 2 A channel region 41 is formed in the oxide semiconductor layer 4 using a thermal annealing process to form the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102.

[0150] For example, in the above-mentioned thermal annealing process, all regions of the ferroelectric field effect transistor integrated chip 10 undergo the same temperature curve. The first ferroelectric field effect transistor 101 and the second ferroelectric field effect transistor 102 with different threshold voltages can be formed by only one thermal annealing process. This achieves threshold voltage differentiation of the ferroelectric field effect transistor 100 in the integrated chip 10, simplifies process control, and improves the fabrication yield of the ferroelectric field effect transistor integrated chip 10.

[0151] It is understandable that the first gate 7 and the second gate 8 can generate different stresses in the above-mentioned thermal annealing process. The stresses are conducted to the channel region 41 through the ferroelectric layer 3, which can cause the channel region 41 to form different grain sizes and oxygen vacancy distributions, thereby making the carrier concentration and mobility of the two channel regions 41 different, thus forming ferroelectric field-effect transistors 100 with different threshold voltages.

[0152] On the other hand, embodiments of this application also provide another method for fabricating a ferroelectric field-effect transistor integrated chip 10, for forming such a... Figure 3 The ferroelectric field-effect transistor integrated chip 10 is shown. Figure 16 A flowchart illustrating a method for fabricating a ferroelectric field-effect transistor integrated chip, provided as an embodiment of this application; Figures 17-20 for Figure 16 The preparation method is illustrated in the following diagrams.

[0153] See Figure 16 The preparation method includes the following steps S1 to S4: Step S1: See Figure 17 and Figure 18 A first gate 7 and a second gate 8 are formed on a substrate 1. The material of the first gate 7 includes at least two materials, the material of the second gate 8 includes at least two materials, and the coefficient of thermal expansion of the material of the first gate 7 is different from that of the second gate 8.

[0154] Step S1 includes the following steps S101 and S102: Step S101: See Figure 17 A first gate 7 is formed on the substrate 1, and the material of the first gate 7 includes a first alloy material.

[0155] It is understandable that by setting the material of the first gate 7 to the first alloy material, the first gate 7 can contain materials with different coefficients of thermal expansion, thereby causing the first gate 7 to undergo different degrees of thermal expansion at high temperatures, thus achieving continuous control of the thermal expansion of the first gate 7, so that the first gate 7 generates the required stress, thereby controlling the grain size and oxygen vacancy distribution of the subsequently formed channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus controlling the threshold voltage of the first ferroelectric field-effect transistor 101.

[0156] For example, the first sub-gate 71 and the second sub-gate 72 can be formed sequentially by a deposition process and a photolithography etching process.

[0157] Step S102: See Figure 18 A second gate 8 is formed on the substrate 1, and the material of the second gate 8 includes a second alloy material. The coefficient of thermal expansion of the first alloy material is different from that of the second alloy material; that is, the coefficients of thermal expansion of the first gate 7 and the second gate 8 are different.

[0158] It is understandable that by setting the material of the second gate 8 to the first alloy material, the second gate 8 can contain materials with different coefficients of thermal expansion, thereby causing the second gate 8 to undergo different degrees of thermal expansion at high temperatures, thus achieving continuous control of the thermal expansion of the second gate 8. This allows the second gate 8 to generate the required stress, thereby controlling the grain size and oxygen vacancy distribution of the subsequently formed channel region 41, thereby changing the carrier concentration and mobility of the channel region 41, and thus controlling the threshold voltage of the second ferroelectric field-effect transistor 102.

[0159] For example, a single-layer alloy material for the first gate 7 or the second gate 8 can be directly formed on the substrate 1 through a single deposition process. The alloy material comprises at least two materials with different coefficients of thermal expansion. For instance, both the first alloy material and the second alloy material can be Ti1- x W x Mo1- Ru Or W1- x Mo x One of them.

[0160] For example, along the direction Z perpendicular to the substrate 1, the thickness of the first gate 7 and the thickness of the second gate 8 may be the same or different.

[0161] Step S2: See Figure 19On the side of the first gate 7 and the second gate 8 away from the substrate 1, a ferroelectric layer 3 and an oxide semiconductor layer 4 are sequentially formed. The coefficient of thermal expansion of the material of the ferroelectric layer 3 is different from that of the materials of the first gate 7 and the second gate 8.

[0162] For example, an atomic layer deposition process can be used to deposit a ferroelectric material layer and an oxide semiconductor material layer on the entire surface in sequence. Then, a photolithography process can be used to etch the oxide semiconductor material layer to form an oxide semiconductor layer 4 and define the active region. Then, the ferroelectric material layer can be etched to form a ferroelectric layer 3.

[0163] For example, the atomic layer deposition process parameters can be: chamber growth temperature of 200°C to 300°C, and oxidant of ozone, water, or oxygen plasma. By setting the above process parameters, the oxide semiconductor layer 4 can be kept under low stress during growth, and the stack of oxide semiconductor layer 4 and ferroelectric layer 3 can generate mechanical stress with the back gate conductive layer 2 in the cooled state.

[0164] It is understandable that when the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8 are different, the thickness ratio of different metal film layers in the first gate 7 and the second gate 8 can be adjusted by thinning the second sub-gate 72, thereby further adjusting the thermal expansion coefficients of the materials of the first gate 7 and the second gate 8, and thus adjusting the threshold voltage of the subsequently formed first ferroelectric field-effect transistor 101 and second ferroelectric field-effect transistor 102, thereby further improving the integration flexibility of multi-threshold voltage devices.

[0165] Furthermore, by using only two deposition processes and two etching processes, a first gate 7 and a second gate 8 with different coefficients of thermal expansion can be formed, so that the first gate 7 and the second gate 8 will generate different stresses in the subsequent thermal annealing process, thereby improving the integration flexibility and manufacturing efficiency of multi-threshold voltage devices.

[0166] Step S3: See Figure 20 Source 5 and drain 6 are formed on the side of oxide semiconductor layer 4 away from substrate 1.

[0167] For example, the source and drain electrode layers can be deposited on the entire surface using a deposition process, and then the source and drain electrode layers can be etched using a photolithography process, thereby simultaneously forming the source 5 and drain 6.

[0168] Step S4: See Figure 3 A channel region 41 is formed in the oxide semiconductor layer 4 using a thermal annealing process to form the first ferroelectric field-effect transistor 101 and the second ferroelectric field-effect transistor 102.

[0169] For example, in the above-mentioned thermal annealing process, all regions of the ferroelectric field effect transistor integrated chip 10 undergo the same temperature curve. The first ferroelectric field effect transistor 101 and the second ferroelectric field effect transistor 102 with different threshold voltages can be formed by only one thermal annealing process. This achieves threshold voltage differentiation of the ferroelectric field effect transistor 100 in the integrated chip 10, simplifies process control, and improves the fabrication yield of the ferroelectric field effect transistor integrated chip 10.

[0170] It is understandable that the first gate 7 and the second gate 8 can generate different stresses in the above-mentioned thermal annealing process. The stresses are conducted to the channel region 41 through the ferroelectric layer 3, which can cause the channel region 41 to form different grain sizes and oxygen vacancy distributions, thereby making the carrier concentration and mobility of the two channel regions 41 different, thus forming ferroelectric field-effect transistors 100 with different threshold voltages.

[0171] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A ferroelectric field-effect transistor integrated chip, characterized in that, include: A substrate, and a back gate conductive layer disposed on the substrate; The back gate conductive layer is made of at least two materials, and the two materials have different coefficients of thermal expansion. A ferroelectric layer is disposed on the side of the back gate conductive layer away from the substrate; the coefficient of thermal expansion of the material of the ferroelectric layer is different from that of the material of the back gate conductive layer. An oxide semiconductor layer is disposed on the side of the ferroelectric layer away from the substrate; the oxide semiconductor layer includes a channel region; The source and drain are disposed on the side of the oxide semiconductor layer away from the substrate; the orthographic projection of the channel region on the substrate is located between the orthographic projection of the source on the substrate and the orthographic projection of the drain on the substrate; The ferroelectric field-effect transistor integrated chip further includes multiple ferroelectric field-effect transistors, namely a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor; the first ferroelectric field-effect transistor includes a first gate located on the back gate conductive layer, and the material of the first gate includes at least two materials; the second ferroelectric field-effect transistor includes a second gate located on the back gate conductive layer, and the material of the second gate includes at least two materials; the coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate.

2. The ferroelectric field-effect transistor integrated chip according to claim 1, characterized in that, The back gate conductive layer includes a first back gate conductive layer and a second back gate conductive layer stacked together; the first gate includes a first sub-gate located in the first back gate conductive layer and a second sub-gate located in the second back gate conductive layer; the second gate includes a third sub-gate located in the first back gate conductive layer and a fourth sub-gate located in the second back gate conductive layer. Along a direction perpendicular to the substrate, the thickness of the first sub-gate is different from the thickness of the third sub-gate, and / or the thickness of the second sub-gate is different from the thickness of the fourth sub-gate.

3. The ferroelectric field-effect transistor integrated chip according to claim 2, characterized in that, The material of the first sub-gate is the same as the material of the third sub-gate, and / or the material of the second sub-gate is the same as the material of the fourth sub-gate; The coefficient of thermal expansion of the material of the first gate is different from that of the material of the second gate.

4. The ferroelectric field-effect transistor integrated chip according to claim 1, characterized in that, The first gate is made of a first alloy material, and the second gate is made of a second alloy material. The coefficient of thermal expansion of the first alloy material is different from that of the second alloy material.

5. The ferroelectric field-effect transistor integrated chip according to claim 1, characterized in that, The difference between the thermal expansion coefficient of the first gate and the thermal expansion coefficient of the material of the second gate is greater than or equal to 4 × 10⁻⁶. -6 / K.

6. The ferroelectric field-effect transistor integrated chip according to claim 5, characterized in that, The difference between the threshold voltage of the first ferroelectric field-effect transistor and the threshold voltage of the second ferroelectric field-effect transistor is greater than or equal to 0.5V.

7. A method for fabricating a ferroelectric field-effect transistor integrated chip, characterized in that, include: A first gate and a second gate are formed on a substrate, wherein the material of the first gate comprises at least two materials, and the material of the second gate comprises at least two materials; the coefficient of thermal expansion of the material of the first gate is different from that of the second gate. A ferroelectric layer and an oxide semiconductor layer are sequentially formed on the side of the first gate and the second gate away from the substrate; the coefficient of thermal expansion of the material of the ferroelectric layer is different from the coefficient of thermal expansion of the materials of the first gate and the second gate. A source and a drain are formed on the side of the oxide semiconductor layer away from the substrate; A channel region is formed within the oxide semiconductor layer using a thermal annealing process to form a first ferroelectric field-effect transistor and a second ferroelectric field-effect transistor.

8. The preparation method according to claim 7, characterized in that, The process of forming the first gate and the second gate on the substrate includes: A back gate conductive layer is formed on a substrate, the back gate conductive layer comprising a first back gate conductive layer and a second back gate conductive layer sequentially stacked on the substrate; the material of the back gate conductive layer comprises at least two materials, the two materials having different coefficients of thermal expansion. The back gate conductive layer is etched to form a first gate and a second gate; the first gate includes a first sub-gate located in the first back gate conductive layer and a second sub-gate located in the second back gate conductive layer; the second gate includes a third sub-gate located in the first back gate conductive layer and a fourth sub-gate located in the second back gate conductive layer. The second sub-gate of the first gate is etched to thin the second sub-gate.

9. The preparation method according to claim 7, characterized in that, The process of forming the first gate and the second gate on the substrate includes: A first gate is formed on a substrate, the first gate comprising a first sub-gate and a second sub-gate sequentially stacked on the substrate; the first sub-gate and the second sub-gate are made of different materials and have different coefficients of thermal expansion; A second gate is formed on the substrate, the second gate including a third sub-gate and a fourth sub-gate sequentially stacked on the substrate; the third sub-gate and the fourth sub-gate are made of different materials and have different coefficients of thermal expansion; Wherein, the first gate and the second gate have different coefficients of thermal expansion; along the direction perpendicular to the substrate, the thickness of the first sub-gate is different from the thickness of the third sub-gate, and / or, the thickness of the second sub-gate is different from the thickness of the fourth sub-gate.

10. The preparation method according to claim 7, characterized in that, The process of forming the first gate and the second gate on the substrate includes: A first gate is formed on a substrate, wherein the material of the first gate includes a first alloy material; A second gate is formed on the substrate, wherein the material of the second gate includes a second alloy material; The coefficient of thermal expansion of the first alloy material is different from that of the second alloy material.

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