A floating gate-free continuously programmable multi-level nonvolatile memory device and a method for regulating the same

Abstract

The application belongs to the field of microelectronic technology, and discloses a non-floating gate continuous programmable multi-level nonvolatile memory device and a regulation method thereof. The device comprises a silicon dioxide / silicon substrate, a hexagonal boron nitride medium layer and a rhenium disulfide channel layer stacked on the substrate from bottom to top, and source and drain electrodes arranged at both ends of the channel layer; the substrate, the hexagonal boron nitride medium layer and the rhenium disulfide channel layer form a van der Waals heterostructure, and the device does not have a floating gate layer. Through the synergistic effect of ultraviolet light irradiation and a gate electric field, the charge occupation behavior of the hexagonal boron nitride medium layer and the defect states at the interface thereof is regulated, the carrier concentration in the rhenium disulfide channel layer is continuously changed, thereby forming multiple stable and distinguishable nonvolatile conductive states, and continuous programmable multi-level nonvolatile storage is realized. The device structure is simple, and more than 6-bit multi-level storage capacity can be realized without a floating gate layer, and the storage capacity can be maintained for more than ten years.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology and relates to a non-floating gate continuously programmable multi-level non-volatile memory device and its control method. Background Technology

[0002] Non-volatile memory has significant application value in information storage and integrated circuit systems. Traditional flash memory devices typically employ floating gate structures or charge trapping layers to store information, and their multi-level storage capacity mainly depends on the discrete adjustment of charge injection. As device sizes continue to shrink, traditional high-field tunneling or hot carrier injection methods easily lead to problems such as higher operating voltages, greater power consumption, and decreased dielectric reliability. More importantly, the inherent existence of floating gate structures or charge trapping layers directly limits the synchronous miniaturization of traditional flash memory and logic operation devices, necessitating 3D stacking to meet the information industry's demand for high-capacity flash memory, resulting in complex processes and drastically increased costs.

[0003] To overcome the aforementioned problems, researchers have introduced two-dimensional materials (such as graphene, transition metal chalcogenides, and hexagonal boron nitride) into non-volatile memory devices. Two-dimensional materials possess atomically flat surfaces, dangling-bond-free van der Waals interfaces, and tunable band structures, offering new possibilities for achieving high-quality heterogeneous integration and reducing operating voltage. Simultaneously, their atomically thin channels enhance gate electrostatic control, effectively suppressing short-channel effects and leakage current issues; the low-defect-density van der Waals heterostructures facilitate precise control of carrier injection, transport, and trapping processes, enabling optimized control of tunneling barriers and interface coupling. Two-dimensional materials enable a shift from traditional high-field driven to interface-controlled charge programming mechanisms, thereby achieving higher programming speeds, better retention characteristics, and higher device reliability while reducing power consumption. For example, Chinese patent CN111785829A discloses a multi-bit flash memory cell employing a graphene / hexagonal boron nitride / molybdenum disulfide floating gate structure. By applying electric fields of varying intensities, electrons tunnel to the graphene layer, achieving 3-bit (8 states) multi-level storage. Chinese patent CN120076432A further discloses a photoelectric synaptic device, also employing a graphene / hexagonal boron nitride / rhenium disulfide floating gate structure. It utilizes optical pulses for erasing and electrical pulses for writing, achieving 10-bit (1024 states) high-precision synaptic weighting. Furthermore, Korean patent KR102611057B1 discloses a memory device with a functionalized hexagonal boron nitride-based charge storage layer. This device functionalizes the hexagonal boron nitride using chemical methods such as oxygen plasma to adjust its charge storage capacity. Chinese patent CN120302675A uses PbI2 as a charge trapping layer, utilizing its natural iodine vacancy defects to achieve charge trapping and obtain a larger storage window.

[0004] However, existing multi-level non-volatile memory devices often have the following shortcomings:

[0005] First, the precision of storage state adjustment is limited, making it difficult to achieve continuous, fine-grained multi-level programming. While schemes such as CN111785829A and CN120076432A achieve multi-level storage, they still fundamentally rely on the discrete accumulation or release of charge in traditional floating gate structures. Even with CN120076432A achieving 10-bit precision, its storage state is still limited by the capacitive coupling effect of the floating gate and the discrete defect trapping characteristics of the tunneling layer, making it difficult to achieve truly continuous, stepless conductance adjustment. The conductance change of floating gate devices depends on the injection and release of electrons within the floating gate. Since electron transport has discrete characteristics, under conditions of device size reduction, a small increase or decrease in electrons can cause a significant threshold voltage shift, resulting in a step-like change in conductance. Simultaneously, defect states in the tunneling medium exhibit random trapping and release behavior of charge carriers, leading to random fluctuations, nonlinear accumulation, and state drift during conductance updates. Furthermore, the capacitive coupling between the floating gate and the channel further amplifies local charge disturbances, making it difficult to keep the conductance increments corresponding to different programming pulses consistent, thus limiting the device's ability to achieve high linearity, high resolution, and truly continuous analog conductance control.

[0006] Secondly, the complex device structure hinders miniaturization and high integration. Traditional floating gate structures require precise control of multiple stacked layers (barrier layer, floating gate layer, tunneling layer, and channel layer), resulting in complex fabrication processes. Furthermore, chemical functionalization methods, such as those in KR102611057B1, require additional processing steps, increasing process complexity and uncertainty. As device dimensions continue to shrink, the parasitic capacitive coupling effect between floating gates significantly increases, easily leading to cell crosstalk and threshold voltage drift. Simultaneously, to ensure charge storage stability, the tunneling layer thickness cannot be further reduced; otherwise, it easily leads to increased leakage current and decreased device reliability, thus limiting further miniaturization. Therefore, the traditional floating gate charge storage mechanism has gradually become a significant bottleneck for device miniaturization and high integration, necessitating the removal of the floating gate structure to achieve a simpler and more easily miniaturized new device architecture. Thirdly, while existing two-dimensional material memory devices possess high-quality interfaces and strong gate control capabilities, they primarily focus on material replacement or stacking structure optimization. Effective technical solutions for achieving continuous programmable multi-level storage by leveraging interface or dielectric defect states are still lacking. In existing studies, defect states are mostly utilized statically and discretely (such as the chemical functionalization of KR102611057B1 and the natural vacancies of CN120302675A). No scheme has been found that utilizes the continuous or quasi-continuous energy level distribution characteristics of defect states and achieves dynamic, continuous, and precise control of the charge occupancy of defect states without using a floating gate layer through the synergistic effect of illumination and electric field.

[0007] Therefore, it is necessary to provide a novel memory device with a relatively simple structure that can realize continuous programmable multi-level non-volatile memory and its control method. Summary of the Invention

[0008] To overcome the shortcomings of existing technologies, the present invention aims to provide a gateless, continuously programmable, multi-level non-volatile memory device and its control method. This device does not rely on traditional floating gate structures, but instead uses the combined effects of light and electric fields to control the charge filling and releasing behavior of the dielectric layer and its interface defect states. This allows for continuous adjustment of the channel conductance state, obtaining multiple stable and distinguishable non-volatile storage states, thereby improving the device's multi-level storage capability and control precision.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] A first aspect of the present invention is to provide a gateless, continuously programmable, multi-level nonvolatile memory device, comprising:

[0011] Silica / silicon substrate

[0012] A hexagonal boron nitride dielectric layer and a rhenium disulfide channel layer are stacked sequentially on the substrate from bottom to top, and the silicon dioxide / silicon substrate, the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer form a van der Waals heterostructure;

[0013] Source and drain electrodes disposed at both ends of the rhenium disulfide channel layer;

[0014] The device does not have a floating gate layer. Through the synergistic effect of ultraviolet light and electric field, the charge occupancy behavior of the defect states at the interface of the hexagonal boron nitride dielectric layer is regulated, so that the carrier concentration in the rhenium disulfide channel layer changes continuously, thereby forming multiple stable and distinguishable non-volatile conduction states, realizing continuous programmable multi-level non-volatile storage.

[0015] Furthermore, the thickness of both the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer is on the order of nanometers, and their planar dimensions are on the order of micrometers.

[0016] Furthermore, both the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer are two-dimensional nanomaterials.

[0017] Furthermore, the defect states exhibit a continuous or quasi-continuous energy level distribution, and the degree of charge filling in the defect states can be continuously adjusted by regulating the parameters of the ultraviolet light illumination and the parameters of the electric field.

[0018] Furthermore, after the ultraviolet light and the electric field are removed, the charge in the defect state remains occupied, so that the device maintains the corresponding conductivity state.

[0019] The present invention also provides a control method based on the above-mentioned non-floating gate continuously programmable multi-level non-volatile memory device, comprising the following steps:

[0020] Under ultraviolet light irradiation, an electric field is applied to drive charge carriers to be injected into the defect states at the interface of the hexagonal boron nitride dielectric layer.

[0021] By adjusting one or more parameters of the ultraviolet light irradiation wavelength, power, pulse width, electric field amplitude, pulse duration, and pulse number, the charge carriers are gradually filled from shallow energy level defect states to deep energy level defect states, thereby achieving continuous adjustment of the charge occupancy of defect states. This results in continuous change of the charge carrier concentration in the rhenium disulfide channel layer, forming multiple stable non-volatile conductivity states.

[0022] After the ultraviolet light and the electric field are removed, the charge stored in the defect state remains occupied, so that the device maintains the corresponding conductivity state.

[0023] Furthermore, the ultraviolet light and the electric field are applied to the device in a manner that is synchronously applied, delayed, or alternately applied.

[0024] Furthermore, the carrier filling process in the defect state is a continuous and adjustable process, rather than a discrete charge injection or release process.

[0025] Furthermore, by adjusting the parameters of the ultraviolet light illumination and the electric field, the multiple conductance states can be clearly distinguished and have no obvious overlap.

[0026] Advantages and beneficial effects of the present invention:

[0027] 1. The device of this invention can realize continuously programmable multi-level non-volatile storage. Through the synergistic effect of light and electric field, the charge filling process of defect states at the dielectric layer and its interface is controlled, causing continuous changes in the channel carrier concentration, thereby forming multiple stable conductive states in the channel and realizing multi-level non-volatile storage. The key to this invention lies in proposing a continuously programmable storage mechanism with photo-electric synergistic control. By combining photoexcitation to generate carriers, photoactivation of defect states, and electric field-driven carrier injection, a continuously adjustable defect state charge filling mechanism is constructed. By adjusting the gate voltage amplitude, pulse duration, and pulse number, the charging rate and degree of the defect states can be precisely controlled, transforming the channel conductance change from a traditional discrete transition mode to a continuously programmable adjustment mode.

[0028] 2. The device of this invention exhibits excellent non-volatile storage characteristics. After the removal of external light and electric field, the device maintains its corresponding conductive state because the charge in the defect state remains occupied, thus achieving non-volatile storage. Even after the external excitation is removed, the charge in the defect state can still maintain stable occupation, giving the device excellent non-volatile storage characteristics.

[0029] 3. The device structure of this invention is simple, which is beneficial for miniaturization and integration. This invention does not rely on a floating gate structure, and the device structure is relatively simple, which is beneficial for device miniaturization and integration.

[0030] 4. This invention is based on the construction of a two-dimensional van der Waals heterostructure, which has high interface quality and is beneficial to improving the stability of device operation and the consistency of multi-level storage.

[0031] 5. This invention offers higher state resolution and improves the storage capacity of a single device. By coordinating illumination and electric field to control the charge occupancy behavior of defect states in the dielectric layer and interface, continuous programmable adjustment of the storage state can be achieved, resulting in higher state resolution compared to traditional discrete storage control methods. By adjusting the combination of illumination and electrical parameters, multiple stable and distinguishable conductivity states can be achieved, which is beneficial for improving the storage capacity of a single device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a continuously programmable multi-level non-volatile memory device provided in an embodiment of the present invention.

[0033] Figure 2 The graph shows the optically controlled hysteresis transfer characteristics provided in the embodiments of the present invention.

[0034] Figure 3 This diagram illustrates the long-term data retention characteristics of a non-volatile storage device provided in an embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram of electron transfer during charge capture provided in an embodiment of the present invention.

[0036] Figure 5 A schematic diagram of electron transfer during charge removal is provided for embodiments of the present invention.

[0037] Figure 6 This is a schematic diagram of a multi-level storage system based on gate voltage amplitude adjustment, provided as an embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of a multi-level storage system based on pulse time adjustment, provided in an embodiment of the present invention.

[0039] Figure 8 This is a schematic diagram of a multi-level storage system based on pulse quantity adjustment, provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the specific embodiments described herein are for illustrative purposes only and do not constitute a limitation on the scope of protection of this invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0041] like Figure 1 As shown, the floating gate-free continuously programmable multi-level non-volatile memory device cell of the present invention includes a SiO2 / Si substrate, hexagonal boron nitride (h-BN) as a dielectric layer, and ReS2 as a channel layer. The three are stacked from bottom to top to form a van der Waals heterostructure. Metal electrodes (Au) are provided at both ends of the ReS2 channel layer, serving as the source and drain, respectively. One end is grounded, and a source-drain voltage V is applied between the source and drain. ds Used to read the channel current I ds V gs This is the gate voltage.

[0042] Figure 2 The optically controlled hysteresis transfer characteristic curve is shown below. Figure 2 As shown, under dark conditions, the forward and reverse scan curves of the device almost completely overlap, exhibiting near-zero hysteresis, characteristic of a stable field-effect transistor. Under the same conditions, with an introduced light intensity of 1 mW / cm²... 2 By irradiating the device with ultraviolet light and repeatedly scanning its transfer characteristic curves, the forward and reverse scan curves of the device clearly separated under the synergistic effect of photoelectric interaction, forming a large hysteresis window. This result indicates that illumination can effectively participate in and enhance the defect state charge modulation process, enabling the device to possess hysteresis characteristics suitable for non-volatile storage.

[0043] Figure 3 This is a long-term data retention characteristic diagram for non-volatile storage devices, such as... Figure 3 As shown, the device current remains stable over long periods in both the on and off states, with a consistent and significant current difference between the two states, without any noticeable attenuation. This non-volatile memory device has a data retention time exceeding 10 years, demonstrating excellent non-volatile storage stability and long-term operational reliability.

[0044] Figure 4 and Figure 5 This diagram illustrates electron transfer during charge capture and removal. Dashed lines represent empty states, and dotted lines represent occupied states. Solid circles represent electrons, and hollow circles represent holes. This represents the bottom conduction band energy level of ReS2. This represents the top energy level of the valence band of ReS2. This represents the bottom conduction band energy level of h-BN. This represents the top energy level of the valence band of h-BN. Table 1 shows the bottom conduction band energy level of SiO2. This represents the top energy level of the valence band of SiO2. Figure 4 and Figure 5 The band structure of charge carriers in the device between different material layers and their transport and occupation behavior in defect states are represented under negative gate voltage (programming process) and positive gate voltage (erasing process), respectively.

[0045] Under negative gate voltage, electrons in the ReS2 channel layer gain energy under the combined action of electric field driving and ultraviolet light excitation, and gradually overcome the potential barrier to inject into the defect states in the h-BN dielectric layer and its interface with SiO2. These defect states exhibit a continuous or quasi-continuous energy distribution, with energy levels arranged from shallow to deep. With increasing applied electric field strength, duration, or number of pulses, electrons preferentially fill shallow energy level defect states and gradually expand to deeper energy levels, forming a gradual filling process from shallow to deep, thus continuously increasing the occupancy of defect states. Under positive gate voltage, electrons trapped in the defect states are gradually released under the driving force of a reverse electric field and sequentially occupy energy levels from shallow to deep, eventually returning to the channel layer or escaping to other layers. This process also exhibits continuous release behavior, gradually reducing the occupancy of defect states. Unlike traditional mechanisms based on discrete defect states or single energy level trapping, the defect states in this invention exhibit a continuous energy level distribution, and their charge occupation and release processes both exhibit gradual evolution behavior rather than discrete transitions. This continuous filling and releasing mechanism enables the channel carrier concentration to change continuously with the degree of defect state occupancy, thereby realizing the continuous adjustment of the device's conductivity state and providing a physical basis for multi-level non-volatile storage.

[0046] Figure 6 This diagram illustrates a multi-stage memory system based on gate voltage amplitude adjustment. With a source-drain voltage Vds = 500mV, a negative gate voltage pulse is applied to the device, simultaneously with a UV light pulse. The gate voltage pulse amplitude gradually varies from -0.1V to -10V, with a pulse period of 1s, and the UV light intensity is 0.5 mW / cm². 2 The pulse period is 1 second. As the gate voltage pulse amplitude gradually changes, the device achieves more than 6 different stable conductance states under the synergistic effect of optoelectronics. The conductance states are clearly spaced and do not overlap significantly, indicating that the device has excellent multi-level storage resolution. Throughout the test, the conductance states remain stable in the time dimension without significant drift or decay, indicating that the device has good retention capability.

[0047] Figure 7 This is a schematic diagram of a multi-level storage system based on pulse time adjustment, where the source-drain voltage V... dsAt a voltage of 500mV, a negative gate voltage pulse is applied to the device, and a UV light pulse is applied simultaneously. Wherein, the gate voltage V... gs The voltage is -1V, and the ultraviolet light intensity is 0.5 mW / cm². 2 The pulse duration gradually changes from 0.05s to 5s. As the pulse duration increases, the degree of defect state charge filling gradually changes, and the device channel current forms multiple stable conductive states accordingly. This indicates that the present invention can not only achieve multi-level storage by changing the gate voltage amplitude, but also achieve continuous programmable control by changing the pulse time. Therefore, the present invention has strong control flexibility and multi-parameter programming capability.

[0048] Figure 8 This is a schematic diagram of a multi-level storage system based on pulse count adjustment, where the source-drain voltage V... ds At a voltage of 500mV, a negative gate voltage pulse is applied to the device, and a UV light pulse is applied simultaneously. Wherein, the gate voltage V... gs The voltage is -1V, and the ultraviolet light intensity is 0.5 mW / cm². 2 The pulse period is 1 second, and the number of pulses gradually increases from 1 to 75. As the number of pulses increases, the degree of defect state charge filling gradually changes, and the device channel current forms multiple stable conductive states accordingly. This indicates that the present invention can not only achieve multi-level storage by changing the gate voltage amplitude, but also achieve continuous programmable control by changing the number of pulses. Therefore, the present invention has strong control flexibility and multi-parameter programming capability.

[0049] The present invention has been described above by way of example. It should be noted that any simple modifications, alterations or other equivalent substitutions that can be made by those skilled in the art without creative effort without departing from the core of the present invention fall within the protection scope of the present invention.

Claims

1. A non-floating gate, continuously programmable, multi-level non-volatile memory device, characterized in that, include: Silica / silicon substrate A hexagonal boron nitride dielectric layer and a rhenium disulfide channel layer are stacked sequentially on the substrate from bottom to top, and the silicon dioxide / silicon substrate, the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer form a van der Waals heterostructure; Source and drain electrodes disposed at both ends of the rhenium disulfide channel layer; The device does not have a floating gate layer. Through the synergistic effect of ultraviolet light and electric field, the charge occupancy behavior of the hexagonal boron nitride dielectric layer and the defect state at the interface with silicon dioxide is regulated, so that the carrier concentration in the rhenium disulfide channel layer changes continuously, thereby forming multiple stable and distinguishable non-volatile conduction states, realizing continuous programmable multi-level non-volatile storage. The defect states are distributed continuously or quasi-continuously in terms of energy. Electrons preferentially fill the shallow energy level defect states and then gradually extend to the deeper energy levels, forming a gradual filling process from shallow to deep. By adjusting one or more parameters of the ultraviolet light irradiation wavelength, power, pulse width, electric field amplitude, pulse duration, and pulse number, the degree of filling of the defect state charge can be continuously adjusted. The device achieves more than 6 bits of different stable conductance states and retains data for more than 10 years.

2. The gateless, continuously programmable, multi-level non-volatile memory device according to claim 1, characterized in that, The thickness of both the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer is on the order of nanometers, and the planar dimensions of both the hexagonal boron nitride dielectric layer and the rhenium disulfide channel layer are on the order of micrometers.

3. The gateless, continuously programmable, multi-level non-volatile memory device according to claim 1, characterized in that, The hexagonal boron nitride dielectric layer is a two-dimensional nano-insulating material; the rhenium disulfide channel layer is a two-dimensional nano-material.

4. The gateless, continuously programmable, multi-level non-volatile memory device according to claim 1, characterized in that, The defect states exhibit a continuous or quasi-continuous energy level distribution. By adjusting the parameters of the ultraviolet light and the electric field, the degree of charge filling in the defect states can be continuously adjusted.

5. The gateless, continuously programmable, multi-level non-volatile memory device according to claim 1, characterized in that, After the ultraviolet light and the electric field are removed, the charge in the defect state remains occupied, so that the device maintains the corresponding conductivity state.

6. A method for controlling a gateless, continuously programmable, multi-level non-volatile memory device according to any one of claims 1-5, characterized in that, include: Under ultraviolet light irradiation, an electric field is applied to drive charge carriers to be injected into the hexagonal boron nitride dielectric layer and the defect states at the interface between it and the silicon dioxide / silicon substrate. By adjusting one or more parameters of the ultraviolet light irradiation power, pulse width, pulse number, electric field amplitude, pulse duration, and pulse number, the charge carriers are gradually filled from shallow energy level defect states to deep energy level defect states, thereby achieving continuous adjustment of the charge occupancy of defect states. This results in continuous change of the charge carrier concentration in the rhenium disulfide channel layer, forming multiple stable non-volatile conductivity states. After the ultraviolet light and the electric field are removed, the charge stored in the defect state remains occupied, so that the device maintains the corresponding conductivity state.

7. The method according to claim 6, characterized in that, The ultraviolet light and the electric field are applied to the device in a manner that is synchronous, delayed, or alternating.

8. The method according to claim 6, characterized in that, The filling process of charge carriers in the defect state is a continuous adjustment process, rather than a discrete charge injection or release process.

9. The method according to claim 6, characterized in that, By adjusting the parameters of the ultraviolet light illumination and the electric field, the multiple stable non-volatile conductivity states can be clearly distinguished and have no obvious overlap.

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