A heterogeneous integrated three-dimensional memory structure and method of fabrication thereof

Abstract

This application relates to the field of semiconductor integrated circuit manufacturing and three-dimensional packaging technology, and discloses a heterogeneous integrated three-dimensional memory structure and its fabrication method. The structure includes a control circuit wafer and a memory array wafer bonded front to front. The control circuit wafer includes a semiconductor substrate, a front-end transistor layer, an isolation oxide layer, a first interconnect metal layer, and a back-end bonding layer. The memory array wafer includes a second interconnect metal layer, memory cells, and a back-end bonding layer. The memory array can be a transistorless memory array or a transistor-containing memory array. The back side of the control circuit wafer has a back via penetrating the semiconductor substrate and the isolation oxide layer, with the bottom of the via exposing the first interconnect metal layer. The method includes independently fabricating two wafers, hybrid bonding, back-end thinning, back-end opening, forming a sidewall insulating layer, aluminum filling, forming aluminum pads, and passivation windowing, thereby improving structural adaptability and reducing the complexity of the back-end electrical connection process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing and three-dimensional packaging technology, specifically to a heterogeneous integrated three-dimensional memory structure and its fabrication method. Background Technology

[0002] With the increasing demands for memory capacity and data access bandwidth, three-dimensional integrated structures are gradually becoming an important technological direction for improving memory density. In existing memories, memory arrays typically require advanced process nodes to reduce memory cell size and increase array density, while peripheral control circuits mainly undertake functions such as decoding, driving, read / write control, sensitive amplification, data pathing, and input / output. Their performance and reliability can usually be met by mature process nodes. If the memory array and peripheral control circuits are integrated on the same wafer, both need to be manufactured within the same process platform. This can easily lead to advanced process nodes being used for the peripheral control circuit area, thereby increasing manufacturing costs and causing the peripheral control circuits to occupy the planar area available for arranging memory cells, limiting the memory capacity per unit chip area.

[0003] For transistor-free memory arrays such as SOM and 1S1R structures, the array mainly consists of memory cells, selectors, and metal interconnects, with low dependence on the front-end transistor layer. If the memory array and peripheral control circuitry are still integrated on the same wafer, the transistor manufacturing area beneath the memory array cannot be fully utilized, resulting in reduced structural area utilization. For transistor-containing memory arrays such as 1T1R structures, although selectors are located within the array, differences in process nodes, thermal budgets, and material compatibility may still exist between the memory array process and the peripheral control circuitry process. Therefore, the same wafer manufacturing method still limits the freedom of choice in process selection for both the memory array and the control circuitry.

[0004] To achieve electrical connections between wafers with different functions, existing 3D integration solutions often employ through-silicon vias (TSVs) or similar vertical interconnect structures. Traditional TSVs typically have a high aspect ratio, and their metal filling process is heavily reliant on barrier layers, seed layers, and copper plating, involving numerous process steps and incurring high equipment and material costs. During metal deposition or plating in high aspect ratio via structures, metal accumulation tends to occur first at the via opening, affecting continuous metal filling at the bottom of the via. This can lead to voids, open circuits, or increased contact resistance, ultimately reducing the interconnect yield of the back-side electrical connection structure.

[0005] When wafer-level bonding is used to achieve interlayer connections between the memory array wafer and the control circuit wafer, the metal interconnects and dielectric layer connections at the bonding interface are highly sensitive to surface morphology, copper pad position relationships, and annealing conditions. If the relative height between the copper pads and the dielectric layer surface is not properly controlled, or if the annealing conditions do not match the copper pad surface morphology, insufficient copper pad contact, high interface resistance, or localized stress concentration can easily occur, affecting the signal transmission stability between the control circuit wafer and the memory array wafer. Therefore, it is necessary to provide a heterogeneous integrated three-dimensional memory structure and its fabrication method that can simultaneously achieve separate manufacturing of the memory array and control circuit, simplified back-side electrical connection processes, and reliable interlayer interconnects. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a heterogeneous integrated three-dimensional memory structure and its fabrication method, which solves the problems of limited area utilization and mutual constraints between process nodes caused by the integration of the memory array and peripheral control circuit on the same wafer in existing memories, as well as the complexity of the process and insufficient interconnect reliability caused by the reliance on high aspect ratio vias in traditional back-side electrical connection structures.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a heterogeneous integrated three-dimensional memory structure, employing the following technical solution: A heterogeneous integrated three-dimensional memory structure includes a control circuit wafer and a memory array wafer bonded face-to-face, and the control circuit wafer and the memory array wafer are stacked along the thickness direction.

[0009] The control circuit wafer sequentially comprises a semiconductor substrate, a front-end transistor layer, an isolation oxide layer, a first interconnect metal layer, and a back-end bonding layer. The memory array wafer comprises a second interconnect metal layer, memory cells, and a back-end bonding layer. The memory array in the memory array wafer includes a memory array without transistors or a memory array containing transistors.

[0010] The back side of the control circuit wafer has a back via penetrating the semiconductor substrate and the isolation oxide layer, with a diameter of 10μm to 100μm. A portion of the first interconnect metal layer is exposed at the bottom of the back via, and a sidewall insulating layer is provided on the sidewall of the back via. The back via is filled with aluminum, which contacts the exposed first interconnect metal layer and extends to the back surface of the control circuit wafer to form aluminum pads. The backmost surface of the control circuit wafer is covered with a passivation layer, which has openings that expose the aluminum pads.

[0011] By adopting the above technical solution, the control circuit wafer and the memory array wafer respectively undertake the peripheral control function and the memory array function. The two are stacked in space along the thickness direction and connected face to face through a back-end bonding layer. This structure allows the control circuit and the memory array to not occupy chip area in the same plane, and more of the planar area of ​​the memory array wafer can be used to arrange memory cells.

[0012] The memory array wafer can be either a transistorless or transistor-containing memory array. When the memory array is transistorless, the wafer mainly consists of memory cells, array interconnect structures, and back-end bonding layers, reducing the area occupied by transistor structures. When the memory array is transistor-containing, the wafer can select memory cells using transistors, making this heterogeneous integrated structure suitable for different types of memory array architectures.

[0013] A back-side via with a diameter of 10μm to 100μm is provided on the back side of the control circuit wafer. This back-side via penetrates the semiconductor substrate and the isolation oxide layer, exposing the first interconnect metal layer at the bottom. Compared with small-diameter, high-aspect-ratio vias, this size range reduces the aspect ratio of the hole structure, which is beneficial for subsequent aluminum deposition within the hole and continuous coverage of the bottom metal layer.

[0014] A sidewall insulating layer is provided on the sidewall of the back via to form dielectric isolation between the aluminum inside the via and the semiconductor substrate, reducing sidewall leakage. The aluminum inside the via contacts the first interconnect metal layer and extends to the back surface to form aluminum pads, thereby forming a conductive path from the back aluminum pads to the first interconnect metal layer. A passivation layer covers the back surface of the control circuit wafer and exposes the aluminum pads through openings, which protects the back metal structure while preserving the external electrical connection area.

[0015] Preferably, both back-end bonding layers include a dielectric layer and copper pads. The control circuit wafer and the memory array wafer are connected by interlocking copper pads. The interconnect pitch of the copper pads is less than 5 μm, and the copper pads have a recess depth of 1 nm to 5 nm on the surface of the dielectric layer where they are located.

[0016] By employing the above technical solution, two wafers form back-end bonding layers, including dielectric layers and copper pads, respectively, before bonding. The dielectric layers provide mechanical connection and insulating support after contact, while the copper pads form interlayer electrical connections after bonding. The interconnect pitch of the copper pads is less than 5μm, which is beneficial for increasing the vertical interconnect density between the control circuit wafer and the memory array wafer.

[0017] The copper pads have a recess depth of 1nm to 5nm relative to the dielectric layer surface. This recess depth provides space for the thermal expansion of the copper material during subsequent heat treatment. During heat treatment, copper has a higher coefficient of thermal expansion than dielectric materials such as silicon dioxide. After the copper pads expand in the thickness direction, the contact area between the upper and lower copper pads increases. Copper atoms at the contact interface diffuse under thermal activation conditions, forming a continuous metal connection interface. This process mainly includes the following stages: In the first stage, the dielectric surfaces of the two back-end bonding layers are bonded together, and the dielectric layer provides the initial mechanical contact interface. In the second stage, the copper pads thermally expand during the heating process, and the expansion of the copper material compensates for the recessed area, causing the upper and lower copper pads to come into contact with each other. In the third stage, copper atoms at the contact interface undergo interfacial diffusion to form a copper-copper bonding interface. In the fourth stage, the silanol groups on the surface of the dielectric layer undergo a dehydration condensation reaction during heat treatment to form a silicon-oxygen-silicon bond network. Through the above process, the back-end bonding layer simultaneously forms dielectric and metallic connections, thereby establishing mechanical support and electrical connections between the control circuit wafer and the memory array wafer.

[0018] Preferably, when the memory array is a transistorless memory array, the memory array is an SOM structure or a 1S1R structure; when the memory array is a transistor-containing memory array, the memory array is a 1T1R structure.

[0019] By adopting the above technical solutions, this heterogeneous integrated structure can adapt to different memory array forms. The SOM and 1S1R structures mainly rely on selectors, memory cells, and interconnect metal layers for array construction, making them suitable for arranging memory cells using the planar area of ​​the memory array wafer. The 1T1R structure has a select transistor for each memory cell, which can be used to control the selection of the memory cell. All of the above different array structures can be connected to the control circuit wafer through the back-end bonding layer of the memory array wafer, and can all use back-side vias and aluminum pads on the back side of the control circuit wafer for back-side electrical connection.

[0020] Preferably, the storage unit is any one of resistive random access memory, magnetoresistive random access memory, phase change random access memory, or ferroelectric random access memory; the sidewall insulating layer is made of silicon dioxide; and the passivation layer is made of silicon nitride.

[0021] By adopting the above technical solutions, the storage unit can be selected according to different non-volatile storage media systems. Resistive random access memory stores information through the high and low resistance state changes of the resistive dielectric layer; magnetoresistive random access memory stores information through the magnetization state changes of the magnetic tunnel junction; phase change random access memory stores information through the resistance difference between the amorphous and crystalline states of the phase change material; ferroelectric random access memory stores information through the polarization state of the ferroelectric thin film.

[0022] Silicon dioxide is used as a sidewall insulating layer on the back via sidewalls to form dielectric isolation between the aluminum and the semiconductor substrate within the via. Silicon nitride is used as a passivation layer covering the back surface to reduce the impact of external moisture, ionic contaminants, and mechanical contact on the back metal structure, while exposing the aluminum pads through openings to preserve the electrical connection area.

[0023] Secondly, this invention provides a method for fabricating a heterogeneous integrated three-dimensional memory structure, employing the following technical solution: A method for fabricating a heterogeneous integrated three-dimensional memory structure includes the following steps: Control circuit wafers and memory array wafers are fabricated independently. The control circuit wafer is fabricated on a semiconductor substrate by sequentially fabricating a front-end transistor layer, an isolation oxide layer, a first interconnect metal layer, and a back-end bonding layer. The memory array wafer is fabricated by sequentially fabricating a second interconnect metal layer, memory cells, and a back-end bonding layer. The memory array in the memory array wafer is fabricated as either a transistorless memory array or a memory array containing transistors.

[0024] The control circuit wafer and the memory array wafer are hybrid bonded face-to-face. The semiconductor substrate of the bonded control circuit wafer is then thinned on the back side. Etching is performed on the back side of the thinned semiconductor substrate to form back vias that penetrate the semiconductor substrate and the isolation oxide layer. The diameter of the back vias is set to 10μm to 100μm until the first interconnect metal layer at the bottom is exposed.

[0025] An insulating layer is formed within the back via, and then etched again to expose the first interconnect metal layer, retaining the insulating layer on the via walls to form a sidewall insulating layer. Aluminum is deposited within the back via, filling the back via and contacting the exposed first interconnect metal layer. Aluminum pads are formed on the back surface of the control circuit wafer, connecting to the aluminum within the back via. A passivation layer is formed on the back surface, and windows are etched to expose portions of the aluminum pads.

[0026] By employing the above technical solution, the control circuit wafer and the memory array wafer are first manufactured separately, and then front-to-front hybrid bonding is performed. This manufacturing sequence allows the front-end transistor process of the control circuit and the memory cell process of the memory array to be completed on different wafers, reducing the mutual influence between different material systems and different temperature processes. After bonding, thinning and vias are performed from the back side of the control circuit wafer. The back-side vias penetrate from the back side through the semiconductor substrate and the isolation oxide layer until the first interconnect metal layer is exposed. This step allows subsequent aluminum deposition to directly contact the first interconnect metal layer, forming a conductive path from the back side surface to the internal metal layer of the control circuit wafer.

[0027] An insulating layer is first formed inside the back via. Then, anisotropic etching is used to remove the insulating layer at the bottom of the via while retaining the insulating layer on the via walls, exposing the first interconnect metal layer at the bottom of the via again, while the via walls remain dielectrically isolated. Subsequently, aluminum is deposited inside the back via, with the aluminum deposited along the via walls and bottom, contacting the exposed first interconnect metal layer. After the aluminum filling is complete, a back-side aluminum pad is formed, and the aluminum pad is exposed by opening a window through a passivation layer. This results in a back-side metal connection structure including a back via, a sidewall insulating layer, aluminum inside the via, and a back-side aluminum pad.

[0028] Preferably, the specific steps of front-to-front hybrid bonding include: bonding the surfaces of the two subsequent bonding layers together at room temperature of 20°C to 30°C; and then performing thermal annealing at a temperature of 300°C to 400°C in a nitrogen atmosphere.

[0029] By adopting the above technical solution, the two subsequent bonding layers first complete surface alignment and contact at room temperature, forming an initial bonding interface between the dielectric layers. Subsequently, thermal annealing is performed, causing the reactive groups on the dielectric layer surface to undergo dehydration condensation, and causing thermal expansion and interface diffusion of the copper pads.

[0030] This reaction forms a silicon-oxygen-silicon bond structure, improving the connection strength between dielectric layers. Simultaneously, the copper pads expand in volume during thermal annealing, reducing the initial gap between the upper and lower copper pads and allowing them to contact. After contact, copper atoms diffuse at the interface, forming a metallic conductive interface. The nitrogen atmosphere reduces copper surface oxidation, which helps maintain the electrical conductivity of the copper-copper bonding interface. The temperature range of 300℃ to 400℃ allows dielectric layer bonding and copper pad bonding to occur simultaneously, while remaining within the thermal budget that semiconductor back-end processes can withstand.

[0031] Preferably, the specific steps for forming a back-side via through the semiconductor substrate and the isolation oxide layer include: using a deep reactive ion etching process, sequentially using a mixed gas containing sulfur fluoride to penetrate the silicon semiconductor substrate, and then switching to a mixed gas containing fluorocarbon to penetrate the isolation oxide layer.

[0032] By employing the above technical solution, the back-side via etching process switches gas systems according to the chemical composition of the material being etched. When the semiconductor substrate is silicon, the plasma containing sulfur fluoride can generate fluorine radicals, which react with silicon to form volatile silicon tetrafluoride. Once the etching interface reaches the isolation oxide layer, the system switches to a mixed gas containing fluorine and carbon. The fluorine-containing active groups in the fluorine-carbon plasma react with the silicon-oxygen bonds in the silicon dioxide to generate silicon-containing volatile products and carbon-containing oxidation products, allowing the isolation oxide layer to be etched further.

[0033] By first etching the silicon substrate and then etching the isolation oxide layer, the back via can continuously penetrate from the back side of the control circuit wafer to above the first interconnect metal layer and expose the first interconnect metal layer, providing a bottom metal interface for subsequent aluminum deposition and electrical contact.

[0034] Preferably, the specific steps for forming the sidewall insulating layer include: uniformly growing a silicon dioxide layer with a thickness of 100nm to 500nm on the inner wall of the back via using a chemical vapor deposition process; then vertically etching the bottom using an anisotropic dry etching process until no insulating layer remains above the first interconnect metal layer, while retaining the silicon dioxide on the sidewall of the back via.

[0035] By employing the above technical solution, the chemical vapor deposition process first deposits silicon dioxide on the sidewalls and bottom of the back-side via, forming a continuous insulating layer on the inner surface of the via. Subsequently, anisotropic dry etching is performed, with the etching direction primarily along the depth of the via. The silicon dioxide at the bottom of the via is removed, while the silicon dioxide on the via walls is retained. This process re-exposes the first interconnect metal layer and keeps the sidewalls of the back-side via insulating. The first interconnect metal layer exposed at the bottom of the via is used to contact the subsequently deposited aluminum, while the silicon dioxide retained on the via walls serves to isolate the aluminum from the semiconductor substrate.

[0036] A silica thickness of 100 nm to 500 nm allows for the formation of a dielectric isolation layer on the via walls, while avoiding excessive reduction in the effective opening within the via due to an excessively thick insulating layer. This thickness range facilitates process matching between sidewall insulation and subsequent metal filling.

[0037] Preferably, the specific steps for forming the aluminum pad are as follows: aluminum is deposited using a physical vapor deposition process until it completely fills the back via, and the surface is smoothed using a chemical mechanical polishing process; then an aluminum thin film layer is deposited again, and an aluminum pad located on the back surface of the control circuit wafer is formed using photolithography and etching processes.

[0038] By employing the above-described technical solution, physical vapor deposition (PVD) is used to deposit aluminum into the back-side vias. Since the diameter of the back-side vias is 10μm to 100μm, the aspect ratio of the via structure is reduced, allowing aluminum to continuously cover the via walls towards the bottom during deposition and contact the exposed first interconnect metal layer. After aluminum deposition within the vias, excess aluminum on the back-side surface is removed by chemical mechanical polishing to obtain a flat surface. Subsequently, an aluminum thin film layer is deposited again, and aluminum pad patterns are defined using photolithography and etching, connecting the aluminum pads to the aluminum within the back-side vias. This process forms a metal structure connecting the aluminum within the vias and the back-side aluminum pads, thereby establishing a conductive connection between the back-side surface and the first interconnect metal layer.

[0039] Preferably, the specific steps for generating a passivation layer on the back side surface are as follows: a silicon nitride film layer with a thickness of 0.5μm to 1.5μm is deposited as a passivation layer using plasma-enhanced chemical vapor deposition at an environment of 300℃ to 350℃, and the passivation layer is etched to form an opening that exposes the aluminum pads.

[0040] By employing the above technical solution, plasma-enhanced chemical vapor deposition (PECVD) forms a silicon nitride film at an temperature of 300℃–350℃. This temperature range is suitable for back-side processes, reducing the thermal impact on the already formed hybrid bonding interfaces, the metal structures within the back-side vias, and the internal devices of the control circuitry wafer. The silicon nitride film covering the back-side surface protects the area around the aluminum pads and the back-side dielectric surface. A passivation layer thickness of 0.5μm–1.5μm provides sufficient back-side protection while facilitating subsequent window etching. After patterning the passivation layer, part of the aluminum pad surface is exposed, allowing the back-side metal pads to be used for external electrical connections.

[0041] This invention provides a heterogeneous integrated three-dimensional memory structure and its fabrication method. It has the following beneficial effects: 1. In this invention, since the control circuit wafer and the memory array wafer are independently fabricated and laminated along the thickness direction, the memory array wafer can be a memory array without transistors or a memory array containing transistors. Therefore, the area occupied by the peripheral control circuit on the memory array plane is reduced, and the structural adaptability and memory array area utilization of the heterogeneous integrated three-dimensional memory are improved.

[0042] 2. In this invention, since a back-side via is provided on the back side of the control circuit wafer, penetrating the semiconductor substrate and the isolation oxide layer, and the aluminum filled in the back-side via contacts the first interconnect metal layer and extends to form an aluminum pad, an electrical connection structure can be formed on the back side of the control circuit wafer, reducing the open circuit risk and process complexity caused by the metal filling of the high aspect ratio via.

[0043] 3. In this invention, since both the back-end bonding layers of the control circuit wafer and the memory array wafer are provided with dielectric layers and copper pads, and the copper pads have a recessed depth on the surface of the dielectric layer, the copper pads can form a bond through thermal expansion and interface diffusion during the thermal annealing process. At the same time, the dielectric layer forms a bonding support, which improves the interlayer electrical connection density and the reliability of interface interconnection. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure in which the peripheral control circuit and the memory array are integrated on the same wafer plane, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the principle of separate manufacturing and heterogeneous integration of the control circuit wafer and the memory array wafer provided in an embodiment of the present invention. Figure 3 A schematic diagram of the heterogeneous integration of a transistorless memory array wafer and a control circuit wafer provided in an embodiment of the present invention; Figure 4 A schematic diagram of the heterogeneous integration of a memory array wafer containing transistors and a control circuit wafer provided in an embodiment of the present invention; Figure 5 This is a flowchart of the preparation method provided in the embodiments of the present invention; Figure 6 This is a graph showing the array function yield comparison test results provided in an embodiment of the present invention; Figure 7 This is a graph showing the comparison test results of the system bit error rate provided in an embodiment of the present invention; Figure 8 Comparison chart of back-side via interconnect yield provided in embodiments of the present invention; Figure 9 This is a comparison chart of the average resistance of a single hole provided in an embodiment of the present invention; Figure 10 This is a comparison chart of interface interconnection yield test results provided in an embodiment of the present invention; Figure 11 This is a comparison chart of the average value and standard deviation of contact resistance provided in an embodiment of the present invention.

[0045] The components are: 1. First interconnect metal layer; 2. Back-end bonding layer; 3. Second interconnect metal layer; 4. Front-end transistor layer; 5. Sidewall insulating layer; 6. Passivation layer; 7. Memory array wafer; 8. Control circuit wafer; 9. Memory cell; 10. Source; 11. Drain; 12. Polysilicon gate; 13. Copper pad; 14. Aluminum pad; 15. Semiconductor substrate; 16. Back-end via; 17. Isolation oxide layer; 18. Peripheral control circuit; 19. Memory array. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] See attached document Figure 1-4 The heterogeneous integrated three-dimensional memory structure of this application includes a control circuit wafer 8 and a memory array wafer 7. The control circuit wafer 8 and the memory array wafer 7 are stacked along the thickness direction and bonded face-to-face through their respective back-end bonding layers 2. The control circuit wafer 8 includes a semiconductor substrate 15, a front-end transistor layer 4, an isolation oxide layer 17, a first interconnect metal layer 1, and a back-end bonding layer 2. The memory array wafer 7 includes a second interconnect metal layer 3, memory cells 9, and a back-end bonding layer 2.

[0048] In a structure, such as Figure 3 As shown, the memory array in the memory array wafer 7 is a transistorless memory array, which can be an SOM structure or a 1S1R structure. At this time, the memory array wafer 7 mainly includes a second interconnect metal layer 3, memory cells 9, and a back-end bonding layer 2 for bonding with the control circuit wafer 8.

[0049] In another structure, such as Figure 4 As shown, the memory array in the memory array wafer 7 is a memory array containing transistors, and the memory array containing transistors can be a 1T1R structure. At this time, the memory array wafer 7 also includes a selection transistor electrically connected to the memory cell 9. The selection transistor includes a source 10, a drain 11, and a polysilicon gate 12. The memory cell 9 and the selection transistor are electrically connected to form a 1T1R memory cell structure.

[0050] The common feature of the two structures described above is that both control circuit wafers 8 have back-side vias 16 that penetrate the semiconductor substrate 15 and the isolation oxide layer 17. The bottom of the back-side via 16 exposes the first interconnect metal layer 1, and the sidewalls of the back-side via 16 are provided with sidewall insulating layers 5. The back-side via 16 is filled with aluminum, which contacts the exposed first interconnect metal layer 1 and extends to the back-side surface of the control circuit wafer 8 to form aluminum pads 14. The backmost surface of the control circuit wafer 8 is covered with a passivation layer 6, which has openings that expose the aluminum pads 14.

[0051] therefore, Figure 3 and Figure 4 The structures shown are all three-dimensional memory structures that are heterogeneously integrated between the control circuit wafer 8 and the memory array wafer 7. The difference between the two is whether the memory array in the memory array wafer 7 contains transistors.

[0052] Preparation Examples 1-4: like Figure 5 As shown, the fabrication method of the heterogeneous integrated three-dimensional memory structure of this application includes the following steps: S101, respectively fabricate control circuit wafer 8 and memory array wafer 7; wherein, semiconductor substrate 15, front-end transistor layer 4, isolation oxide layer 17, first interconnect metal layer 1 and back-end bonding layer 2 are formed on control circuit wafer 8, and second interconnect metal layer 3, memory cell 9 and back-end bonding layer 2 are formed on memory array wafer 7. S102, perform front-to-front hybrid bonding of the control circuit wafer 8 and the memory array wafer 7; S103, perform back-side thinning on the semiconductor substrate 15 of the bonded control circuit wafer 8; S104, a back via 16 is formed by etching from the back side of the thinned control circuit wafer 8, so that the back via 16 penetrates the semiconductor substrate 15 and the isolation oxide layer 17, and exposes the first interconnect metal layer 1. S105, an insulating layer is formed inside the back through hole 16, and the insulating layer at the bottom of the back through hole 16 is removed, while the insulating layer on the side wall of the back through hole 16 is retained to form a side wall insulating layer 5. S106, aluminum is deposited in the back via 16, such that the aluminum fills the back via 16 and contacts the exposed first interconnect metal layer 1. S107, an aluminum pad 14 is formed on the back surface of the control circuit wafer 8 to connect with the aluminum in the back via 16; S108, a passivation layer 6 is formed on the back side surface, and the passivation layer 6 is etched to form an opening that exposes the aluminum pad 14.

[0053] The following examples 1-4 illustrate the specific fabrication method of memory cell 9. Memory cell 9 can be disposed in a SOM structure or a 1S1R structure without transistors, or in a 1T1R structure containing transistors.

[0054] Preparation Example 1: This example provides a method for fabricating a resistive random access memory (RRAM) cell, including the following steps: (1) A titanium nitride (TiN) thin film with a thickness of 20 nm was sputtered and deposited on the bottom insulating medium using physical vapor deposition (PVD) process as the bottom electrode layer; (2) Using atomic layer deposition (ALD) process, with tetramethylamine hafnium (TEMAH) and water vapor (H2O) as precursors, a hafnium oxide (HfOx) thin film with a thickness of 10 nm is deposited on the bottom electrode layer as a resistive switching dielectric layer at a deposition temperature of 250 °C. (3) A 20 nm thick platinum (Pt) thin film was sputtered and deposited on top of the resistive switching dielectric layer using physical vapor deposition process; (4) Photoresist is applied sequentially and exposed and developed. Then, the top electrode layer, resistive switching dielectric layer and bottom electrode layer are continuously etched downwards using inductively coupled plasma (ICP) dry etching process. After removing the photoresist, an independent resistive switching memory cell pillar is formed.

[0055] Preparation Example 2: This example provides a method for fabricating a phase-change random access memory (PCRAM) cell, including the following steps: (1) Using physical vapor deposition, deposit tungsten (W) or titanium nitride (TiN) with a thickness of 15 nm as the bottom electrode at the required location; (2) A phase change material layer with a thickness of 30 nm is deposited by sputtering using a DC magnetron sputtering process with a germanium antimony tellurium (Ge2Sb2Te5, abbreviated as GST) alloy target as the target source and argon (Ar) gas as the working gas. (3) On top of the phase change material layer, a 15 nm thick titanium nitride (TiN) layer is deposited again as the top electrode using physical vapor deposition. (4) The pattern of memory cell 9 is defined by photolithography, and each film layer is etched by reactive ion etching (RIE) process containing a mixture of fluorine-based and chlorine-based gases. Finally, annealing is performed to stabilize the crystal structure of the phase change material and form an independent phase change memory cell.

[0056] Preparation Example 3: This example provides a method for fabricating a magnetoresistive random access memory (MRAM) cell, comprising the following steps: (1) Tantalum (Ta) and ruthenium (Ru) with a thickness of 5 nm were deposited sequentially on the substrate using a sputtering process as the bottom electrode and seed layer; (2) A 2.5 nm thick CoFeB fixed magnetic layer is sequentially sputtered onto the seed layer, a 1.2 nm thick Magnesium Oxide (MgO) insulating tunnel barrier layer is deposited using radio frequency sputtering, and a 2.0 nm thick CoFeB free magnetic layer is sputtered onto the seed layer. (3) Deposit a tantalum (Ta) or ruthenium (Ru) layer with a thickness of 5 nm above the free magnetic layer as the top electrode layer; (4) Place the wafer with the thin film deposition completed in a high vacuum annealing furnace at 300°C and apply a strong magnetic field of 1.0 Tesla in the direction parallel to the film surface. Anneal for 2 hours to induce magnesium oxide crystallization and establish the magnetic anisotropy of the fixed layer. (5) The above multilayer structure is physically bombarded and etched by an argon ion beam with a specific tilt angle using ion beam etching (IBE) to form a magnetoresistive memory cell column.

[0057] Preparation Example 4: This example provides a method for fabricating a ferroelectric random access memory (FeRAM) cell, comprising the following steps: (1) A titanium nitride (TiN) thin film with a thickness of 15 nm was sputtered using physical vapor deposition as the bottom electrode; (2) A 10 nm thick hafnium zirconium oxide (Hf0.5Zr0.5O2, abbreviated as HZO) ferroelectric thin film was deposited at 300 °C by alternating introduction of hafnium precursor, zirconium precursor and oxygen plasma using plasma-enhanced atomic layer deposition (PEALD) process. (3) A titanium nitride (TiN) film with a thickness of 15 nm was deposited on top of the ferroelectric film as the top electrode using physical vapor deposition process; (4) In a nitrogen atmosphere, the wafer is annealed at 450°C for 60 seconds using a rapid thermal annealing (RTA) device to induce a phase transition in the ferroelectric thin film and form an orthorhombic crystal structure with strong ferroelectricity. (5) The top electrode, ferroelectric thin film and bottom electrode are patterned by conventional photolithography and dry etching processes to form an independent ferroelectric memory cell structure.

[0058] Examples 1-4, see appendix Figure 3 : Example 1: This embodiment provides a heterogeneous integrated three-dimensional memory structure and its fabrication method, including the following steps: (1) For the control circuit wafer 8, a front-end transistor layer 4, an isolation oxide layer 17, a first interconnect metal layer 1 and a back-end bonding layer 2 are sequentially fabricated on a P-type silicon semiconductor substrate 15. For the memory array wafer 7, a second interconnect metal layer 3, a resistive random access memory (RRAM) fabricated using the method of Preparation Example 1 as a memory cell 9, and a back-end bonding layer 2 are sequentially fabricated, and the memory array wafer 7 is restricted to not containing any transistor structure, so as to form a memory array with a transistor-free 1S1R structure or SOM structure. The back-end bonding layer 2 of both wafers is manufactured using the damascus process and includes a silicon dioxide dielectric layer and copper pads 13 with an interconnect pitch of 1 μm. By adjusting the slurry selection ratio of chemical mechanical polishing (CMP), the copper pad 13 has a 1 nm recess depth on the surface of the dielectric layer it is located in.

[0059] (2) At room temperature of 20°C, the silicon dioxide dielectric layers on the surfaces of the two back bonding layers 2 are aligned and contacted, and then closed by adsorption through van der Waals forces. It is then sent to an annealing furnace and thermally annealed at 300°C in a nitrogen atmosphere, so that the dielectric layer forms covalent bonds and the copper pads 13 complete metal bonding due to thermal expansion.

[0060] (3) Thin the back side of the semiconductor substrate 15 of the bonded control circuit wafer 8 to the set thickness; The Deep Reactive Ion Etching (DRIE) process is used. First, a mixed gas containing sulfur hexafluoride (SF6) is used to penetrate the silicon substrate. Then, a mixed gas containing carbon tetrafluoride (CF4) is used to penetrate the isolation oxide layer 17 to etch out the back via 16 until the bottom first interconnect metal layer 1 is exposed. The diameter of the back via 16 is set to 10 μm.

[0061] (4) A silicon dioxide insulating layer with a thickness of 100 nm is uniformly grown on the inner wall of the back through-hole 16 using chemical vapor deposition (CVD) process; An anisotropic dry etching process is used to vertically etch the bottom until there is no insulating layer remaining above the first interconnect metal layer 1, while retaining the insulating layer on the hole wall to form the sidewall insulating layer 5.

[0062] (5) Aluminum is deposited using physical vapor deposition until the back through-hole 16 is completely filled, and the surface is ground smooth using CMP process; Subsequently, an aluminum thin film was deposited again, and after photolithography and etching, aluminum pads 14 were formed on the back surface.

[0063] (6) A silicon nitride film with a thickness of 0.5 μm is deposited on the back side surface as a passivation layer 6 using plasma enhanced chemical vapor deposition (PECVD) at 300°C, and etched to open windows to expose part of the aluminum pads 14 for external testing and packaging.

[0064] Example 2: This embodiment provides a heterogeneous integrated three-dimensional memory structure and its fabrication method, including the following steps: (1) For the control circuit wafer 8, a front-end transistor layer 4, an isolation oxide layer 17, a first interconnect metal layer 1 and a back-end bonding layer 2 are sequentially fabricated on a semiconductor substrate 15. For the memory array wafer 7, a second interconnect metal layer 3, a phase change random access memory (PCRAM) fabricated using the method of Preparation Example 2 as a memory cell 9, and a subsequent bonding layer 2 are fabricated sequentially. The array wafer has no transistors to form a transistor-free memory array. The interconnect pitch of the copper pads 13 in the two back-end bonding layers 2 is designed to be 3 μm, and the depth of their recess on the dielectric layer surface is controlled to be 3 nm.

[0065] (2) At room temperature of 25°C, the silicon dioxide dielectric layer on the wafer surface is adsorbed and closed; Subsequently, thermal annealing was performed at 350°C in a nitrogen atmosphere to complete the hybrid bonding.

[0066] (3) After thinning the back side of the control circuit wafer 8, the silicon substrate and the isolation oxide layer 17 are etched alternately using the DRIE process to etch out the back side via 16 until the bottom first interconnect metal layer 1 is exposed. The diameter of the back side via 16 is set to 50 μm.

[0067] (4) Deposit a silicon dioxide layer with a thickness of 300 nm on the inner wall of the back through-hole 16; The bottom of the hole is penetrated by anisotropic vertical etching, while retaining the sidewall insulating layer 5.

[0068] (5) Aluminum is deposited to fill the back through hole 16 and ground flat, and aluminum film is deposited again and patterned to form aluminum pad 14 on the back surface.

[0069] (6) Using PECVD process, a silicon nitride passivation layer 6 with a thickness of 1.0 μm is deposited on the back side surface at 325°C, and the opening of the exposed aluminum pad 14 is etched out.

[0070] Example 3: This embodiment provides a heterogeneous integrated three-dimensional memory structure and its fabrication method, including the following steps: (1) The preparatory steps are the same as those in Examples 1 and 2; the difference is that the ferroelectric random access memory (FeRAM) manufactured by the method in Example 4 is used as the storage cell 9 in the storage array wafer 7, and the storage array in the storage array wafer 7 is a storage array without transistors. The interconnect pitch of the copper pads 13 in the two back-end bonding layers 2 is designed to be 4.5 μm, and the recess depth of the copper pads 13 on the dielectric layer surface is controlled to be 5 nm.

[0071] (2) The silicon dioxide dielectric layer on the wafer surface is adsorbed and closed at 30°C. Subsequently, thermal annealing was performed at 400°C in a nitrogen atmosphere to complete the mixed bonding.

[0072] (3) After thinning the back side of the control circuit wafer 8, the DRIE process is used to etch through the semiconductor substrate 15 and the isolation oxide layer 17 until the first interconnect metal layer 1 is exposed to form the back side via 16. The diameter of the back side via 16 is set to 100 μm.

[0073] (4) Deposit a silicon dioxide layer with a thickness of 500 nm on the inner wall of the back through-hole 16; The sidewall insulating layer 5 is retained after anisotropic etching.

[0074] (5) Aluminum filling the back via 16 and aluminum pads 14 located on the back side surface are formed by PVD deposition of aluminum, CMP planarization and secondary deposition and etching.

[0075] (6) Using PECVD process, a silicon nitride passivation layer 6 with a thickness of 1.5 μm is deposited on the back side surface at 350°C, and the opening of the exposed aluminum pad 14 is etched out.

[0076] Examples 1 to 3 mainly illustrate heterogeneous integration schemes when the memory array in memory array wafer 7 does not contain transistor structures. Example 4 below illustrates a heterogeneous integration scheme when the memory array in memory array wafer 7 includes transistor structures.

[0077] Example 4: This embodiment provides a three-dimensional memory structure and its fabrication method that heterogeneously integrates a 1T1R memory array wafer containing transistors and a control circuit wafer, including the following steps: (1) For the control circuit wafer 8, a front-end transistor layer 4, an isolation oxide layer 17, a first interconnect metal layer 1 and a back-end bonding layer 2 are sequentially fabricated on a semiconductor substrate 15. For the memory array wafer 7, a selection transistor is formed on the array substrate. The selection transistor includes a source 10, a drain 11, and a polysilicon gate 12. Then, a second interconnect metal layer 3 electrically connected to the selection transistor is formed, and a resistive random access memory (RRAM) is fabricated as a memory cell 9 using the method of Preparation Example 1. The memory cell 9 is electrically connected to the selection transistor to form a memory array with a 1T1R structure. After that, a back-end bonding layer 2 is formed on the memory array wafer 7.

[0078] (2) Both back-end bonding layers 2 are manufactured using the damascus process and include a silicon dioxide dielectric layer and copper pads 13. The interconnect pitch of the copper pads 13 is 3 μm, and the recess depth of the copper pads 13 on the surface of the dielectric layer is 3 nm.

[0079] (3) Align the control circuit wafer 8 and the memory array wafer 7 containing the 1T1R structure face to face, so that the silicon dioxide dielectric layers of the two back-end bonding layers 2 are bonded at room temperature, and then thermally annealed at 350°C in a nitrogen atmosphere to complete the hybrid bonding.

[0080] (4) The semiconductor substrate 15 of the bonded control circuit wafer 8 is thinned on the back side, and then a deep reactive ion etching process is used to sequentially etch the semiconductor substrate 15 and the isolation oxide layer 17 from the back side of the control circuit wafer 8 to form a back via 16 that penetrates the semiconductor substrate 15 and the isolation oxide layer 17 until the first interconnect metal layer 1 is exposed. The diameter of the back via 16 is 50 μm.

[0081] (5) A silicon dioxide insulating layer with a thickness of 300 nm is grown on the inner wall of the back via 16 using chemical vapor deposition. Then, an anisotropic dry etching process is used to remove the silicon dioxide insulating layer at the bottom of the back via 16 until there is no insulating layer remaining above the first interconnect metal layer 1. The silicon dioxide on the sidewall of the back via 16 is retained as the sidewall insulating layer 5.

[0082] (6) Aluminum is deposited in the back hole 16 using physical vapor deposition process, so that the aluminum fills the back hole 16 and contacts the exposed first interconnect metal layer 1. Then, the back surface is smoothed by chemical mechanical polishing process.

[0083] (7) A thin aluminum film layer is deposited again on the back surface of the control circuit wafer 8, and an aluminum pad 14 is formed on the back surface by photolithography and etching process. The aluminum pad 14 is connected to the aluminum in the back through hole 16.

[0084] (8) A silicon nitride film with a thickness of 1.0 μm is deposited on the back side surface as a passivation layer 6 at an environment of 325°C using plasma-enhanced chemical vapor deposition process, and the passivation layer 6 is etched to form an opening for exposing the aluminum pad 14.

[0085] Comparative Examples 1-4: Comparative Example 1: Compared with Example 2, the difference is that the etching diameter of the back-side via 16 is set to 2μm (simulating traditional small-size TSV), and physical vapor deposition process is still used to try to deposit aluminum for filling, while the rest are the same.

[0086] Comparative Example 2: Compared with Example 2, the difference is that after forming the back-side via 16 with a diameter of 50 μm, aluminum deposition was not used for filling. Instead, conventional barrier layer deposition, seed layer deposition and electroplating copper processes were used for filling and smoothing. All other aspects are the same.

[0087] Comparative Example 3: Compared with Example 2, the difference is that the depth of the copper pad 13 on the surface of the dielectric layer is controlled to be 10nm by adjusting the CMP polishing process, and the heat annealing temperature during hybrid bonding is set to 200°C, while the rest are the same.

[0088] Comparative Example 4: Compared with Example 2, the difference is that instead of using a scheme of separate fabrication and mixed bonding of two wafers, a front-end logic transistor layer, an interconnect layer, and an array of memory cells 9 above are sequentially fabricated on the same semiconductor substrate 15 (i.e., conventional monolithic isomorphic integration). In this structure, there are no control circuit wafers 8 and memory array wafers 7 bonded face to face, nor are there back vias 16, sidewall insulating layers 5, and aluminum pads 14 located on the back surface of the semiconductor substrate 15 and isolation oxide layer 17 that penetrate the control circuit wafer 8. External electrical connections are made using same-side pads or conventional interconnection methods.

[0089] Test Example 1-3: Test Example 1: The heterogeneous integrated wafer that has completed the back-side surface passivation and windowing process is placed on the wafer carrier of the fully automated probe station. The working environment temperature of the wafer carrier is maintained at 25°C. The probe position is adjusted so that the test probe establishes direct physical and electrical contact with the aluminum pad 14 exposed on the back side of the underlying control circuit wafer 8.

[0090] A semiconductor parameter analyzer and signal generator are used to input the power supply voltage and digital control command signals containing address information to the aluminum pad 14 via probes. The logic circuit module within the underlying control circuit wafer 8 receives the signals, decodes the commands, generates the corresponding word line and bit line drive voltages, and routes the drive voltages to the upper level through the internal interconnect metal layer.

[0091] The driving voltage is transmitted to the second interconnect metal layer 3 inside the top layer memory array wafer 7 through the copper-copper hybrid bonding interface formed by front-to-front bonding. The second interconnect metal layer 3 selects the target memory cell 9 according to the decoded address and applies a set or reset programming pulse to the target memory cell 9 to change the physical state of its internal material.

[0092] After the programming pulse ends, the control circuit sends a read command to the same target memory cell 9, applies a non-destructive read bias voltage of 0.2V, detects the loop current flowing through the back via 16, logic circuit, hybrid bonding interface and memory cell 9, and calculates and records the low resistance state (LRS) or high resistance state (HRS) resistance value of the corresponding memory cell 9.

[0093] The MarchC+ test algorithm is used to generate test stimulus vectors, and a global traversal test is performed on the memory cells 9 in the upper-layer memory array wafer 7. The total number of memory cells 9 that can correctly respond to state flips and resistance readings is recorded to calculate the array yield, and the number of electrical error bits during the read and write process is counted to calculate the system bit error rate.

[0094] This test case uses Examples 1-3 as representative samples to perform system-level read / write function tests. Examples 1-3 all have a control circuit wafer 8, a memory array wafer 7, a back-end bonding layer 2 with front-to-front bonding, a back-end via 16, a sidewall insulating layer 5, and an aluminum pad 14, used to verify the electrical connection path in the heterogeneous integrated structure of this application, which consists of the back-side aluminum pad 14, the back-end via 16, the first interconnect metal layer 1, the hybrid bonding interface, and the second interconnect metal layer 3.

[0095] Table 1. Test results of system-level read / write functionality and resistance distribution of the storage arrays in Examples 1-3

[0096] in conclusion: According to Table 1 and appendix Figure 6 With appendix Figure 7 The data shows that the heterogeneous integrated three-dimensional memories in Examples 1 to 3 all achieved an array functional yield of over 98.9%, maintained an average resistance value of two to three orders of magnitude between the high-resistivity and low-resistivity states during the switching window, and had a system bit error rate of 10%. -5 Magnitude range. Combined with Figure 6 columnar distribution and Figure 7 As can be seen from the curve trend, Example 2 achieved the highest array functional yield of 99.67%, with the corresponding system bit error rate reduced to 8.72×10⁻⁶. -6 .

[0097] Test results confirm the electrical feasibility of the physical separation architecture between the control circuit and the transistorless memory array, as well as the heterogeneous hybrid bonding process. The back via 16 is filled with 10μm to 100μm diameter aluminum using physical vapor deposition, allowing the aluminum within the back via 16 to contact the first interconnect metal layer 1 and extend to the back surface of the control circuit wafer 8 to form aluminum pads 14. The high-frequency drive signal emitted by the bottom control circuit passes through the silicon substrate, the bottom dielectric, and the hybrid bonding interface without producing signal hysteresis or waveform distortion that would cause memory dielectric flip-over failure.

[0098] The copper pad 13 is recessed to a depth of 1nm to 5nm and thermally annealed in the temperature range of 300℃ to 400℃ to establish a stable interlayer interface contact. The thermal budget of this process does not cause degradation of the short-channel control capability of the bottom front-end transistor, nor does it destroy the resistive switching mechanism of the top-end memory cell 9.

[0099] Figure 6 and Figure 7 The presented data distribution difference reflects the marginal impact of via process and annealing parameters on overall conductivity yield. The test results of each embodiment confirm that the heterogeneous integration structure of control circuit wafer 8 and memory array wafer 7, the aluminum filling structure in the back via 16, and the wafer-level hybrid bonding interface can form a continuous electrical connection path.

[0100] Test Example 2: The test wafer with the back metallization process completed is fixed on the vacuum stage of the semiconductor parameter testing system, and the test environment temperature is set to room temperature of 25°C.

[0101] Test patterns of 16-via arrays on the back side were randomly selected from the wafer center, the central ring, and the edge regions to correspond to chip locations. The test patterns employed a Kelvin four-wire structure and a daisy-chain structure containing 100 consecutive vias to eliminate contact resistance interference and evaluate macroscopic interconnect characteristics.

[0102] The probe system is aligned with the test endpoint of aluminum pad 14, and a DC scanning test current ranging from 1mA to 10mA is applied. Voltage drop data across the test circuit is acquired simultaneously, and the physical contact resistance of each via's independent structure is calculated.

[0103] Set a threshold value for the resistance of a single hole. When the measured resistance of a single hole is less than 5Ω, it is considered to be in a passable state. When the resistance of a single hole is greater than or equal to 5Ω or the output voltage of the test instrument reaches the upper limit of the range, it is considered to be in an open circuit state.

[0104] The resistance data of the test structures in the selected area are statistically analyzed and the arithmetic mean is taken. The percentage of the number of qualified conduction devices is calculated out of the total number of tests, and the yield of the 16 interconnection of the back-side via is obtained.

[0105] This test example is used to evaluate the interconnect electrical characteristics between the back via 16, the sidewall insulating layer 5, the aluminum filling the back via 16, and the aluminum pad 14. The test object is the back-side metallization structure common to Examples 1-4, and is not contingent on whether the memory array in the memory array wafer 7 contains transistors.

[0106] Table 2. Test results of electrical characteristics of the back-side via 16 interconnect in Example 2 and Comparative Example 1

[0107] in conclusion: According to Table 2 and appendix Figure 8 With appendix Figure 9 According to the data, the interconnect yield of the back-side via 16 in Example 2 reached 99.18%, the open-circuit failure rate was only 0.82%, and the average resistance per via was 1.27Ω. In Comparative Example 1, the interconnect yield of the back-side via 16 dropped to 14.63%, the open-circuit failure rate was as high as 85.37%, and the average resistance per via increased to 485.21Ω. Combined with... Figure 8 The bar chart shows the precipitous difference in yield. Figure 9 The logarithmic resistance jumps shown above experimental results confirm that the size setting of the back via 16 has a decisive influence on the filling effect of the physical vapor deposition process.

[0108] Comparative Example 1 uses a small aperture of 2μm, which results in an excessively high aspect ratio of the via. During the sputtering deposition of aluminum target, metal atoms accumulate at the aperture and prematurely seal (Pinch-off), preventing subsequent aluminum atoms from entering the depth of the hole. This creates a large volume insulating void inside, making it impossible to establish a conductive path connecting the bottom first interconnect metal layer 1, resulting in high open circuit failure and abnormal impedance.

[0109] Example 2 employs a large 50μm aperture to reduce the aspect ratio of the vias. Physically sputtered aluminum atoms can continuously adhere along the sidewall insulating layer 5 and reach the bottom of the via, forming a continuous conductive layer covering the underlying metal. This dimensional design allows inexpensive physical vapor deposition (PVD) processes, typically used for surface wiring, to handle deep-via interconnects through the substrate, achieving high-yield, low-impedance physical connections and eliminating the reliance on complex electroplating solutions and high-cost processes inherent in traditional deep-via interconnects.

[0110] Since the formation methods of the back via 16, the sidewall insulating layer 5, the aluminum filling the back via 16, and the aluminum pad 14 in Example 4 are the same as those in Example 2, the test results of the interconnect electrical characteristics of the back via 16 can be used to illustrate the conductivity of the back metallization structure itself.

[0111] Test Example 3: The test wafer, after hybrid bonding and back-side processing, is placed on the substrate of the semiconductor probe station, and the test environment temperature is kept constant at 25°C.

[0112] Test areas are selected on the wafer surface to evaluate the interlayer interface. The test areas include daisy chain test patterns consisting of 10,000 consecutive copper-copper bonding nodes connected in series, as well as Kelvin test patterns for independently extracting the resistance of a single node.

[0113] Contact the probes of the probe station with the input and output pads of the test pattern, and operate the semiconductor parameter analyzer to apply a scanning bias voltage of 10mV to 100mV to the test circuit, and measure the output current of the corresponding circuit.

[0114] The contact resistance value of a single bond node is calculated based on the Kelvin test pattern. A threshold for judging this contact resistance is set. When the resistance value is greater than 1Ω, the node is recorded as an open circuit failure.

[0115] The resistance data of all sampled test patterns are collected, and the percentage of conductive nodes in the total test is calculated to obtain the interface interconnection yield. At the same time, the arithmetic mean and standard deviation of the contact resistance of conductive nodes are calculated to evaluate the dispersion of the resistance distribution.

[0116] This test example is used to evaluate the interface interconnect performance of the copper pads 13 in the back-end bonding layer 2 between the control circuit wafer 8 and the memory array wafer 7. This interface interconnect structure is an interlayer connection structure common to Examples 1-4, and is not contingent on whether the memory array in the memory array wafer 7 contains transistors.

[0117] Table 3. Test results of electrical stability of the bonding interface in Example 2 and Comparative Example 3

[0118] in conclusion: According to Table 3 and appendix Figure 10 With appendix Figure 11 Based on the data, Example 2 achieved an interface interconnect yield of 99.82%, with an average contact resistance of 18.34 mΩ and a standard deviation of 1.42 mΩ. Comparative Example 3 achieved an interface interconnect yield of 42.15%, with an average contact resistance of 876.51 mΩ and a standard deviation of 312.88 mΩ. The heterogeneous integration hybrid bonding mechanism relies on van der Waals forces on the dielectric layer surface for adhesion, combined with thermal annealing to induce thermal expansion of the copper pads 13 to achieve metal interconnection.

[0119] Example 2 uses a 3nm recess depth combined with an annealing temperature of 350℃. The volume expansion of the copper material under these thermal parameters fills the preset initial gap, causing the upper and lower copper grains to be squeezed against each other at the interface. The diffusion of atoms at the grain boundaries and surface forms a continuous metallic lattice. The macroscopic electrical properties are characterized by low interfacial contact resistance, and a low standard deviation of resistance distribution due to the tight and uniform connection of each node.

[0120] Comparative Example 3 uses a 10nm recess depth combined with an annealing temperature of 200℃. The reduced annealing temperature limits the thermal expansion rate of the copper material, while the initial spacing of 10nm exceeds the maximum thermal expansion range that can be covered under this low-temperature condition. The upper and lower copper pads 13 failed to form physical contact, or the interface stress was insufficient to trigger atomic-level diffusion, leaving microscopic physical voids in the interface region. Macroscopic test results show that a large number of nodes experienced open-circuit failure, and a small number of weakly conductive nodes exhibited high contact resistance. Furthermore, due to the random distribution of contact states, the standard deviation of the resistance values ​​was discrete.

[0121] Test data show that limiting the depth of the copper pad 13 recess to the range of 1nm to 5nm and using thermal annealing parameters of 300℃ to 400℃ are necessary conditions for establishing stable hybrid bonding interlayer interconnects.

[0122] Since the control circuit wafer 8 and the memory array wafer 7 in Embodiment 4 are also bonded face-to-face through the back-end bonding layer 2 containing copper pads 13, the above test results regarding the interconnection performance of the copper pad 13 interface can be used to illustrate the interconnection stability of the interlayer bonding structure itself.

Claims

1. A heterogeneous integrated three-dimensional memory structure, characterized in that, The device includes a control circuit wafer (8) and a memory array wafer (7) bonded face-to-face, wherein the control circuit wafer (8) and the memory array wafer (7) are stacked along the thickness direction; The control circuit wafer (8) sequentially comprises a semiconductor substrate (15), a front-end transistor layer (4), an isolation oxide layer (17), a first interconnect metal layer (1), and a back-end bonding layer (2). The memory array wafer (7) includes a second interconnect metal layer (3), memory cells (9) and a back-end bonding layer (2). The memory array in the memory array wafer (7) includes a memory array without transistors or a memory array containing transistors. The back side of the control circuit wafer (8) is provided with a back via (16) that penetrates the semiconductor substrate (15) and the isolation oxide layer (17), and the diameter of the back via (16) is 10μm to 100μm; The bottom of the back through hole (16) exposes a portion of the first interconnect metal layer (1), and the sidewall of the back through hole (16) is provided with a sidewall insulating layer (5). The back through-hole (16) is filled with aluminum, which contacts the exposed first interconnect metal layer (1) and extends to the back surface of the control circuit wafer (8) to form an aluminum pad (14). The backmost surface of the control circuit wafer (8) is covered with a passivation layer (6) having an opening that exposes the aluminum pads (14).

2. The heterogeneous integrated three-dimensional memory structure according to claim 1, characterized in that, Both of the back-end bonding layers (2) include a dielectric layer and a copper pad (13). The control circuit wafer (8) and the memory array wafer (7) are connected by the copper pads (13) that are bonded to each other, and the interconnect pitch of the copper pads (13) is less than 5 μm. The copper pad (13) has a recess depth of 1 nm to 5 nm on the surface of the dielectric layer where it is located.

3. The heterogeneous integrated three-dimensional memory structure according to claim 1, characterized in that, When the memory array is a transistorless memory array, the memory array is an SOM structure or an 1S1R structure; When the memory array is a memory array containing transistors, the memory array is a 1T1R structure.

4. The heterogeneous integrated three-dimensional memory structure according to claim 1, characterized in that, The storage unit (9) is any one of resistive random access memory, magnetoresistive random access memory, phase change random access memory or ferroelectric random access memory; The sidewall insulating layer (5) is made of silicon dioxide; The passivation layer (6) is made of silicon nitride.

5. A method for fabricating a heterogeneous integrated three-dimensional memory structure, characterized in that, The method for fabricating a heterogeneous integrated three-dimensional memory structure as described in any one of claims 1-4 includes the following steps: The control circuit wafer (8) and the memory array wafer (7) are fabricated independently. The control circuit wafer (8) wherein a front-end transistor layer (4), an isolation oxide layer (17), a first interconnect metal layer (1) and a back-end bonding layer (2) are sequentially fabricated on a semiconductor substrate (15). The memory array wafer (7) is fabricated sequentially with a second interconnect metal layer (3), a memory cell (9) and a back-end bonding layer (2). The memory array in the memory array wafer (7) is fabricated as a memory array without transistors or a memory array containing transistors. The control circuit wafer (8) and the memory array wafer (7) are mixed-bonded front to front; The semiconductor substrate (15) of the bonded control circuit wafer (8) is thinned on the back side; Etching is performed on the back side of the thinned semiconductor substrate (15) to form a back side via (16) that penetrates the semiconductor substrate (15) and the isolation oxide layer (17). The diameter of the back side via (16) is set to 10 μm to 100 μm until the first interconnect metal layer (1) at the bottom is exposed. An insulating layer is formed inside the back through hole (16), and then etched again to expose the first interconnect metal layer (1), while the insulating layer on the hole wall is retained to form a sidewall insulating layer (5). Aluminum is deposited in the back through hole (16) so that the aluminum fills the back through hole (16) and contacts the exposed first interconnect metal layer (1); An aluminum pad (14) is formed on the back surface of the control circuit wafer (8) and is connected to the aluminum in the back through hole (16). A passivation layer (6) is generated on the back side surface and etched to open a window, exposing part of the aluminum pad (14).

6. The preparation method according to claim 5, characterized in that, The specific steps of the front-to-front hybrid bonding include: The surfaces of the two back bonding layers (2) are bonded together at room temperature of 20℃~30℃. Subsequently, it was heat-annealed in a nitrogen atmosphere at a temperature of 300℃~400℃.

7. The preparation method according to claim 5, characterized in that, The specific steps for forming a back-side via (16) penetrating the semiconductor substrate (15) and the isolation oxide layer (17) include: A deep reactive ion etching process is employed, in which a mixed gas containing sulfur fluoride is used to penetrate the silicon semiconductor substrate (15) sequentially, and then a mixed gas containing fluorine carbon is used to penetrate the isolation oxide layer (17).

8. The preparation method according to claim 5, characterized in that, The specific steps for forming the sidewall insulating layer (5) include: A silicon dioxide layer with a thickness of 100 nm to 500 nm is uniformly grown on the inner wall of the back through hole (16) using a chemical vapor deposition process as the insulating layer; Subsequently, an anisotropic dry etching process was used to vertically etch the bottom until no insulating layer remained above the first interconnect metal layer (1), and the silicon dioxide on the sidewall of the back via (16) was retained.

9. The preparation method according to claim 5, characterized in that, The specific steps for forming the aluminum pad (14) are as follows: Aluminum was deposited using physical vapor deposition until the back via (16) was completely filled, and the surface was smoothed using chemical mechanical polishing. Subsequently, an aluminum thin film layer is deposited again, and the aluminum pad (14) is formed on the back surface of the control circuit wafer (8) using photolithography and etching processes.

10. The preparation method according to claim 5, characterized in that, The specific steps for generating the passivation layer (6) on the back side surface are as follows: a silicon nitride film layer with a thickness of 0.5μm to 1.5μm is deposited as the passivation layer (6) in an environment of 300℃ to 350℃ using plasma-enhanced chemical vapor deposition process, and the passivation layer (6) is etched to form an opening that exposes the aluminum pad (14).

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