Stacked capacitor device and method of manufacturing the same

Abstract

This invention provides a stacked capacitor device and a method for manufacturing the same. The stacked capacitor device includes at least one first die, at least one second die, and a plurality of through-hole structures. A first capacitor element is disposed on a first surface of the first die, and a second capacitor element is disposed on a first surface of the second die, with the first surface of the second die facing the first surface of the first die. The plurality of through-hole structures extend from the second surface of the second die, pass through the second die, and are respectively coupled to the first capacitor element and the second capacitor element. The number of first dies and the number of second dies are both one or more.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure, and more particularly to a stacked capacitor device and a method for manufacturing the same. Background Technology

[0002] As the economic benefits of Moore's Law diminish, it's no longer feasible to achieve exponential performance and complexity improvements solely through advancements in manufacturing processes and architecture. Therefore, the industry has shifted from simply relying on process improvements to increase the number of transistors per unit area on a single silicon wafer to enhancing overall performance and functionality through complex system-on-a-chip (SoC) designs with relatively controllable costs. Chiplet technology has gained significant attention in this regard, aiming to achieve higher transistor density and performance at a relatively low cost.

[0003] Chiplet breaks down the many components that would otherwise be included in a single chip into smaller units, enhances their functionality, redesigns and remanufactures them, and uses advanced packaging technology to form a system chip, in which a single capacitor element (Si Cap) is created.

[0004] However, due to the limited area of ​​the chip substrate, if the charging capacity is to be increased, it can only be increased in the vertical direction, but excessively tall capacitors often face the problem of collapse. Summary of the Invention

[0005] The present invention provides a stacked capacitor device that increases capacitance by stacking and joining multiple dies.

[0006] The present invention also provides a method for manufacturing a stacked capacitor device, which can increase capacitance while avoiding the production of excessively high capacitance elements.

[0007] A stacked capacitor device of the present invention includes at least one first die, a first capacitor element, at least one second die, a second capacitor element, and a plurality of through-substrate via structures. The first capacitor element is disposed on a first surface of the first die, and the second capacitor element is disposed on a first surface of the second die, with the first surface of the second die facing the first surface of the first die. The plurality of through-substrate via (TSV) structures extend from the second surface of the second die, pass through the second die, and are respectively coupled to the first capacitor element and the second capacitor element.

[0008] The second die includes a dielectric layer, and the second capacitor element is disposed on the surface of the dielectric layer. The second capacitor element includes a trench capacitor, and the trench capacitor is formed within the dielectric layer. The first and second capacitor elements include stacked capacitors.

[0009] The stacked capacitor device further includes a redistribution layer disposed on a second surface of a second die, and the redistribution layer is coupled to a via structure. A first surface of the second die is bonded to the first surface of the first die. The first surface of the first die includes a BEOL structure formed above a first capacitor element, and the BEOL structure includes an interconnect layer with a multilayer structure. A portion of the via structure passes through the second die and connects to the interconnect layer of the BEOL structure. There are multiple first dies, and each of the multiple first dies has a first capacitor element on its first surface. There are multiple second dies, and each of the multiple second dies has a second capacitor element on its first surface.

[0010] A method for manufacturing a stacked capacitor device according to the present invention includes the following steps: Preparing a first die, wherein a first capacitor element is formed on a first surface of the first die; Preparing a second die, wherein a second capacitor element is formed on a first surface of the second die; Stacking the second die on the first die, with the first surface of the second die facing the first surface of the first die; Thinning the second surface of the second die, wherein the second surface is opposite to the first surface of the second die; Forming a plurality of through-hole structures, wherein the through-hole structures extend from the second surface of the second die through the second die and are respectively coupled to the first capacitor element and the second capacitor element.

[0011] The steps for fabricating the second die include forming the second capacitor element on a semiconductor substrate. The steps for fabricating the second die include first forming a dielectric layer on the semiconductor substrate, and then forming the second capacitor element on the dielectric layer. The step of thinning the second surface of the second die includes removing the semiconductor substrate. After forming the via structure, a redistribution layer may be formed on the second surface of the second die, and the redistribution layer couples to the multiple via structures. The method of stacking the second die on the first die includes fusion bonding or hybrid bonding of the first die and the second die.

[0012] Prior to forming the aforementioned through-hole structure, the following steps may be repeated at least once: preparing another second die, stacking another second die on the first die, thinning the second surface of the other second die, and forming a plurality of through-hole structures, wherein a second second capacitor element is formed on the first surface of the other second die.

[0013] In another embodiment of the present invention, after the step of forming the above-described through-hole structure, the following steps may be included: a step of preparing another first die, a step of preparing another second die, a step of stacking another second die on the other first die, a step of thinning the second surface of the other first die, a step of thinning the second surface of the other second die, and a step of joining the second surfaces of the two dies together, wherein a first surface of the other first die forms another first capacitor element, and a first surface of the other second die forms another second capacitor element.

[0014] The first part of the above-mentioned through-hole structure is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, and the second part of the above-mentioned through-hole structure is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element.

[0015] Based on the above, the method of the present invention can stack multiple dies, fabricate a capacitor element on each die first, and then couple the capacitor element of each die with multiple through-hole structures. Therefore, the process of the present invention is simple and can significantly increase the capacitance while avoiding the fabrication of excessively tall capacitor elements.

[0016] To make the above features of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1 , Figure 3 , Figures 8-9 , Figure 11 and Figure 12 These are cross-sectional views of a stacked capacitor device according to different embodiments of the present invention;

[0018] Figure 2 yes Figure 1 A schematic diagram of the circuit connection of the capacitors in a stacked capacitor device.

[0019] Figures 4A-4G , Figures 5A-5E , Figures 6A-6D , Figures 7A-7D , Figures 10A-10E and Figures 13A-13E This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to different embodiments of the present invention. Detailed Implementation

[0020] Figure 1 This is a cross-sectional view of a stacked capacitor device according to a first embodiment of the present invention.

[0021] Please refer to Figure 1The stacked capacitor device 100 of the first embodiment includes a first die S1, a second die S2, a first capacitor element C1, a second capacitor element C2, and a plurality of through-hole structures V1 and V2. The first capacitor element C1 is disposed on the first surface S11 of the first die S1, for example, the first capacitor element C1 is formed on a semiconductor substrate S1. The second capacitor element C2 is disposed on the first surface S21 of the second die S2, for example, the first capacitor element C1 is formed on another semiconductor substrate S2. The first surface S21 of the second die S2 faces the first surface S11 of the first die S1. The number of second dies S2 is one, but not limited to this. The number of second dies S2 may exceed one. The aforementioned through-hole structures V1 and V2 extend from the second surface S22 of the second die S2, pass through the second die S2, and are respectively coupled to the first capacitor element C1 and the second capacitor element C2. Detailed circuit connections will be provided later. Figure 2 Marking.

[0022] Next, the first die S1 may have an oxide layer 102a formed on the first capacitor element C1 to planarize its surface, facilitating the formation of subsequent circuits. The circuits may be formed, for example, in a back end of line (BEOL) structure above the semiconductor substrate SS1 and the first capacitor element C1. The BEOL structure includes a BEOL insulating layer 104a and an interconnect layer W1 with a multilayer structure therein. The BEOL insulating layer 104a is, for example, an oxide layer. The interconnect layer W1 includes a copper layer, an aluminum layer, or a combination thereof. Similarly, the second die S2 may have an oxide layer 102b formed on the second capacitor element C2 to planarize its surface, facilitating the formation of subsequent circuits. The circuits may be formed, for example, in a BEOL structure above the semiconductor substrate SS2 and the second capacitor element C2. The BEOL structure includes a BEOL insulating layer 104b and an interconnect layer W2 with a multilayer structure therein. The BEOL insulating layer 104b is, for example, an oxide layer. The interconnect layer W2 includes a copper layer, an aluminum layer, or a combination thereof. The stacked capacitor device 100 is obtained by joining the first surface S11 of the first die S1 and the first surface S21 of the second die S2; for example, the oxide layer 106a formed on the BEOL insulating layer 104a and the oxide layer 106b formed on the BEOL insulating layer 104b can be joined to the first die S1 by fusion bonding or hybrid bonding, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b.

[0023] exist Figure 1In the process, through-hole structures V1 and V2 are respectively connected to interconnect layers W1 and W2, and a hard mask layer 108 can be provided on the second surface S22 of the second die S2 to facilitate the formation of through-hole structures V1 and V2. The materials of through-hole structures V1 and V2 are, for example, copper or other suitable metals or alloys, and a pad layer 110, such as a silicon oxide layer or other suitable insulating material layer, can be provided on the sidewalls of both through-hole structures V1 and V2. Figure 1 In this process, the padding layer 110 does not contact the interconnect layer W1 and / or the interconnect layer W2, but the padding layer 110 may directly contact the interconnect layer W1 and / or the interconnect layer W2.

[0024] The stacked capacitor device 100 of the first embodiment further includes a redistribution layer RDL disposed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to via structures V1 and V2. The redistribution layer RDL includes a redistribution insulating layer 112 and a conductive redistribution pattern extending within the redistribution insulating layer 112. For example, the redistribution insulating layer 112 may contain polyimide (PI) or other suitable materials. The redistribution pattern may include multiple conductive lines 114 and redistribution vias 116, and the redistribution layer RDL may also include bonding pads 118, and the lower conductive lines 114 are connected to the upper bonding pads 118 through the redistribution vias 116.

[0025] The first capacitor element C1 is electrically connected to the interconnect layer W1, so the via structure V1 can be coupled to the first capacitor element C1 through the interconnect layer W1; similarly, the second capacitor element C2 is electrically connected to the interconnect layer W2, so the via structure V2 can be coupled to the second capacitor element C2 through the interconnect layer W2. Detailed circuit connections are as follows: Figure 2 As shown, and in Figure 2 Used with Figure 1 The same component symbols are used to represent the same or similar components, and the contents of the same or similar components can also be referenced. Figure 1 The relevant explanations will not be repeated here. Furthermore, in order to display the circuit connections within the same cross-section, therefore... Figure 2 Seemingly more Figure 1 The area is large, but it should be known that Figure 2 The structures (such as different through-hole structures) may be distributed across different cross-sections, so the overall area of ​​the stacked capacitor device does not increase as a result.

[0026] Please refer to Figure 2The first capacitor element C1 includes a first capacitor electrode TE, a second capacitor electrode BE, and a dielectric layer SC between the first capacitor electrode TE and the second capacitor electrode BE; the second capacitor element C2 also includes a first capacitor electrode TE, a second capacitor electrode BE, and a dielectric layer SC between the first capacitor electrode TE and the second capacitor electrode BE. The first capacitor element C1 and the second capacitor element C2 in the attached figures are schematic structures, which can be planar capacitors, trench capacitors, cylindrical capacitors, or combinations thereof. Through-hole structure V1 is coupled to the first capacitor electrode TE of the first capacitor element C1, through-hole structure V2 is coupled to the first capacitor electrode TE of the second capacitor element C2, through-hole structure V1' is coupled to the second capacitor electrode BE of the first capacitor element C1, and through-hole structure V2' is coupled to the second capacitor electrode BE of the second capacitor element C2. Therefore, a portion of the through-hole structures V1 and V2 are coupled to the first capacitor electrode TE of different capacitor elements, while other portions of the through-hole structures V2' and V1' are coupled to the second capacitor electrode BE of different capacitor elements. Figure 2 In the diagram, both through-hole structures V1 and V2 are connected to the power supply voltage (V). DD Therefore, the first capacitor electrode TE of both the first capacitor element C1 and the second capacitor element C2 is coupled to V. DD Comparison Figure 1 The via structures V1 and V2 in the redistribution layer RDL can be electrically connected to the same bonding pad 118 via the conductive line 114 in the redistribution layer RDL. Similarly, both via structures V1' and V2' are connected to the ground voltage (V). SS Therefore, the second capacitor electrode BE of both the first capacitor element C1 and the second capacitor element C2 is coupled to V. SS ; and so on.

[0027] Figure 3 This is a cross-sectional view of a stacked capacitor device according to a second embodiment of the present invention.

[0028] Please refer to Figure 3The difference between the stacked capacitor device 300 and the first embodiment is that a third die S3 is stacked above the second die S2, that is, two dies (which can also be regarded as two second dies S2) are stacked above the first die S1. A third capacitor element C3 is disposed on the first surface S31 of the third die S3, for example, the third capacitor element C3 is formed on another semiconductor substrate ss3. The first surface S31 of the third die S3 may also have an oxide layer 302 covering the third capacitor element C3 to planarize its surface, so as to facilitate the formation of subsequent circuits, wherein the circuits are formed, for example, in a back-end process (BEOL) structure on the semiconductor substrate ss3 and the third capacitor element C3, and the BEOL structure includes a BEOL insulating layer 304 and an interconnect layer W4 having a multilayer structure therein, and the interconnect layer W4 is electrically coupled to the third capacitor element C3, similar to... Figure 2 The circuit connection method. BEOL insulating layer 304, for example, an oxide layer; interconnect layer W4 includes a copper layer, an aluminum layer, or a combination thereof. Interconnect layer W3 can be connected to the via structure V4 in the third die S3 via redistribution layer RDL. The third die S3 in the stacked capacitor device 300 can be joined to the second die S2 by fusion bonding or hybrid bonding; for example, the oxide layer of the second surface S22 of the second die S2 and the oxide layer of the first surface S31 of the third die S3 can be joined to form an oxide layer 306 with a bonding surface BS, wherein the interconnect layer W3 has a multilayer structure. Interconnect layer W3 can connect via structures V1 and V2 in the second die S2 and via structure V3 in the third die S3.

[0029] exist Figure 3 In this process, a hard mask layer 308 can be provided on the second surface S32 of the third die S3 to facilitate the formation of through-hole structures V3 and V4. The materials of through-hole structures V3 and V4 are, for example, copper or other suitable metals or alloys, and a pad layer 310, such as a silicon oxide layer or other suitable insulating material layer, can be provided on the sidewalls of both through-hole structures V3 and V4. Figure 3In this configuration, the padding layer 310 does not contact the interconnect layer W3 and / or the interconnect layer W4, but is not limited thereto; the padding layer 310 may directly contact the interconnect layer W3 and / or the interconnect layer W4. The redistribution layer RDL is disposed on the second surface S32 of the third die S3, and the redistribution layer RDL is coupled to the via structures V3 and V4. The redistribution layer RDL may include a redistribution insulating layer 312 and conductive redistribution patterns extending within the redistribution insulating layer 312. For example, the redistribution insulating layer 312 may contain PI or other suitable materials. The redistribution pattern may include multiple conductive lines 314 and redistribution vias 316. The materials of the conductive lines 314 and redistribution vias 316 in the redistribution pattern may be, for example, copper, aluminum, tungsten, silver, gold, or other suitable metals or alloys. The redistribution layer RDL may also include bonding pads 318, and the lower conductive lines 314 are connected to the upper bonding pads 318 via redistribution vias 316. The material of the bonding pads 318 may be, for example, aluminum, copper, or other suitable metals or alloys. The exposed surface of the bonding pads 318 may also be provided with conductive terminals (not shown), such as BGA balls or C4 bumps.

[0030] According to the second embodiment, it is possible to stack multiple dies and package them into a single capacitor element (Si Cap), which can expand the charging capacity within a limited wafer substrate area and avoid the problem of excessive capacitor element collapse.

[0031] Figures 4A to 4G This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to a third embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same or similar components, and the contents of the same or similar components can also refer to the relevant description of the first embodiment above, and will not be repeated here.

[0032] Please refer to Figure 4AFirst, a first die S1 and a second die S2 are prepared, and the method for preparing the first die S1 can be the same as or different from the method for preparing the second die S2. If the method for preparing the first die S1 is the same as the method for preparing the second die S2, first dies S1 and second dies S2 with the same or similar structures can be formed. A first capacitor element C1 is first formed on the first surface S11 of the first die S1. The steps are, for example, first forming the first capacitor element C1 on a semiconductor substrate ss1, forming an oxide layer 102a on the first capacitor element C1 and performing a planarization process, and then forming a BEOL structure including a BEOL insulating layer 104a and an interconnect layer W1 with a multilayer structure, wherein the interconnect layer W1 is, for example, a copper layer, and then forming another oxide layer 106a on the above-mentioned BEOL structure. A second capacitor element C2 is first formed on the first surface S21 of the second die S2. The steps include, for example, first forming the second capacitor element C2 on another semiconductor substrate SS2, forming an oxide layer 102b on the second capacitor element C2 and performing a planarization process, then forming a BEOL structure including a BEOL insulating layer 104b and an interconnect layer W2 with a multilayer structure, wherein the interconnect layer W2 is, for example, a copper layer, and then forming another oxide layer 106b on the BEOL structure. Next, the second die S2 is stacked on the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1. The stacking method is, for example, fusion bonding of the first die S1 and the second die S2, and a bonding surface BS is formed between the oxide layers 106a and 106b. However, the invention is not limited to this; the method of stacking the second die S2 on the first die S1 can be, for example, a hybrid bonding wafer-level stacking process.

[0033] Next, please refer to Figure 4B After stacking the second die S2 on the first die S1, a step of thinning the second surface S22 of the second die S2 is performed. Thinning the second surface S22 of the second die S2 may involve thinning the back side of the semiconductor substrate S2. Then, a hard mask layer 108 can be formed on the thinned second surface S22, and a photolithography etching process can be used to form an opening VO1 extending from the second surface S22 through the second die S2. To prevent oxidation of the interconnect layer W1 (such as a copper layer), the opening VO1 stops within the oxide layer 106a above the interconnect layer W1, preventing the interconnect layer W1 from being exposed.

[0034] Then, please refer to Figure 4C Using another photolithography etching process, an opening VO2 is formed extending from the second surface S22 of the second die S2 through the semiconductor substrate ss2. The opening VO2 stops in the oxide layer 102b above the interconnect layer W2 and does not expose the interconnect layer W2.

[0035] Next, please refer to Figure 4DA padding layer 110, such as a silicon oxide layer or other suitable insulating material layer, is formed on the inner surfaces of openings VO1 and VO2. The method of forming the padding layer 110 includes, but is not limited to, depositing a padding material conformally on the surface of the hard mask layer 108 and the inner surfaces of openings VO1 and VO2, and then removing the padding material other than openings VO1 and VO2.

[0036] Then, please refer to Figure 4E First, the padding layer 110 at the bottom of opening VO1 and opening VO2 is removed. Then, further etching is performed until the interconnect layer W1 below opening VO1 and the interconnect layer W2 below opening VO2 are exposed. Since the thickness of the padding layer 110 in opening VO1 and opening VO2 is similar, and the remaining portion of the oxide layer 106a below opening VO1 and the remaining portion of the oxide layer 102b below opening VO2 are about the same thickness, this etching step can be performed simultaneously.

[0037] Then, please refer to Figure 4F A via structure V1 is formed within opening VO1, and a via structure V2 is formed within opening VO2. The method for forming via structures V1 and V2 includes, but is not limited to, depositing a metal material to fill openings VO1 and VO2, followed by an etch-back or planarization process to remove the metal material outside openings VO1 and VO2. Furthermore, a barrier layer (not shown) may be formed on the inner surfaces of openings VO1 and VO2 before depositing the metal material. The formed via structure V1 extends from the second surface S22 through the second die S2 and is coupled to the interconnect layer W1, while the formed via structure V2 extends from the second surface S22 through the semiconductor substrate ss2 in the second die S2 and is coupled to the interconnect layer W2. Detailed circuit connections can be found in [reference needed]. Figure 2 The relevant explanations are omitted here.

[0038] Please refer to Figure 4G A redistribution layer RDL can be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to via structures V1 and V2. The method for forming the redistribution layer RDL includes, but is not limited to, forming multiple conductive lines 114 connecting via structures V1 and V2, depositing a redistribution insulating layer 112, and then forming redistribution vias 116 and bonding pads 118 in the redistribution insulating layer 112, exposing the bonding pads 118. Subsequently, conductive terminals (not shown), such as BGA balls or C4 bumps, can be formed on the exposed surface of the bonding pads 118.

[0039] Figures 5A to 5E This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to the fourth embodiment of the present invention.

[0040] Please refer to Figure 5A The previous process flow can be referenced. Figures 4A to 4F Then, an oxide layer 500 and an interconnect layer W3 are formed on the second surface S22 of the second die S2. The interconnect layer W3 connects the through-hole structures V1 and V2.

[0041] Please refer to Figure 5B The third die S3 is prepared using the same method as the second die S2, so the third die S3 can also be considered as another second die. A third capacitor element C3 is first formed on the first surface S31 of the third die S3. For example, the steps include first forming the third capacitor element C3 on a semiconductor substrate ss3, forming an oxide layer 302 on the third capacitor element C3 and performing a planarization process, and then forming a BEOL structure including a BEOL insulating layer 304 and an interconnect layer W4 with a multilayer structure. The interconnect layer W4 is, for example, a copper layer, and the interconnect layer W4 is electrically coupled to the third capacitor element C3, similarly. Figure 2 The circuit connection method. Then, another oxide layer 502 is formed on the above BEOL structure. Next, a third die S3 is stacked on the second die S2, and the first surface S31 of the third die S3 also faces the first surface S11 of the first die S1, wherein the stacking method is, for example, fusion bonding or hybrid bonding, and a bonding surface BS is formed between the oxide layer 500 and the oxide layer 502.

[0042] exist Figure 5C For reference Figure 4B and Figure 4C In this manner, after thinning the third die S3, a hard mask layer 308 is formed on the second surface S32. Then, openings VO3 and VO4 are formed extending from the second surface S32 of the third die S3 through the semiconductor substrate ss3 of the third die S3. Opening VO3 is located within the oxide layer 502 above the interconnect layer W3, but is not limited to this. Opening VO3 can also be located within the oxide layer 500 above the interconnect layer W3. Different photolithography etching processes can be used to form openings VO3 and VO4 of different depths, and to prevent the interconnect layers W3 and W4 (such as copper layers) from being exposed and oxidized.

[0043] Subsequently, Figure 5D For reference Figures 4D to 4F In this manner, a liner layer 310 is formed on the inner surface of openings VO3 and VO4, exposing the interconnect layer W3 below opening VO3 and the interconnect layer W4 below opening VO4, and forming through-hole structures V3 and V4 therein, respectively.

[0044] If you need to stack other dies, you can repeat the above steps. Figures 5A to 5D The steps.

[0045] exist Figure 5E For reference, please refer to the following: Figure 4G In this manner, a redistribution layer RDL comprising a redistribution insulating layer 312, a conductive line 314, a redistribution via 316 and a bonding pad 318 can be formed on the second surface S32 of the third die S3, and the redistribution layer RDL is coupled to via structures V3 and V4.

[0046] Figures 6A to 6D This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to the fifth embodiment of the present invention.

[0047] Please refer to Figure 6A First, a first die S1 and a second die S2 are prepared. The method for preparing the first die S1 can be the same as or different from the method for preparing the second die S2. If the method for preparing the first die S1 is the same as the method for preparing the second die S2, first dies S1 and second dies S2 with the same or similar structures can be formed. A first capacitor element C1 is first formed on the first surface S11 of the first die S1. The steps are as follows: first, the first capacitor element C1 is formed on a semiconductor substrate ss1, and an oxide layer 102a is formed on the first capacitor element C1 and planarized. Then, a BEOL structure including a BEOL insulating layer 104a and an interconnect layer W1 with a multilayer structure is formed thereon. Next, another oxide layer 106a and a metal layer ML1 located in the oxide layer 106a are formed on the BEOL structure. The metal layer ML1 is electrically connected to the interconnect layer W1, and the metal layer ML1 is, for example, an aluminum layer or other metal material layer that is not easily oxidized. A second capacitor element C2 is first formed on the first surface S21 of the second die S2. The steps include, for example, first forming the second capacitor element C2 on another semiconductor substrate SS2, forming an oxide layer 102b on the second capacitor element C2 and performing a planarization process, then forming a BEOL structure including a BEOL insulating layer 104b and an interconnect layer W2 with a multilayer structure. Next, another oxide layer 106b and a metal layer ML2 located in the oxide layer 106b are formed on the BEOL structure, wherein the metal layer ML2 is electrically connected to the interconnect layer W2, and the metal layer ML2 is, for example, an aluminum layer or other metal material layer that is less prone to oxidation. Next, the second die S2 is stacked on the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1. The stacking method is, for example, fusion bonding of the first die S1 and the second die S2, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b. However, the invention is not limited to this; the method of stacking the second die S2 on the first die S1 is, for example, hybrid bonding.

[0048] Please refer to Figure 6B The second surface S22 of the second die S2 is thinned, and then the opening VO1 and opening VO2 are formed simultaneously by photolithography etching process. The metal layer ML1 in the deeper opening VO1 can be used as the etching stop layer.

[0049] Please refer to Figure 6C A via structure V1 is formed within opening VO1, and a via structure V2 is formed within opening VO2. The method for forming via structures V1 and V2 includes, but is not limited to, depositing a metal material to fill openings VO1 and VO2, followed by an etch-back or planarization process to remove the metal material outside openings VO1 and VO2. Before depositing the metal material, if necessary, a film layer such as a liner layer (not shown) or a barrier layer (not shown) may be formed on the inner surface or sidewall of openings VO1 and VO2.

[0050] exist Figure 6D For reference, please refer to the following: Figure 4G As explained above, a redistribution layer RDL can be formed on the second surface S22 of the second die S2, so it will not be elaborated further.

[0051] Figures 7A to 7D This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to the sixth embodiment of the present invention.

[0052] Please refer to Figure 7A The previous process flow can be referenced. Figures 6A to 6C Then, an oxide layer 700 and an interconnect layer W3 and a metal layer ML3 are first formed on the second surface S22 of the second die S2, and the interconnect layer W3 and the metal layer ML3 are electrically connected, wherein the metal layer ML3 is, for example, an aluminum layer or other metal material layer that is not easily oxidized.

[0053] Please refer to Figure 7B The third die S3 is prepared using the same method as the second die S2, so the third die S3 can also be considered as another second die. A third capacitor element C3 is first formed on the first surface S31 of the third die S3. An oxide layer 302 is formed on the third capacitor element C3 and planarized. Then, a BEOL structure including a BEOL insulating layer 304 and a multilayer interconnect layer W4 is formed on it. The interconnect layer W4 is electrically coupled to the third capacitor element C3, similar to... Figure 2 The circuit connection method is as follows. Next, another oxide layer 700 and a metal layer ML4 therein are formed on the above BEOL structure, and the interconnect layer W4 and the metal layer ML4 are electrically connected, wherein the metal layer ML4 is, for example, an aluminum layer or other metal material layer that is not easily oxidized. Next, a third die S3 is stacked on the second die S2, and the first surface S31 of the third die S3 also faces the first surface S11 of the first die S1, wherein the above stacking method is, for example, fusion bonding or hybrid bonding, and a bonding surface BS is formed between the oxide layer 700 and the oxide layer 702.

[0054] exist Figure 7C For reference, please refer to the following: Figures 6B to 6C The third die S3 is thinned to form through-hole structures V3 and V4. Through-hole structure V3 is coupled to the first capacitor element C1 and the second capacitor element C2 via metal layer ML3. Through-hole structure V4 is coupled to the third capacitor element C3 via metal layer ML4.

[0055] exist Figure 7D For reference, please refer to the following: Figure 5E As explained above, a redistribution layer RDL can be formed on the second surface S32 of the third die S3, so it will not be elaborated further.

[0056] Figure 8 This is a cross-sectional view of a stacked capacitor device according to the seventh embodiment of the present invention.

[0057] Please refer to Figure 8 The difference between the stacked capacitor device 800 and the first embodiment is that, in the stacked capacitor device 800, only the first die S1 has a semiconductor substrate ss1; the other dies do not have semiconductor substrates. Instead, a dielectric layer D2 is used, and the second capacitor element C2 is formed on it. Therefore, the total thickness of the stacked capacitor device 800 can be significantly reduced. For example, the thickness of the thinned semiconductor substrate may be more than 10 times greater than the thickness of the dielectric layer D2, so the semiconductor substrate-free design is more suitable for use in devices such as mobile devices that require small volume. The dielectric layer D2 and the second capacitor element C2 formed on the surface D2s of the dielectric layer D2, together with the oxide layer 102b and the BEOL structure covering the second capacitor element C2, can be regarded as the second die S2. If the first die S1 and the second die S2 are manufactured using the same process, the first die S1 may include a semiconductor substrate ss1, a dielectric layer D1 thereon, a first capacitor element C1 formed on the surface D1s of the dielectric layer D1, an oxide layer 102a, and a BEOL structure covering the first capacitor element C1. The materials of the dielectric layer D1 and the dielectric layer D2 are, for example, silicon oxide or other suitable dielectric materials.

[0058] exist Figure 8 In the process, via structures V1 and V2 connect interconnect layers W1 and W2 respectively. Since the via process does not require etching the semiconductor substrate, this step can be omitted. Figure 1 The hard mask layer 108 directly etches through the dielectric layer D2, oxide layer 102b, BEOL insulating layer 104b, oxide layer 106a, and oxide layer 106b, which have similar etch rates, and stops at the interconnect layers W1 and W2. Furthermore, because the semiconductor substrate-free design reduces the total thickness of the stacked capacitor device 800, the depth of the via structure V1 (and via structure V2) also decreases. Therefore, the aspect ratio of via structure V1 and via structure V2 naturally decreases, reducing the difficulty of the process.

[0059] Figure 9 This is a cross-sectional view of another stacked capacitor device according to the seventh embodiment.

[0060] exist Figure 9 In the middle, the stacked capacitor device 900 and Figure 8 The difference between the stacked capacitor devices 800 is that a third die S3 is stacked above the second die S2, that is, two dies (or two second dies S2) are stacked above the first die S1. The first surface S31 of the third die S3 faces downward. Therefore, the third die S3 also does not contain a semiconductor substrate, but may include a dielectric layer D3, a third capacitor element C3 formed on the dielectric layer D3, an oxide layer 302, and a BEOL structure covering the third capacitor element C3 (such as a BEOL insulating layer 304 and an interconnect layer W4). As for the redistribution layer RDL, it is disposed on the back side D3b of the dielectric layer D3, and the redistribution layer RDL is coupled to via structures V3 and V4. The redistribution layer RDL may include a redistribution insulating layer 312 and conductive redistribution patterns extending within the redistribution insulating layer 312, such as conductive lines 314, redistribution vias 316, bonding pads 318, etc., but is not limited to these.

[0061] Figures 10A to 10E This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to the eighth embodiment of the present invention.

[0062] Please refer to Figure 10AFirst, a first die S1 and a second die S2 are prepared. The method for preparing the first die S1 can be the same as or different from the method for preparing the second die S2. If the method for preparing the first die S1 is the same as the method for preparing the second die S2, first dies S1 and second dies S2 with the same or similar structures can be formed. For example, the method for preparing the first die S1 is to form a dielectric layer D1 on a semiconductor substrate ss1, form a first capacitor element C1 on the surface D1s of the dielectric layer D1, then form an oxide layer 102a on the first capacitor element C1, and form a BEOL structure on the oxide layer 102a. The BEOL structure may include a BEOL insulating layer 104a, an interconnect layer W1, and an aluminum pad AP that is less prone to oxidation. Then, another oxide layer 106a is formed on the BEOL structure. The method for fabricating the second die S2 is similar to that for fabricating the first die S1. For example, a dielectric layer D2 is formed on a semiconductor substrate ss2, a second capacitor element C2 is formed on the surface D2s of the dielectric layer D2, an oxide layer 102b is formed on the second capacitor element C2, a BEOL structure is formed on the oxide layer 102b, and then another oxide layer 106b is formed on the BEOL structure. Then, the second die S2 is stacked on the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1. The stacking method is, for example, fusion bonding or hybrid bonding of the first die S1 and the second die S2, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b.

[0063] Please refer to Figure 10B After the step of stacking the second die S2 on the first die S1, a step of thinning the second surface S22 of the second die S2 is performed, for example, removing... Figure 10A The semiconductor substrate SS2 is located in the middle. The semiconductor substrate SS2 can be removed by wet etching. The back side of the semiconductor substrate SS2 can be polished first using a planarization process such as CMP, and then the semiconductor substrate SS2 can be completely removed by wet etching.

[0064] Please refer to Figure 10C Using another photolithography etching process, openings VO1 and VO2 are formed extending from the second surface S22 of the second die S2 through the second die S2, with openings VO1 and VO2 stopping at different aluminum pads AP.

[0065] Please refer to Figure 10DA pad layer 110 is formed on the inner surfaces of openings VO1 and VO2. The method for forming the pad layer 110 includes, but is not limited to, conformally depositing a pad material on the dielectric layer D2 and on the inner surfaces of openings VO1 and VO2. Then, a via structure V1 is formed in opening VO1 and a via structure V2 is formed in opening VO2. The method for forming via structures V1 and V2 includes, but is not limited to, first depositing a metal material to fill openings VO1 and VO2, and then performing an etch-back or planarization process to remove the metal material and the aforementioned pad material outside of openings VO1 and VO2.

[0066] Please refer to Figure 10E A redistribution layer RDL can be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to via structures V1 and V2. The method for forming the redistribution layer RDL includes, but is not limited to, forming multiple conductive lines 114 connecting via structures V1 and V2, depositing a redistribution insulating layer 112, and then forming redistribution vias 116 and bonding pads 118 in the redistribution insulating layer 112, exposing the bonding pads 118. Subsequently, conductive terminals (not shown), such as BGA balls or C4 bumps, can be formed on the exposed surface of the bonding pads 118.

[0067] Figure 11 This is a cross-sectional view of a stacked capacitor device according to the ninth embodiment of the present invention.

[0068] Please refer to Figure 11 Stacked capacitor device 1100 and Figure 9The difference between the stacked capacitor devices 900 is that a trench capacitor TC1 is further formed in the dielectric layer D1. In some embodiments, the dielectric layer D1 includes a first film layer L1 and a second film layer L2. The first film layer L1 is formed on the semiconductor substrate ss1, the second film layer L2 is formed on the first film layer L1, and the trench capacitor TC1 is formed between the first film layer L1 and the second film layer L2. A planar capacitor PC1 can be formed on the second film layer L2. The trench capacitor TC1 and the planar capacitor PC1 are the first capacitor elements disposed on the first die S1, so the capacitance can be further increased. The trench capacitor TC1 includes an upper electrode 400, a lower electrode 404, and a dielectric layer 402 therebetween. The planar capacitor PC1 also includes an upper electrode 406, a lower electrode 410, and a dielectric layer 408 therebetween. The upper electrode 400 of the trench capacitor TC1 can be electrically connected to the upper electrode 406 of the planar capacitor PC1 via a circuit structure 412a. The lower electrode 404 of the trench capacitor TC1 can be electrically connected to the lower electrode 410 of the planar capacitor PC1 via a circuit structure 412b. The circuit structure 412a is connected to the interconnect layer W1 in the BEOL structure and can be coupled to the via structure V1 via the less oxidizable aluminum pad AP on the interconnect layer W1. The interconnect layer W1 connected to the circuit structure 412b is also connected to the via structure V1 formed in other cross sections (not shown).

[0069] exist Figure 11 In the second die S2, the dielectric layer D2 also contains a trench capacitor TC2 and a planar capacitor PC2. The dielectric layer D2 includes a first film layer L1 and a second film layer L2. Since the second die S2 is flipped and bonded to the first die S1, the second film layer L2 is located below the first film layer L1. The trench capacitor TC2 is formed between the first film layer L1 and the second film layer L2, and the planar capacitor PC2 is formed on the second film layer L2. Therefore, the trench capacitor TC2 and the planar capacitor PC2 are the second capacitor elements disposed on the second die S2. The trench capacitor TC2 is similar to the trench capacitor TC1, and the planar capacitor PC2 is similar to the trench capacitor TC1. Therefore, their circuit design and connection method can refer to the first die S1, and different electrodes of the trench capacitor TC2 and the planar capacitor PC2 can be coupled out through different through-hole structures V2. A third die S3 is stacked on top of the second die S2, meaning that two dies (which can also be considered as two second dies S2) are stacked on top of the first die S1. Therefore, the structure of the third die S3 is the same as that of the second die S2, so it will not be described again.

[0070] Please refer to Figure 11Interconnect layer W3 connects the via structure V1 in the second die S2 and the via structure V3 in the third die S3, and connects the lower conductive line 314 to the upper bonding pad 318 through the redistribution via 316 in the redistribution layer RDL. Interconnect layer W4 couples the different electrodes of trench capacitor TC3 and planar capacitor PC3 to different via structures V4, and connects them to different upper bonding pads 318 through the conductive line 314 and redistribution via 316 in the redistribution layer RDL.

[0071] Figure 12 This is a cross-sectional view of a stacked capacitor device according to the tenth embodiment of the present invention.

[0072] Please refer to Figure 12 The difference between the stacked capacitor device 1200 and the ninth embodiment is that, in the stacked capacitor device 1200, in addition to the capacitor elements in the first die S1 and the second die S2 each including multiple capacitors, for example, the first capacitor element C1 includes two stacked capacitors SC1, and the second capacitor element C2 includes two stacked capacitors SC2. The two stacked capacitors SC1 can be connected in series or in parallel, and the two stacked capacitors SC2 can be connected in series or in parallel. Furthermore, the die stacking method in the stacked capacitor device 1200 is as follows: first, the second die S2 is stacked on the first die S1; then, the second die S2' is stacked on the first die S1'; and finally, the second die S2' is stacked on the second die S2. The first die S1' has essentially the same components as the first die S1, and the second die S2' has essentially the same components as the second die S2. The differences between them may only exist in the interconnection of the back-end process and the redistribution layer. A redistribution layer RDL can be provided on the second surface S22 of the second die S2 to facilitate circuit connections. Furthermore, the stacked capacitor device 1200 also includes a through-hole structure V7 penetrating the first die S1' and the second die S2'. Figure 12 In the diagram, via structure V1” couples interconnect layer W1' to interconnect layer W3', and via structure V2” couples interconnect layer W2' to interconnect layer W3. Via structure V6 couples conductive line 314 to interconnect layer W1', and via structure V5 couples conductive line 314 to interconnect layer W2'. Even if some connections are not shown, it should be understood that there are connecting layers in other cross-sections.

[0073] Figures 13A to 13E This is a cross-sectional schematic diagram of the manufacturing process of a stacked capacitor device according to the eleventh embodiment of the present invention.

[0074] Please refer to Figure 13AFirst, a first die S1 and a second die S2 are prepared, and the methods for preparing the first die S1 and the second die S2 can refer to the description in the foregoing embodiments. In some embodiments, a plurality of stacked capacitors SC1 can be formed in the first die S1, and a plurality of stacked capacitors SC2 can be formed in the second die S2. Then, the second die S2 is stacked on the first die S1, with the first surface S21 of the second die S2 facing the first surface S11 of the first die S1, wherein the stacking method is, for example, fusion bonding or hybrid bonding of the first die S1 and the second die S2, and a bonding surface BS is formed between the oxide layer 106a and the oxide layer 106b.

[0075] Next, please refer to Figure 13B After the step of stacking the second die S2 on the first die S1, a step of thinning the second surface S22 of the second die S2 is performed, for example, removing... Figure 13A The semiconductor substrate ss2 is used. The relevant process can be referred to the description in the foregoing embodiment. Then, through-hole structures V1 and V2 are formed, extending from the second surface S22 of the second die S2 and passing through the second die S2. Through-hole structure V1 is located on an aluminum pad AP in the contact BEOL insulating layer 104a, and through-hole structure V2 is located on an aluminum pad AP in the BEOL insulating layer 104b. Through-hole structure V1 is electrically coupled to a first capacitor element C1, and through-hole structure V2 is electrically coupled to a second capacitor element C2. There can be multiple through-hole structures V1 and V2, which are similar. Figure 2 The circuit connection method.

[0076] Then, please refer to Figure 13C A redistribution layer RDL can be formed on the second surface S22 of the second die S2, and the redistribution layer RDL is coupled to via structures V1 and V2. The method for forming the redistribution layer RDL can refer to the description in the foregoing embodiment. Next, an oxide layer 106c can be formed on the redistribution layer RDL.

[0077] Please refer to Figure 13D Repeat the preceding steps to stack another first die S1' and a second die S2', and form another oxide layer 106d with the second surface S22 of the second die S2', which can then be fused to the oxide layer 106c. Then, a through-hole structure V5 and a through-hole structure V6 extending from the second surface S12 of the first die S1' through the first die S1' are formed.

[0078] Please refer to Figure 13EA via structure V7 is formed, extending from the second surface S12 of the first die S1' through the first die S1' and the second die S2, and is located in the aluminum pad AP in the second die S2. Another redistribution layer RDL can be formed on the second surface S12, and the redistribution layer RDL is coupled to the via structures V5, V6, and V7. The method for forming the redistribution layer RDL can refer to the description in the foregoing embodiment, and exposes the bonding pad 318. Conductive terminals (not shown), such as BGA balls or C4 bumps, can then be formed on the exposed surface of the bonding pad 318.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A stacked capacitor device, characterized in that, include: At least one first die; A first capacitor element is disposed on the first surface of the at least one first die; At least one second die is stacked on the first surface of the first die; A second capacitor element is disposed on the first surface of the at least one second die, and the first surface of the at least one second die faces the first surface of the at least one first die; as well as Multiple through-hole structures extend from the second surface of the at least one second die through the at least one second die and are respectively coupled to the first capacitor element and the second capacitor element.

2. The stacked capacitor device according to claim 1, characterized in that, The at least one second die includes a dielectric layer, and the second capacitor element is disposed on the surface of the dielectric layer.

3. The stacked capacitor device according to claim 1, characterized in that, The first capacitor element and the second capacitor element each include a plurality of stacked capacitors.

4. The stacked capacitor device according to claim 1, characterized in that, The first portion of the plurality of through-hole structures is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, and the second portion of the plurality of through-hole structures is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element.

5. The stacked capacitor device according to claim 1, characterized in that, The first surface of the at least one second die is engaged with the first surface of the first die.

6. The stacked capacitor device according to claim 1, characterized in that, The first surface of the first die includes a BEOL structure formed above the first capacitor element, the BEOL structure including interconnect layers with a multilayer structure.

7. The stacked capacitor device according to claim 1, characterized in that, The number of the at least one first die is multiple, and each of the multiple first dies has a first capacitor element on its first surface. The number of the at least one second die is multiple, and each of the multiple second dies has a second capacitor element on its first surface.

8. A method for manufacturing a stacked capacitor device, characterized in that, include: The step of preparing the first die, wherein a first capacitor element is formed on the first surface of the first die; The step of preparing the second die, wherein a second capacitor element is formed on the first surface of the second die; The step of stacking the second die on the first die, wherein the first surface of the second die faces the first surface of the first die; The step of thinning the second surface of the second die, wherein the second surface is relative to the first surface of the second die; as well as The step of forming a plurality of through-hole structures, wherein the plurality of through-hole structures extend from the second surface of the second die through the second die and are respectively coupled to the first capacitor element and the second capacitor element.

9. The method for manufacturing a stacked capacitor device according to claim 8, characterized in that, The first portion of the plurality of through-hole structures is coupled to the first capacitor electrode of the first capacitor element and the first capacitor electrode of the second capacitor element, and the second portion of the plurality of through-hole structures is coupled to the second capacitor electrode of the first capacitor element and the second capacitor electrode of the second capacitor element.

10. The method for manufacturing a stacked capacitor device according to claim 8, characterized in that, Methods of stacking the second die on the first die include fusion bonding or hybrid bonding of the first die and the second die.

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