Ferroelectric capacitors and their manufacturing methods, semiconductor modules, electronic equipment
By introducing a van der Waals interface buffer layer into the ferroelectric capacitor device, the problems of interface reaction and defects in traditional ferroelectric memories are solved, achieving low leakage current and long-term stability, and improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2026-04-29
- Publication Date
- 2026-07-31
AI Technical Summary
In traditional ferroelectric memories, the interface between the electrode and the ferroelectric layer is prone to the formation of reaction layers, oxygen vacancies, and lattice defects, leading to problems such as large leakage current, short data retention time, and reduced polarization.
A first buffer layer and a second buffer layer are introduced between the electrode layer and the ferroelectric layer. All contact interfaces are van der Waals interfaces, and the layers are connected by van der Waals forces to avoid chemical reactions and atomic diffusion.
It effectively suppresses interface dead layers, reduces leakage current, improves long-term stability, and enhances the performance and reliability of ferroelectric capacitors.
Smart Images
Figure CN122497083A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a ferroelectric capacitor and its manufacturing method, a semiconductor module, and an electronic device. Background Technology
[0002] Ferroelectric memories, as a non-volatile memory technology, have attracted much attention due to their advantages such as high-speed read / write and low power consumption. Hafnium oxide-based ferroelectric thin films are the core materials for next-generation ferroelectric memories and have been extensively studied. They can be used in high-density, high-speed, low-power non-volatile memories, neuromorphic computing, low-power logic circuits, and other fields.
[0003] The interface between a traditional electrode and the ferroelectric layer is prone to the formation of reaction layers, oxygen vacancies, contaminants, and lattice defects, leading to the following problems:
[0004] 1. Dead layer at the interface: Chemical reactions, atomic interdiffusion, and lattice mismatch between the electrode and the ferroelectric layer can form a non-ferroelectric layer several nanometers thick at the interface. This "dead layer" generates a strong depolarization field, significantly weakening the polarization of the ferroelectric layer, leading to a decrease in remanent polarization and an increase in coercivity.
[0005] 2. Interface Defects: Defects such as oxygen vacancies at the interface can form conductive paths, leading to higher leakage current, increased static power consumption, and shorter data hold time. The resulting charge traps cause switching response lag and fatigue.
[0006] 3. Thermal mismatch and stress lead to instability in the ferroelectric domain structure;
[0007] Current attempts have been made to introduce transition layers such as oxide buffer layers, but these buffer layers may still cause interfacial reactions or lattice mismatch, making it difficult to simultaneously achieve defect suppression and high-quality electrical properties.
[0008] Therefore, effectively suppressing interface dead layers, reducing leakage current, and improving the long-term stability of the interface are key technical bottlenecks for improving the performance of ferroelectric capacitors. Summary of the Invention
[0009] In view of this, the present disclosure proposes a ferroelectric capacitor device, the ferroelectric capacitor device comprising:
[0010] Substrate;
[0011] A first electrode layer is disposed on the substrate;
[0012] A first buffer layer is disposed on the first electrode layer;
[0013] A ferroelectric layer is disposed on the first buffer layer;
[0014] A second buffer layer is disposed on the ferroelectric layer;
[0015] The second electrode layer is disposed on the second buffer layer.
[0016] The first buffer layer and the second buffer layer are made of van der Waals material, and the contact interfaces between the first electrode layer and the first buffer layer, the ferroelectric layer and the first buffer layer, the ferroelectric layer and the second buffer layer, and the second buffer layer and the second electrode layer are all van der Waals interfaces.
[0017] In one possible implementation, the materials of the first electrode layer and the second electrode layer include any one of TiN, TaN, TiC, TaC, Au, and Ag.
[0018] The thickness of both the first electrode layer and the second electrode layer is 10-50 nm.
[0019] In one possible implementation, the van der Waals material includes any one of inorganic molecular crystal materials, organic molecular crystal materials, and organic-inorganic hybrid molecular crystal materials.
[0020] The thickness of both the first buffer layer and the second buffer layer is 1-5 nm.
[0021] In one possible implementation, the substrate is any one of silicon, silicon dioxide, silicon nitride, silicon carbide, gallium nitride, gallium arsenide, sapphire, lanthanum strontium manganese oxide, strontium titanate, polyimide film, and mica;
[0022] The ferroelectric layer is a zirconium-doped hafnium oxide-based ferroelectric thin film with a thickness of 3-15 nm.
[0023] According to another aspect of this disclosure, a semiconductor module is provided, the semiconductor module including the aforementioned ferroelectric capacitor element.
[0024] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the semiconductor module described above.
[0025] According to another aspect of this disclosure, a method for manufacturing a ferroelectric capacitor is provided, the method comprising:
[0026] A first electrode layer is deposited on the substrate;
[0027] A first buffer layer is grown on the first electrode layer using a high-vacuum thermal evaporation process, and the material of the first buffer layer is van der Waals material.
[0028] A ferroelectric layer is deposited on the first buffer layer;
[0029] A second buffer layer is grown on the ferroelectric layer using a high-vacuum thermal evaporation process, and the material of the second buffer layer is van der Waals material.
[0030] A second electrode layer is formed on the second buffer layer to obtain the ferroelectric capacitor device.
[0031] Wherein, the contact interface between the first electrode layer and the first buffer layer, the contact interface between the ferroelectric layer and the first buffer layer, the contact interface between the ferroelectric layer and the second buffer layer, and the contact interface between the second buffer layer and the second electrode layer are all van der Waals interfaces.
[0032] In one possible implementation, the growth of the first buffer layer on the first electrode layer using a high-vacuum thermal evaporation process and the growth of the second buffer layer on the ferroelectric layer using a high-vacuum thermal evaporation process both include:
[0033] The van der Waals material is placed in a heating container, and the heating container is heated to a first temperature;
[0034] The substrate is heated at a second temperature, wherein the substrate is disposed at the opening of the heating container, the object to be operated is placed on the substrate, the substrate is provided with an opening and closing component, the opening and closing component is configured to open or close in response to an operation signal, the object to be operated includes a device after deposition of a first electrode layer or a device after deposition of a ferroelectric layer, and the second temperature is lower than the first temperature.
[0035] The opening and closing component is controlled to open for a preset time to grow the first buffer layer or the second buffer layer on the object to be operated.
[0036] In one possible implementation, depositing the first electrode layer on the substrate includes:
[0037] The first electrode layer is obtained by depositing a first electrode layer material on the substrate at a first sputtering rate for a first duration using magnetron sputtering.
[0038] In one possible implementation, forming a second electrode layer on the second buffer layer includes:
[0039] Photoresist is coated onto the second buffer layer and photolithography is performed to form an electrode pattern. After depositing the electrode metal, the photoresist is removed to obtain the second electrode layer; or
[0040] An electrode metal layer is deposited on the second buffer layer, and the electrode metal layer is photolithographically etched to obtain the second electrode layer.
[0041] This embodiment of the invention provides a first buffer layer between the first electrode layer and the ferroelectric layer, and a second buffer layer between the ferroelectric layer and the second electrode layer. All contact interfaces between the first electrode layer and the first buffer layer, the ferroelectric layer and the first buffer layer, the ferroelectric layer and the second buffer layer, and the second buffer layer and the second electrode layer are van der Waals interfaces. These layers are connected by van der Waals forces, which effectively suppresses dead layers at the interfaces, reduces leakage current, and improves the long-term stability of the interfaces, thereby significantly enhancing the performance of the ferroelectric capacitor.
[0042] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0043] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0044] Figure 1 A schematic diagram of the structure of a ferroelectric capacitor device according to an embodiment of the present disclosure is shown.
[0045] Figure 2 A schematic flowchart of a method for manufacturing a ferroelectric capacitor device according to an embodiment of the present disclosure is shown.
[0046] Figure 3 A schematic diagram of an evaporation coating machine is shown. Detailed Implementation
[0047] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0048] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0049] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0050] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0051] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0052] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0053] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.
[0054] Please see Figure 1 , Figure 1 A schematic diagram of the structure of a ferroelectric capacitor device according to an embodiment of the present disclosure is shown.
[0055] like Figure 1 As shown, the ferroelectric capacitor includes:
[0056] Substrate;
[0057] The first electrode layer 2 is disposed on the substrate 1;
[0058] The first buffer layer 3 is disposed on the first electrode layer 2;
[0059] Ferroelectric layer 4 is disposed on the first buffer layer 3;
[0060] The second buffer layer 5 is disposed on the ferroelectric layer 4;
[0061] The second electrode layer 6 is disposed on the second buffer layer 5.
[0062] The first buffer layer 3 and the second buffer layer 5 are made of van der Waals material. The contact interface between the first electrode layer 2 and the first buffer layer 3, the contact interface between the ferroelectric layer 4 and the first buffer layer 3, the contact interface between the ferroelectric layer 4 and the second buffer layer 5, and the contact interface between the second buffer layer 5 and the second electrode layer 6 are all van der Waals interfaces.
[0063] This embodiment of the invention provides a first buffer layer 3 between the first electrode layer 2 and the ferroelectric layer 4, and a second buffer layer 5 between the ferroelectric layer 4 and the second electrode layer 6. The contact interfaces between the first electrode layer 2 and the first buffer layer 3, the ferroelectric layer 4 and the first buffer layer 3, the ferroelectric layer 4 and the second buffer layer 5, and the second buffer layer 5 and the second electrode layer 6 are all van der Waals interfaces. These layers are connected by van der Waals forces, which effectively suppresses dead layers at the interfaces, reduces leakage current, and improves the long-term stability of the interfaces, thereby significantly enhancing the performance of the ferroelectric capacitor.
[0064] Among them, the van der Waals interface refers to the atomic-level contact surface between two layers of materials. The two layers are held together by only weak intermolecular attraction (van der Waals force), without forming strong chemical bonds, atomic diffusion, or chemical reactions. It is a clean, mild, and non-damaging interface.
[0065] The embodiments disclosed herein do not limit the thickness, material, or manufacturing method of each layer in the ferroelectric capacitor device. Those skilled in the art can set the thickness and material of each layer according to actual conditions and needs, and manufacture the ferroelectric capacitor device using appropriate processes as needed.
[0066] Please see Figure 2 , Figure 2 A schematic flowchart of a method for manufacturing a ferroelectric capacitor device according to an embodiment of the present disclosure is shown.
[0067] For example, such as Figure 2 As shown, the method described in this embodiment of the disclosure may include:
[0068] Step S11: Deposit a first electrode layer 2 on substrate 1;
[0069] Step S12: A first buffer layer 3 is grown on the first electrode layer 2 using a high-vacuum thermal evaporation process. The material of the first buffer layer 3 is van der Waals material.
[0070] Step S13: Deposit a ferroelectric layer 4 on the first buffer layer 3;
[0071] Step S14: A second buffer layer 5 is grown on the ferroelectric layer 4 using a high-vacuum thermal evaporation process. The material of the second buffer layer 5 is van der Waals material.
[0072] Step S15: A second electrode layer 6 is formed on the second buffer layer 5 to obtain the ferroelectric capacitor.
[0073] The contact interfaces between the first electrode layer 2 and the first buffer layer 3, the contact interfaces between the ferroelectric layer 4 and the first buffer layer 3, the contact interfaces between the ferroelectric layer 4 and the second buffer layer 5, and the contact interfaces between the second buffer layer 5 and the second electrode layer 6 are all van der Waals interfaces.
[0074] This embodiment of the present disclosure involves depositing a first electrode layer 2 on a substrate 1; growing a first buffer layer 3 on the first electrode layer 2 using a high-vacuum thermal evaporation process, wherein the material of the first buffer layer 3 is van der Waals material; depositing a ferroelectric layer 4 on the first buffer layer 3; growing a second buffer layer 5 on the ferroelectric layer 4 using a high-vacuum thermal evaporation process, wherein the material of the second buffer layer 5 is van der Waals material; and forming a second electrode layer 6 on the second buffer layer 5 to obtain the ferroelectric capacitor device. This method can effectively suppress interface dead layers, reduce leakage current, and improve the long-term stability of the interface, thereby effectively improving the performance of the ferroelectric capacitor device.
[0075] The material of substrate 1 is not limited in the embodiments disclosed herein. In one possible implementation, the substrate (substrate refers to the supporting substrate for growing semiconductor devices and functional thin films, and is the basic carrier for the fabrication of micro-nano electronic and optoelectronic devices) 1 can be any one of silicon, silicon dioxide, silicon nitride, silicon carbide, gallium nitride, gallium arsenide, sapphire, lanthanum strontium manganese oxide (Lanthanum strontium manganese oxide, chemical formula (La,Sr)MnO3, is a typical perovskite structure magnetoresistive material, often used as a functional layer material for magnetic sensors and electron spin-related devices), strontium titanate (Strontium titanate, chemical formula SrTiO3, is a commonly used perovskite single crystal substrate, suitable for growing various oxide functional thin films), polyimide film (polyimide, abbreviated as PI, is a high-temperature resistant and bend-resistant high-performance organic polymer, often used to prepare flexible substrates for flexible electronic devices), and mica.
[0076] The embodiments disclosed herein do not limit the specific implementation of the growth substrate 1, and those skilled in the art can set it according to actual conditions and needs.
[0077] In one possible implementation, step S11, depositing a first electrode layer 2 on the substrate 1, may include:
[0078] The first electrode layer 2 is obtained by depositing the first electrode layer 2 material on the substrate 1 at a first sputtering rate for a first duration using magnetron sputtering.
[0079] This disclosure does not limit the specific implementation of the magnetron sputtering method. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs. The core of the magnetron sputtering method is to use a magnetic field to confine high-energy electrons in the plasma, extend the electron trajectory, and significantly improve ionization efficiency and sputtering rate, so as to achieve high-quality thin film deposition at low temperature. The steps may include: introducing an inert gas (usually high-purity Ar) into a vacuum chamber, and generating plasma by breakdown after applying high voltage; the magnetic field confines electrons near the surface of the target material (such as TiN) to enhance the Ar... + Ion concentration, high-energy Ar + The target surface is continuously bombarded; target atoms / molecules are sputtered out and deposited on the surface of substrate 1 along a near-linear trajectory, gradually forming a dense thin film and finally obtaining the first electrode layer 2.
[0080] The specific materials of the first electrode layer 2 and the second electrode layer 6 in this embodiment are not limited. Those skilled in the art can select appropriate materials to make the electrodes of the ferroelectric capacitor according to the actual situation and needs. In one possible implementation, the materials of the first electrode layer 2 and the second electrode layer 6 may include any one of TiN, TaN, TiC, TaC, Au, Ag, etc.
[0081] The present invention does not limit the thickness of the first electrode layer 2 and the second electrode layer 6. Those skilled in the art can set the thickness according to the actual situation and needs. For example, the thickness of the first electrode layer 2 and the second electrode layer 6 can both be 10-50nm.
[0082] The specific value of the first sputtering rate is not limited in the embodiments disclosed herein. Those skilled in the art can set it according to actual conditions and needs. For example, in the embodiments disclosed herein, a TiN thin film can be deposited on a SiO2 / Si substrate 1 using magnetron sputtering at a first sputtering rate of 0.017 nm / s for a deposition time of about 30 min and a deposition thickness of about 30 nm.
[0083] This disclosure does not limit the specific materials of the first buffer layer 3 and the second buffer layer 5. For example, the first buffer layer 3 and the second buffer layer 5 can be made of van der Waals materials. In one possible implementation, the van der Waals material can include any one of inorganic molecular crystal materials, organic molecular crystal materials, and organic-inorganic hybrid molecular crystal materials.
[0084] The thickness of the first buffer layer 3 and the second buffer layer 5 is 1-5 nm.
[0085] For example, inorganic molecular crystal materials may include bismuth trioxide (Bi₂O₃), bismuth iodide (BiI₃), antimony trichloride (SbCl₃), antimony tribromide (SbBr₃), etc., while organic molecular crystals may include polytetrafluoroethylene (PTFE), polyvinylidene fluoride-trifluoroethylene copolymer P (VDF-TrFE), n-alkanes (such as hexadecane C), etc. 36 H 74 )wait.
[0086] For example, organic-inorganic hybrid molecular crystal materials may include aluminum octahydroxyquinoline (Alq3), two-dimensional Ruddlesden-Popper perovskites (such as phenylethylamine lead iodide PEA2PbI4), etc.
[0087] Of course, the above description of van der Waals materials is exemplary and should not be regarded as a limitation on the embodiments of this disclosure. Those skilled in the art can select appropriate materials according to actual conditions and needs.
[0088] This disclosure provides an exemplary description of possible implementations for fabricating the first buffer layer 3 and the second buffer layer 5 using bismuth trioxide (Bi2O3).
[0089] Please see Figure 3 , Figure 3 A schematic diagram of an evaporation coating machine is shown.
[0090] In one possible implementation, such as Figure 3 As shown, steps S12 and S14, which involve growing a first buffer layer 3 on the first electrode layer 2 using a high-vacuum thermal evaporation process and growing a second buffer layer 5 on the ferroelectric layer 4 using a high-vacuum thermal evaporation process, can each include:
[0091] The van der Waals material is placed in a heating container (crucible), and the heating container is heated to a first temperature;
[0092] The substrate is heated at a second temperature, wherein the substrate is disposed at the opening of the heating container, the object to be operated is placed on the substrate, the substrate is provided with an opening and closing component (baffle), the opening and closing component is configured to open or close in response to an operation signal, the object to be operated includes a device after deposition of the first electrode layer 2 or a device after deposition of the ferroelectric layer 4, and the second temperature is lower than the first temperature;
[0093] The opening and closing component is controlled to open for a preset time to grow the first buffer layer 3 or the second buffer layer 5 on the object to be operated.
[0094] The specific values of the first temperature and the second temperature are not limited in the embodiments disclosed herein. Those skilled in the art can set them according to actual conditions and needs. For example, the first temperature can be 400°C (or other temperatures of 300~500°C), and the second temperature can be 120°C (or other temperatures of 100~150°C).
[0095] For example, in this embodiment of the disclosure, a high-vacuum thermal evaporation coating system can be used for evaporation growth. If there is no molecular orientation induction during the deposition process, a polycrystalline thin film structure can be obtained. In the high-vacuum system, high-purity Sb2O3 powder is placed in a crucible and heated (400°C), and the substrate temperature is heated to 120°C. The baffle (opening and closing component) of the substrate is opened to start growth, and the coating thickness (1-5 nm) is controlled by the evaporation time.
[0096] For example, such as Figure 3 As shown, the crucible, opening and closing components, substrate, etc. are all arranged in the vacuum chamber. The crucible can be placed on the insulating support base, which is fixed to the bottom of the vacuum chamber.
[0097] It should be understood that the above description of the evaporation coating machine is exemplary and should not be regarded as a limitation on the embodiments of this disclosure. Those skilled in the art can use other evaporation coating machines according to actual conditions and needs.
[0098] The present invention does not limit the specific implementation of step S13, which involves depositing a ferroelectric layer 4 on the first buffer layer 3. Those skilled in the art can implement it by referring to relevant technologies according to actual conditions and needs.
[0099] For example, the ferroelectric layer 4 is a zirconium-doped hafnium oxide-based ferroelectric thin film (Hf). 0.5 Zr 0.5 O2 (abbreviated as HZO), with a zirconium doping content of 50%, and the ferroelectric layer thickness is 3-15nm.
[0100] For example, in an embodiment of this disclosure, a ferroelectric layer 4 can be obtained by controlling the alternating growth of HfO2 thin films and ZrO2 thin films in a 1:1 ratio during the atomic layer deposition (ALD) process on the first buffer layer 3, wherein the growth temperature can be 250°C.
[0101] In one possible implementation, a second electrode layer 6 is formed on the second buffer layer 5, including:
[0102] Photoresist is coated onto the second buffer layer 5 and photolithography is performed to form an electrode pattern. After depositing the electrode metal, the photoresist is removed to obtain the second electrode layer 6; or
[0103] An electrode metal layer is deposited on the second buffer layer 5, and the electrode metal layer is photolithographically etched to obtain the second electrode layer 6.
[0104] This disclosure does not limit the specific implementation of the process of forming the second electrode layer 6, which involves "coating photoresist on the second buffer layer 5 and performing photolithography to form an electrode pattern, depositing electrode metal, and then removing the photoresist to obtain the second electrode layer 6". Those skilled in the art can implement this process according to actual conditions and needs, referring to relevant technologies. For example, it may include: sequentially ultrasonically cleaning the substrate 1 with the second buffer layer 5 with acetone, anhydrous ethanol, and deionized water for 3-5 minutes each, and then drying it with high-purity nitrogen to remove surface organic residues and particulate matter; spin-coating positive / negative photoresist onto the surface of the second buffer layer 5 at a spin speed of 3000-5000 r / min for 30-60 s to prepare a uniform photoresist film with a thickness of 1.0-2.0 μm; placing the coated device on a hot plate and baking it at 90-110℃ for 1-2 minutes to remove the solvent from the photoresist and enhance the adhesion between the photoresist and the buffer layer; and using an ultraviolet lithography system to selectively expose the photoresist through an electrode mask. Light exposure at a dose of 10-20 mJ / cm² is used to precisely define the electrode pattern (dots, squares, interdigitated fingers, etc.). The exposed device is then immersed in a specialized developer for 30-60 seconds, development is terminated with deionized water, and the device is dried with nitrogen to form a photoresist cutout window on the buffer layer surface, consistent with the electrode pattern. The device is then baked at 90-100℃ for 30-60 seconds to reinforce the edges of the photoresist pattern and prevent pattern collapse during metal deposition. High-vacuum thermal evaporation / low-damage magnetron sputtering is then used to create the cutout window. Electrode metal (Au / Pt / Ag) is deposited simultaneously on the window and photoresist surface, with a deposition thickness of 50-100 nm. The entire process is carried out at low temperature (≤100℃) to avoid damaging the buffer layer. The device is immersed in acetone solution for 5-10 min with ultrasonic oscillation, and the photoresist and the metal layer on its surface are simultaneously stripped, leaving only the electrode metal in the cutout window of the buffer layer. The residual stripping solution is washed with anhydrous ethanol and deionized water in sequence, and then dried with high-purity nitrogen to obtain a patterned, undamaged second electrode layer 6.
[0105] This disclosure does not limit the specific implementation of "depositing an electrode metal layer on the second buffer layer 5 and performing photolithography etching on the electrode metal layer to obtain the second electrode layer 6". Those skilled in the art can implement it according to actual conditions and needs, referring to relevant technologies. For example, it may include: using magnetron sputtering / thermal evaporation to deposit a dense electrode metal layer (TiN / TaN / Au) over the entire surface of the second buffer layer 5, with a deposition thickness of 50-100 nm, covering the entire surface of the buffer layer; performing plasma cleaning (low power, ≤50W) on the entire surface of the metal layer to remove surface contaminants and enhance the adhesion of the photoresist; and spin-coating photoresist onto the surface of the electrode metal layer, with spin-coating parameters and soft baking process (as described above). After UV exposure, development, and hardening, an electrode protection pattern is formed on the photoresist (the photoresist-covered area is the retained electrode, and the uncovered area is the metal to be etched); wet etching (using a special etching solution for the corresponding metal (ammonia-hydrogen peroxide system for TiN, iodine-ethanol system for Au), low-temperature etching for 10-30s to remove excess metal without photoresist protection) or dry etching (using reactive ion etching (RIE), low power, low gas pressure etching, strictly controlling the etching endpoint to avoid etching damage to the underlying second buffer layer 5); the device is immersed in acetone / resist remover to remove the remaining photoresist on the surface, and then cleaned with deionized water; high-purity nitrogen is used to dry it, resulting in a well-patterned second electrode layer 6 that is tightly bonded to the buffer layer.
[0106] Of course, the above description of forming the second electrode layer 6 is exemplary and should not be regarded as a limitation on the embodiments of this disclosure. In other embodiments, those skilled in the art can form the second electrode layer 6 in other ways according to the actual situation and needs, referring to relevant technologies.
[0107] It is worth noting that, after forming the second electrode layer 6, the embodiments of this disclosure may also include other process steps, such as an annealing step, in which rapid annealing is performed under a nitrogen atmosphere at an annealing temperature of 400-750°C, an annealing time of 10-60s, a heating rate of 15-60°C / s, and a cooling rate of 10-60°C / s, so as to crystallize the ferroelectric thin film and obtain ferroelectric properties.
[0108] This embodiment introduces a molecular crystal thin film as a buffer layer between the electrode and the ferroelectric layer 4, achieving weak and dense van der Waals (vdW) interactions and interfaces between each layer. This results in a capacitor structure where all components are connected by van der Waals forces, avoiding strong chemical bonds and atomic diffusion. At the same time, the high-quality tunneling barrier constructed in this way eliminates defect-assisted leakage mechanisms. This is a manufacturing strategy that solves traditional interface problems and device reliability problems from the "atomic manufacturing" level.
[0109] The ferroelectric capacitor device of this disclosure can suppress interfacial chemical reactions, reduce defect density, and buffer interfacial stress, thereby improving the stability of residual polarization retention in the ferroelectric layer 4, reducing switching voltage, reducing leakage current, and extending device fatigue life. This invention can be applied to non-volatile memories, ferroelectric field-effect transistors, ferroelectric logic devices, and other fields.
[0110] The technical solution of the present invention has the following beneficial technical effects:
[0111] The first buffer layer 3 and the second buffer layer 5 are "attached" to the ferroelectric layer 4 and the electrode through weak van der Waals forces, thus avoiding strong chemical bonding and atomic diffusion.
[0112] The integrity of the surface atoms of the ferroelectric layer 4 and its intrinsic ferroelectricity were preserved, and the "dead layer" was almost eliminated.
[0113] The molecular crystal layer (first buffer layer 3, second buffer layer 5) is usually a good insulator or a wide bandgap semiconductor, which can serve as a high-quality tunneling barrier to effectively block charge from being injected directly into the ferroelectric layer 4 from the electrode.
[0114] The vdW interface itself is very "clean" and has no defect states generated by chemical reactions, thus fundamentally eliminating defect-assisted leakage mechanisms.
[0115] At the same time, the effects of charge trapping and domain wall pinning are greatly weakened;
[0116] During polarization switching, ferroelectric capacitors experience less electrochemical stress at the interface, thus greatly extending the device's read / write endurance and allowing it to withstand more switching cycles, meeting the requirements of high-reliability storage applications.
[0117] A "clean" vdW interface also reduces the sources of trapped charges that can generate a stable built-in electric field, making polarization reversals in the positive and negative directions more symmetrical, effectively suppressing the imprinting effect, and ensuring the long-term stability and distinguishability of the "0" and "1" states.
[0118] It should be understood that in related technologies, once the work function of the electrode and the band structure of the ferroelectric layer 4 are determined, the band alignment of the interface is essentially fixed and difficult to optimize. However, the molecular crystal scheme (first buffer layer 3, second buffer layer 5) of this disclosure can be selected from organic molecules or other inorganic molecular units with different dipole moments or energy levels. These molecular layers can introduce an additional electric dipole layer between the electrode and the ferroelectric layer 4, thereby modulating the effective work function and optimizing the band alignment. This provides great flexibility for designing devices with specific functions (such as ferroelectric tunnel junctions that enhance the tunneling electroresistivity effect).
[0119] It should be understood that inorganic ferroelectric materials are typically rigid and prone to stress concentration at the interface, leading to cracking or failure when bent. The molecular crystal layers (first buffer layer 3, second buffer layer 5) of this disclosure possess inherent flexibility and can serve as stress buffer layers, effectively releasing the mechanical stress generated during device bending and protecting the function of the ferroelectric layer 4. This makes it possible to construct high-performance flexible, wearable ferroelectric memories and sensors.
[0120] In summary, the embodiments of this disclosure introduce van der Waals interfaces constructed from molecular crystals into ferroelectric capacitor devices, which is a revolutionary strategy to solve traditional interface problems from the "atomic manufacturing" level. By constructing an atomically flat, chemically inert, and defect-free "perfect" interface, the embodiments of this disclosure can comprehensively improve the core performance indicators of the device.
[0121] According to another aspect of this disclosure, a semiconductor module is provided, the semiconductor module including the aforementioned ferroelectric capacitor element.
[0122] The embodiments disclosed herein do not limit the specific type of semiconductor module. Those skilled in the art can set it according to actual conditions and needs. For example, the semiconductor module may include a sensor module, a memory module, etc.
[0123] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the semiconductor module described above.
[0124] This disclosure does not limit the specific type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include terminal devices and servers. The terminal device may be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.
[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0126] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A ferroelectric capacitor device, characterized by, The ferroelectric capacitor includes: Substrate; A first electrode layer is disposed on the substrate; A first buffer layer is disposed on the first electrode layer; A ferroelectric layer is disposed on the first buffer layer; A second buffer layer is disposed on the ferroelectric layer; The second electrode layer is disposed on the second buffer layer. The first buffer layer and the second buffer layer are made of van der Waals material, and the contact interfaces between the first electrode layer and the first buffer layer, the ferroelectric layer and the first buffer layer, the ferroelectric layer and the second buffer layer, and the second buffer layer and the second electrode layer are all van der Waals interfaces.
2. The ferroelectric capacitor device according to claim 1, characterized in that, The materials of the first electrode layer and the second electrode layer include any one of TiN, TaN, TiC, TaC, Au, and Ag. The thickness of both the first electrode layer and the second electrode layer is 10-50 nm.
3. The ferroelectric capacitor device according to claim 1, characterized in that, The van der Waals materials include any one of inorganic molecular crystal materials, organic molecular crystal materials, and organic-inorganic hybrid molecular crystal materials. The thickness of both the first buffer layer and the second buffer layer is 1-5 nm.
4. The ferroelectric capacitor device according to claim 1, characterized in that, The substrate is any one of silicon, silicon dioxide, silicon nitride, silicon carbide, gallium nitride, gallium arsenide, sapphire, lanthanum strontium manganese oxide, strontium titanate, polyimide film, and mica; The ferroelectric layer is a zirconium-doped hafnium oxide-based ferroelectric thin film with a thickness of 3-15 nm.
5. A semiconductor module, characterized in that, The semiconductor module includes a ferroelectric capacitor as described in any one of claims 1-4.
6. An electronic device, characterized in that, The electronic device includes the semiconductor module as described in claim 5.
7. A method for manufacturing a ferroelectric capacitor, characterized in that, The method includes: A first electrode layer is deposited on the substrate; A first buffer layer is grown on the first electrode layer using a high-vacuum thermal evaporation process, and the material of the first buffer layer is van der Waals material. A ferroelectric layer is deposited on the first buffer layer; A second buffer layer is grown on the ferroelectric layer using a high-vacuum thermal evaporation process, and the material of the second buffer layer is van der Waals material. A second electrode layer is formed on the second buffer layer to obtain the ferroelectric capacitor device. Wherein, the contact interface between the first electrode layer and the first buffer layer, the contact interface between the ferroelectric layer and the first buffer layer, the contact interface between the ferroelectric layer and the second buffer layer, and the contact interface between the second buffer layer and the second electrode layer are all van der Waals interfaces.
8. The method according to claim 7, characterized in that, The process of growing a first buffer layer on the first electrode layer using a high-vacuum thermal evaporation process and growing a second buffer layer on the ferroelectric layer using a high-vacuum thermal evaporation process both include: The van der Waals material is placed in a heating container, and the heating container is heated to a first temperature; The substrate is heated at a second temperature, wherein the substrate is disposed at the opening of the heating container, the object to be operated is placed on the substrate, the substrate is provided with an opening and closing component, the opening and closing component is configured to open or close in response to an operation signal, the object to be operated includes a device after deposition of a first electrode layer or a device after deposition of a ferroelectric layer, and the second temperature is lower than the first temperature. The opening and closing component is controlled to open for a preset time to grow the first buffer layer or the second buffer layer on the object to be operated.
9. The method according to claim 7, characterized in that, The deposition of the first electrode layer on the substrate includes: The first electrode layer is obtained by depositing a first electrode layer material on the substrate at a first sputtering rate for a first duration using magnetron sputtering.
10. The method according to claim 7, characterized in that, A second electrode layer is formed on the second buffer layer, including: Photoresist is coated onto the second buffer layer and photolithography is performed to form an electrode pattern. After depositing the electrode metal, the photoresist is removed to obtain the second electrode layer; or An electrode metal layer is deposited on the second buffer layer, and the electrode metal layer is photolithographically etched to obtain the second electrode layer.