A method for manufacturing a vertical structure insulated gate heterojunction transistor and the transistor

Abstract

This invention provides a method for fabricating a vertical-structure insulated-gate heterojunction transistor and the transistor itself. The method includes: providing and cleaning a substrate; epitaxially growing an N-type Ga2O3 drift layer on the substrate; forming trenches in the N-type Ga2O3 drift layer and filling the trenches with a P-type semiconductor material; planarizing the filled surface and sequentially epitaxially growing an N-type Ga2O3 capping layer and a P-type AlN capping layer; forming a sidewall structure on the P-type AlN capping layer; and using the sidewall structure as a mask to form an N-type Ga2O3 capping layer. + Heavily doped source region; deposit gate dielectric layer on the entire surface including sidewall structure; form N-doped source region; + The source region, gate dielectric layer, and source, gate, and drain electrodes are electrically connected to the back side of the substrate. This enables the fabrication of a vertically structured insulated-gate heterojunction transistor that requires no high-temperature annealing, boasts excellent interface quality, and offers good process compatibility, fundamentally overcoming the inherent limitations of ion implantation technology.

Description

Technical Field

[0001] This invention relates to the field of ultra-wide bandgap semiconductor power device technology, specifically to a method for fabricating a vertical structure insulated gate heterojunction transistor and the transistor itself. Background Technology

[0002] Aluminum nitride (AlN), as a representative of ultra-wide bandgap semiconductors, boasts a bandgap of approximately 6.1 eV, a theoretical critical breakdown electric field as high as 15 MV / cm, and excellent thermal conductivity. Its theoretical performance far surpasses that of traditional silicon (Si), silicon carbide (SiC), and gallium nitride (GaN), demonstrating immense potential in high-voltage, high-temperature, and high-power-density power electronics applications. In particular, AlN-based vertical-structure insulated-gate heterojunction transistors combine the high mobility of the two-dimensional electron gas channel of a heterojunction with the ease of high-voltage blocking in a vertical structure, making them considered one of the ideal architectures for realizing next-generation high-performance power switches. However, a significant gap remains between the actual device performance of AlN materials and their theoretical limits. Currently, reliable devices simultaneously possessing high current density, high breakdown voltage, and large size are lacking. This gap primarily stems from core challenges such as material epitaxial quality, effective control of the heterojunction-dielectric interface states, and reliable management of the device's edge electric field. One of the fundamental technical bottlenecks is that AlN lacks an efficient and reliable p-type doping process, which makes it difficult to adopt the pn junction-based termination protection structure that is maturely used in Si or SiC power devices. This severely restricts the realization and stability of the breakdown voltage of AlN-based vertical devices.

[0003] In existing technologies, a proposed approach to achieve electrical isolation and low-resistance ohmic contacts in AlN-based vertical transistors is the use of a "dual ion implantation method." The main process steps of this method include: first, ion implantation of acceptor impurities (such as magnesium or carbon) in specific regions between the active regions of the device to form lateral electrical isolation, i.e., a current blocking layer; subsequently, shallow, high-dose donor impurity ion implantation (such as silicon) at the designed source region locations to form heavily doped n+ regions, thus creating conditions for the fabrication of source ohmic contacts.

[0004] However, the aforementioned existing ion implantation-based technologies have inherent and serious drawbacks, with the core issue being the "high-temperature annealing" process necessary for impurity activation. First, to electrically activate the implanted silicon ions and repair lattice damage, extremely high temperatures (typically exceeding 1500°C) are required for annealing. Under this extreme thermal condition, the pre-implanted acceptor impurities (such as magnesium or carbon) undergo significant longitudinal and lateral thermal diffusion, causing the precisely designed current-blocking junction profile to become blurred or even fail. This creates parasitic leakage paths between the source and drain of the device, deteriorating its isolation characteristics and drastically reducing its breakdown voltage. Second, such a high-temperature process severely damages the interface quality of AlN-based heterojunctions (e.g., AlGaN / AlN), leading to inter-atomic mixing, increased roughness, and the generation of new defects. This results in a significant degradation of the areal density and electron mobility of the two-dimensional electron gas channel, fundamentally weakening the device's conduction and frequency characteristics. Finally, this process route has extremely stringent requirements for the thermal stability of the material system, and is inherently incompatible with AlN-based heterojunction epitaxial structures that are extremely sensitive to high temperatures, resulting in a narrow process window and difficulty in guaranteeing device performance and reliability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method for fabricating a vertical structure insulated gate heterojunction transistor and the transistor itself.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a vertical structure insulated gate heterojunction transistor, comprising: S1. Provide and clean the substrate; S2. Epitaxial growth of an N-type Ga2O3 drift layer on the substrate; S3. A trench is formed in the N-type Ga2O3 drift layer and the trench is filled with a P-type semiconductor material; S4. The filled surface is planarized, and an N-type Ga2O3 capping layer and a P-type AlN capping layer are epitaxially grown sequentially. S5. Form a sidewall structure on the P-type AlN capping layer, and use the sidewall structure as a mask to form N-type Ga2O3 capping layer. + Heavily doped source region; S6. Deposit a gate dielectric layer on the entire surface including the sidewall structure; S7. Formed separately with N + The heavily doped source region, the gate dielectric layer, and the source, gate, and drain electrodes electrically connected to the back side of the substrate.

[0007] In a second aspect, the present invention provides a vertical structure insulated gate heterojunction transistor, comprising: Substrate; An N-type Ga2O3 drift layer disposed on a substrate; Multiple trenches are formed in the N-type Ga2O3 drift layer, and the trenches are filled with P-type semiconductor material; An N-type Ga2O3 capping layer and a P-type AlN capping layer are sequentially stacked on top of an N-type Ga2O3 drift layer and a P-type semiconductor material. A sidewall structure that penetrates the P-type AlN cap layer and extends into part of the N-type Ga2O3 cap layer; Located at the bottom of the sidewall structure, N formed in the N-type Ga2O3 capping layer + Heavily doped source region; A grid dielectric layer covering the surface of the sidewall structure; and, With N + The source, gate, and drain are electrically connected to the heavily doped source region, the gate dielectric layer, and the back side of the substrate, respectively.

[0008] This invention provides a method for fabricating a vertical-structure insulated-gate heterojunction transistor and the transistor itself. The method for fabricating the vertical-structure insulated-gate heterojunction transistor includes: providing and cleaning a substrate 1; epitaxially growing an N-type Ga2O3 drift layer 2 on the substrate 1; forming a trench 3 in the N-type Ga2O3 drift layer 2 and filling the trench 3 with a P-type semiconductor material; planarizing the filled surface and sequentially epitaxially growing an N-type Ga2O3 capping layer 4 and a P-type AlN capping layer 5; forming a sidewall structure on the P-type AlN capping layer 5, and using the sidewall structure as a mask, forming an N-type Ga2O3 capping layer 4... + 7. Heavily doped source region; 8. Gate dielectric layer 8 deposited on the entire surface including the sidewall structure; forming N-doped source region 7; +The heavily doped source region 7, the gate dielectric layer 8, and the source 9, gate 10, and drain 11 are electrically connected to the back side of the substrate 1. In this invention, firstly, a current blocking region is formed by filling a trench with P-type semiconductor material, replacing the ion implantation process requiring high-temperature annealing in existing technologies. This avoids extreme heat treatment exceeding 1500°C and solves the problems of blurred junction contours, parasitic leakage current, and reduced breakdown voltage caused by impurity thermal diffusion. Secondly, since the entire fabrication process (epitaxy growth, planarization, deposition, etc.) is carried out at lower or controllable temperatures, no high-temperature annealing step is required, protecting the heterojunction interface quality between the P-type AlN cap layer and the N-type Ga2O3 capping layer. This solves the problems of interface atomic mixing, increased roughness, and degradation of the two-dimensional electron gas channel performance. Finally, based on the more thermally stable Ga2O3 material system, the AlN-based heterojunction, which is extremely sensitive to high temperatures, is replaced, and it is compatible with milder processes, reducing the stringent requirements for material thermal sensitivity. This resolves the contradiction between a narrow process window and the difficulty in guaranteeing device performance and reliability. In summary, the fabrication of vertical insulated gate heterojunction transistors with excellent interface quality and good process compatibility without high-temperature annealing has been achieved, fundamentally overcoming the inherent defects of existing ion implantation technology.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1 A schematic flowchart illustrating a method for fabricating a vertical structure insulated gate heterojunction transistor according to an embodiment of the present invention; Figure 2 Exemplary transistor device structure diagrams corresponding to each fabrication process are shown; Figure 3 An exemplary schematic diagram of a vertical insulated gate heterojunction transistor is shown. Detailed Implementation

[0011] To address the aforementioned problems in existing technologies, the "vertical structure insulated gate heterojunction transistor" proposed in this invention employs a novel device architecture and integration process, and its main advantages are: Avoiding high-temperature injection activation: By employing selective epitaxial growth, low-temperature passivation / dielectric deposition, or innovative in-situ doping processes, high-quality current blocking layers and low-resistivity source region contacts can be directly formed without the need for subsequent extreme high-temperature annealing, fundamentally avoiding doping diffusion and interface thermal damage problems.

[0012] Optimize electric field management and termination: By integrating field plates, junction termination extensions, or etching mesa structures, the electric field distribution at the device edge, especially in the gate and drain corner regions, can be effectively modulated. This compensates for the lack of p-type doping in AlN, which makes it difficult to form traditional pn junction terminations, thereby fully leveraging the potential of AlN material for high breakdown electric field and improving the actual breakdown voltage of the device.

[0013] Improved interface characteristics and reliability: By introducing a composite interface layer, surface passivation, and optimized gate stack, the interface state density between the heterojunction channel and the gate dielectric / passivation layer is significantly reduced, enhancing the stability and gate control efficiency of the two-dimensional electron gas channel, while improving the long-term operational reliability of the device.

[0014] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0015] In order to overcome the inherent defects of existing ion implantation technology from the root, this invention provides a method for fabricating a vertical structure insulated gate heterojunction transistor. Figure 1 This is a schematic flowchart illustrating a method for fabricating a vertical-structure insulated-gate heterojunction transistor according to an embodiment of the present invention. Figure 1 As shown, it includes: S1. Provide and clean the substrate.

[0016] This invention employs a standard RCA process to clean a p-type AlN substrate 1, removing organic and inorganic contaminants and metal ions. Finally, a short rinse with diluted HF solution removes the natural oxide layer on the surface, resulting in an atomically clean surface.

[0017] Objective: To provide a clean substrate surface for high-quality epitaxial growth and ensure interface quality.

[0018] S2. An N-type Ga2O3 drift layer is epitaxially grown on the substrate.

[0019] In this step, an MOCVD apparatus is used to epitaxially grow an N-type Ga₂O₃ drift layer 2 on a cleaned P-type AlN substrate 1. The growth temperature is approximately 1050°C, and the required n-type doping concentration (typically 1e¹⁶ cm⁻¹) is achieved by controlling the SiH₄ flow rate. - (On the order of 3), the thickness is designed according to the target breakdown voltage (e.g., 10-15 µm).

[0020] Objective: To form the main drift region of the device that can withstand high voltages, the thickness and doping concentration of which determine the basic breakdown voltage.

[0021] S3. A trench is formed in the N-type Ga2O3 drift layer and the trench is filled with a P-type semiconductor material.

[0022] Optionally, S3 includes: S31. A groove pattern is formed on the surface of the N-type Ga2O3 drift layer 2; S32. Using a dry etching process, grooves 3 are formed by etching according to the groove pattern; S33. P-type semiconductor material is filled into trench 3 by selective epitaxial growth process.

[0023] Optionally, in S33, the P-type semiconductor material is P-type AlN, and the selective epitaxial growth process is metal-organic chemical vapor deposition.

[0024] Figure 2 Exemplary transistor device structure diagrams corresponding to each fabrication process are shown. Figure 2 Figure (a) exemplarily shows the transistor device structure diagram following S3.

[0025] In this step, photoresist is spin-coated onto the surface of the N-type Ga2O3 drift layer 2, and then exposed and developed to form a trench array pattern. Cl2 / BCl3-based ICP dry etching is used to precisely etch the N-type Ga2O3 drift layer 2, forming trenches with controllable depth (e.g., 1.5 µm) and steep sidewalls, and then the photoresist is removed.

[0026] Objective: To define the region for subsequent filling with P-type material, which is key to forming a three-dimensional charge-compensated structure (superjunction concept).

[0027] Next, selective epitaxial growth is performed using MOCVD or MBE. Growth conditions are optimized (such as lower temperature and specific precursor ratio) so that P-type AlN (with Mg doping) grows only on the exposed bottom of the trench (AlN substrate) and sidewalls, and does not grow laterally overgrown on the top of the N-type Ga2O3 drift layer 2 mesa until the trench is completely filled.

[0028] Objective: To form periodic P-type AlN pillars in the N-type Ga2O3 drift layer 2. These P pillars, together with the N-type Ga2O3 drift layer 2, provide charge compensation, which optimizes the lateral electric field distribution and significantly improves the device breakdown voltage.

[0029] S4. The filled surface is planarized, and an N-type Ga2O3 capping layer and a P-type AlN capping layer are epitaxially grown sequentially.

[0030] In this step, chemical mechanical polishing is first performed to remove the P-type AlN overflowing above the trench 3, thereby planarizing the surface globally and exposing the mesa of the N-type Ga2O3 drift layer 2 and the filled AlN trenches. In the same epitaxial apparatus, a thin N-type Ga2O3 capping layer 4 (thickness ~0.5 µm) is epitaxially grown on the planarized surface.

[0031] The purpose of this step is to obtain a smooth surface for subsequent processes; and to prepare the thin capping layer for the formation of channels and gate control areas.

[0032] Next, a p-type AlN cap layer 5 is epitaxially grown. Specifically, a thin p-type AlN cap layer 5 (~100 nm) is epitaxially grown on the n-type Ga2O3 capping layer 4 at a low temperature (~900°C). The Mg doping concentration is precisely controlled.

[0033] The purpose of this process is that the P-type AlN cap layer 5 will serve as part of the gate control or current blocking layer of the device, forming a pn junction with the underlying N-type Ga2O34.

[0034] Figure 2 Figures (b) and (c) exemplarily illustrate the transistor device structure diagrams following S4. Figure 2 Figure (b) is a schematic diagram of the structure after the growth of the N-type Ga2O3 capping layer (4). Figure 2 Figure (c) is a schematic diagram of the structure after the growth of the P-type AlN cap layer (5).

[0035] S5. Form a sidewall structure on the P-type AlN capping layer, and use the sidewall structure as a mask to form N-type Ga2O3 capping layer. + Heavily doped source region.

[0036] Optionally, S5 includes: S51. A SiO2 deposition layer 6 is deposited on the P-type AlN cap layer 5, and the SiO2 deposition layer 6, the underlying P-type AlN cap layer 5, and part of the N-type Ga2O3 capping layer 4 are patterned and etched to form a sidewall structure. S52. Using the sidewall structure as a mask, ion implantation is performed on the exposed N-type Ga2O3 capping layer 4 to form N + Heavy doped source region 7.

[0037] Optionally, after S5, the fabrication method of the vertical structure insulated gate heterojunction transistor further includes: Remove the SiO2 deposit layer 6 and treat N + The heavily doped source region 7 is activated by high-temperature annealing.

[0038] Optionally, the high-temperature annealing activation is a rapid thermal annealing performed in a nitrogen atmosphere, with an annealing temperature of not less than 1200°C.

[0039] Optionally, in S52, ion implantation is silicon ion implantation.

[0040] In step S5, plasma-enhanced chemical vapor deposition is first used to deposit a uniformly thick SiO2 thin film, namely SiO2 deposition layer 6 (~150 nm), at ~300°C. This treatment can serve as a hard mask for subsequent sidewall etching and protect the active region.

[0041] Next, photolithography defines the source contact window region. Reactive ion etching is used, with photoresist as a mask, to first etch the SiO2 deposition layer 6. Then, using SiO2 deposition layer 6 as a hard mask, the underlying P-type AlN cap layer 5 and part of the N-type Ga2O3 capping layer 4 are etched downwards to form the sidewall structure. This process defines the sidewall positions of the future channel, forming the mesa or trench gate structure of the device, providing a window for subsequent ion implantation and source contact.

[0042] Then, using the sidewall structure formed in the previous step as a mask, Si ion implantation was performed. The implantation energy and dose were designed to ensure the formation of a high concentration of N in the N-type Ga2O3 capping layer 4 at the bottom of the sidewall. + Heavy doped source region 7. This process can form a heavily doped source region at a predetermined location to reduce the ohmic contact resistance of the subsequent source metal.

[0043] Finally, the SiO2 deposited layer on the surface is completely removed using a buffered oxide etchant or dry etching. Rapid thermal annealing (temperature ~1200°C, time ~30 seconds) is then performed in an N2 atmosphere. This high-temperature process is used to repair ion implantation damage and activate implanted Si impurities, forming effective N2 deposits. + Heavy doped source region 7.

[0044] Figure 2 Figure (d) exemplarily shows the structure of a transistor device after the deposition of SiO2 deposition layer 6. Figure 2 Figure (e) shows the structure of the transistor device after the sidewall structure has been etched. Figure 2 Figure (f) shows the formation of N. + The transistor device structure diagram following the heavily doped source region 7.

[0045] S6. Deposit a grid dielectric layer on the entire surface including the sidewall structure.

[0046] In step S6, atomic layer deposition (ALD) is used to deposit a high-quality, high-k dielectric Al2O3 layer on the entire surface of the sample at ~300°C, forming the gate dielectric layer 8. The gate dielectric layer (8) has a thickness of approximately 20-30 nm. The ALD process ensures the formation of a uniform, dense film with low interface states on the surface of complex sidewall structures.

[0047] Furthermore, in some other embodiments, other high-k dielectrics can be used instead of Al2O3 materials, as long as the material can achieve the same technical effect as this invention. Alternatively, N-type and P-type multilayer structures can be directly epitaxially grown alternately on the substrate, and then the device units are defined by deep etching of the mesa. The mesa sidewalls naturally form a columnar structure with alternating PN phases. "Multilayer epitaxy + mesa etching" is an alternative technical path for realizing "superjunction" devices and is considered an alternative structure.

[0048] Figure 2 Figure (g) exemplarily illustrates the structure of a transistor device after the deposition of the gate dielectric layer 8.

[0049] S7. Formed separately with N + The heavily doped source region, the gate dielectric layer, and the source, gate, and drain electrodes electrically connected to the back side of the substrate.

[0050] Figure 2 The (h) diagram exemplarily illustrates the transistor device structure after the deposition of source electrode 9. Figure 2 Figure (i) exemplarily illustrates a transistor device structure diagram after the deposition of gate 10 and drain 11.

[0051] In step S7, source contact holes are defined by photolithography, and Al2O3 in the area is removed by dry etching. A Ti / Al / Ni / Au multilayer metal is deposited, and after stripping, it undergoes rapid thermal annealing to form a low-resistance ohmic contact. Next, the gate region is defined by photolithography, and Ni / Au is deposited as the gate electrode. Finally, the back side of the wafer is thinned and polished, and Ni / Au metal is deposited on the entire back side of the P-type AlN substrate. After medium-temperature annealing, a reliable ohmic contact is formed on the back side of the P-type AlN substrate, completing the fabrication of all electrodes of the device and realizing electrical connection.

[0052] This invention provides a method for fabricating a vertical-structure insulated-gate heterojunction transistor. First, a current-blocking region is formed by filling a trench with P-type semiconductor material, replacing the ion implantation process requiring high-temperature annealing in existing technologies. This avoids extreme heat treatment exceeding 1500°C and solves the problems of blurred junction profiles, parasitic leakage, and reduced breakdown voltage caused by impurity thermal diffusion. Second, since the entire fabrication process (epitaxy growth, planarization, deposition, etc.) is performed at lower or controllable temperatures, a high-temperature annealing step is unnecessary, protecting the heterojunction interface quality between the P-type AlN cap layer and the N-type Ga2O3 capping layer. This solves the problems of interfacial atomic mixing, increased roughness, and degradation of the two-dimensional electron gas channel performance. Finally, based on the more thermally stable Ga2O3 material system, the high-temperature-sensitive AlN-based heterojunction is replaced, and the method is compatible with milder processes, reducing the stringent requirements for material thermal sensitivity. This resolves the contradiction between a narrow process window and the difficulty in guaranteeing device performance and reliability. In summary, this invention enables the fabrication of vertical structure insulated gate heterojunction transistors that do not require high-temperature annealing, have excellent interface quality, and good process compatibility, thus overcoming the inherent defects of existing ion implantation technology from the root.

[0053] This corresponds to a method for fabricating a vertically structured insulated-gate heterojunction transistor. Figure 3 An exemplary schematic diagram of a vertically structured insulated-gate heterojunction transistor is shown, such as... Figure 3 As shown, it includes: Substrate 1; N-type Ga2O3 drift layer 2 disposed on substrate 1; Multiple trenches 3 are formed in the N-type Ga2O3 drift layer 2, and the trenches 3 are filled with P-type semiconductor material; An N-type Ga2O3 capping layer 4 and a P-type AlN capping layer 5 are sequentially stacked on top of an N-type Ga2O3 drift layer 2 and a P-type semiconductor material; A sidewall structure that penetrates the P-type AlN cap layer 5 and extends into part of the N-type Ga2O3 capping layer 4; Located at the bottom of the sidewall structure, N formed in the N-type Ga2O3 capping layer + Heavy doped source region 7; A grid dielectric layer 8 covering the surface of the sidewall structure; and, With N + The source region 7, the gate dielectric layer 8, and the back side of the substrate 1 are electrically connected to the source 9, the gate 10, and the drain 11, respectively.

[0054] Optionally, the P-type semiconductor material filled in the trench 3 is P-type AlN.

[0055] Optionally, the gate dielectric layer 8 is made of Al2O3.

[0056] In summary, the innovation of this invention lies in: 1. A vertical heterostructure of "P-type AlN substrate + N-type Ga2O3 drift layer" is adopted. The ultra-wide bandgap and ultra-high theoretical breakdown field strength of AlN (~6.1 eV) far exceeding those of GaN (~3.4 eV) provide the underlying material foundation for achieving the ultimate breakdown voltage of the device. Simultaneously, the high thermal conductivity of AlN (~300 W / m·K) greatly improves the heat dissipation capability of the device.

[0057] 2. By etching and epitaxially filling P-type AlN in the N-type Ga2O3 drift layer to form a three-dimensional trench array, a charge balance region similar to a "superjunction" was constructed. This alternating vertical structure of "Ga2O3 n pillars" and "AlN p pillars" can optimize the lateral electric field from a triangular distribution to a rectangular distribution, thereby significantly reducing the specific on-resistance of the drift region under the same breakdown voltage, approaching the material limit.

[0058] 3. On a P-type AlN cap / cover layer, sidewalls are formed by etching and a high-k dielectric (Al₂O₃) is deposited as the gate, achieving fully depleted insulated gate control. This structure can effectively modulate the channel, resulting in higher switching speeds and lower gate leakage current. The sidewall structure is used as a self-aligned mask for N-type AlN control. + Ion implantation forms the source region, ensuring precise alignment between the gate and the source region and reducing parasitic capacitance.

[0059] 4. Avoids high-temperature ion implantation annealing: The core P-type region (trench filling) and N-type drift layer are both achieved through epitaxial growth, rather than ion implantation. Ion implantation is only used in the shallow source region, and can be activated by subsequent optimized rapid thermal annealing, fundamentally avoiding the problems of Mg diffusion and heterojunction interface degradation caused by high temperature in traditional dual implantation.

[0060] 5. Selective epitaxial growth of P-type AlN in Ga2O3 trenches is the key to achieving a high-quality PN interface and ensures the charge compensation effect.

[0061] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0062] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In this description, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the inventive concept, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a vertical-structure insulated-gate heterojunction transistor, characterized in that, include: S1. Provide and clean the substrate (1); S2. An N-type Ga2O3 drift layer (2) is epitaxially grown on the substrate (1); S3. A trench (3) is formed in the N-type Ga2O3 drift layer (2) and the trench (3) is filled with a P-type semiconductor material; S4. The filled surface is planarized, and an N-type Ga2O3 capping layer (4) and a P-type AlN capping layer (5) are epitaxially grown sequentially. S5. A sidewall structure is formed on the P-type AlN cap layer (5), and using the sidewall structure as a mask, N-type Ga2O3 capping layer (4) is formed. + Heavy doped source region (7); S6. Deposit a grid dielectric layer (8) on the entire surface containing the sidewall structure; S7. Forming respectively with the N + The heavily doped source region (7), the gate dielectric layer (8), and the back side of the substrate (1) are electrically connected to the source (9), gate (10), and drain (11).

2. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 1, characterized in that, S3 include: S31. A groove pattern is formed on the surface of the N-type Ga2O3 drift layer (2); S32. Using a dry etching process, the grooves (3) are formed by etching according to the groove pattern; S33. P-type semiconductor material is filled into the trench (3) by selective epitaxial growth process.

3. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 2, characterized in that, In S33, the P-type semiconductor material is P-type AlN, and the selective epitaxial growth process is metal-organic chemical vapor deposition.

4. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 1, characterized in that, S5 include: S51. Deposit a SiO2 deposition layer (6) on the P-type AlN cap layer (5), pattern and etch the SiO2 deposition layer (6) and the underlying P-type AlN cap layer (5) and part of the N-type Ga2O3 capping layer (4) to form the sidewall structure; S52. Using the sidewall structure as a mask, ion implantation is performed on the exposed N-type Ga2O3 capping layer (4) to form the N-type Ga2O3 capping layer. + Heavy doped source region (7).

5. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 4, characterized in that, Following S5, the method for fabricating the vertical structure insulated gate heterojunction transistor further includes: Remove the SiO2 deposited layer (6) and treat the N + The heavily doped source region (7) is activated by high-temperature annealing.

6. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 5, characterized in that, The high-temperature annealing activation is a rapid thermal annealing performed in a nitrogen atmosphere, with an annealing temperature of not less than 1200°C.

7. The method for fabricating a vertical structure insulated gate heterojunction transistor according to claim 4, characterized in that, In S52, the ion implantation is silicon ion implantation.

8. A vertically structured insulated-gate heterojunction transistor, characterized in that, include: Substrate (1); An N-type Ga2O3 drift layer (2) is disposed on the substrate (1); Multiple trenches (3) are formed in the N-type Ga2O3 drift layer (2), and the trenches (3) are filled with P-type semiconductor material; An N-type Ga2O3 capping layer (4) and a P-type AlN capping layer (5) are sequentially stacked on the N-type Ga2O3 drift layer (2) and the P-type semiconductor material; The sidewall structure extends through the P-type AlN cap layer (5) and into part of the N-type Ga2O3 cap layer (4); Located at the bottom of the sidewall structure, N formed in the N-type Ga2O3 capping layer + Heavy doped source region (7); A grid dielectric layer (8) covering the surface of the sidewall structure; and, With the N + The source (9), gate (10), and drain (11) are electrically connected to the heavily doped source region (7), the gate dielectric layer (8), and the back side of the substrate (1), respectively.

9. The transistor according to claim 8, characterized in that, The P-type semiconductor material filled in the trench (3) is P-type AlN.

10. The transistor according to claim 8, characterized in that, The material of the gate dielectric layer (8) is Al2O3.

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