Method of forming shielded gate MOSFET
By injecting ions into the shielding gate to break the Si-Si bonds, combined with thermal oxidation and high-density plasma chemical vapor deposition processes, the problems of insufficient thickness and quality of the shielding gate MOSFET isolation layer were solved, achieving an isolation layer without depressions and voids, thus improving device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-04-24
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies often result in depressions and voids when forming the isolation layer of a shielded gate MOSFET, and the thickness is difficult to meet process requirements, affecting device performance.
By injecting ions into the shielding gate to break the Si-Si bonds, combined with thermal oxidation and high-density plasma chemical vapor deposition processes, dangling bonds are formed, increasing the thickness of the isolation layer. The thickness of the isolation layer is then adjusted by etch-back and filling to avoid depressions and voids.
The thickness of the isolation layer was achieved, avoiding depressions and voids, thus improving the quality of the isolation layer and the performance of the device.
Smart Images
Figure CN122497090A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming a shielded gate MOSFET. Background Technology
[0002] Shielded gate MOSFETs represent the most advanced power MOSFET technology currently available, offering advantages such as lower on-resistance and faster switching speeds. In system applications, they exhibit lower conduction losses and lower switching losses, resulting in higher conversion and transmission efficiency.
[0003] Please refer to Figure 1 The existing shielded gate MOSFET includes: an epitaxial layer 101, a P-type body region 102 located within the epitaxial layer 101 and close to the surface of the epitaxial layer 101, a gate oxide layer 103 and a source region 104 located on the surface of the P-type body region 102, with a portion of the source region 104 extending into the P-type body region 102. A shielding gate trench with straight sidewalls extends from the surface of the P-type body region 102 into the interior of the epitaxial layer 101. A shielding gate 105 is formed within the shielding gate trench, the shielding gate 105 being separated from the bottom and sidewalls of the shielding gate trench by a first gate dielectric layer 106; an isolation layer 107 located above the shielding gate 105; and a second gate polysilicon 108 located on the isolation layer 107, the second gate polysilicon 108 being separated from the sidewalls of the shielding gate trench by a second gate dielectric layer 109. The isolation layer 107 is an inter-poly oxide layer of a specific thickness, which provides electrical isolation between the shielding gate 105 and the second gate polysilicon 108, ensuring that the second gate polysilicon 108 can independently control the channel conductivity characteristics, while avoiding the charge of the shielding gate 105 from interfering with the stability of the threshold voltage of the second gate polysilicon 108.
[0004] In the prior art, the first method for forming the isolation layer 107 is the HDP CVD process, which uses high-density plasma chemical vapor deposition to deposit an oxide layer, completely fills the shielding gate trench, and then etches the oxide layer back to obtain the isolation layer 107 of the required thickness. The high-density plasma chemical vapor deposition method does not affect the sidewall dimensions of the shielding gate trench, and the thickness of the isolation layer 107 can be flexibly adjusted.
[0005] However, before forming the isolation layer 107, the first gate dielectric layer is formed by depositing oxide and etching back. Since the shielding gate 105 cannot be etched, the surface of the first gate dielectric layer on both sides of the shielding gate 105 is lower than the surface of the shielding gate 105 after etching back, resulting in depressions on both sides of the shielding gate 105. This leads to a large depth-to-width ratio of the deep trenches on both sides. HDP is greatly affected by the depth-to-width ratio of the shielding gate trenches. Shielding gate trenches with a large depth-to-width ratio are prone to causing voids in the isolation layer 107, and the etching back is greatly affected by the lifetime of the wet etching solution.
[0006] The second method for forming the isolation layer 107 is a thermal oxidation process. After the shielding gate 105 is etched, the shielding gate 105 is thermally oxidized. In order to prevent the sidewalls of the shielding gate trench from being oxidized and affecting the size of the shielding gate trench, the sidewalls of the shielding gate 105 will use an oxide-nitride-oxide process to ensure that only the shielding gate 105 is oxidized during thermal oxidation, while the sidewalls of the shielding gate trench are protected by nitride.
[0007] However, the thickness of the oxide layer in the thermal oxidation process is greatly affected by the size of the shielding gate 105. As the size of the shielding gate 105 becomes smaller and smaller, the oxidation rate slows down, and the thickness of the resulting isolation layer is difficult to meet the process requirements. Summary of the Invention
[0008] The purpose of this invention is to provide a method for forming a shielded gate MOSFET, which can form an isolation layer of sufficient thickness. Furthermore, it can form an isolation layer without voids, thereby improving the quality of the isolation layer.
[0009] To achieve the above objectives, the present invention provides a method for forming a shielded gate MOSFET, comprising:
[0010] An epitaxial layer is provided, and a shielding gate trench is formed within the epitaxial layer;
[0011] A first oxide layer and a shielding gate are formed. The first oxide layer covers the inner wall of the shielding gate trench and the surface of the outer epitaxial layer. The shielding gate is located in the lower part of the shielding gate trench and is separated from the inner wall of the shielding gate trench by the first oxide layer.
[0012] Ions are injected into the shielding gate to break the si-si bonds of the shielding gate and form dangling bonds;
[0013] A thermal oxidation process is performed to form an isolation layer on the shielding grid;
[0014] The first oxide layer on the upper part of the shielding gate trench and the surface of the epitaxial layer is etched back to expose the inner wall of the upper part of the shielding gate trench, and the remaining first oxide layer on the lower part of the shielding gate trench serves as the first gate dielectric layer.
[0015] A second oxide layer is formed by high-density plasma chemical vapor deposition and then etched back to release part of the space above the shielding gate trench. The remaining part of the second oxide layer on the surface of the isolation layer is then added to increase the thickness of the isolation layer.
[0016] A second gate dielectric layer is formed on the sidewall of the upper portion of the shielding gate trench;
[0017] A second gate polysilicon is formed within the shielding gate trench. The second gate polysilicon is separated from the inner wall of the upper part of the shielding gate trench by a second gate dielectric layer and is isolated from the shielding gate by the isolation layer.
[0018] Optionally, in the method for forming the shielded gate MOSFET, the ions injected into the shielded gate include As ions or Ar ions.
[0019] Optionally, in the method for forming the shielded gate MOSFET, ions are implanted into the shielded gate at an angle perpendicular to the surface of the shielded gate.
[0020] Optionally, in the method for forming the shielded gate MOSFET, a second gate dielectric layer is formed on the sidewall located on the upper portion of the shielded gate trench by a thermal oxidation process.
[0021] Optionally, in the method for forming the shielded gate MOSFET, forming a second oxide layer by high-density plasma chemical vapor deposition and etching back to release part of the space above the shielded gate trench, and leaving the remaining portion of the second oxide layer on the surface of the isolation layer to increase the thickness of the isolation layer includes:
[0022] A second oxide layer is formed by high-density plasma chemical vapor deposition, which fills the upper portion of the shielding gate trench and extends to the surface of the epitaxial layer.
[0023] Grinding removes part of the second oxide layer to expose the surface of the epitaxial layer;
[0024] The second oxide layer is partially etched, leaving the remaining portion of the second oxide layer on the surface of the isolation layer to increase the thickness of the isolation layer.
[0025] Optionally, in the method for forming the shielded gate MOSFET, a portion of the second oxide layer is wet-etched, leaving the remaining portion of the second oxide layer on the surface of the isolation layer, to increase the thickness of the isolation layer.
[0026] Optionally, in the method for forming the shielded gate MOSFET, the method for forming the shielded gate includes:
[0027] The shielding trench is filled with polycrystalline silicon material;
[0028] The polycrystalline silicon material is etched to form a shielding gate.
[0029] Optionally, in the method for forming the shielded gate MOSFET, after forming the second gate polysilicon within the shielded gate trench, the method further includes:
[0030] A P-shaped body region is formed in the epitaxial layer on both sides of the shielding grid trench;
[0031] A gate oxide layer is formed on the surface of the P-type body region;
[0032] A source region is formed on the surface of the gate oxide layer, and a portion of the source region extends through the gate oxide layer into the P-type body region.
[0033] Optionally, in the method for forming the shielded gate MOSFET, an epitaxial layer is provided, and a portion of the epitaxial layer is etched downward from the surface of the epitaxial layer and stops within the epitaxial layer to form a shielded gate trench within the epitaxial layer.
[0034] Optionally, in the method for forming the shielded gate MOSFET, the materials of both the first oxide layer and the second oxide layer include silicon dioxide.
[0035] In the method for forming a shielded gate MOSFET provided by this invention, ions are implanted into the shielded gate to break the Si-Si bonds and form dangling bonds. Then, a thermal oxidation process is used to form an isolation layer on the shielded gate. The breaking of the Si-Si bonds and the formation of dangling bonds accelerates the oxidation rate of the polysilicon in the top shielded gate, thus ensuring the required thickness of the isolation layer. Furthermore, when the first oxide layer on the upper part of the shielded gate trench is etched back to form the first gate dielectric layer, the presence of the isolation layer prevents depressions on both sides of the shielded gate, reduces the aspect ratio of the deep trenches on both sides, and thus prevents voids when the subsequent HDP oxide layer thickness is increased. It also reduces the difficulty of filling the second oxide layer. After increasing the isolation layer thickness, an isolation layer with the required thickness is finally obtained. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the structure of a shielded gate MOSFET in the prior art;
[0037] Figure 2 This is a flowchart of a method for forming a shielded gate MOSFET according to an embodiment of the present invention;
[0038] Figures 3 to 9 This is a schematic diagram of the structure during the formation process of the shielded gate MOSFET according to an embodiment of the present invention;
[0039] In the figure: 101-epitaxy layer, 102-P-type body region, 103-gate oxide layer, 104-source region, 105-shielding gate, 106-first gate dielectric layer, 107-isolation layer, 108-second gate polysilicon, 109-second gate dielectric layer, 201-epitaxy layer, 202-shielding gate trench, 203-first oxide layer, 204-shielding gate, 205-isolation layer, 206-first gate dielectric layer, 207-second oxide layer, 208-second gate dielectric layer, 209-second gate polysilicon, 210-P-type body region, 211-gate oxide layer, 212-source region. Detailed Implementation
[0040] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0041] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0042] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0043] Please refer to Figure 2 The present invention provides a method for forming a shielded gate MOSFET, comprising:
[0044] S11: Provides an epitaxial layer, within which a shielding gate trench is formed;
[0045] S12: Form a first oxide layer and a shielding gate. The first oxide layer covers the inner wall of the shielding gate trench and the surface of the epitaxial layer. The shielding gate is located in the lower part of the shielding gate trench and is separated from the inner wall of the shielding gate trench by the first oxide layer.
[0046] S13: Ions are injected into the shielding gate to break the si-si bonds of the shielding gate and form dangling bonds;
[0047] S14: Perform a thermal oxidation process to form an isolation layer on the shielding grid;
[0048] S15: Re-etch the first oxide layer on the upper part of the shielding gate trench and the surface of the epitaxial layer to expose the inner wall of the upper part of the shielding gate trench, and use the remaining first oxide layer on the lower part of the shielding gate trench as the first gate dielectric layer.
[0049] S16: A second oxide layer is formed by high-density plasma chemical vapor deposition and etched back to release part of the space above the shielding gate trench. The remaining part of the second oxide layer on the surface of the isolation layer is used to increase the thickness of the isolation layer.
[0050] S17: A second grid dielectric layer is formed on the sidewall of the upper part of the shielding grid trench;
[0051] S18: A second gate polysilicon is formed in the shielding gate trench. The second gate polysilicon is separated from the inner wall of the upper part of the shielding gate trench by the second gate dielectric layer and is isolated from the shielding gate by the isolation layer.
[0052] Please refer to Figure 3 First, an epitaxial layer 201 is provided. A portion of the epitaxial layer 201 is etched downwards from its surface and stops within the epitaxial layer 201, forming a shielding gate trench 202 within it. An oxide, such as silicon dioxide, is deposited to form a first oxide layer 203, which covers the inner wall of the shielding gate trench 202 and the surface of the epitaxial layer 201. The shielding gate trench 202 is filled with polysilicon, and a portion of the polysilicon is etched back, thereby forming a shielding gate 204 within the shielding gate trench 202. The shielding gate 204 is located in the lower portion of the shielding gate trench and is separated from the inner wall of the shielding gate trench by the first oxide layer 203.
[0053] Please refer to Figure 4 Ions are implanted into the shielding gate 204 to break the Si-Si bonds in the shielding gate 204 and form dangling bonds. The ions implanted into the shielding gate 204 include As or Ar ions. Ions are implanted into the shielding gate 204 at an angle perpendicular to the surface of the shielding gate 204. During ion implantation, the first oxide layer 203 covers the epitaxial layer 201.
[0054] Please refer to Figure 5 A thermal oxidation process is performed to oxidize a portion of the shielding gate 204 near the surface into silicon dioxide, thereby forming an isolation layer 205 on the shielding gate 204. The isolation layer 205 is silicon dioxide. Because the Si-Si bonds of the shielding gate 204 are broken to form dangling bonds, the oxidation rate and thickness of the shielding gate 204 are increased. The first oxide layer 203 on the upper part of the shielding gate trench and the surface of the epitaxial layer 201 is etched back to expose the inner wall of the upper part of the shielding gate trench. The remaining first oxide layer on the lower part of the shielding gate trench serves as the first gate dielectric layer 206. At this time, due to the presence of the isolation layer 205, a portion of the isolation layer 205 is etched away simultaneously when the first oxide layer 203 on the upper part of the shielding gate trench and the surface of the epitaxial layer 201 is etched back. Therefore, after etching back, the surfaces of the first gate dielectric layers 206 on both sides of the shielding gate 204 are flush with the surface of the shielding gate 204, that is, no depressions appear on both sides of the shielding gate 204.
[0055] Please refer to Figure 6 and Figure 7 A second oxide layer 207, which can be made of silicon dioxide, is formed using high-density plasma chemical vapor deposition (HDP). The second oxide layer 207 fills the upper portion of the shielding gate trench and extends to cover the surface of the epitaxial layer 201. Part of the second oxide layer 207 is removed by grinding to expose the surface of the epitaxial layer 201. A portion of the second oxide layer 207 is then wet-etched to release the upper portion of the shielding gate trench. A portion of the second oxide layer 207 is retained on the surface of the original isolation layer 205, thereby increasing the thickness of the isolation layer 205 to meet the required thickness.
[0056] Please refer to Figure 8 A second gate dielectric layer 208 is formed on the sidewall of the upper portion of the shielding gate trench, which can be formed by thermally oxidizing the sidewall of the upper portion of the shielding gate trench to form an oxide. The second gate dielectric layer 208 is located on the inner wall of the upper portion of the shielding gate trench. Polysilicon is filled into the shielding gate trench to form a second gate polysilicon 209. The second gate polysilicon 209 is separated from the inner wall of the upper portion of the shielding gate trench by the second gate dielectric layer 208 and is isolated from the shielding gate 204 by the isolation layer 205.
[0057] Please refer to Figure 9 A P-type body region 210 is formed in the epitaxial layer 201 on both sides of the shielding gate trench; a gate oxide layer 211 is formed on the surface of the P-type body region 210; a source region 212 is formed on the surface of the gate oxide layer 211, and a portion of the source region 212 extends through the gate oxide layer 211 into the P-type body region 210.
[0058] In summary, in the method for forming a shielded gate MOSFET provided in this embodiment of the invention, ions are implanted into the shielded gate to break the Si-Si bonds of the shielded gate, forming dangling bonds. Then, a thermal oxidation process is used to form an isolation layer on the shielded gate. The breaking of the Si-Si bonds and the formation of dangling bonds accelerates the oxidation rate of the polysilicon in the top shielded gate, thereby ensuring the required thickness of the isolation layer. Furthermore, when the first oxide layer on the upper part of the shielded gate trench is etched back to form the first gate dielectric layer, the presence of the isolation layer prevents depressions on both sides of the shielded gate, reduces the aspect ratio of the deep trenches on both sides, and thus prevents voids when the subsequent HDP oxide layer thickness is increased. It also reduces the difficulty of filling the second oxide layer. After increasing the isolation layer thickness, an isolation layer with the required thickness is finally obtained.
[0059] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for forming a shielded gate MOSFET, characterized in that, include: An epitaxial layer is provided, and a shielding gate trench is formed within the epitaxial layer; A first oxide layer and a shielding gate are formed. The first oxide layer covers the inner wall of the shielding gate trench and the surface of the outer epitaxial layer. The shielding gate is located in the lower part of the shielding gate trench and is separated from the inner wall of the shielding gate trench by the first oxide layer. Ions are injected into the shielding gate to break the si-si bonds of the shielding gate and form dangling bonds; A thermal oxidation process is performed to form an isolation layer on the shielding grid; The first oxide layer on the upper part of the shielding gate trench and the surface of the epitaxial layer is etched back to expose the inner wall of the upper part of the shielding gate trench, and the remaining first oxide layer on the lower part of the shielding gate trench serves as the first gate dielectric layer. A second oxide layer is formed by high-density plasma chemical vapor deposition and then etched back to release part of the space above the shielding gate trench. The remaining part of the second oxide layer on the surface of the isolation layer is then added to increase the thickness of the isolation layer. A second gate dielectric layer is formed on the sidewall of the upper portion of the shielding gate trench; A second gate polysilicon is formed within the shielding gate trench. The second gate polysilicon is separated from the inner wall of the upper part of the shielding gate trench by a second gate dielectric layer and is isolated from the shielding gate by the isolation layer.
2. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, The ions injected into the shielding grid include As ions or Ar ions.
3. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, Ions are injected into the shielding grid at an angle perpendicular to the surface of the shielding grid.
4. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, A second gate dielectric layer is formed on the sidewall of the upper portion of the shielding gate trench using a thermal oxidation process.
5. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, A second oxide layer is formed by high-density plasma chemical vapor deposition and etched back to release part of the space above the shielding gate trench. The remaining portion of the second oxide layer on the surface of the isolation layer is then etched back to increase the thickness of the isolation layer. A second oxide layer is formed by high-density plasma chemical vapor deposition, which fills the upper portion of the shielding gate trench and extends to the surface of the epitaxial layer. Grinding removes part of the second oxide layer to expose the surface of the epitaxial layer; The second oxide layer is partially etched, leaving the remaining portion of the second oxide layer on the surface of the isolation layer to increase the thickness of the isolation layer.
6. The method for forming a shielded gate MOSFET as described in claim 5, characterized in that, The second oxide layer is partially etched using a wet etching process, leaving the remaining portion of the second oxide layer on the surface of the isolation layer to increase the thickness of the isolation layer.
7. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, Methods for forming a shielding barrier include: The shielding trench is filled with polycrystalline silicon material; The polycrystalline silicon material is etched to form a shielding gate.
8. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, After forming the second gate polysilicon within the shielding gate trench, the method further includes: A P-shaped body region is formed in the epitaxial layer on both sides of the shielding grid trench; A gate oxide layer is formed on the surface of the P-type body region; A source region is formed on the surface of the gate oxide layer, and a portion of the source region extends through the gate oxide layer into the P-type body region.
9. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, An epitaxial layer is provided, and a portion of the epitaxial layer is etched downward from the surface of the epitaxial layer and stops within the epitaxial layer to form a shielding gate trench within the epitaxial layer.
10. The method for forming a shielded gate MOSFET as described in claim 1, characterized in that, The materials of both the first oxide layer and the second oxide layer include silicon dioxide.