An Enhanced GaN HEMT Device and Its Fabrication Method
By employing a fabrication method involving groove etching and oxygen annealing, the etching precision and uniformity issues of enhanced GaN HEMT devices were resolved, reducing fabrication complexity and damage, and achieving the stability and output characteristics of enhanced devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGNAN UNIV
- Filing Date
- 2026-05-22
- Publication Date
- 2026-07-31
AI Technical Summary
The etching process for existing grooved gate structure enhancement-type GaN HEMT devices requires high precision and has poor uniformity. The fabrication process is complex and suffers from etching damage and surface state problems.
The fabrication method employing trench etching-gate fabrication-oxygen annealing involves defining the gate above the trench and performing oxygen annealing to form an oxide layer, thereby optimizing the channel surface, reducing etching damage, and improving etching margin and threshold voltage uniformity.
It improves etching margin and threshold voltage uniformity, reduces fabrication costs, and retains good output characteristics while realizing enhanced devices.
Smart Images
Figure CN122497091A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor electronic device technology, specifically relating to an enhancement-mode GaN HEMT device and its fabrication method. Background Technology
[0002] GaN HEMTs possess excellent high-temperature and high-voltage resistance, demonstrating significant advantages in various fields such as power electronics, high-frequency communications, and automotive electronics. For device safety, they are often required to operate in a normally-off state, meaning that the system will not burn out due to loss of gate control when operating under high voltage. Current GaN HEMT devices are predominantly depletion-mode, which is detrimental to circuit design and operational stability; therefore, there is a need to develop enhanced-mode devices.
[0003] Enhancement-mode GaN HEMTs mainly include two types: grooved gate structures and p-type GaN gate structures. For grooved gate structures, etching is used to thin the AlGaN layer in the channel region, forming a groove. When the AlGaN layer is thin enough, the concentration of the two-dimensional electron gas induced in the GaN channel layer is almost negligible, thus achieving source-drain isolation at zero gate voltage and obtaining normally-off devices. However, the fabrication of grooved gate structures is difficult, mainly due to two challenges: First, the AlGaN barrier layer is generally quite thin (about 20 nm), while to form normally-off devices, etching to a thickness of about 1-3 nm is required. This places high demands on etching precision and uniformity; improper etching can lead to instability in the threshold voltage. Second, etching methods can cause varying degrees of surface damage, affecting device performance, such as high leakage current and current collapse. Therefore, it is necessary to explore more suitable fabrication methods to solve the problems of high etching difficulty and high leakage current.
[0004] To avoid etching damage and surface state issues inherent in conventional recessed gate technology, prior art patent CN112086362 A discloses a method for fabricating gallium nitride-enhanced HEMT devices. This method involves oxygen plasma oxidation of the gate region followed by in-situ annealing to generate GaON nanophases, thereby optimizing the channel surface. While effective, this method still requires precise recessed etching to remove the entire barrier layer, additional plasma processing equipment, and precise process control. Furthermore, an insulating dielectric layer must be deposited subsequently, making the process relatively complex. Therefore, a more optimized device structure is needed to simplify the fabrication process. Summary of the Invention
[0005] Technical issues Existing etching processes for grooved gate structure-enhanced GaN HEMTs have high precision requirements, poor uniformity, and complex fabrication processes.
[0006] Technical content To address the aforementioned technical problems, this invention provides an enhanced GaN HEMT device and its fabrication method. This method can improve the etching margin and threshold voltage uniformity of the grooved gate enhanced GaN HEMT, and reduce the device fabrication cost.
[0007] To achieve the above objectives, the present invention provides a method for fabricating an enhanced GaN HEMT device, comprising the following steps: Step 1: Epitaxially grow the nucleation layer, buffer layer, channel layer, and barrier layer sequentially on the substrate; Step 2: Define the source and drain regions above the barrier layer, deposit metal to form the source and drain, and anneal the source and drain to form ohmic contacts. Step 3: Etch away part of the barrier layer between the source and drain to obtain a groove; Step 4: Define the gate region above the groove, and form the gate in the gate region; Step 5: Use photoresist to block the source region, drain region and gate region, and etch away the barrier layer and part of the channel layer outside the region to achieve isolation; Step 6: Remove the photoresist and anneal the device in an oxygen atmosphere to form an oxide layer on the surface of the barrier layer and channel layer that are not covered by the gate, source, and drain.
[0008] Furthermore, in step 1, the substrate material includes one or more of sapphire, Si, GaN, SiC, and diamond, the nucleation layer material is AlN, the buffer layer material is iron-doped or carbon-doped semi-insulating GaN, the channel layer material is GaN, and the barrier layer material is AlGaN.
[0009] Furthermore, the nucleation layer has a thickness of 50~150nm, the buffer layer has a thickness of 1~5μm, the channel layer has a thickness of 100~250nm, and the barrier layer has a thickness of 10~50nm.
[0010] Furthermore, in step 2, the source material is two or more of Ti, Al, Ni, Au, and Pt, and the top must be one or more of Au and Pt.
[0011] Furthermore, in step 2, the drain material is two or more of Ti, Al, Ni, Au, and Pt, and the top must be one or more of Au and Pt.
[0012] Furthermore, in step 2, the thickness of the source electrode is 200~500nm.
[0013] Furthermore, in step 2, the thickness of the drain electrode is 200~500nm.
[0014] Specifically, in step 2, the source is a Ti / Al / Ni / Au stacked metal, and the thicknesses of each metal layer are 20~100nm, 50~150nm, 50~150nm, and 20~100nm, respectively.
[0015] Specifically, in step 2, the drain is a Ti / Al / Ni / Au stacked metal, and the thicknesses of each metal layer are 20~80nm, 50~150nm, 50~150nm, and 20~80nm, respectively.
[0016] Furthermore, in step 2, the distance between the source and drain is 20~100μm.
[0017] Furthermore, in step 2, the annealing temperature is 800~900℃, and the annealing is carried out in a nitrogen atmosphere for 0.5~2 minutes.
[0018] Furthermore, in step 3, the etching depth of the barrier layer is 10-40 nm, the remaining depth is 10-20 nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.
[0019] Furthermore, in step 4, the gate material is two or more of Ni, TiN, NiN, Au, and Pt, and the top must be one or more of Au and Pt.
[0020] Furthermore, in step 4, the thickness of the gate material is 200~350nm.
[0021] Specifically, in step 4, the gate material is a Ni / Au multilayer metal, with the thicknesses of each metal layer being 150~250nm and 20~100nm, respectively.
[0022] Furthermore, the etching depth in step 5 is 50-100 nm, and the etching depth is greater than the thickness of the barrier layer.
[0023] Furthermore, the etched area in step 5 is the channel layer and barrier layer at the edge of the device.
[0024] Furthermore, the annealing temperature in step 6 is 400-600℃, and the annealing time is 10-30 min.
[0025] Furthermore, the oxide layer in step 6 is obtained by oxidizing and transforming the barrier layer and the channel layer. The transformed thickness of the barrier layer is 7-17 nm, and the remaining barrier layer thickness is 1-3 nm. This thickness is determined by the threshold voltage design value.
[0026] The present invention also provides an enhancement-mode GaN HEMT device, which is fabricated according to the above-described method for fabricating an enhancement-mode GaN HEMT device. Its specific structure comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer; a source and a drain are disposed on the barrier layer; a groove is disposed in the barrier layer between the source and drain; a gate is disposed above the groove; an oxide layer is disposed in the area outside the gate, source, and drain; the oxide layer is obtained by oxidizing and transforming the barrier layer and the channel layer.
[0027] Beneficial effects 1. This invention creatively employs a "groove etching-gate fabrication-oxygen annealing" method, which provides a large etching margin for the AlGaN barrier layer, avoiding over-etching caused by etching process inhomogeneities and improving the yield of large-size wafer fabrication. The gate metal can be used as a self-aligned mask to accurately define the oxide region, and the thicker AlGaN layer remaining below the gate can serve as a dielectric layer, eliminating the need for additional gate dielectric deposition processes. Oxygen annealing converts the AlGaN barrier layer into an oxide layer at a relatively slow rate, making it easier to fabricate a 1-3nm thick AlGaN barrier layer in the channel region for etching the remaining AlGaN barrier layer. This increases the device's process window and enhances the flexibility of the device's threshold voltage design. The annealing process can simultaneously optimize the Schottky contact interface between the gate metal and the barrier layer, reducing the interface state density and enhancing channel control capabilities.
[0028] 2. By adopting a design with a thicker AlGaN barrier layer below the gate and a thinner AlGaN barrier layer in other areas, the concentration of two-dimensional electron gas in the channel outside the gate region is reduced, while the concentration of two-dimensional electron gas in the channel of the gate region can still be maintained at a high level, thus achieving enhancement-mode devices while retaining good output characteristics. Attached Figure Description
[0029] Figure 1 This is a structural diagram of a method for fabricating an enhancement-type GaN HEMT device according to an embodiment of the present invention, in which a nucleation layer, a buffer layer, a channel layer, and a barrier layer are sequentially epitaxially grown on a substrate.
[0030] Figure 2 In order to be in Figure 1 The structure diagram after the source and drain are formed on the structure.
[0031] Figure 3 In order to be in Figure 2 The structural diagram after etching grooves on the structure.
[0032] Figure 4 In order to be in Figure 3 The structure diagram after the gate is formed on the structure.
[0033] Figure 5 In order to be in Figure 4 The structure diagram after etching and isolation on the structure.
[0034] Figure 6 In order to be in Figure 5 The structural diagram after oxidation annealing. Figure 7 The test results of the device before and after annealing are shown in the example. Figure 8 The test results are for the example device and the comparative device.
[0035] The components are: 1. Substrate; 2. Nucleation layer; 3. Buffer layer; 4. Channel layer; 5. Barrier layer; 6. Source and drain; 7. Gate; 8. Oxide layer. Detailed Implementation
[0036] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0037] Example 1 A 100nm AlN nucleation layer, a 3μm GaN buffer layer, a 200nm GaN channel layer, and a 20nm AlGaN barrier layer were sequentially deposited on a silicon substrate using MOCVD. Figure 1 As shown.
[0038] The source and drain regions were defined above the AlGaN barrier layer using photolithography. A 50 / 100 / 100 / 50 nm Ti / Al / Ni / Au multilayer metal was deposited using sputtering. After lift-off, the source and drain were formed, with a 50 μm spacing between them. The source and drain were then annealed at 850 °C for 1 min in a nitrogen atmosphere to form ohmic contacts. Figure 2 As shown.
[0039] A 30μm wide channel region was defined between the source and drain electrodes using photolithography. ICP etching was then performed on the exposed AlGaN barrier layer to a depth of 10nm to form a groove. Figure 3 As shown.
[0040] The gate region is defined above the trench using photolithography. A 200 / 50nm thick Ni / Au multilayer metal is deposited using sputtering. After lift-off, the gate is formed with a width of 10μm. Figure 4 As shown.
[0041] Photolithography is used to cover the device regions (source, drain, and gate regions), and ICP etching is used to etch the exposed areas (device edges) to achieve isolation between devices. The etching depth is 50nm. Figure 5 As shown.
[0042] The device was subjected to oxygen annealing in a rapid annealing furnace at 400℃ for 20 minutes, converting the 7nm thick AlGaN barrier layer into an oxide layer while retaining the 3nm AlGaN barrier layer, thus forming the device. Figure 6 As shown.
[0043] Comparative Example 1 A 100 nm AlN nucleation layer, a 3 μm GaN buffer layer, a 200 nm GaN channel layer, and a 20 nm AlGaN barrier layer were sequentially deposited on a silicon substrate using MOCVD.
[0044] The source and drain regions were defined above the AlGaN barrier layer using photolithography. A 50 / 100 / 100 / 50 nm Ti / Al / Ni / Au stacked metal was deposited using sputtering. After stripping, the source and drain were formed with a spacing of 50 μm between them. The source and drain were then annealed at 850 °C for 1 min in a nitrogen atmosphere to form ohmic contacts.
[0045] A 30μm wide channel region was defined in the middle of the source and drain using photolithography. The exposed AlGaN barrier layer was etched using ICP at a depth of 17nm to form a groove.
[0046] The gate region is defined above the trench using photolithography. A 200 / 50nm thick Ni / Au stacked metal is deposited using sputtering. After being stripped, the gate is formed with a gate width of 10μm.
[0047] The device regions (source, drain, and gate regions) are covered using photolithography, and the exposed regions (device edges) are etched using ICP to achieve isolation between devices, with an etching depth of 50nm.
[0048] Compared to the examples, the comparative example is a traditional groove structure GaN HEMT fabrication method, which is difficult to control while maintaining a 3nm AlGaN thickness, and also lacks the oxygen annealing process after gate fabrication.
[0049] The samples prepared in the examples and comparative examples were tested under the following conditions: the device was placed on the probe stage, and voltages were applied to the gate and drain using an Agilent B1505A device, with the source grounded. The data on the change of drain current with drain voltage under different gate voltages were recorded.
[0050] The test results of the device before and after annealing in the example are as follows: Figure 7As shown, before annealing, the device's threshold voltage was -0.7V, indicating a depletion-mode device; after annealing, the threshold voltage was 0.5V, achieving an enhancement-mode device. Furthermore, the output current of the device after annealing was greater than before, indicating that annealing repaired the etching defects and reduced the interface state density between the gate metal and the AlGaN barrier layer.
[0051] The test results of the embodiment device and the comparative device are as follows: Figure 8 As shown, it can be seen that the device in the embodiment has a larger output current under the same gate voltage, indicating that the design of a thick AlGaN barrier layer under the gate and a thin AlGaN barrier layer in other areas can achieve enhancement-mode devices while retaining good output characteristics.
[0052] The embodiments provided above are not intended to limit the scope of the invention, nor are the described steps intended to limit the order of execution. Any obvious modifications made to the invention by those skilled in the art based on existing common knowledge also fall within the scope of protection defined by the claims.
Claims
1. A method for fabricating an enhancement-mode GaN HEMT device, characterized in that, Includes the following steps: Step 1: Epitaxially grow the nucleation layer, buffer layer, channel layer, and barrier layer sequentially on the substrate; Step 2: Define the source and drain regions above the barrier layer, deposit metal to form the source and drain, and anneal the source and drain to form ohmic contacts. Step 3: Etch away part of the barrier layer between the source and drain to obtain a groove; Step 4: Define the gate region above the groove, and form the gate in the gate region; Step 5: Use photoresist to block the source region, drain region and gate region, and etch away the barrier layer and part of the channel layer outside the region to achieve isolation; Step 6: Remove the photoresist and anneal the device in an oxygen atmosphere to form an oxide layer on the surface of the barrier layer and channel layer that are not covered by the gate, source, and drain, thus obtaining an enhancement-mode GaN HEMT device; the annealing temperature is 400-600℃ and the annealing time is 10-30min.
2. The preparation method according to claim 1, characterized in that, In step 1, the substrate material includes one or more of sapphire, Si, GaN, SiC, and diamond. The nucleation layer material is AlN, the buffer layer material is iron-doped or carbon-doped semi-insulating GaN, the channel layer material is GaN, and the barrier layer material is AlGaN.
3. The preparation method according to claim 1, characterized in that, The nucleation layer has a thickness of 50~150nm, the buffer layer has a thickness of 1~5μm, the channel layer has a thickness of 100~250nm, and the barrier layer has a thickness of 10~50nm.
4. The preparation method according to claim 1, characterized in that, In step 2, the source electrode material is two or more of Ti, Al, Ni, Au, and Pt, and the top must be one or more of Au and Pt; the thickness of the source electrode is 200~500nm.
5. The preparation method according to claim 1, characterized in that, In step 2, the drain material is two or more of Ti, Al, Ni, Au, and Pt, and the top must be one or more of Au and Pt; the thickness of the drain is 200~500nm.
6. The preparation method according to claim 1, characterized in that, In step 2, the annealing temperature is 800~900℃, and it is carried out in a nitrogen atmosphere for 0.5~2 minutes.
7. The preparation method according to claim 1, characterized in that, In step 3, the etching depth of the barrier layer is 10-40 nm, the remaining depth is 10-20 nm, and the sum of the etching depth and the remaining depth of the barrier layer is equal to the thickness of the barrier layer.
8. The preparation method according to claim 1, characterized in that, In step 4, the gate material is two or more of Ni, TiN, NiN, Au, and Pt, and the top must be one or more of Au and Pt; the thickness of the gate material is 200~350nm.
9. The preparation method according to claim 1, characterized in that, The etching depth in step 5 is 50-100nm, and the etching depth is greater than the thickness of the barrier layer.
10. An enhancement-mode GaN HEMT device, characterized in that, The enhanced GaN HEMT device is fabricated according to any one of claims 1 to 8; the structure of the device is: a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked from bottom to top; a source and a drain are disposed on the barrier layer; a groove is disposed in the middle part of the barrier layer between the source and the drain; a gate is disposed above the groove; an oxide layer is disposed in the area other than the gate, source and drain; the oxide layer is obtained by oxidation and transformation of the barrier layer and the channel layer.