A high-speed and high-reliability trench-gate silicon carbide VDMOS and a preparation method thereof

Abstract

This invention provides a high-speed, high-reliability trench-gate silicon carbide VDMOS and its fabrication method, relating to the semiconductor field. The method includes: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; forming a barrier layer above the drift layer, etching the barrier layer to form vias, and forming a P-type region by ion implantation; reforming the barrier layer, etching, and ion implantation to form a P-type well region and an N-type source region; reforming the barrier layer, etching, and oxidizing to form a gate insulating dielectric layer, wherein trenches are provided in the gate insulating dielectric layer; reforming the barrier layer, etching the barrier layer to form vias, and depositing to form a field plate insulating layer, repeating this step until all field plate insulating layers are deposited; reforming the barrier layer, etching, and depositing to form a gate metal layer, a Schottky metal layer, and a source metal layer; removing the barrier layer to complete the fabrication, reducing the on-resistance of the device and improving the switching speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a high-speed, high-reliability trench-gate silicon carbide VDMOS and its fabrication method. Background Technology

[0002] Silicon carbide VDMOS devices, due to their wide bandgap characteristics, naturally possess high voltage withstand capability compared to Si VDMOS devices. The trench gate, due to its structural characteristics, has the advantage of low on-resistance. However, due to the electric field concentration at the gate corner, its gate reliability has always been a problem that has troubled engineers. At the same time, parasitic gate leakage capacitance affects the switching speed of the device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-speed, high-reliability trench gate silicon carbide VDMOS and its fabrication method, thereby reducing the on-resistance of the device and improving the switching speed.

[0004] In a first aspect, the present invention provides a method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS, comprising the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a gate metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and form a P-type region by ion implantation; Step 3: Remove the barrier layer from Step 2 and reform the barrier layer. Etch the barrier layer to form vias. Ion implantation is performed to form a P-type well region. Step 4: Ion implantation to form an N-type source region; Step 5: Remove the barrier layer from Step 3 and reform the barrier layer; etch the barrier layer to form a via; etch the drift layer to form a second groove; oxidize to form a gate insulating dielectric layer, wherein the gate insulating dielectric layer has trenches. Step 6: Remove the barrier layer from Step 5 and reform the barrier layer. Etch the barrier layer to form vias and deposit the field plate insulating layer. Repeat this step until all field plate insulating layers are deposited. There are at least three field plate insulating layers, and the thickness of the field plate insulating layer closer to the center is greater. Step 7: Remove the barrier layer from Step 6, reform the barrier layer, etch the barrier layer to form vias, and deposit the gate metal layer. Step 8: Remove the barrier layer from Step 7 and reform the barrier layer. Etch the barrier layer to form vias and etch the drift layer. Then deposit the Schottky metal layer. Step 9: Remove the barrier layer from Step 8 and reform the barrier layer. Etch the barrier layer to form vias and etch the drift layer. Then deposit the source metal layer, remove the barrier layer, and complete the fabrication.

[0005] Furthermore, the doping concentration of the drift layer is less than that of the P-type region.

[0006] Furthermore, the number of insulating layers on the field plate is odd, and they are arranged symmetrically on the left and right sides.

[0007] Furthermore, the side of the outermost field plate insulation layer is connected to the inner side of the trench.

[0008] Furthermore, the thickness of the Schottky metal layer is equal to the sum of the thicknesses of the P-type well region and the N-type source region.

[0009] Secondly, the present invention provides a high-speed, high-reliability trench-gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the preparation method of the high-speed, high-reliability trench-gate silicon carbide VDMOS described in the first aspect.

[0010] The advantages of this invention are: I. The present invention adopts a trench gate structure and constructs field plate insulating layers of different thicknesses inside the trench gate, thereby forming an inversion layer with decreasing spacing from both sides of the gate to the middle when the device is turned on. This inversion layer can reduce the on-resistance below the trench gate of the device. Second, the field plate insulating layers of different thicknesses of the present invention can form a high-concentration inversion layer near the conductive channel and a low-concentration inversion layer near the middle of the trench gate, while having low gate leakage capacitance, which can ensure that the device has low on-resistance and high switching speed. Third, the top height of the field plate insulating layer constructed at the corner of the trench gate of the present invention is lower than the bottom of the P-type well region, thereby improving the withstand voltage at the corner of the device gate while ensuring the switching speed of the device and improving the gate reliability of the device. IV. The present invention constructs a Schottky metal layer outside the N-type source region and the P-type well region. The Schottky metal layer forms a parasitic Schottky body diode of the device, which reduces the on-state voltage drop of the body diode and reduces the on-state loss of the body diode. Fifth, the present invention constructs a P-type region on the outside of the Schottky metal, which can form a parasitic pn junction diode that can withstand large currents. At the same time, it forms pn junction isolation between cells at the gate structure of the device to avoid crosstalk between the electrical characteristics of cells. Attached Figure Description

[0011] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0012] Figure 1 This is a cross-sectional schematic diagram of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention.

[0013] Figure 2 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0014] Figure 3 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0015] Figure 4 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0016] Figure 5 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0017] Figure 6 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0018] Figure 7 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0019] Figure 8 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0020] Figure 9 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0021] Figure 10 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0022] Figure 11 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0023] Figure 12 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0024] Figure 13 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0025] Figure 14 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 three.

[0026] Figure 15 This is a cross-sectional view of the process of a high-speed, high-reliability trench-gate silicon carbide VDMOS according to the present invention. Figure 10 Four. Detailed Implementation

[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0031] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0032] like Figures 1 to 15 As shown in the figure, this application provides a method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS, which includes the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 110; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102; Step 2: Form a barrier layer 200 above the drift layer 102, etch the barrier layer 200 to form a via, and form a P-type region 103 by ion implantation; Step 3: Remove the barrier layer 200 from Step 2 and reform the barrier layer 200. Etch the barrier layer 200 to form a via. Perform ion implantation to form a P-type well region 105. Step 4: Ion implantation to form N-type source region 106; Step 5: Remove the barrier layer 200 from step 3 and reform the barrier layer 200. Etch the barrier layer 200 to form a through hole. Etch the drift layer 102 to form a second groove 1021. Oxidize to form a gate insulating dielectric layer 107. The gate insulating dielectric layer 107 has a trench 1071 inside. Step 6: Remove the barrier layer 200 from step 5 and reform the barrier layer 200. Etch the barrier layer 200 to form a via. Deposit to form a field plate insulating layer 1072. Repeat this step until all field plate insulating layers 1072 are deposited. There are at least three field plate insulating layers 1072, and the thickness of the field plate insulating layer 1072 closer to the center is greater. Preferably, five field plate insulating layers 1072 are provided. By the above method, the outermost two side field plate insulating layers 1072 are formed first; then the next outermost two side field plate insulating layers 1072 are formed; and finally the middle field plate insulating layer 1072 is formed. Step 7: Remove the barrier layer 200 from step 6, reform the barrier layer 200, etch the barrier layer 200 to form a via, and deposit the gate metal layer 108. Step 8: Remove the barrier layer 200 from step 7 and reform the barrier layer 200. Etch the barrier layer 200 to form a via and etch the drift layer 102. Then deposit the Schottky metal layer 104. Step 9: Remove the barrier layer 200 from step 8 and reform the barrier layer 200. Etch the barrier layer 200 to form vias and etch the drift layer 102. Then deposit the source metal layer 109. Remove the barrier layer 200 to complete the fabrication.

[0033] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the P-type region 103.

[0034] In this embodiment, preferably, the number of field plate insulating layers 1072 is odd, and they are arranged symmetrically on the left and right.

[0035] In this embodiment, preferably, the side of the outermost field plate insulation layer 1072 is connected to the inner side of the groove 1071.

[0036] In this embodiment, preferably, the thickness of the Schottky metal layer 104 is equal to the sum of the thicknesses of the P-type well region 105 and the N-type source region 106.

[0037] like Figure 1 and Figure 6 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 101, A drift layer 102, the lower side of which is connected to the upper side of the silicon carbide substrate 101, and the drift layer 102 is provided with a first groove (not shown) and a second groove 1021; P-shaped region 103, the lower part of which is disposed in the first groove; Schottky metal layer 104, the lower side of which is connected to the upper side of drift layer 102, and the outer side of which is connected to the side of P-type region 103; P-type well region 105, the lower side of which is connected to the upper side of drift layer 102, and the outer side of which is connected to the inner side of Schottky metal layer 104. N-type source region 106, the lower side of which is connected to the upper side of P-type well region 105, and the outer side of which is connected to the inner side of Schottky metal layer 104; A gate insulating dielectric layer 107 is disposed at its lower part within the second groove 1021. The outer side of the gate insulating dielectric layer 107 is connected to the inner side of the P-type well region 105 and the inner side of the N-type source region 106, respectively. A trench 1071 is provided in the gate insulating dielectric layer 107. At least three field plate insulating layers 1072 are provided at the bottom of the trench 1071, and the field plate insulating layers 1072 closer to the middle position are thicker. A gate metal layer 108 is disposed within the trench 1071; Source metal layer 109, the lower side of which is connected to the upper side of N-type source region 106, upper side of Schottky metal layer 104 and upper side of P-type region 103 respectively; And a drain metal layer 110, which is connected to the lower side of the silicon carbide substrate 101.

[0038] In another embodiment of the present invention, both the silicon carbide substrate 101 and the drift layer 102 are N-type; the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 102 is 5-10e15cm. -3 The doping concentration of P-type region 103 is 6-10e17cm. -3 The doping concentration of the P-type well region 105 is 6-10e16cm. -3 The doping concentration of the N-type source region 106 is 2-8e18cm. -3 The gate insulating dielectric layer 107 is a high-k dielectric such as silicon dioxide or hafnium dioxide, the field plate insulating layer 1072 is an insulating material with low process difficulty such as silicon dioxide or silicon nitride, and the Schottky metal layer 104, the gate metal layer 108 and the source metal layer 109 are one or more alloys of copper, nickel and aluminum. The doping concentration of the N-type silicon carbide substrate 101 is to ensure a low-resistance ohmic contact with the drain metal layer 110, thereby reducing the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is mainly to comprehensively consider the device's breakdown voltage and on-resistance. A higher doping concentration results in lower on-resistance but lower breakdown voltage. The doping concentration of the P-type well region 105 is to comprehensively ensure low gate charge, reduce switching losses, improve switching speed, and reduce leakage current. A higher doping concentration in the P-type well region 105 results in lower leakage current but higher gate charge, and vice versa. The doping concentration of P-type region 103 serves three purposes: first, to form pn junction isolation between the gate structures of the cells; second, to form the parasitic pn junction body diode of the device to ensure the freewheeling capability of the device body diode; and third, to form a lateral pn junction breakdown structure near the top of the gate, thereby avoiding the concentration of the electric field at the gate structure. The doping concentration of the N-type source region 106 is to reduce the source resistance of the device; The functions of the field plate insulating layer 1072 are: first, to ensure that the electric field distribution at the bottom of the device can increase the electron concentration on the gate corner side when the device is turned on, thereby reducing the on-resistance of the device; second, to reduce the gate leakage capacitance of the device, thereby improving the switching speed of the device; and third, to increase the insulating layer thickness at the corner of the trench gate in the cell, thereby improving the reliability of the trench gate. The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to ensure support during the device fabrication process; the thickness of the N-type drift layer 102 is 30-50 μm, because this structure can be applied to different withstand voltage ranges of 3KV-5KV, and the withstand voltage range is mainly affected by the thickness of the N-type drift layer. The width of the P-type region 103 is 2μm and the thickness is 10μm. This width, combined with the doping concentration, ensures the contact area between the P-type region 103 and the N-type drift layer 102, thereby enabling the large current freewheeling of the parasitic diode of the device. Its thickness is to ensure the lateral diffusion of the space charge region during reverse breakdown, thereby improving the breakdown voltage of the device and ensuring the gate reliability of the device. The Schottky metal layer 104 has a width of 500 nm and a thickness of 600 nm. Its bottom is flush with the bottom of the P-type well region 105 and its top is flush with the N-type source region 106. The width is to ensure the current capability of the parasitic Schottky diode, and the thickness is to ensure the reverse breakdown voltage characteristic of the device. If the thickness is too large, the breakdown voltage of the Schottky junction will be affected. If the thickness is too small, the current characteristic of the Schottky diode will be affected. The source metal layer 109 has a width of 4μm and a thickness of 300nm. This is to ensure the contact area between the source metal layer 109 and the P-type region 103 and the N-type source region 106, and to reduce the source contact resistance. The N-type source region 106 has a width of 1.5 μm and a thickness of 300 nm. This is to ensure a low ohmic contact resistance with the source metal layer 109 and to ensure current capability. The width of the P-type well region 105 is 1.5 μm and the thickness is 300 nm, which is to ensure the pressure-resistant structure; The gate insulating dielectric layer 107 has a bottom thickness of 100nm and a thickness of 50nm on the left and right sides. This is to ensure the gate control capability of the device. At the same time, the process conditions determine that when the thickness on the left and right sides is 50nm, the thickness of the bottom insulating dielectric layer is 100nm. The gate metal layer 108 has a thickness of 1 μm and a width of 2.3 μm. This is to ensure that the bottom of the gate metal layer 108 is lower than the bottom of the corresponding P-type well regions 105 on the left and right sides, thereby ensuring the gate control capability of the device and ensuring the low resistance of the conductive channel. The field plate insulating layer 1072 comprises three groups, which are symmetrical from left to right. They are all 300nm wide, with a thickness of 100nm on the outermost edge, 300nm on the second edge, and 600nm in the middle. The spacing between each field plate insulating layer 1072 is 200nm. The outermost field plate insulating layer 1072 is in direct contact with the inner side and bottom edge of the gate insulating dielectric layer 107 to ensure the thickness of the insulating dielectric at the corner of the trench gate, thereby improving the gate reliability of the device.

[0039] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS, characterized in that: Includes the following steps: Step 1: Deposit metal on the lower side of the silicon carbide substrate to form a drain metal layer; grow an epitaxial layer on the upper side of the silicon carbide substrate to form a drift layer; Step 2: Form a barrier layer above the drift layer, etch the barrier layer to form vias, and form a P-type region by ion implantation; Step 3: Remove the barrier layer from Step 2 and reform the barrier layer. Etch the barrier layer to form vias. Ion implantation is performed to form a P-type well region. Step 4: Ion implantation to form an N-type source region; Step 5: Remove the barrier layer from Step 3 and reform the barrier layer; etch the barrier layer to form a via; etch the drift layer to form a second groove; oxidize to form a gate insulating dielectric layer, wherein the gate insulating dielectric layer has trenches. Step 6: Remove the barrier layer from Step 5 and reform the barrier layer. Etch the barrier layer to form vias and deposit the field plate insulating layer. Repeat this step until all field plate insulating layers are deposited. There are at least three field plate insulating layers, and the thickness of the field plate insulating layer closer to the center is greater. Step 7: Remove the barrier layer from Step 6, reform the barrier layer, etch the barrier layer to form vias, and deposit the gate metal layer. Step 8: Remove the barrier layer from Step 7 and reform the barrier layer. Etch the barrier layer to form vias and etch the drift layer. Then deposit the Schottky metal layer. Step 9: Remove the barrier layer from Step 8 and reform the barrier layer. Etch the barrier layer to form vias and etch the drift layer. Then deposit the source metal layer, remove the barrier layer, and complete the fabrication.

2. The method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the drift layer is less than that of the P-type region.

3. The method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The number of insulating layers on the field plate is odd, and they are arranged symmetrically on the left and right.

4. The method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The outermost side of the field plate insulation layer is connected to the inner side of the trench.

5. The method for fabricating a high-speed, high-reliability trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the Schottky metal layer is equal to the sum of the thicknesses of the P-type well region and the N-type source region.

6. A high-speed, high-reliability trench-gate silicon carbide VDMOS, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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