Semiconductor device and method of manufacturing the same

Abstract

This application discloses a semiconductor device and its fabrication method, belonging to the field of semiconductor technology. The semiconductor device includes: a substrate comprising an active region and a passive region surrounding the active region; a source and a drain, spaced apart along a first direction in the active region of the substrate; a gate located on the substrate between the source and the drain, wherein the top dimension of the gate in the active region is larger than its bottom dimension, and both the top and bottom dimensions are dimensions along the first direction; and a protective structure located in the passive region of the substrate, situated on opposite sides of the active region along the first direction. This application can reduce the risk of gate damage, prevent electrical failure, and improve the yield and reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and its fabrication method. Background Technology

[0002] In the fabrication of semiconductor devices (such as pHEMT devices), after forming the gate using a mask layer, the mask layer needs to be removed by immersion and rinsing with a solution. However, the gate has a large top dimension and a small bottom dimension. During the removal process, the fluid scouring force of the solution acts directly on the gate, which can easily cause the gate to partially peel off from the substrate or tilt and collapse as a whole, resulting in gate damage and electrical failure, which seriously reduces the yield and reliability of the device. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and a method for fabricating the same, which can reduce the risk of gate damage, avoid electrical failure, and improve the yield and reliability of the device.

[0004] In a first aspect, this application provides a semiconductor device, comprising: The substrate includes an active region and a passive region surrounding the active region; The source and drain electrodes are distributed at intervals along a first direction in the active region of the substrate; A gate is located on the substrate between the source and the drain, wherein the top dimension of the gate in the active region is larger than the bottom dimension, and both the top dimension and the bottom dimension are dimensions in a first direction; The protective structure is located in the passive region of the substrate and on opposite sides of the active region in the first direction.

[0005] According to the semiconductor device of this application, by setting a protective structure in the passive region of the substrate, and the protective structure being located on opposite sides of the active region in the first direction, i.e., the protective structure being located on opposite sides of the gate in the first direction, the impact of fluid on the gate during the removal of the mask layer is effectively dispersed and resisted, thereby improving the structural stability of the gate in the removal process, reducing the risk of gate damage, avoiding gate electrical failure, and improving the yield and reliability of the device. Moreover, the protective structure is located in the passive region of the substrate and is not connected to any active or passive device, so it does not affect the electrical performance of the device.

[0006] According to one embodiment of this application, the gate extends from the active region to the passive region along a second direction, the second direction being perpendicular to the first direction; The protective structure includes a first protective substructure, which extends along the second direction.

[0007] According to one embodiment of this application, the edge of the first protective substructure in the second direction is flush with the same-side edge of the active region, or the edge of the first protective substructure in the second direction extends beyond the same-side edge of the active region.

[0008] According to one embodiment of this application, the protection structure further includes a second protection substructure, which is connected to at least one side of the first protection substructure in the second direction, and the second protection substructure extends along the first direction and overlaps with the active region in the second direction.

[0009] According to one embodiment of this application, the thickness of the protective structure is greater than or equal to half the maximum thickness of the gate, and less than or equal to the maximum thickness of the gate; and / or, The top dimension of the protective structure is less than or equal to the bottom dimension; and / or, The size of the protective structure in the first direction is greater than or equal to the maximum size of the gate in the first direction.

[0010] According to one embodiment of this application, the protective structure is disposed on the same layer as the gate and is made of the same material.

[0011] According to one embodiment of this application, the protective structure may be disposed in the same layer as the source and drain, and made of the same material.

[0012] According to one embodiment of this application, the distance between the protective structure and the source and the drain is greater than 2 micrometers and less than or equal to 10 micrometers.

[0013] According to one embodiment of this application, the protective structure is disposed near the edge of the substrate; or... The passive region of the substrate has a cutting channel, and the protective structure is located close to the cutting channel.

[0014] Secondly, this application provides a method for fabricating a semiconductor device, comprising: A substrate, a source, and a drain are provided. The substrate includes an active region and a passive region disposed around the active region. The source and the drain are distributed at intervals along a first direction in the active region of the substrate. A mask layer is formed covering the substrate, the source electrode, and the drain electrode; A gate is formed on the substrate between the source and the drain through the mask layer; the top dimension of the gate in the active region is larger than the bottom dimension, and both the top dimension and the bottom dimension are dimensions in a first direction; wherein, at the same time as the gate is formed, or before the mask layer is formed, a protective structure is formed in the passive region of the substrate, and the protective structure is located on opposite sides of the active region in the first direction; The mask layer is peeled off.

[0015] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: By setting a protective structure in the passive region of the substrate, and with the protective structure located on opposite sides of the active region in the first direction, i.e., the protective structure located on opposite sides of the gate in the first direction, the impact of fluid on the gate during the stripping of the mask layer is effectively dispersed and resisted, improving the structural stability of the gate during the stripping process, reducing the risk of gate damage, avoiding gate electrical failure, and improving the yield and reliability of the device. Moreover, the protective structure is located in the passive region of the substrate and is not connected to any active or passive device, so it does not affect the electrical performance of the device.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the top views of the semiconductor device provided in the embodiments of this application; Figure 2 This is a cross-sectional view of the semiconductor device provided in the embodiments of this application; Figure 3 This is a second top view of the semiconductor device provided in the embodiments of this application; Figure 4 This is a schematic flowchart of the semiconductor device fabrication method provided in the embodiments of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] The semiconductor devices and their fabrication methods provided in the embodiments of this application are described below with reference to the accompanying drawings.

[0020] Figure 1 This is a top view of the semiconductor device provided in an embodiment of this application. Figure 2 for Figure 1 The cross-sectional view at the dashed line AA'. The semiconductor devices may include HEMT (High Electron Mobility Transistor), pHEMT (Pseudo-High Electron Mobility Transistor), etc., but are not specifically limited here.

[0021] like Figure 1 and Figure 2 As shown, the semiconductor device includes a substrate 1, a source 2, a drain 3, a gate 4, and a protective structure 5.

[0022] The substrate 1 includes an active region 11 and a passive region 12 surrounding the active region 11. The active region 11 is the core region affecting the electrical performance of the device, while the passive region 12 is used to house passive components such as resistors, capacitors, and inductors. The region outside the active region 11 is the passive region 12.

[0023] In some embodiments, substrate 1 may include a substrate, a buffer layer, a channel layer, a barrier layer, and a capping layer stacked sequentially. The channel layer and the barrier layer form a heterojunction, generating piezoelectric polarization and spontaneous polarization effects, thereby forming a two-dimensional electron gas (2DEG) at the heterojunction interface. It should be noted that substrate 1 may also include other film layers, which are not specifically limited here.

[0024] Source 2 and drain 3 are spaced apart along the first direction X in the active region 11 of the substrate 1. There can be one or more source 2 and drain 3. Multiple source 2 and multiple drain 3 can be alternately distributed along the first direction X. The materials of the source 2 and drain 3 can include AuGe / Ni / Au, Au / Ge / Au / Ni / Au, Ti / Al / Ni / Au alloy, Ti / Al / Mo / Au alloy, Ti / Al / Ti / TiN alloy, etc., to reduce contact resistance.

[0025] Gate 4 is located on substrate 1 between source 2 and drain 3. The top dimension of gate 4 in active region 11 is larger than its bottom dimension. Both the top and bottom dimensions are dimensions in the first direction X, that is, the top dimension is the dimension of the top of gate 4 in the first direction X, and the bottom dimension is the dimension of the bottom of gate 4 in the first direction X. The top of gate 4 is the end of gate 4 away from substrate 1, and the bottom of gate 4 is the end of gate 4 close to substrate 1. Gate 4 can be Y-shaped or T-shaped, etc., to achieve a shorter gate length while obtaining low gate resistance, thereby improving the high-frequency characteristics of the device.

[0026] Source 2, drain 3, and gate 4 are located on the same side of substrate 1. Gate 4 is located at least in the active region 11 of substrate 1, and may also extend into the passive region 12 of substrate 1. There may be one or more gates 4. A gate 4 is provided between any two adjacent source 2 and drain 3. The gate 4 may include a Pt / Ti / Pt / Au composite metal layer, etc.

[0027] In some embodiments, the substrate 1 between the source 2 and the drain 3 has a first groove, and the gate 4 is disposed in the first groove.

[0028] The protective structure 5 is located in the passive region 12 of the substrate 1 and on opposite sides of the active region 11 in the first direction X. The protective structure 5 is located outside the source electrode 2 and the drain electrode 3, and is spaced apart from them. The protective structure 5 can extend on the substrate 1 in a direction intersecting the first direction X. There are at least two protective structures 5, with at least one protective structure 5 provided on each opposite side of the active region 11 in the first direction X.

[0029] It should be noted that after forming the gate using a mask layer (such as photoresist), the mask layer needs to be stripped. The unique structure of the gate presents significant challenges in the stripping process. During stripping, heated solutions such as N-methylpyrrolidone (NMP) are used for immersion and rinsing to remove excess metal and the mask layer. During this process, the fluid scouring force of the NMP solution directly acts on the suspended, mechanically unstable gate, especially the gate located at the chip edge, which, lacking the physical shielding and protection of surrounding structures, becomes the area most severely impacted by the fluid. This can easily lead to partial stripping of the gate from the substrate, or overall tilting and collapse, causing gate damage, electrical failure, and severely reducing the yield and reliability of the process. Related technologies attempt to alleviate this problem by optimizing stripping process parameters (such as solution temperature, rinsing pressure, angle, and time), but the effects are limited and may affect the stripping effect of other structures or introduce residues, impacting the electrical performance of the device.

[0030] In this embodiment, a protective structure 5 is provided in the passive region 12 of the substrate 1, and the protective structure 5 is located on opposite sides of the active region 11 in the first direction X. That is, the protective structure 5 is located on opposite sides of the gate 4 in the first direction X. This effectively disperses and resists the impact of fluid on the gate 4 when the mask layer is peeled off, fundamentally solving the problem of the gate 4 being peeled off from the substrate 1 or tilting or collapsing as a whole. In particular, it protects the most vulnerable outer gate, improves the structural stability of the gate 4 in the peeling process, reduces the risk of damage to the gate 4, avoids electrical failure of the gate 4, and improves the yield and reliability of the device. Moreover, the protective structure 5 is located in the passive region 12 of the substrate 1 and is electrically isolated. It is not connected to any active or passive device and has no effect on all key electrical parameters of the device, such as threshold voltage, transconductance, saturation current, and cutoff frequency. That is, it does not affect the electrical performance of the device.

[0031] In some embodiments, such as Figure 1 and Figure 3 As shown, gate 4 extends from active region 11 to passive region 12 along the second direction Y, which is perpendicular to the first direction X. Gate 4 can be located in active region 11 and passive region 12. The top dimension of gate 4 in passive region 12 in the first direction X is smaller than the bottom dimension, and the bottom dimension of gate 4 in passive region 12 in the first direction X is larger than the bottom dimension of gate 4 in active region 11 in the first direction X.

[0032] The gate 4 of the passive region 12 has a larger bottom dimension in the first direction X, and the top dimension of the gate 4 of the passive region 12 is smaller than the bottom dimension, resulting in a more stable structure. It is less affected by fluid impact during the stripping process; that is, the gate 4 of the passive region 12 will not tilt or collapse when subjected to fluid impact. In contrast, the gate 4 of the active region 11 has a smaller bottom dimension in the first direction X, and the top dimension of the gate 4 of the active region 11 is larger than the bottom dimension, resulting in an unstable structure. Therefore, the protective structure 5 is disposed on opposite sides of the active region 11 in the first direction X to disperse and resist the impact of fluid on the gate 4 of the active region 11, thereby improving the structural stability of the gate 4 of the active region 11.

[0033] The protection structure 5 includes a first protection substructure 51, which extends along the second direction Y. The first protection substructure 51 is spaced apart from the source 2 and the drain 3, respectively.

[0034] The gate 4 of the active region 11 has a smaller size (bottom size) in the first direction X. When the gate 4 of the active region 11 is impacted by fluid along the first direction X, the first protective substructure 51 extends along the second direction Y as a barrier, bearing most of the impact force, which greatly reduces the fluid force reaching the inner gate 4, thereby effectively preventing the bottom of the gate 4 from breaking or the whole gate from collapsing, and improving the structural stability of the gate 4 of the active region 11.

[0035] In some embodiments, the edge of the first protective substructure 51 in the second direction Y is flush with the edge on the same side of the active region 11. For example... Figure 1 As shown, the upper edge of the first protective substructure 51 is flush with the upper edge of the active region 11, and / or, the lower edge of the first protective substructure 51 is flush with the lower edge of the active region 11.

[0036] In some embodiments, the edge of the first protective substructure 51 in the second direction Y extends beyond the edge on the same side of the active region 11. For example... Figure 3 As shown, the upper edge of the first protective substructure 51 extends beyond the upper edge of the active region 11, and / or, the lower edge of the first protective substructure 51 extends beyond the lower edge of the active region 11.

[0037] In this embodiment, the first protective substructure 51 extends in the second direction Y, covering the area of ​​the active region 11 in the second direction Y, increasing the protection range of the protective structure 5, further effectively dispersing and resisting the impact force of the fluid when peeling off the mask layer, reducing the fluid impact force reaching the gate 4, and reducing the risk of damage to the gate 4.

[0038] In some embodiments, such as Figure 3 As shown, the protection structure 5 further includes a second protection substructure 52, which is connected to at least one side of the first protection substructure 51 in the second direction Y. The second protection substructure 52 extends along the first direction X and overlaps with the active region 11 in the second direction Y. The second protection substructure 52 is spaced apart from the source 2, drain 3 and gate 4, respectively.

[0039] In this embodiment, the second protective substructure 52 can extend to at least one side of the active region 11 in the second direction Y, further increasing the protection range of the protective structure 5, further effectively dispersing and resisting the impact force of the fluid when peeling off the mask layer, reducing the fluid impact force reaching the gate 4, and reducing the risk of damage to the gate 4.

[0040] In some embodiments, the thickness of the protective structure 5 is greater than or equal to half the maximum thickness of the gate 4, and less than or equal to the maximum thickness of the gate 4. This ensures that the protective structure 5 can effectively disperse and resist the impact force of the fluid during mask layer stripping, greatly reducing the fluid impact force reaching the gate 4 and lowering the risk of damage to the gate 4.

[0041] In some embodiments, the dimension of the protective structure 5 in the first direction X is greater than or equal to the maximum dimension of the gate 4 in the first direction X. This ensures that the protective structure 5 can effectively disperse and resist the impact force of the fluid during mask layer peeling, greatly reducing the fluid impact force reaching the gate 4 and lowering the risk of damage to the gate 4.

[0042] In some embodiments, the material of the protective structure 5 can be a metallic material or an insulating material, as long as the protective structure 5 is formed before the mask layer is removed and is electrically in a floating or grounded state, not connected to any active or passive device, does not participate in the operation of the device, and does not affect the DC and RF performance of the device.

[0043] In some embodiments, the protective structure 5 is disposed on the same layer as the gate 4 and is made of the same material. The protective structure 5 and the gate 4 can be formed in the same process, that is, the gate structure 5 is formed synchronously through the same photolithography and evaporation process steps as the gate 4.

[0044] The protective structure 5 is made of the same material as the gate 4; for example, the protective structure 5 may include a Pt / Ti / Pt / Au composite metal layer, etc. The protective structure 5 has a different morphology than the gate 4; for example, the protective structure 5 may be a solid metal strip to effectively disperse and block fluid impacts.

[0045] When the protection structure 5 and the gate 4 are formed in the same process, the active region 11 of the substrate 1 has a first groove, the passive region 12 of the substrate 1 has a second groove, the second groove is located on opposite sides of the active region 11 in the first direction X, the gate 4 is located in the first groove, and the protection structure 5 is located in the second groove.

[0046] In this embodiment, the protection structure 5 and the gate 4 are formed in the same process, which hardly increases the process complexity and process cost.

[0047] In some embodiments, the protective structure 5 is disposed in the same layer as the source electrode 2 and the drain electrode 3, and is made of the same material. The protective structure 5, the source electrode 2, and the drain electrode 3 can be formed in the same process, that is, the protective structure 5 is formed simultaneously through the same photolithography and evaporation process steps as the source electrode 2 and the drain electrode 3. The protective structure 5 is made of the same material as the source electrode 2 and the drain electrode 3.

[0048] In this embodiment, the protection structure 5 is formed in the same process as the source 2 and the drain 3, which hardly increases the process complexity and process cost.

[0049] In some embodiments, the distance between the protective structure 5 and the source 2 and drain 3 is greater than 2 micrometers and less than or equal to 10 micrometers. When the material of the protective structure 5 is a conductive material, the distance between the protective structure 5 and the source 2 and drain 3 is set to prevent leakage between the protective structure 5 and the source 2 and drain 3.

[0050] In some embodiments, the protective structure 5 is disposed near the edge of the substrate 1. This ensures that the placement of the protective structure 5 does not affect the performance of the device.

[0051] In some embodiments, the passive region 12 of the substrate 1 is provided with a dicing channel, and the protective structure 5 is disposed close to the dicing channel. This ensures that the placement of the protective structure 5 does not affect the performance of the device.

[0052] According to the semiconductor device provided in the embodiments of this application, by setting a protective structure 5 in the passive region 12 of the substrate 1, and the protective structure 5 being located on opposite sides of the active region 11 in the first direction X, that is, the protective structure 5 being located on opposite sides of the gate 4 in the first direction X, the impact of fluid on the gate 4 during the peeling of the mask layer is effectively dispersed and resisted. This fundamentally solves the problem of the gate 4 being peeled off from the substrate 1 or tilting or collapsing as a whole. In particular, it protects the most vulnerable outer gate, improves the structural stability of the gate 4 in the peeling process, reduces the risk of damage to the gate 4, avoids electrical failure of the gate 4, and improves the yield and reliability of the device. Moreover, the protective structure 5 is located in the passive region 12 of the substrate 1 and is electrically isolated. It is not connected to any active or passive device and has no effect on all key electrical parameters of the device, such as threshold voltage, transconductance, saturation current, and cutoff frequency. That is, it does not affect the electrical performance of the device. It is widely applicable to semiconductor devices that use fragile and dense metal structures and peeling processes, and has strong universality.

[0053] Accordingly, this application also provides a method for fabricating a semiconductor device, which can fabricate the semiconductor device described in the above embodiments.

[0054] The method for fabricating a semiconductor device provided in this application includes: A substrate, a source, and a drain are provided. The substrate includes an active region and a passive region disposed around the active region. The source and drain are spaced apart in the active region of the substrate along a first direction. Form a mask layer covering the substrate, source, and drain; A gate is formed on the substrate between the source and drain through a mask layer; the top dimension of the gate in the active region is larger than the bottom dimension, and both the top and bottom dimensions are dimensions in the first direction; wherein, at the same time as the gate is formed, or before the mask layer is formed, a protective structure is formed in the passive region of the substrate, and the protective structure is located on opposite sides of the active region in the first direction. Remove the mask layer.

[0055] The protective structure can be formed simultaneously with the gate or before the mask layer is formed. For example, the protective structure can be formed simultaneously with the source and drain or after the source and drain are formed.

[0056] As an example, such as Figure 4 As shown, the method for fabricating a semiconductor device provided in this application includes steps 110 to 140.

[0057] Step 110: Provide a substrate, a source, and a drain. The substrate includes an active region and a passive region surrounding the active region. The source and drain are spaced apart in the active region of the substrate along a first direction.

[0058] Step 120: Form a mask layer covering the substrate, source, and drain.

[0059] The mask layer may include photoresist. The mask layer may include a first opening and a second opening, the first opening defining the region of the gate and the second opening defining the region of the protective structure.

[0060] Step 130: Form a gate on the substrate between the source and drain through a mask layer, and form a protective structure in the passive region of the substrate. The protective structure is located on opposite sides of the active region in the first direction. The top dimension of the gate of the active region is larger than the bottom dimension, and both the top dimension and the bottom dimension are dimensions in the first direction.

[0061] An electron beam evaporation process is used to form a gate on the substrate between the source and drain through a first opening, while a protective structure is formed in the passive region of the substrate through a second opening.

[0062] Step 140: Peel off the mask layer.

[0063] The structure formed in step 130 is immersed in a hot NMP solution to remove the mask layer. During the stripping process, the protective structure first withstands the fluid impact force flowing towards the inner gate, thereby protecting the gate.

[0064] After the stripping is completed, the protective structure remains in the passive region of the substrate and will not be processed in subsequent processes.

[0065] This embodiment does not change the existing core process steps (photolithography, evaporation, and stripping). It achieves the simultaneous formation of the gate and protection structure by only modifying the photomask pattern design, which increases the process complexity and cost by almost nothing.

[0066] According to the semiconductor device fabrication method provided in the embodiments of this application, by setting a protective structure in the passive region of the substrate, and the protective structure being located on opposite sides of the active region in the first direction, that is, the protective structure being located on opposite sides of the gate in the first direction, the impact of fluid on the gate during the removal of the mask layer is effectively dispersed and resisted, thereby improving the structural stability of the gate in the removal process, reducing the risk of gate damage, avoiding gate electrical failure, and improving the yield and reliability of the device. Moreover, the protective structure is located in the passive region of the substrate and is not connected to any active or passive device, so it does not affect the electrical performance of the device.

[0067] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0068] In the description of this application, "multiple" means two or more.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0070] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized by, include: The substrate includes an active region and a passive region surrounding the active region; The source and drain electrodes are distributed at intervals along a first direction in the active region of the substrate; A gate is located on the substrate between the source and the drain, wherein the top dimension of the gate in the active region is larger than the bottom dimension, and both the top dimension and the bottom dimension are dimensions in the first direction; The protective structure is located in the passive region of the substrate and on opposite sides of the active region in the first direction.

2. The semiconductor device according to claim 1, wherein The gate extends from the active region to the passive region along a second direction, the second direction being perpendicular to the first direction; The protective structure includes a first protective substructure, which extends along the second direction.

3. The semiconductor device according to claim 2, characterized in that, The edge of the first protective substructure in the second direction is flush with the edge of the active region on the same side, or the edge of the first protective substructure in the second direction extends beyond the edge of the active region on the same side.

4. The semiconductor device according to claim 3, characterized in that, The protective structure further includes a second protective substructure, which is connected to at least one side of the first protective substructure in the second direction. The second protective substructure extends along the first direction and overlaps with the active region in the second direction.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the protective structure is greater than or equal to half the maximum thickness of the gate, and less than or equal to the maximum thickness of the gate; and / or, The top dimension of the protective structure is less than or equal to the bottom dimension; and / or, The size of the protective structure in the first direction is greater than or equal to the maximum size of the gate in the first direction.

6. The semiconductor device according to claim 1, characterized in that, The protective structure is disposed in the same layer as the gate and is made of the same material.

7. The semiconductor device according to claim 1, characterized in that, The protective structure is disposed in the same layer as the source and drain electrodes and is made of the same material.

8. The semiconductor device according to claim 1, characterized in that, The distance between the protective structure and the source and drain is greater than 2 micrometers and less than or equal to 10 micrometers.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The protective structure is positioned near the edge of the substrate; or... The passive region of the substrate has a cutting channel, and the protective structure is located close to the cutting channel.

10. A method for fabricating a semiconductor device, characterized in that, include: A substrate, a source, and a drain are provided. The substrate includes an active region and a passive region disposed around the active region. The source and the drain are distributed at intervals along a first direction in the active region of the substrate. A mask layer is formed covering the substrate, the source electrode, and the drain electrode; A gate is formed on the substrate between the source and the drain through the mask layer; the top dimension of the gate in the active region is larger than the bottom dimension, and both the top dimension and the bottom dimension are dimensions in the first direction; wherein, at the same time as the gate is formed, or before the mask layer is formed, a protective structure is formed in the passive region of the substrate, and the protective structure is located on opposite sides of the active region in the first direction; The mask layer is peeled off.

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