Semiconductor device and method for manufacturing semiconductor device
By employing a thin contact layer design with high impurity concentration and low-energy ion implantation in trench semiconductor devices, the warpage problem caused by high-energy implantation was solved, achieving low-energy contact layer and improved electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MITSUBISHI ELECTRIC CORP
- Filing Date
- 2026-01-13
- Publication Date
- 2026-07-31
AI Technical Summary
In structures where the interlayer insulating film is buried together with the gate electrode in a trench, high-energy ion implantation causes semiconductor layer warping and makes it difficult to achieve low-energy formation of the contact layer.
A thin contact layer with high impurity concentration is adopted. The contact layer is formed by low-energy ion implantation, and an interlayer insulating film and gate electrode are buried in the trench to avoid the contact layer from overlapping with the source layer. Appropriate manufacturing process steps are combined to control impurity distribution.
This achieves low-energy formation of the contact layer, suppresses warping of the semiconductor layer, improves electrode adhesion and electrical performance stability, and reduces the threshold voltage and on-resistance of the MOSFET.
Smart Images
Figure CN122497097A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to trench gate semiconductor devices. Background Technology
[0002] Trench gate semiconductor devices are known. For example, Patent Document 1 discloses a structure in which the contact layer connecting the source electrode and the base region is formed to be shallower than the base layer.
[0003] Patent Document 1: Japanese Patent Application Publication No. 2013-214660
[0004] In trench-gate semiconductor devices, a structure has been developed in which an interlayer insulating film covering the gate electrode is buried together with the gate electrode in the trench. This structure can shorten the spacing between semiconductor element cells and reduce the unevenness of the upper surface of the semiconductor layer, thereby improving the adhesion between the semiconductor layer and the electrode.
[0005] When the interlayer insulating film is buried together with the gate electrode in a trench, the trench needs to be formed deeper, and the depths of the base layer, source layer, and contact layer also need to be increased accordingly. In particular, the contact layer needs to have a higher impurity concentration, so ion implantation for forming the contact layer must be performed with high energy. However, high-energy ion implantation can cause warping of the semiconductor layer (wafer). Summary of the Invention
[0006] This disclosure was made to solve the problems mentioned above, and its purpose is to enable low-energy ion implantation for forming the contact layer in a semiconductor device in which the interlayer insulating film and the gate electrode are buried together in a trench.
[0007] The semiconductor device disclosed herein comprises: a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon; a base layer of a second conductivity type formed on a surface portion of the semiconductor layer on the first main surface side; a source layer of the first conductivity type formed on the surface portion of the base layer; a trench penetrating the source layer and the base layer and reaching the drift layer; a gate insulating film formed on the inner surface of the trench; a gate electrode formed on the gate insulating film and embedded in the trench; an interlayer insulating film formed on the gate electrode and embedded in the trench, not covering the upper surface of the source layer; and a contact layer of the second conductivity type formed on the surface portion of the base layer, having a thickness thinner than the thickness of the source layer and a higher impurity concentration than the impurity concentration of the base layer.
[0008] According to this disclosure, it is possible to achieve low-energy ion implantation for forming a contact layer. Attached Figure Description
[0009] Figure 1 This is a diagram showing the structure of the semiconductor device involved in Embodiment 1.
[0010] Figure 2 This is a flowchart illustrating the manufacturing method of the semiconductor device involved in Embodiment 1.
[0011] Figure 3 This is a diagram showing the structure of the semiconductor device involved in Embodiment 2.
[0012] Figure 4 This is a diagram showing the structure of the semiconductor device involved in Embodiment 3.
[0013] Figure 5 This is a diagram showing the structure of the semiconductor device involved in Embodiment 4.
[0014] Figure 6 This is a flowchart illustrating a variation of the manufacturing method of the semiconductor device according to Embodiment 4.
[0015] Figure 7 This is a flowchart illustrating a variation of the manufacturing method of the semiconductor device according to Embodiment 4.
[0016] Figure 8 This is a diagram showing the structure of the semiconductor device involved in Embodiment 5.
[0017] Figure 9 This is a diagram showing the structure of the semiconductor device involved in Embodiment 6.
[0018] Figure 10 This is a diagram showing the structure of the semiconductor device involved in Embodiment 7.
[0019] Figure 11 This is a flowchart illustrating the manufacturing method of the semiconductor device according to Embodiment 7.
[0020] Figure 12 This is a diagram showing the structure of the semiconductor device involved in Embodiment 8.
[0021] Explanation of reference numerals in the attached figures
[0022] 10...Semiconductor layer; 11...Drift layer; 12...Base layer; 13...Source layer; 14...Contact layer; 15...Electrical field mitigation layer; 16...Connection layer; 17...Low resistance layer; 20...Trench; 21...Gate insulating film; 22...Gate electrode; 23...Interlayer insulating film. Detailed Implementation
[0023] In the following embodiments, the first conductivity type is described as N-type and the second conductivity type as P-type, but conversely, the first conductivity type can be described as P-type and the second conductivity type as N-type. Furthermore, N-type with relatively high impurity concentration is denoted as "N+", N-type with relatively low impurity concentration is denoted as "N-", P-type with relatively high impurity concentration is denoted as "P+", and P-type with relatively low impurity concentration is denoted as "P-". Here, the level of impurity concentration in each region is defined by the peak concentration. That is, a region with high (or low) impurity concentration means a region with high (or low) peak impurity concentration.
[0024] <Implementation Method 1>
[0025] Figure 1 This is a diagram illustrating the structure of the semiconductor device according to Embodiment 1. Here, the semiconductor element included in the semiconductor device will be described as a MOSFET. However, the semiconductor element can be any trench-type insulated-gate semiconductor element, such as an IGBT (Insulated Gate Bipolar Transistor) or other element besides a MOSFET.
[0026] like Figure 1 Thus, the semiconductor device according to Embodiment 1 is formed using a semiconductor layer 10 having an N-type drift layer 11. In this embodiment, the semiconductor layer 10 is made of silicon carbide (SiC). Furthermore, Figure 1 The upper surface of the semiconductor layer 10 shown is defined as the "first principal surface," and the surface opposite to the first principal surface in the semiconductor layer 10 is defined as the "second principal surface." Furthermore, in Figure 1 The upper part of semiconductor layer 10 is shown, and the second main surface is not shown. Figure 1 .
[0027] A P-type base layer 12 is formed on the surface portion of the first main surface of the semiconductor layer 10. An N-type source layer 13 and a P-type contact layer 14 are selectively formed on the surface portion of the base layer 12. In this embodiment, when viewed from above, the contact layer 14 appears as an island surrounded by the base layer 12. The impurity concentration of the contact layer 14 is higher than that of the base layer 12. Although the thickness of the contact layer 14 is thinner than that of the source layer 13, the formation region of the contact layer 14 does not overlap with the formation region of the source layer 13, therefore the contact layer 14 is electrically connected to the base layer 12.
[0028] A trench 20 is formed on the first main surface of the semiconductor layer 10, penetrating the source layer 13 and the base layer 12 and reaching the drift layer 11. A gate insulating film 21 is formed on the inner surface of the trench 20. A gate electrode 22 is disposed on the gate insulating film 21 in a manner that is buried within the trench 20. An interlayer insulating film 23 is formed on the gate electrode 22. The interlayer insulating film 23 is buried within the trench 20 and does not cover the upper surface of the source layer 13. Since the source layer 13 needs to have a portion opposite to the gate electrode 22, the source layer 13 is formed deep, such that the bottom of the source layer 13 is located deeper than the bottom of the interlayer insulating film 23.
[0029] Although not shown in the diagram, a source electrode is disposed on the semiconductor layer 10 including the trench 20. The source electrode is connected to the source layer 13 and the contact layer 14. In addition, the source electrode is electrically connected to the base layer 12 through the contact layer 14. The source electrode and the gate electrode 22 are insulated from each other by an interlayer insulating film 23.
[0030] A P-type electric field mitigation layer 15 is formed on the bottom surface of the trench 20. Additionally, a P-type connection layer 16 is formed on one sidewall of the trench 20, electrically connecting the electric field mitigation layer 15 to the base layer 12. The connection layer 16 does not need to be formed continuously along the extension direction of the trench 20, but can be formed locally at certain intervals. When the connection layer 16 is formed locally, it can also be provided on both sides of the trench 20. Alternatively, in order to reduce the on-resistance of the MOSFET, an N-type well layer with a higher impurity concentration than the drift layer 11 can be formed on the portion of the sidewall of the trench 20 where the connection layer 16 is not formed.
[0031] According to the semiconductor device of Embodiment 1, since the thickness of the contact layer 14 is thinner than that of the source layer 13, the contact layer 14 can be formed by ion implantation with relatively low energy. Therefore, warping in the semiconductor layer 10 can be suppressed. In addition, the formation region of the contact layer 14 does not overlap with the formation region of the source layer 13, thereby also achieving the effect of suppressing deviations in the threshold voltage and on-resistance of the MOSFET.
[0032] In this embodiment, an example is shown where the semiconductor layer 10 is made of silicon carbide (SiC), which is known as a wide-bandgap semiconductor. However, the material of the semiconductor layer 10 can also be silicon (Si). Since implanted impurities are difficult to diffuse in SiC, high-temperature heat treatment is required to allow the impurities to diffuse sufficiently. High-temperature heat treatment is also a significant factor causing warpage of the semiconductor layer 10. Therefore, the effect of suppressing warpage of the semiconductor layer 10 caused by ion implantation is particularly effective when the semiconductor layer 10 is made of SiC.
[0033] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor device according to Embodiment 1. Hereinafter, based on... Figure 2 The manufacturing method of the semiconductor device according to Embodiment 1 will be described.
[0034] First, an N-type semiconductor substrate is prepared as the semiconductor layer 10. Then, by performing ion implantation of impurities onto the entire surface of the first main surface of the semiconductor layer 10, a P-type base layer 12 is formed on the surface portion of the first main surface of the semiconductor layer 10 (step S1).
[0035] Next, using photolithography, an implantation mask made of photoresist with an opening in the formation region of the source layer 13 is formed on the first main surface of the semiconductor layer 10 (step S2). Then, by using the implantation mask, ion implantation of impurities is performed to form an N-type source layer 13 on the surface portion of the base layer 12 (step S3).
[0036] Next, a TEOS oxide film is formed on the first main surface of the semiconductor layer 10, and the TEOS oxide film is patterned using photolithography to form an etch mask with an opening in the formation region of the trench 20 (step S4). Then, the trench 20 is formed on the first main surface of the semiconductor layer 10 by etching using the etch mask, penetrating the source layer 13 and the base layer 12 and reaching the drift layer 11 (step S5).
[0037] Next, a TEOS oxide film is formed on the first main surface of the semiconductor layer 10, and the TEOS oxide film is patterned using photolithography to form an implantation mask with an opening in the formation region of the electric field mitigation layer 15 (step S6). Then, ion implantation of impurities is performed using the implantation mask to form a P-type electric field mitigation layer 15 on the bottom surface of the trench 20 (step S7).
[0038] Next, a photoresist is formed on the first main surface of the semiconductor layer 10, and the photoresist is patterned using photolithography to form an implantation mask with an opening in the portion of the trench 20 adjacent to the formation region of the interconnect layer 16 (step S8). Then, ion implantation is performed from an inclined direction using this implantation mask to form a P-type interconnect layer 16 on the sidewall of the trench 20 (step S9). Alternatively, as needed, a voltage-holding structure such as an N-type well layer or a P-type guard ring can be formed on the sidewall of the trench 20 by selective ion implantation based on the same method as in steps S8 and S9.
[0039] Next, a TEOS oxide film is formed on the first main surface of the semiconductor layer 10, and the TEOS oxide film is patterned using photolithography to form an implantation mask with an opening in the formation region of the contact layer 14 (step S10). In this embodiment, the formation region of the contact layer 14 does not overlap with the formation region of the source layer 13. Then, ion implantation of impurities is performed using this implantation mask to form a P-type contact layer 14 on the surface of the base layer 12 (step S11). The ion implantation for forming the electric field mitigation layer 15 and the contact layer 14 is performed at a high temperature (e.g., 200 degrees Celsius), and the implantation mask for the electric field mitigation layer 15 and the implantation mask for the contact layer 14 are formed from a TEOS oxide film instead of a photoresist.
[0040] Furthermore, the N-type region remaining in the semiconductor layer 10 where the base layer 12, source layer 13, contact layer 14, electric field mitigation layer 15, and connection layer 16 have not been formed becomes the drift layer 11.
[0041] Next, a gate insulating film 21 composed of a high-temperature silicon oxide (THO) film is formed on the inner surface of the trench 20 by CVD (Chemical Vapor Deposition) (step S12).
[0042] Next, polysilicon is formed by filling trench 20, and gate electrode 22 is formed by etchback of the polysilicon (step S13).
[0043] Subsequently, a TEOS oxide film is formed on the first main surface of the semiconductor layer 10 in such a way as to cover the gate electrode 22, and the TEOS oxide film on the outside of the trench 20 (the TEOS oxide film on the first main surface) is removed by etching, thereby forming an interlayer insulating film 23 embedded in the trench 20 (step S14).
[0044] Through the above procedures, the task is completed. Figure 1The structure of the semiconductor device shown.
[0045] Furthermore, in the etching process (step S10) of the TEOS oxide film of the implantation mask used to form the contact layer 14, over-etching is used to etch the surface of the semiconductor layer 10 at the region where the contact layer 14 is formed to a depth of tens of nm (specifically, 5 nm or more and 100 nm or less). Therefore, in the semiconductor device according to this embodiment, the upper surface of the contact layer 14 is recessed to a depth of 5 nm or more and 100 nm or less.
[0046] Furthermore, since the formation region of the contact layer 14 does not overlap with the formation region of the source layer 13, in the formation process of the contact layer 14 (step S11), when the contact layer 14 is formed by one ion implantation, the peak value of the impurity concentration of the contact layer 14 appears only once in the depth direction of the semiconductor layer 10.
[0047] <Implementation Method 2>
[0048] Figure 3 This is a diagram illustrating the structure of the semiconductor device according to Embodiment 2. Compared to the structure of Embodiment 1 (…), Figure 1 In Embodiment 2, the semiconductor device is structured such that the contact layer 14 is formed into a stripe shape that is sandwiched between the base layer 12 on both sides and intersects with the trench 20 when viewed from above. The other structures are the same as in Embodiment 1, so descriptions are omitted.
[0049] According to the semiconductor device of Embodiment 2, compared with Embodiment 1, the area of the contact layer 14 can be increased, thereby reducing the connection resistance between the contact layer 14 and the source electrode.
[0050] The semiconductor device described in Embodiment 2 can be used with the manufacturing method described in Embodiment 1. Figure 2 It is formed using the same method.
[0051] <Implementation Method 3>
[0052] Figure 4 This is a diagram illustrating the structure of the semiconductor device according to Embodiment 3. Compared to the structure of Embodiment 1 (…), Figure 1 In Embodiment 3, the semiconductor device has a structure in which the contact layer 14 is formed into an island shape that, when viewed from above, is sandwiched between the source layer 13 in the extension direction of the trench 20 and between the base layer 12 in a direction perpendicular to the extension direction of the trench 20. Other structures are the same as in Embodiment 1, and therefore descriptions are omitted.
[0053] According to the semiconductor device of Embodiment 3, compared with Embodiment 1, the area of the source layer 13 can be increased, thereby reducing the on-resistance of the MOSFET.
[0054] The semiconductor device described in Embodiment 3 can be used with the manufacturing method described in Embodiment 1. Figure 2 It is formed using the same method.
[0055] <Implementation Method 4>
[0056] Figure 5 This is a diagram showing the structure of the semiconductor device according to Embodiment 4. Compared to the structure of Embodiment 1 (… Figure 1 In Embodiment 4, the semiconductor device is structured such that the contact layer 14 is formed as an island surrounded by the source layer 13 when viewed from above. Other structures are the same as in Embodiment 1, and therefore descriptions are omitted.
[0057] According to the semiconductor device of Embodiment 4, compared with Embodiment 3, the area of the source layer 13 can be further increased, thereby reducing the on-resistance of the MOSFET.
[0058] The semiconductor device according to Embodiment 4 can be used with the manufacturing method described in Embodiment 1. Figure 2 It is formed using the same method.
[0059] In addition, such as Figure 6 As shown in the flowchart, the source layer 13 can also be formed using two ion implantation processes: a process of forming a source layer 13 shallower than the contact layer 14 over the entire surface of the semiconductor layer 10 by ion implantation (step S15), and a process of selectively forming a source layer 13 deeper than the contact layer 14 by ion implantation using an implantation mask (step S4). Therefore, even if the implantation mask for the source layer 13 and the implantation mask for the contact layer 14 are misaligned, it is possible to prevent the formation of a gap between the source layer 13 and the contact layer 14.
[0060] Additionally, to prevent the injection mask used for source layer 13 from shifting position relative to the injection mask used for contact layer 14, source layer 13 can also be formed using a self-aligned process. Specifically, as... Figure 7As shown in the flowchart, before the formation of the source layer 13, an implantation mask for the contact layer 14 with an opening is formed in the formation region of the contact layer 14 (step S10). The contact layer 14 is formed by ion implantation using this implantation mask (step S11). Next, polysilicon is deposited to cover the implantation mask for the contact layer 14, and the polysilicon is etched back to form a polysilicon film buried in the opening of the implantation mask for the contact layer 14. Subsequently, when the implantation mask for the contact layer 14 is removed by hydrofluoric acid (HF), a polysilicon film remains on the formation region of the contact layer 14, and this polysilicon film is used as the implantation mask for the source layer 13 (step S2). Then, ion implantation is performed using this implantation mask to form an N-type source layer 13 with a thickness greater than that of the contact layer 14 on the surface portion of the base layer 12 (step S3). According to this method, the positional misalignment of the injection mask used for the source layer 13 and the injection mask used for the contact layer 14 is prevented, and the formation of a gap between the source layer 13 and the contact layer 14 is prevented.
[0061] <Implementation Method 5>
[0062] Figure 8 This is a diagram illustrating the structure of the semiconductor device according to Embodiment 5. Compared to the structure of Embodiment 1 (… Figure 1 In Embodiment 5, the semiconductor device has a structure in which the contact layer 14 is formed into a stripe shape that, when viewed from above, is sandwiched between the source layer 13 on both sides and intersects with the trench 20. The other structures are the same as in Embodiment 1, so descriptions are omitted.
[0063] According to the semiconductor device of Embodiment 5, compared with Embodiment 4, the area of the contact layer 14 can be increased, thereby reducing the connection resistance between the contact layer 14 and the source electrode, and reducing the on-resistance of the MOSFET.
[0064] The semiconductor device according to Embodiment 5 can be used with the manufacturing method described in Embodiment 1. Figure 2 ) or variations of the manufacturing method described in Embodiment 4 ( Figure 6 or Figure 7 It is formed using the same method.
[0065] <Implementation Method 6>
[0066] Figure 9 This is a diagram showing the structure of the semiconductor device according to Embodiment 6. Compared to the structure of Embodiment 1 (… Figure 1The semiconductor device according to Embodiment 6 has a structure in which a low-resistance layer 17 is formed within an electric field mitigation layer 15 located on the bottom surface of the trench 20. The low-resistance layer 17 is formed on the surface portion of the electric field mitigation layer 15 (near the bottom surface of the trench 20), and the impurity concentration distribution in the low-resistance layer 17 in the depth direction of the semiconductor layer 10 is the same as the impurity concentration distribution in the contact layer 14 in the depth direction of the semiconductor layer 10. Other structures are the same as in Embodiment 1, and therefore descriptions are omitted. Furthermore, the low-resistance layer 17 can also be applied to embodiments other than Embodiment 1.
[0067] According to the semiconductor device of Embodiment 6, compared with Embodiment 1, the substantial impurity concentration of the electric field mitigation layer 15 is higher, thus improving the function of the electric field mitigation layer 15 in mitigating the electric field near the bottom surface of the trench 20.
[0068] The semiconductor device according to Embodiment 6 can be manufactured using the same method as described in Embodiment 1. Figure 2 ) or variations of the manufacturing method described in Embodiment 4 ( Figure 6 or Figure 7 The same method is used. However, in the step of forming the implantation mask for the contact layer 14 (step S10), instead of completely filling the trench 20 with the TEOS oxide film, the thickness of the TEOS oxide film is reduced to a degree that allows a nest (void) to be formed in the center of the trench 20. By performing the ion implantation step (step S11) to form the contact layer 14 in this state, the low-resistivity layer 17 and the contact layer 14 can be formed simultaneously. As a result of the simultaneous formation of the contact layer 14 and the low-resistivity layer 17, the impurity concentration distribution in the depth direction of the semiconductor layer 10 becomes the same in the contact layer 14 and the low-resistivity layer 17.
[0069] <Implementation Method 7>
[0070] Figure 10 This is a diagram showing the structure of the semiconductor device according to Embodiment 7. Compared to the structure of Embodiment 4 ( Figure 5 In Embodiment 7, the semiconductor device has a recess on the upper surface of the contact layer 14. The depth of the recess is the degree to which the bottom of the contact layer 14, which is thinner than the source layer 13, is located deeper than the bottom of the source layer 13. Figure 5 Similarly, when viewed from above, the contact layer 14 appears as an island surrounded by the source layer 13. Other structures are the same as in Embodiment 1, therefore descriptions are omitted.
[0071] Figure 11 This is a flowchart illustrating the manufacturing method of the semiconductor device according to Embodiment 7. Compared to the method described in Embodiment 1... Figure 2 Flowchart Figure 11The flowchart omits the process of forming the injection mask for the source layer 13 (step S2), and after the process of forming the injection mask for the contact layer 14 (step S10), an etching process for the formation area of the contact layer 14 is added (step S16).
[0072] Since step S2 is omitted, in step S3, impurity ion implantation is performed on the entire surface of the first main surface of the semiconductor layer 10, and the source layer 13 is formed on the entire surface of the first main surface of the semiconductor layer 10.
[0073] In step S16, the implantation mask used for the contact layer 14 formed in step S10 is used as an etching mask to etch the first main surface of the semiconductor layer 10. This forms a depression on a portion of the upper surface of the region where the contact layer 14 is formed. In this state, ion implantation is performed in the region where the depression is formed (step S11), thereby enabling the formation of the contact layer 14 reaching the base layer 12 below the source layer 13 using relatively low-energy ion implantation. That is, even if a thin contact layer 14 is formed using relatively low-energy ion implantation, the bottom of the contact layer 14 can be located deeper than the bottom of the source layer 13.
[0074] According to the semiconductor device of Embodiment 7, similarly to Embodiment 1, the contact layer 14 can be formed by ion implantation with relatively low energy, thus suppressing warping in the semiconductor layer 10. Furthermore, similarly to Embodiment 4, the area of the source layer 13 can be increased, thus reducing the on-resistance of the MOSFET.
[0075] <Implementation Method 8>
[0076] In embodiment 8, an example of applying embodiment 7 to embodiment 5 is shown. Figure 12 This is a diagram showing the structure of the semiconductor device according to Embodiment 8. Compared to the structure of Embodiment 5 ( Figure 8 In the structure of the semiconductor device according to Embodiment 8, a recess is provided on the upper surface of the contact layer 14. The depth of the recess is the degree to which the bottom of the contact layer 14, which is thinner than the source layer 13, is located deeper than the bottom of the source layer 13. Figure 8 Similarly, when viewed from above, the contact layer 14 appears as stripes sandwiched between the source layer 13 on both sides and intersecting with the trench 20. Other structures are the same as in Embodiment 1, so descriptions are omitted.
[0077] The semiconductor device according to Embodiment 8 can be manufactured using the manufacturing method described in Embodiment 7. Figure 11 )form.
[0078] Since the contact layer 14 can be formed by ion implantation with relatively low energy in the semiconductor device according to Embodiment 8, just like in Embodiment 7, warping in the semiconductor layer 10 can be suppressed. In addition, compared with Embodiment 7, the area of the contact layer 14 can be increased, thereby reducing the connection resistance between the contact layer 14 and the source electrode, and reducing the on-resistance of the MOSFET.
[0079] Furthermore, it is possible to freely combine the various implementation methods, or appropriately modify or omit the various implementation methods.
[0080] <Postscript>
[0081] The various forms disclosed herein will be recorded hereafter as appendices.
[0082] (Note 1) A semiconductor device, wherein,
[0083] have:
[0084] The semiconductor layer has a first main surface and a second main surface opposite to the first main surface, and a drift layer of a first conductivity type is formed thereon.
[0085] The base layer of the second conductivity type is formed on the surface portion of the first main surface side of the semiconductor layer.
[0086] The source layer of the first conductivity type is formed on the surface portion of the base layer;
[0087] The trench penetrates the aforementioned source layer and the aforementioned base layer and reaches the aforementioned drift layer;
[0088] A gate insulating film is formed on the inner surface of the trench;
[0089] A gate electrode is formed on the gate insulating film and embedded in the trench.
[0090] An interlayer insulating film is formed on the gate electrode and buried in the trench, without covering the upper surface of the source layer; and
[0091] The contact layer of the second conductivity type is formed on the surface of the base layer and is thinner than the source layer and has a higher impurity concentration than the base layer.
[0092] (Note 2) In the semiconductor device according to Note 1, wherein,
[0093] When viewed from above, the contact layer appears as an island surrounded by the base layer.
[0094] (Note 3) The semiconductor device according to Note 1, wherein,
[0095] When viewed from above, the contact layer appears as stripes sandwiched between the base layer on both sides and intersecting with the grooves.
[0096] (Note 4) The semiconductor device according to Note 1, wherein,
[0097] When viewed from above, the contact layer appears as an island, sandwiched between the source layer in the direction of the trench's extension and between the base layer in a direction perpendicular to the direction of the trench's extension.
[0098] (Note 5) The semiconductor device according to Note 1, wherein,
[0099] When viewed from above, the aforementioned contact layer appears as an island surrounded by the aforementioned source layer.
[0100] (Note 6) The semiconductor device according to Note 1, wherein,
[0101] When viewed from above, the contact layer appears as stripes sandwiched between the source layer on both sides and intersecting with the trench.
[0102] (Note 7) The semiconductor device according to Note 1, wherein,
[0103] The upper surface of the contact layer is recessed on the first main surface of the semiconductor layer.
[0104] The bottom of the aforementioned contact layer is located deeper than the bottom of the aforementioned source layer.
[0105] (Note 8) The semiconductor device according to Note 7, wherein,
[0106] When viewed from above, the aforementioned contact layer appears as an island surrounded by the aforementioned source layer.
[0107] (Note 9) The semiconductor device according to Note 7, wherein,
[0108] When viewed from above, the contact layer appears as stripes sandwiched between the source layer on both sides and intersecting with the trench.
[0109] (Note 10) The semiconductor device according to any one of Notes 1 to 6, wherein,
[0110] The upper surface of the contact layer is recessed on the first main surface of the semiconductor layer at a depth of 5 nm or more and 100 nm or less.
[0111] (Note 11) The semiconductor device according to any one of Notes 1 to 6, wherein,
[0112] The peak value of the impurity concentration in the aforementioned contact layer appears only once in the depth direction of the aforementioned semiconductor layer.
[0113] (Note 12) The semiconductor device according to any one of Notes 1 to 11, wherein,
[0114] The bottom of the aforementioned source layer is located at a depth deeper than the bottom of the aforementioned insulating film.
[0115] (Note 13) The semiconductor device according to any one of Notes 1 to 12, wherein,
[0116] It also has:
[0117] The electric field mitigation layer of the second conductivity type is formed on the bottom surface of the trench; and
[0118] A low-resistance layer is formed within the electric field mitigation layer located at the bottom surface of the trench, and the impurity concentration distribution in the depth direction of the semiconductor layer is the same as the impurity concentration distribution in the depth direction of the contact layer.
[0119] (Note 14) The semiconductor device according to any one of Notes 1 to 13, wherein,
[0120] The aforementioned semiconductor layer is made of silicon carbide.
[0121] (Appendix 15) A method for manufacturing a semiconductor device, wherein,
[0122] have:
[0123] A process for preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon.
[0124] The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer.
[0125] The process of forming a source layer by ion implantation of impurities of the first conductivity type into the surface portion of the base layer; and
[0126] The process involves ion implantation of the second type of impurities into the surface portion of the base layer to form a contact layer with a higher impurity concentration than the base layer and a thinner thickness than the source layer.
[0127] The formation region of the base layer does not overlap with the formation region of the contact layer.
[0128] (Appendix 16) A method for manufacturing a semiconductor device, wherein,
[0129] have:
[0130] A process for preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon.
[0131] The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer.
[0132] A process of forming a contact layer with a higher impurity concentration than that of the base layer on the surface of the base layer by using a first mask with an opening to implant impurities of the second conductivity type into the base layer.
[0133] The process of forming the second mask on the contact layer formation area by embedding the second mask into the opening of the first mask and removing the first mask; and
[0134] The process involves using the second mask to implant ions of the first conductivity type of impurities into the surface portion of the base layer, thereby forming a source layer with a thickness greater than that of the contact layer.
[0135] (Appendix 17) A method for manufacturing a semiconductor device, wherein,
[0136] have:
[0137] A process for preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon.
[0138] The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer.
[0139] The process of forming a source layer by implanting ions of the first conductivity type of impurities into the surface portion of the base layer.
[0140] The process of forming a depression on a portion of the upper surface of the aforementioned source layer; and
[0141] The process involves ion implantation of the second type of impurities into the region where the aforementioned depressions are formed, thereby forming a contact layer with a higher impurity concentration than the base layer and a thinner thickness than the source layer.
Claims
1. A semiconductor device, characterized in that, have: A semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon; A base layer of the second conductivity type is formed on the surface portion of the first main surface side of the semiconductor layer; The source layer of the first conductivity type is formed on the surface portion of the base layer; The trench penetrates the source layer and the base layer and reaches the drift layer; A gate insulating film is formed on the inner surface of the trench; A gate electrode is formed on the gate insulating film and embedded in the trench; An interlayer insulating film is formed on the gate electrode and buried in the trench, without covering the upper surface of the source layer; as well as The contact layer of the second conductivity type is formed on the surface portion of the base layer, and its thickness is thinner than that of the source layer and its impurity concentration is higher than that of the base layer.
2. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact layer appears as an island surrounded by the base layer.
3. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact layer appears as stripes sandwiched between the base layer on both sides and intersecting with the trench.
4. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact layer appears as an island, sandwiched between the source layer in the direction of the trench's extension and between the base layer in a direction perpendicular to the direction of the trench's extension.
5. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact layer appears as an island surrounded by the source layer.
6. The semiconductor device according to claim 1, characterized in that, When viewed from above, the contact layer appears as stripes sandwiched between the source layer on both sides and intersecting with the trench.
7. The semiconductor device according to claim 1, characterized in that, The upper surface of the contact layer is recessed on the first main surface of the semiconductor layer. The bottom of the contact layer is located deeper than the bottom of the source layer.
8. The semiconductor device according to claim 7, characterized in that, When viewed from above, the contact layer appears as an island surrounded by the source layer.
9. The semiconductor device according to claim 7, characterized in that, When viewed from above, the contact layer appears as stripes sandwiched between the source layer on both sides and intersecting with the trench.
10. The semiconductor device according to any one of claims 1 to 6, characterized in that, The upper surface of the contact layer is recessed at a depth of 5 nm or more and 100 nm or less on the first main surface of the semiconductor layer.
11. The semiconductor device according to any one of claims 1 to 6, characterized in that, The peak value of the impurity concentration in the contact layer appears only once in the depth direction of the semiconductor layer.
12. The semiconductor device according to any one of claims 1 to 11, characterized in that, The bottom of the source layer is located deeper than the bottom of the insulating film.
13. The semiconductor device according to any one of claims 1 to 12, characterized in that, It also has: The electric field mitigation layer of the second conductivity type is formed on the bottom surface of the trench; and A low-resistance layer is formed within the electric field mitigation layer located at the bottom surface of the trench, and the impurity concentration distribution in the depth direction of the semiconductor layer is the same as the impurity concentration distribution in the contact layer in the depth direction of the semiconductor layer.
14. The semiconductor device according to any one of claims 1 to 13, characterized in that, The semiconductor layer is made of silicon carbide.
15. A method for manufacturing a semiconductor device, characterized in that, have: The process of preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon; The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer; The process of forming a source layer by implanting ions of the first conductivity type of impurities into the surface portion of the base layer; as well as The process involves ion implantation of impurities of the second conductivity type into the surface portion of the base layer to form a contact layer with a higher impurity concentration than the base layer and a thinner thickness than the source layer. The formation region of the base layer does not overlap with the formation region of the contact layer.
16. A method for manufacturing a semiconductor device, characterized in that, have: The process of preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon; The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer; A process of forming a contact layer with a higher impurity concentration than the base layer surface portion by ion implantation of the second conductivity type of impurities into the base layer using a first mask with an opening. The process of forming the second mask over the formation area of the contact layer by embedding the second mask into the opening of the first mask and removing the first mask; as well as The process involves using the second mask to implant ions of impurities of the first conductivity type into the surface portion of the base layer, thereby forming a source layer with a thickness greater than that of the contact layer.
17. A method for manufacturing a semiconductor device, characterized in that, have: The process of preparing a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and having a drift layer of a first conductivity type formed thereon; The process of forming a base layer by ion implantation of a second type of impurity into the surface portion of the first main surface of the semiconductor layer; The process of forming a source layer by implanting ions of the first conductivity type of impurities into the surface portion of the base layer; The process of forming a recess on a portion of the upper surface of the source layer; as well as The process involves ion implantation of impurities of the second conductivity type into the region where the depression is formed, thereby forming a contact layer with a higher impurity concentration than the base layer and a thinner thickness than the source layer.