A terminal passivation structure of a power semiconductor device and a method of manufacturing the same

Abstract

This invention relates to a terminal passivation structure for a power semiconductor device, comprising: a semiconductor substrate having a terminal region and an active region, the active region having an internal electrode; a passivation stack covering the semiconductor terminal region, the passivation stack comprising at least a silicon dioxide layer and a silicon nitride layer stacked sequentially; and a polyimide layer disposed above the silicon nitride layer; wherein the polyimide layer has at least one completely removed polyimide region between the chip edge of the semiconductor substrate and the internal electrode, the completely removed polyimide region exposing the underlying silicon nitride layer, dividing the polyimide layer into at least two mutually isolated polyimide segments to block the continuous migration path of moisture along the interface between the silicon nitride layer and the polyimide layer. This structure meets the long-term reliability requirements of SiC power devices under harsh high-voltage and high-humidity conditions.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a terminal passivation structure for a power semiconductor device and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is a wide bandgap semiconductor material with a large bandgap (approximately 3.26 eV) and a critical breakdown electric field strength (approximately 3 × 10⁻⁶ eV). 6 With its outstanding advantages such as high voltage-to-cm (V / cm), high thermal conductivity (approximately 4.9 W / cm·K), and good radiation resistance, SiC-based power semiconductor devices are ideal for fabricating high-voltage power semiconductor devices. Compared with traditional silicon (Si)-based power devices, SiC-based power semiconductor devices can operate stably at higher operating voltages, higher operating temperatures, and higher switching frequencies, making them of significant application value in the field of power electronics.

[0003] Silicon carbide MOSFETs (SiC MOSFETs), representing SiC power devices, have been widely used in electric vehicle (EV / xEV) drive systems, solar inverters, energy storage converters, industrial motor drives, and high-frequency switching power supplies due to their advantages such as high power density, fast switching speed, and low conduction losses. In EV applications, on-board power conversion systems (main drive inverters, on-board chargers (OBCs), DC-DC converters, etc.) need to operate stably for extended periods at bus voltages ranging from 400V to 800V. Simultaneously, vehicles face extreme environments such as heavy rain, high temperatures, and high humidity, creating a typical high-temperature, high-humidity, and high-voltage combined stress environment. To evaluate the long-term reliability of power devices under these application conditions, industry standards employ the High Voltage High Humidity High Temperature Reverse Bias (HV-H3TRB) accelerated life test to simulate the actual service conditions of the devices.

[0004] In the manufacturing of SiC power devices, passivation stacks are typically used to protect the chip surface. A typical passivation stack structure, from bottom to top, includes: a silicon dioxide (SiO2) layer formed by thermal oxidation or chemical vapor deposition, and a silicon nitride (SiN) layer formed by plasma-enhanced chemical vapor deposition (PECVD). At the outermost layer of the passivation stack, a polyimide (PI) film is usually coated as the top protective layer to provide additional mechanical protection and electrical insulation. Due to its excellent heat resistance, electrical insulation, and mechanical toughness, polyimide has become the mainstream choice for passivation protection before packaging power semiconductor devices.

[0005] However, during the HV-H3TRB accelerated reliability testing, researchers discovered a hidden failure mechanism in the passivation layer system of SiC power devices: moisture in the environment undergoes capillary penetration and accumulation along the interface between the silicon nitride layer and the polyimide layer (i.e., the SiN / PI interface), forming a continuous micro-leakage path extending from the chip edge along the SiN / PI interface towards the internal electrodes under a high electric field. The existence of this continuous micro-leakage path induces oxidation of the SiC surface in the field limiting ring (FLR) region at the chip edge, leading to degradation of the terminal withstand voltage. Furthermore, it promotes the electrochemical corrosion and degradation of internal electrodes (such as source and drain metals), ultimately causing device parameter deviations and even failure. Since this micro-leakage path typically generates leakage current in the microampere to nanoampere range, it is difficult to effectively identify using conventional online leakage current monitoring methods; therefore, its harm is insidious and has a long-term cumulative effect.

[0006] Existing technologies address the aforementioned microleakage problem at the SiN / PI interface primarily by adjusting the overall window size of the polyimide (i.e., retracting the polyimide edge entirely into the chip) to reduce its coverage area, thereby decreasing the contact area between the SiN / PI interface and moisture. However, this approach only shortens the total length of the microleakage path and cannot fundamentally cut off the continuous migration pathway of moisture along the interface. Under long-term high-voltage bias conditions, moisture may still gradually penetrate from the edge into the internal electrode region along the remaining continuous interface, resulting in limited improvement in device reliability. Furthermore, excessive retraction of the polyimide weakens the mechanical protection effect on the termination area, affecting the long-term mechanical reliability of the chip.

[0007] Therefore, existing technologies are still insufficient in effectively blocking the micro-drain path at the SiN / PI interface, making it difficult to meet the long-term reliability requirements of SiC power devices under harsh high-voltage and high-humidity conditions. Summary of the Invention

[0008] The purpose of this invention is to provide a terminal passivation structure for power semiconductor devices and its fabrication method, so as to fundamentally cut off the microleakage path of continuous water vapor migration along the silicon nitride / polyimide interface, and significantly improve the long-term reliability of power semiconductor devices under high voltage, high humidity, high temperature reverse bias (HV-H3TRB) test conditions. The technical problem to be solved by this invention is achieved through the following technical solution.

[0009] According to a first aspect of this application, a terminal passivation structure for a power semiconductor device is provided, comprising: A semiconductor substrate having a terminal region and an active region, wherein an internal electrode is disposed in the active region; A passivation stack is applied over the terminal region of the semiconductor substrate, the passivation stack comprising at least a silicon dioxide (SiO2) layer and a silicon nitride (SiN) layer stacked sequentially. A polyimide layer is disposed above the silicon nitride layer; The polyimide layer has at least one polyimide-completely removed region between the chip edge of the semiconductor substrate and the internal electrode. The polyimide-completely removed region exposes the underlying silicon nitride layer and divides the polyimide layer into at least two mutually isolated polyimide segments to block the path of continuous migration of water vapor along the interface between the silicon nitride layer and the polyimide layer.

[0010] Preferably, the polyimide-completely removed region is located above at least a portion of the terminal region, and the width of the polyimide-completely removed region is 20 μm to 100 μm.

[0011] Preferably, the at least two polyimide segments include an edge segment and an inner segment, the edge segment covers the edge side of the chip, the inner segment covers the inner electrode region, the interval between the edge segment and the inner segment forms the polyimide complete removal region, and the number of polyimide segments is 2 to 5.

[0012] Preferably, the polyimide layer has one, two, or more regions where the polyimide is completely removed, dividing the polyimide layer into two or more mutually isolated polyimide segments.

[0013] Preferably, the exposed silicon nitride layer forms an annular blocking band in the polyimide-completely removed region, the annular blocking band surrounding the internal electrode in a top view perpendicular to the surface of the semiconductor substrate.

[0014] Preferably, the terminal region includes a field-limiting ring structure, and the polyimide complete removal region at least covers the region above the field-limiting ring structure.

[0015] According to a second aspect of this application, a method for fabricating the terminal passivation structure of the above-mentioned power semiconductor device is provided, comprising the following steps: A passivation stack is formed on a semiconductor substrate, the passivation stack comprising at least a silicon dioxide layer and a silicon nitride layer formed sequentially, the semiconductor substrate having a terminal region and an active region, the active region having an internal electrode; A polyimide layer is formed over the silicon nitride layer; The polyimide layer is patterned to form at least one polyimide-completely removed region between the chip edge of the semiconductor substrate and the internal electrode, exposing the silicon nitride layer below the polyimide-completely removed region. The polyimide layer is divided into at least two mutually isolated polyimide segments to block the path of continuous migration of water vapor along the interface between the silicon nitride layer and the polyimide layer.

[0016] Preferably, the patterning process employs a photolithographic patterning process, specifically including: spin-coating photoresist onto the polyimide layer; exposing and developing the photoresist to form a patterned mask; using the patterned mask as a shield, dry etching the polyimide layer to form a completely removed polyimide region; and removing the patterned mask.

[0017] Preferably, the patterning process employs a laser windowing process, in which a predetermined area of ​​the polyimide layer is directly removed by a laser to form a completely removed polyimide area; the wavelength of the laser is 355nm to 1064nm, and the pulse energy density is 0.5J / cm² to 5J / cm².

[0018] Preferably, the width of the polyimide-completely removed area is 20 μm to 100 μm; the polyimide layer is formed by spin coating and thermosetting process, with a curing temperature of 200°C to 400°C and a curing time of 30 min to 120 min.

[0019] The embodiments of the present invention have the following advantages: Completely blocking interface microleakage paths: By introducing a polyimide-removed region between the chip edge and the internal electrodes, the originally continuous SiN / PI interface is physically broken. Even if moisture intrudes from the chip edge and accumulates at the local SiN / PI interface, it cannot cross the exposed SiN blocking band to continue migrating towards the internal electrodes. This fundamentally blocks the possibility of moisture forming a continuous conductive microleakage path, significantly extending the device's lifetime under HV-H3TRB accelerated testing.

[0020] Suppress terminal region degradation: The polyimide completely removed region preferably covers the field limiting ring (FLR) region, which can effectively prevent SiC oxidation in the FLR region and electrochemical corrosion of the internal electrodes induced by water vapor accumulation, and significantly improve the long-term stability of the terminal pressure-resistant structure under high pressure, high humidity and high temperature environment.

[0021] Multiple blocking effects are doubled: Compared with the design of a single polyimide completely removed area, the use of a multi-segment interval structure (i.e., setting two or more polyimide completely removed areas) can form multiple series blocking barriers. Even if a single blocking band fails due to local defects, the subsequent blocking bands can still play a protective role, further improving the reliability and redundancy of the structure.

[0022] Good process compatibility and limited cost increase: The terminal passivation structure proposed in this invention is fully compatible with the existing standard manufacturing process of SiC devices. It only requires adjustment of the pattern design based on the conventional patterning process of polyimide (photolithography windowing or laser windowing). No new materials or equipment need to be introduced, and the cost increase is minimal.

[0023] High design flexibility: The width (20μm to 100μm), position and number of polyimide-completely removed regions can be flexibly adjusted according to the terminal design and process capabilities of different devices, with a wide range of applications, and can be promoted to various SiC power devices and silicon-based high voltage power devices. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the terminal passivation structure of a power semiconductor device according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the terminal passivation structure of a power semiconductor device according to Embodiment 2 of the present invention; Figure 3 This is a flowchart illustrating a method for fabricating a terminal passivation structure for a power semiconductor device according to Embodiment 3 of the present invention.

[0025] Figure reference numerals: 1—Semiconductor substrate; 2—Field confinement ring (FLR) structure; 3—Internal electrode; 4—Silicon dioxide (SiO2) layer; 5—Silicon nitride (SiN) layer; 6—Polyimide (PI) layer; 6a—Edge segment; 6b—Internal segment; 6c—Middle segment; 7—Polyimide completely removed region (exposed silicon nitride ring). Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] It should be noted that the above detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] The core idea of ​​this invention is to design the polyimide layer in the terminal region of the power semiconductor device as a discontinuous segmented structure, forming at least one completely removed region between the polyimide segments that exposes the underlying silicon nitride. This exposed silicon nitride region serves as a physical barrier, cutting off the path of continuous migration of moisture along the SiN / PI interface from the chip edge to the internal electrode, thereby effectively suppressing interface microleakage failure under high voltage, high humidity and high temperature (HV-H3TRB) conditions.

[0029] Example 1: Two-segment terminal passivation structure (including a single area where polyimide is completely removed)

[0030] like Figure 1 As shown, this embodiment provides a terminal passivation structure for a SiC MOSFET, including: Semiconductor substrate 1 is an N-type 4H-SiC epitaxial wafer with an epitaxial layer doping concentration of approximately 5 × 10¹. 5 cm -3 The active and termination regions are structured to support power devices. The termination region includes a multi-turn field-limiting ring (FLR) structure 2, typically with 5 to 20 turns, and each FLR has a junction depth of approximately 0.5 μm to 1.5 μm, used to disperse the high electric field at the termination and improve the device breakdown voltage. The internal electrodes 3 include source metal (such as an Al / Ti stack) and drain metal (such as a Ti / Ni / Ag stack), formed on the front and back sides of the active region, respectively.

[0031] In this embodiment, the passivation stack comprises, from bottom to top: Silicon dioxide layer 4: Deposited on the chip surface using plasma-enhanced chemical vapor deposition (PECVD) with a thickness of 800 nm. Process parameters were: deposition temperature 350℃, pressure 800 mTorr, RF power 300 W, precursor gas tetraethyl orthosilicate (TEOS) at a flow rate of 500 sccm, and O2 flow rate of 1000 sccm. After deposition, the film was annealed at 600℃ in a nitrogen atmosphere for 30 min to densify the film and improve its density and insulation properties.

[0032] Silicon nitride layer 5: Continuously deposited on top of the SiO2 layer using PECVD process, with a thickness of 500 nm. Process parameters were: deposition temperature 350℃, pressure 500 mTorr, RF power 200 W, precursor gases SiH4 (flow rate 100 sccm) and NH3 (flow rate 200 sccm), and carrier gas N2 flow rate 500 sccm. The resulting SiN film has a refractive index of approximately 2.0 ± 0.05 (measurement wavelength 633 nm), reflecting its near-stoichiometric composition.

[0033] A polyimide layer 6 is formed on top of the silicon nitride layer 5. The specific steps are as follows: The photosensitive polyimide precursor (PI precursor) is spin-coated onto the wafer surface at a speed of 1500 rpm using a spin coating process. The pre-baking temperature is 100℃ and the time is 3 min. Then, patterned exposure (exposure dose 200 mJ / cm²) and development are performed. Subsequently, it is thermally cured in a nitrogen atmosphere at 300℃ for 60 min to finally form a patterned polyimide layer with a thickness of about 4 μm.

[0034] The key technical feature of this embodiment is that the polyimide layer 6 has a completely removed polyimide region 7 between the chip edge and the internal electrode 3. This completely removed region 7 is located above the FLR termination region 2 and has a width of 50 μm. This completely removed polyimide region 7 divides the polyimide layer 6 into two mutually isolated polyimide segments: an edge segment 6a (covering approximately 100 μm of the outermost edge of the chip) and an internal segment 6b (covering the internal electrode and the area above the active region). In a top-view direction, the completely removed region 7 forms a uniformly wide annular exposed silicon nitride band, surrounding the internal electrode 3, completely severing the continuity of the SiN / PI interface.

[0035] The HV-H3TRB accelerated life test verified that (test conditions: temperature 85℃, relative humidity 85%, drain-source reverse bias voltage of 80% of the device's rated voltage, duration 1000h). Compared with the control group device using a traditional continuous polyimide passivation structure, the drain current increment (ΔI_DSS) of the device in this embodiment was reduced to less than 30% of that of the control group. No failures caused by microleakage at the SiN / PI interface occurred, indicating that the two-segment discontinuous structure has a significant blocking effect on the microleakage path.

[0036] Example 2: Multi-segment spaced terminal passivation structure (including two polyimide completely removed areas)

[0037] This embodiment, based on Embodiment 1, further designs the polyimide layer as a three-segment structure with two completely removed polyimide regions to construct a dual barrier, suitable for applications with higher reliability requirements. See also Figure 2 .

[0038] The materials and process parameters of the semiconductor substrate 1 and the passivation stack (SiO2 layer 4 and SiN layer 5) are the same as those in Example 1.

[0039] The method for forming and patterning the polyimide layer 6 is the same as in Example 1, but the patterning design is different: In this example, two polyimide-completely removed regions 7 are set between the chip edge and the internal electrode 3, forming three mutually isolated polyimide segments, namely: Edge segment 6a: Covers the chip edge side, with a width of approximately 80μm, and its main function is to provide mechanical protection for the chip's cut edges; The middle section 6c is located between the two completely removed areas 7, with a width of about 60μm. It covers the middle section of the FLR terminal area 2 and provides additional insulation protection. Internal segment 6b: Covers the internal electrode 3 and the area above the active region, serving as the main functional protection area, with a thickness of 4μm.

[0040] The widths of the two polyimide-completely removed regions 7 are 40 μm (near the chip edge) and 50 μm (near the internal electrode), respectively. Both are located above the FLR termination region 2, and each forms a complete ring of exposed silicon nitride in the top view direction, together constituting a series of dual blocking barriers.

[0041] According to the HV-H3TRB accelerated life test (test conditions are the same as in Example 1), the three-segment structure device in this example shows a further reduction of drain current increment (ΔI_DSS) of approximately 40% compared to the device in Example 1 (two-segment structure), resulting in a significant improvement in reliability margin. During the 1500-hour extended test, no interface microleakage failure occurred in the device of this example, fully verifying the multiple blocking advantages of the multi-segment spacing structure.

[0042] Comparative example: Continuous polyimide passivation structure

[0043] This comparative example uses a traditional continuous polyimide passivation structure. Compared with Examples 1 and 2, the only difference is that the polyimide layer is continuously distributed from the chip edge to the internal electrode, without any polyimide complete removal region, the SiN layer 5 is completely covered by the continuous polyimide layer above the terminal region, and the SiN / PI interface remains continuous from the chip edge to the internal electrode.

[0044] The HV-H3TRB accelerated life test (test conditions: temperature 85℃, relative humidity 85%, reverse bias voltage 80% of rated voltage) verified that the comparative device showed a significant abnormal increase in drain current (ΔI_DSS exceeding 100% of the initial value) after approximately 600 hours of testing. The failure mechanism was analyzed as follows: moisture migrated from the chip edge to the internal source metal region along the continuous SiN / PI interface, leading to source metal corrosion and degradation. In contrast, the device in Example 1 still showed ΔI_DSS less than 30% of the initial value at the end of the 1000-hour test under the same conditions, and the device in Example 2 showed no failure during the 1500-hour test, fully demonstrating the technical superiority of the discontinuous polyimide passivation structure proposed in this invention.

[0045] Example 3: Preparation method of terminal passivation structure based on laser windowing technology

[0046] This embodiment provides a method for fabricating terminal passivation structures using a laser windowing process. It is applicable to the post-processing modification of full-surface polyimide passivation structures that have already undergone photolithographic patterning, or to the fabrication of polyimide regions requiring complete removal with high-precision dimensional requirements. See also... Figure 3 .

[0047] Step 1, passivation stack formation: SiO2 layer 4 and SiN layer 5 are sequentially formed on the surface of SiC wafer. The process parameters are the same as in Example 1, with SiO2 layer thickness of 600nm and SiN layer thickness of 400nm.

[0048] Step 2, overall coating of polyimide layer: Using a non-photosensitive polyimide precursor, it is coated on the entire wafer surface by spin coating process (1000 rpm, 60 s). After pre-baking at 100℃ for 5 min, it is thermally cured at 370℃ in a nitrogen atmosphere for 90 min to form a complete polyimide layer with a thickness of about 6 μm.

[0049] Step 3, First photolithography windowing: Using conventional photolithography, the polyimide layer is patterned to form ohmic contact windows in the internal electrode area and conventional windows on the outer edge of the chip. Then, dry etching (O2 plasma, power 500W, pressure 80mTorr, etching time determined according to endpoint detection) is performed to remove the polyimide in the window area, while retaining the polyimide coverage of the internal active area and the chip edge.

[0050] Step 4: Laser windowing to form a completely removed polyimide region: An ultraviolet laser (wavelength 355nm, pulse width 10ns, repetition frequency 50kHz) is used to ablate and window the polyimide layer. The laser spot diameter is approximately 20μm. Through multi-channel scanning (10μm spacing between adjacent scan channels), a 50μm wide annular region for complete polyimide removal is formed. The laser pulse energy density is set to 1.5J / cm², which is sufficient to completely remove 4μm to 6μm thick polyimide while maintaining controllable damage to the underlying SiN layer (SiN thinning is less than 20nm, confirmed by ellipsometry measurement).

[0051] After laser windowing is completed, the wafer surface is cleaned (using N-methylpyrrolidone (NMP) solvent for ultrasonic cleaning, followed by rinsing with deionized water and spin-drying) to remove residual carbide polyimide particles from laser ablation and ensure the cleanliness of the exposed SiN surface.

[0052] Step 5, Post-processing: After laser windowing, the wafer is subjected to conventional back-side metallization (Ti / Ni / Ag, with thicknesses of 100nm / 200nm / 300nm respectively, using electron beam evaporation process), followed by sintering metallization (N2 / H2 mixed atmosphere, temperature 380℃, time 2min) to complete the preparation of the entire terminal passivation structure.

[0053] The polyimide-completely removed area formed by the laser windowing process in this embodiment has a regular sidewall morphology (observed by scanning electron microscopy (SEM), the sidewall tilt angle is about 70° to 85°), and the width uniformity deviation is less than ±3μm (3σ), which meets the size requirements of high-precision terminal passivation structure.

[0054] In summary, this invention introduces at least one polyimide-completely removed region in the terminal region of a power semiconductor device, designs the polyimide layer as a discontinuous segmented structure, and utilizes exposed silicon nitride blocking bands to cut off the continuous migration path of moisture at the SiN / PI interface. This effectively suppresses the interface microleakage failure mechanism under high pressure, high humidity, and high temperature conditions, significantly improves the pass rate and device lifetime of SiC power devices in HV-H3TRB accelerated reliability testing, and is fully compatible with existing semiconductor manufacturing processes, thus possessing significant engineering application value.

[0055] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0056] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0057] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0058] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways, such as rotated 90 degrees or in other orientations, and the spatial relative descriptions used herein will be interpreted accordingly.

[0059] In the detailed description above, reference has been made to the accompanying drawings, which form part of this document. In the drawings, similar symbols typically identify similar parts unless the context otherwise indicates otherwise. The illustrated embodiments described in the detailed specification, drawings, and claims are not intended to be limiting. Other embodiments may be used and other changes may be made without departing from the spirit or scope of the subject matter presented herein.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A termination passivation structure of a power semiconductor device, characterized by, include: A semiconductor substrate having a terminal region and an active region, wherein an internal electrode is disposed in the active region; A passivation stack is applied over the terminal region of the semiconductor substrate, the passivation stack comprising at least a silicon dioxide layer and a silicon nitride layer stacked sequentially. A polyimide layer is disposed above the silicon nitride layer; The polyimide layer has at least one polyimide-completely removed region between the chip edge of the semiconductor substrate and the internal electrode. The polyimide-completely removed region exposes the underlying silicon nitride layer and divides the polyimide layer into at least two mutually isolated polyimide segments to block the path of continuous migration of water vapor along the interface between the silicon nitride layer and the polyimide layer.

2. The termination passivation structure of a power semiconductor device according to claim 1, characterized by, The polyimide-completely removed region is located above at least a portion of the terminal region, and the width of the polyimide-completely removed region is 20 μm to 100 μm.

3. The termination passivation structure of a power semiconductor device according to claim 1, characterized by, The at least two polyimide segments include an edge segment and an inner segment, the edge segment covers the edge side of the chip, the inner segment covers the inner electrode region, the interval between the edge segment and the inner segment forms the polyimide complete removal region, and the number of polyimide segments is 2 to 5.

4. The termination passivation structure of a power semiconductor device according to claim 3, characterized by The polyimide layer has one, two, or more regions where the polyimide is completely removed, dividing the polyimide layer into two or more isolated polyimide segments.

5. The termination passivation structure for a power semiconductor device according to claim 1, wherein The exposed silicon nitride layer forms an annular blocking band in the polyimide-completely removed region, the annular blocking band surrounding the internal electrode in a top view perpendicular to the surface of the semiconductor substrate.

6. The terminal passivation structure of claim 1, wherein The terminal region includes a field-limiting ring structure, and the polyimide complete removal region at least covers the region above the field-limiting ring structure.

7. A method of producing a termination passivation structure of a power semiconductor device as claimed in any one of claims 1 to 6, characterized in that Includes the following steps: A passivation stack is formed on a semiconductor substrate, the passivation stack comprising at least a silicon dioxide layer and a silicon nitride layer formed sequentially, the semiconductor substrate having a terminal region and an active region, the active region having an internal electrode; A polyimide layer is formed over the silicon nitride layer; The polyimide layer is patterned to form at least one polyimide-completely removed region between the chip edge of the semiconductor substrate and the internal electrode, exposing the silicon nitride layer below the polyimide-completely removed region. The polyimide layer is divided into at least two mutually isolated polyimide segments to block the path of continuous migration of water vapor along the interface between the silicon nitride layer and the polyimide layer.

8. The preparation method according to claim 7, characterized in that, The patterning process employs a photolithography patterning technique, specifically including: spin-coating photoresist onto the polyimide layer; exposing and developing the photoresist to form a patterned mask; using the patterned mask as a shield, dry etching the polyimide layer to form a completely removed polyimide region; and removing the patterned mask.

9. The preparation method according to claim 7, characterized in that, The patterning process employs a laser windowing technique, which directly removes a predetermined area of ​​the polyimide layer using a laser to form a completely removed polyimide area. The wavelength of the laser is 355nm to 1064nm, and the pulse energy density is 0.5J / cm² to 5J / cm².

10. The preparation method according to claim 7, characterized in that, The width of the polyimide-completely removed area is 20 μm to 100 μm; the polyimide layer is formed by spin coating and thermosetting process, with a curing temperature of 200°C to 400°C and a curing time of 30 min to 120 min.

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