Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle
By designing continuous arc surfaces and thickened insulating layers at the bottom and corners of the gate trench, the problem of easy breakdown of the gate insulating layer is solved, thereby improving the reliability and current conduction performance of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANHUI YOFC ADVANCED SEMICONDUCTOR CO LTD
- Filing Date
- 2026-03-19
- Publication Date
- 2026-07-31
AI Technical Summary
In the prior art, the gate insulating layer of trench gate semiconductor devices is easily broken down under high voltage conditions, mainly because the bottom corner of the gate trench is a sharp right angle, which leads to electric field concentration.
The bottom and corners of the gate trench are designed as continuous arc surfaces bulging toward the second surface, and the thickness of the insulating layer at these locations is increased to be greater than that at the sidewalls. At the same time, P-type doped regions are avoided, and a shallower second region is used to reduce the width of the depletion layer.
It reduces the electric field strength at the bottom and corners of the gate trench, reduces the risk of insulation breakdown, improves the reliability of semiconductor devices, increases on-state current, and reduces on-state resistance.
Smart Images
Figure CN122497100A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology
[0002] The high-voltage operating environment of trench gate semiconductor devices places high demands on the reliability of the gate insulating layer. In related technologies, the bottom corner of the gate trench is a sharp right angle, which leads to electric field concentration in the gate insulating layer at the bottom corner of the gate trench, making the gate insulating layer prone to breakdown. Summary of the Invention
[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which can reduce the electric field strength at the bottom and corners of the gate trench, thereby reducing the risk of the insulating layer being broken down.
[0004] In a first aspect, this application provides a semiconductor device, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other along the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. The semiconductor body is provided with a gate trench extending from the first surface into the semiconductor body. The bottom and bottom corner surfaces of the gate trench are continuous arc surfaces convex toward the second surface. An insulating layer is located at the bottom, bottom corner, and sidewall of the gate trench, wherein the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench. A gate structure is filled in the gate trench; The source electrode is located on the first surface of the semiconductor body; The drain is located on the second surface of the semiconductor body.
[0005] According to the semiconductor device of this application, the bottom and bottom corner surfaces of the gate trench are continuous arc surfaces that bulge towards the second surface, avoiding the bottom corner of the gate trench being a sharp right angle. Furthermore, the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench, thereby reducing the electric field strength at the bottom and bottom corner of the gate trench, reducing the risk of the insulating layer being broken down, and improving the reliability of the semiconductor device.
[0006] According to one embodiment of this application, the thickness of the insulating layer gradually increases in the direction from the bottom edge of the gate trench toward the bottom center.
[0007] According to one embodiment of this application, the interface between the insulating layer at the bottom of the gate trench and the gate structure is a continuous arc surface that bulges toward the first surface.
[0008] According to one embodiment of this application, the semiconductor body further includes a second region having a second conductivity type, the second region extending from the first surface into the semiconductor body; The depth of the second region along the thickness direction is less than or equal to the depth of the gate trench along the thickness direction.
[0009] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other along the thickness direction, the semiconductor body including a first region having a first conductivity type and a well region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, the first region being located on the first surface, and the well region being located on the side of the first region away from the first surface; A gate trench is formed extending from the first surface into the semiconductor body, wherein the bottom and bottom corner surfaces of the gate trench are continuous arc surfaces that convex toward the second surface; An insulating layer is formed at the bottom, bottom corner, and sidewall of the gate trench, wherein the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench. A gate structure is filled in the gate trench; A source electrode is formed on the first surface of the semiconductor body; A drain electrode is formed on the second surface of the semiconductor body.
[0010] According to one embodiment of this application, forming a gate trench extending from the first surface into the semiconductor body includes: An initial gate trench is formed extending from the first surface into the semiconductor body, wherein the bottom surface of the initial gate trench is planar; A doped region is formed covering the bottom and bottom corner of the initial gate trench. The surface of the doped region on the side away from the initial gate trench is a continuous arc surface that convexes toward the second surface, forming the surface at the bottom and bottom corner of the gate trench. The sidewall of the initial gate trench forms the sidewall of the gate trench. The formation of an insulating layer at the bottom, bottom corners, and sidewalls of the gate trench includes: The surface of the gate trench is subjected to thermal oxidation treatment to form the insulating layer at the bottom, bottom corners and sidewalls of the gate trench.
[0011] According to one embodiment of this application, forming a doped region covering the bottom and bottom corners of the initial gate trench includes: A mask layer is formed on the first surface and the surface of the initial gate trench; The mask layer at the bottom of the initial gate trench is thinned. Ion implantation is performed on the bottom of the initial gate trench using the thinned mask layer to form an initial doped region; Remove the mask layer; Ion diffusion is performed on the initial doped region to form a doped region covering the bottom and bottom corners of the initial gate trench.
[0012] According to one embodiment of this application, the doping concentration of the initial doped region is 1×10¹. 5 cm - ³~5×10¹ 6 cm - ³.
[0013] Thirdly, this application provides a power module including a substrate and a semiconductor device as described in the first aspect above, wherein the substrate is used to support the semiconductor device.
[0014] Fourthly, this application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in the first aspect above, the semiconductor device being electrically connected to the circuit board.
[0015] Fifthly, this application provides a vehicle including a load and a power conversion circuit as described in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.
[0016] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: The bottom and corner surfaces of the gate trench are continuous arc surfaces that bulge towards the second surface to avoid the bottom corners of the gate trench being sharp right angles. In addition, the thickness of the insulating layer at the bottom and corners of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench, which reduces the electric field strength at the bottom and corners of the gate trench, reduces the risk of the insulating layer being broken down, and improves the reliability of the semiconductor device. Furthermore, by setting a shallower second region, i.e., the depth of the second region is less than or equal to the depth of the gate trench, the depletion layer width between the second region and the gate trench is reduced, thereby increasing the on-state current and reducing the on-state resistance.
[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 2 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 3 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 4 This is a second schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 5 This is the third schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 6 This is the fourth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 7 This is the fifth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 8 This is the sixth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 9 This is the seventh schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 10 This is the eighth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 11 This is the ninth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 12 This is the tenth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 13 This is eleventh of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 14This is the twelfth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application. Detailed Implementation
[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0020] The following description, with reference to the accompanying drawings, describes the semiconductor device and its fabrication method, power module, power conversion circuit, and vehicle provided in embodiments of this application.
[0021] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. The semiconductor device may be a trench MOSFET semiconductor device.
[0022] like Figure 1 As shown, the semiconductor device provided in this application embodiment includes a semiconductor body 1, an insulating layer 2, a gate structure 3, a source 4, and a drain 5.
[0023] The semiconductor body 1 may include a single semiconductor epitaxial layer 11, or a stacked structure formed by multiple semiconductor epitaxial layers 11. In some embodiments, the semiconductor body 1 may further include a substrate 10, that is, the semiconductor body 1 may include a substrate 10 and at least one semiconductor epitaxial layer 11 formed on one side of the substrate 10. Figure 1 The semiconductor body 1 shown includes a substrate 10 and a semiconductor epitaxial layer 11 formed on one side of the substrate 10.
[0024] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer 11, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer 11. In some embodiments, both the material of the semiconductor epitaxial layer 11 and the material of the substrate 10 can be SiC. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.
[0025] The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. When the semiconductor body 1 includes a substrate 10 and a semiconductor epitaxial layer 11, the second surface S2 is the surface of the substrate 10 away from the semiconductor epitaxial layer 11, and the first surface S1 is the surface of the semiconductor epitaxial layer 11 away from the substrate 10. Figure 1The second surface S2 shown is the bottom surface of the semiconductor body 1, and the first surface S1 is the top surface of the semiconductor body 1.
[0026] The semiconductor body 1 has a first conductivity type, which can be either N-type or P-type. The semiconductor body 1 can be doped with N-type dopant ions to form an N-type semiconductor body; these N-type dopant ions can include P (phosphorus) or N (nitrogen) ions, etc. The semiconductor body 1 can also be doped with P-type dopant ions to form a P-type semiconductor body; these P-type dopant ions can include Al (aluminum) ions or B (boron) ions, etc.
[0027] The semiconductor body 1 includes a first region 14 and a well region 12. The first region 14 is located on a first surface S1, and the well region 12 is located on the side of the first region 14 opposite to the first surface S1. The conductivity type of the well region 12 is a second conductivity type, which is opposite to the first conductivity type. The conductivity type of the first region 14 is the first conductivity type.
[0028] As an example, the semiconductor body 1 is an N-type semiconductor body, that is, the substrate 10 is an N-type substrate, and the semiconductor epitaxial layer 11 is an N-type epitaxial layer. The well region 12 is a P-type well region (PW), and the first region 14 is an N-type doped region, which can also be called an N+ contact region.
[0029] The semiconductor body 1 is provided with a gate trench 13 extending from the first surface S1 into the semiconductor body 1. When the semiconductor body 1 includes a substrate 10 and a semiconductor epitaxial layer 11, the gate trench 13 extends from the first surface S1 into the semiconductor epitaxial layer 11.
[0030] The bottom and corner surfaces of the gate trench 13 are continuous arc surfaces that bulge towards the second surface S2. Specifically, the bottom of the gate trench 13 is located on the side of the gate trench 13 facing away from the first surface S1, and the corner of the gate trench 13 is located at the junction of the bottom and sidewall of the gate trench 13. The bottom and corner surfaces of the gate trench 13 are continuous arc surfaces, which connect to the surface of the sidewall of the gate trench 13.
[0031] Insulating layer 2 is located at the bottom, bottom corners, and sidewalls of gate trench 13, and covers the surface of gate trench 13, including the surfaces at the bottom, bottom corners, and sidewalls of gate trench 13. The thickness of insulating layer 2 at the bottom and bottom corners of gate trench 13 is greater than the thickness of insulating layer 2 at the sidewalls of gate trench 13.
[0032] The thickness of the insulating layer 2 at the sidewall of the gate trench 13 can be the same as the thickness of the insulating layer at the sidewall of the gate trench in related technologies. The thickness of the insulating layer 2 at the bottom of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewall of the gate trench 13, and the thickness of the insulating layer 2 at the bottom corner of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewall of the gate trench 13. The thickness of the insulating layer 2 at the bottom of the gate trench 13 can be greater than, less than, or equal to the thickness of the insulating layer 2 at the bottom corner of the gate trench 13, and is not specifically limited here. The material of the insulating layer 2 may include silicon oxide, etc.
[0033] The gate structure 3 fills the gate trench 13. The insulating layer 2 is located between the gate trench 13 and the gate structure 3, and is used to isolate the gate structure 3 from the semiconductor body 1. The material of the gate structure 3 may include polysilicon, etc.
[0034] The source electrode 4 is located on the first surface S1 of the semiconductor body 1. The source electrode 4 is in contact with the first region 14. The material of the source electrode 3 may include metals such as aluminum, copper, and nickel.
[0035] In some embodiments, the semiconductor device may further include a dielectric layer 6, which is located on the side of the gate structure 3 facing away from the second surface S2 and covers the gate structure 3. A source electrode 4 is also located on the side of the dielectric layer 6 facing away from the semiconductor body 1, i.e., the dielectric layer 6 is located between the source electrode 4 and the gate structure 3, serving to isolate the source electrode 4 from the gate structure 3. The material of the dielectric layer 6 may include silicon oxide, silicon nitride, etc.
[0036] The drain electrode 5 is located on the second surface S2 of the semiconductor body 1. The drain electrode 5 may cover the second surface S2 of the semiconductor body 1. The material of the drain electrode 5 may include metals such as aluminum, copper, and nickel.
[0037] Trench MOSFET semiconductor devices have advantages such as high current density and small cell size. However, the high electric field at the bottom and corners of the gate trench leads to a very high electric field on the insulating layer. In related technologies, the bottom corners of the gate trench are sharp right angles, resulting in concentrated electric field on the insulating layer, which makes it prone to breakdown.
[0038] In this embodiment, the bottom and corner surfaces of the gate trench 13 are continuous arc surfaces that bulge towards the second surface S2, avoiding sharp right angles at the bottom corners of the gate trench 13. Furthermore, the thickness of the insulating layer 2 at the bottom and corners of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewalls of the gate trench 13, thereby reducing the electric field strength at the bottom and corners of the gate trench 13, lowering the risk of the insulating layer 2 being broken down, and thus better protecting the insulating layer 2 and improving the reliability of the semiconductor device.
[0039] In some embodiments, the thickness of the insulating layer 2 gradually increases in the direction from the bottom edge of the gate trench 13 toward the bottom center. The insulating layer 2 at the bottom of the gate trench 13 has the greatest thickness at the bottom center and the smallest thickness at the bottom edge. The thickness of the insulating layer 2 at the bottom edge of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewalls of the gate trench 13.
[0040] The thickness relationship between the insulating layer 2 at the bottom edge of the gate trench 13 and the insulating layer 2 at the bottom corner of the gate trench 13 is not specifically limited, nor is the thickness relationship between the insulating layer 2 at the bottom center of the gate trench 13 and the insulating layer 2 at the bottom corner of the gate trench 13.
[0041] In some embodiments, the interface between the insulating layer 2 at the bottom of the gate trench 13 and the gate structure 3 is a continuous arc surface protruding in the direction of the first surface S1, and the interface between the insulating layer 2 at the bottom of the gate trench 13 and the gate trench 13 is a continuous arc surface protruding in the direction of the second surface S2, so that the thickness of the insulating layer 2 at the center of the bottom of the gate trench 13 is the largest, and the thickness of the insulating layer 2 at the bottom edge of the gate trench 13 is the smallest.
[0042] In some embodiments, the semiconductor body 1 further includes a second region 15 extending from the first surface S1 into the semiconductor body 1. When the semiconductor body 1 includes a substrate 10 and a semiconductor epitaxial layer 11, the second region 15 extends from the first surface S1 into the semiconductor epitaxial layer 11. The source electrode 4 is also in contact with the second region 15.
[0043] The conductivity type of the second region 15 is the second conductivity type. As an example, the second region 15 is a P-type doped region, which can also be called a P+ contact region.
[0044] The depth of the second region 15 along the thickness direction X is less than or equal to the depth of the gate trench 13 along the thickness direction X. The depth of the second region 15 may be the same as the depth of the gate trench 13, or the depth of the second region 15 may be slightly less than the depth of the gate trench 13.
[0045] Related technologies employ a P-type doped region at the bottom of the gate trench to form a shielding layer, thereby reducing the electric field at the bottom of the gate trench. However, this approach can easily reduce the electron conduction path and decrease the on-state current. Furthermore, these technologies also incorporate a source trench in the semiconductor body, with the source trench being deeper than the gate trench, increasing the depletion layer width.
[0046] In this embodiment, there is no need to set a P-type doped region at the bottom of the gate trench, nor is there a need to set a source trench. By setting a shallower second region 15, the depth of the second region 15 can be equal to or slightly less than the depth of the gate trench 13, thereby reducing the depletion layer width between the second region 15 and the gate trench 13, thereby increasing the on-state current and reducing the on-state resistance.
[0047] In some embodiments, the semiconductor device further includes a passivation layer 7, which is located on the side of the source electrode 4 away from the semiconductor body 1. The passivation layer 7 protects the semiconductor device and reduces the impact of the external environment on its performance. For example, the passivation layer 7 can prevent the semiconductor device from reacting with substances such as oxygen and water in the external environment, prevent corrosion of the semiconductor device surface, and extend the lifespan of the semiconductor device. The material of the passivation layer 7 may include silicon oxide, silicon nitride, PI, etc.
[0048] According to the semiconductor device provided in the embodiments of this application, the bottom and corner surfaces of the gate trench 13 are continuous arc surfaces convex toward the second surface S2, avoiding sharp right angles at the bottom corners of the gate trench 13. Furthermore, the thickness of the insulating layer 2 at the bottom and corners of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewalls of the gate trench 13, reducing the electric field strength at the bottom and corners of the gate trench 13 and lowering the risk of the insulating layer 2 being broken down, thereby better protecting the insulating layer 2 and improving the reliability of the semiconductor device. Moreover, by providing a shallower second region 15, the depth of the second region 15 is less than or equal to the depth of the gate trench 13, reducing the depletion layer width between the second region 15 and the gate trench 13, thereby increasing the on-state current and reducing the on-state resistance.
[0049] Accordingly, this application also provides a method for fabricating a semiconductor device.
[0050] Figure 2 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.
[0051] like Figure 2 As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S160.
[0052] Step S110: Provide a semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other along the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region having a second conductivity type. The first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface.
[0053] In some embodiments, combined with Figure 3As shown, the semiconductor body 1 may include a substrate 10 and a semiconductor epitaxial layer 11. First, a substrate 10 is provided, and then the semiconductor epitaxial layer 11 is formed on one side of the substrate 10 in the thickness direction X by methods such as vapor phase epitaxy, liquid phase epitaxy, or solid phase epitaxy. The material of the substrate 10 and the material of the semiconductor epitaxial layer 11 may be the same, or the materials of the substrate 10 and the semiconductor epitaxial layer 11 may be different. In some embodiments, both the material of the semiconductor epitaxial layer 11 and the material of the substrate 10 may be SiC.
[0054] The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. The second surface S2 is the surface of the substrate 10 away from the semiconductor epitaxial layer 11, and the first surface S1 is the surface of the semiconductor epitaxial layer 11 away from the substrate 10.
[0055] Combination Figure 4 As shown, the semiconductor epitaxial layer 11 is doped to form a first region 14, a second region 15, and a well region 12. The first region 14 is located on the first surface S1, the well region 12 is located on the side of the first region 14 facing away from the first surface S1, and the second region 15 extends from the first surface S1 into the semiconductor epitaxial layer 11. Doping can include methods such as ion implantation, ion diffusion, or vapor deposition.
[0056] As an example, plasma-enhanced chemical vapor deposition (PECVD) and photolithography are used to transfer the photomask pattern onto the mask. Then, ion implantation is performed on the semiconductor epitaxial layer to sequentially form a well region 12, a first region 14, and a second region 15. Multiple second regions 15 can be formed, spaced apart. Finally, the mask is removed.
[0057] Specifically, the semiconductor body 1 has a first conductivity type, meaning that both the substrate 10 and the semiconductor epitaxial layer 11 have the first conductivity type. The well region 12 has a second conductivity type, which is the opposite of the first conductivity type. The first region 14 has a first conductivity type, and the second region 15 has a second conductivity type.
[0058] As an example, the semiconductor body 1 is an N-type semiconductor body, that is, the substrate 10 is an N-type substrate, and the semiconductor epitaxial layer 11 is an N-type epitaxial layer. The well region 12 is a P-type well region (PW), the first region 14 is an N-type doped region, which can also be called an N+ contact region. The second region 15 is a P-type doped region, which can also be called a P+ contact region.
[0059] Step S120: Form a gate trench extending from the first surface into the semiconductor body, wherein the bottom and bottom corner surfaces of the gate trench are continuous arc surfaces convex toward the second surface.
[0060] Combination Figures 5 to 11As shown, the gate trench 13 extends from the first surface S1 into the semiconductor epitaxial layer 11. The bottom and bottom corner surfaces of the gate trench 13 are continuous arc surfaces, which are connected to the surfaces of the sidewalls of the gate trench 13.
[0061] In some embodiments, forming a gate trench extending from the first surface into the semiconductor body in step 120 includes: An initial gate trench 13' is formed extending from the first surface S1 into the semiconductor body 1, and the bottom surface of the initial gate trench 13' is a plane. A doped region 16 is formed to cover the bottom and bottom corner of the initial gate trench 13'. The surface of the doped region 16 facing away from the initial gate trench 13' is a continuous arc surface that bulges toward the second surface S2, forming the surface at the bottom and bottom corner of the gate trench 13. The sidewall of the initial gate trench 13' forms the sidewall of the gate trench 13.
[0062] Combination Figure 5 As shown, an etching process is used to etch the semiconductor epitaxial layer 11 to form an initial gate trench 13' that extends from the first surface S1 through the first region 14 and the well region 12 into the semiconductor epitaxial layer 11. The initial gate trench 13' is located between two adjacent second regions 15. The bottom surface of the initial gate trench 13' is planar, and the bottom corners of the initial gate trench 13' can be rounded.
[0063] Then, doped regions 16 are formed at the bottom and bottom corners of the initial gate trench 13' to form the gate trench 13. The surface of the doped region 16 facing away from the initial gate trench 13' forms the bottom and bottom corner surfaces of the gate trench 13, and the surface of the doped region 16 facing away from the initial gate trench 13' is a continuous arc surface, making the bottom and bottom corner surfaces of the gate trench 13 a continuous arc surface. The doped region 16 is located at the bottom and bottom corners of the gate trench 13.
[0064] In some embodiments, a doped region 16 is formed covering the bottom and bottom corners of the initial gate trench 13', including: An initial doped region 16' is formed at the bottom of the initial gate trench 13'; Ion diffusion is performed on the initial doped region 16' to form a doped region 16 covering the bottom and bottom corner of the initial gate trench 13'.
[0065] Specifically, the semiconductor epitaxial layer 11 at the bottom of the initial gate trench 13' is doped to form an initial doped region 16'. The surface of the initial doped region 16' facing away from the initial gate trench 13' is planar. A small amount of uniform diffusion is performed on the ions in the initial doped region 16' to form a doped region 16, making the surface of the doped region 16 facing away from the initial gate trench 13' a continuous arc surface.
[0066] In some embodiments, an initial doped region 16' is formed at the bottom of the initial gate trench 13', including: A mask layer 81 is formed on the surface of the first surface S1 and the initial gate trench 13'; The mask layer 81 at the bottom of the initial gate trench 13' is thinned. Ion implantation is performed on the bottom of the initial gate trench 13' through the thinned mask layer 81 to form the initial doped region 16'; Remove the mask layer 81.
[0067] Combination Figure 6 As shown, a thin film deposition process is used to deposit a mask layer 81 over the entire surface, that is, the mask layer 81 covers the surface of the first surface S1 and the surface of the initial gate trench 13' (including the bottom, bottom corner and sidewall surfaces of the initial gate trench 13').
[0068] Then, combine Figure 7 As shown, a photoresist layer 82 is formed on the side of the mask layer 81 facing away from the semiconductor body 1. The photoresist layer 82 has a photoresist opening 83, which corresponds to the position of the bottom of the initial gate trench 13', that is, the orthographic projection of the photoresist opening 83 on the first surface S1 overlaps with the orthographic projection of the bottom of the initial gate trench 13' on the first surface S1.
[0069] Through the photoresist opening 83, and using a dry etching process, the mask layer 81 at the bottom of the initial gate trench 13' is etched to thin the mask layer 81 at the bottom of the initial gate trench 13'. Figure 8 As shown, the photoresist layer 82 is removed. Then, at room temperature, low-energy, low-dose ion implantation is performed on the semiconductor epitaxial layer 11 at the bottom of the initial gate trench 13' through the thinned mask layer 81 to form an initial doped region 16' at the bottom of the initial gate trench 13'.
[0070] In this process, the mask layer 81 is used to block the ion beam during ion implantation. The thickness of the mask layer 81 at the bottom of the initial gate trench 13' is reduced to decrease its ability to block ions, allowing more ions to penetrate into the semiconductor epitaxial layer 11 and achieve local doping, that is, to achieve doping of the semiconductor epitaxial layer 11 at the bottom of the initial gate trench 13'.
[0071] Then, combine Figure 9 As shown, remove mask layer 81.
[0072] This ensures that the depth and doping concentration of the initial doped region 16' are met. After ion diffusion, the doped region 16' is formed and covers the bottom and corners of the initial gate trench 13', thus forming a gate trench 13 that meets the requirements.
[0073] In some embodiments, ion diffusion is performed on the initial doped region 16', including: Thermal oxidation is performed on the surfaces of the first surface S1 and the initial gate trench 13' to form a sacrificial oxide layer 9 on the surfaces of the first surface and the initial gate trench, while ion diffusion is performed on the initial doped region 16'. 9. Remove the sacrificial oxide layer.
[0074] After forming the well region 12, the first region 14, the second region 15, and the initial gate trench 13' in the semiconductor body 1, damage occurs on the first surface S1 and the surface of the initial gate trench 13' of the semiconductor body 1, affecting device performance. In this embodiment, a thermal oxidation process is used to repair the surfaces of the first surface S1 and the initial gate trench 13', improving surface quality and avoiding impact on device performance.
[0075] Thermal oxidation is a process that oxidizes silicon materials at high temperatures, resulting in the formation of silicon oxide on the surface of the silicon material. (Combined with...) Figure 10 As shown, the surfaces of the first surface S1 and the initial gate trench 13' are subjected to thermal oxidation, during which the damaged layers on the surfaces of the first surface S1 and the initial gate trench 13' are consumed. Furthermore, during the thermal oxidation process, ions in the initial doped region 16' diffuse uniformly in a small amount, causing the doped region 16 formed after diffusion to cover the bottom and bottom corners of the initial gate trench 13'. The surface of the doped region 16 facing away from the initial gate trench 13' is a continuous arc surface, constituting the surfaces at the bottom and bottom corners of the gate trench 13. The doped region 16 is located at the bottom and bottom corners of the gate trench 13.
[0076] Combination Figure 11 As shown, by removing the sacrificial oxide layer 9, the damaged layers on the first surface S1 and the initial gate trench 13' surface are also removed, exposing the undamaged surfaces, thus achieving the repair of the first surface S1 and the initial gate trench 13' surface.
[0077] In some embodiments, the initial doped region 16' is a lightly doped region. For example, the doping concentration of the initial doped region 16' is 1 × 10¹. 5 cm - ³~5×10¹ 6 cm - ³.
[0078] This ensures that after the initial doped region 16' is thermally oxidized, the resulting doped region 16 covers the bottom and corners of the initial gate trench 13', forming a gate trench 13 that meets the requirements.
[0079] The doping concentration of the initial doped region 16' described in the above embodiments is merely exemplary and can be set according to the circumstances in practical applications. This application does not impose any limitations.
[0080] Step S130: An insulating layer is formed at the bottom, bottom corner and sidewall of the gate trench, wherein the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench.
[0081] Combination Figure 12 As shown, the insulating layer 2 covers the surface of the gate trench 13, which includes the bottom, bottom corners, and sidewalls. The thickness of the insulating layer 2 at the sidewalls of the gate trench 13 can be the same as the thickness of the insulating layer at the sidewalls of the gate trench in related technologies. The thickness of the insulating layer 2 at the bottom of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewalls of the gate trench 13, and the thickness of the insulating layer 2 at the bottom corners of the gate trench 13 is greater than the thickness of the insulating layer 2 at the sidewalls of the gate trench 13. The thickness of the insulating layer 2 at the bottom of the gate trench 13 can be greater than, less than, or equal to the thickness of the insulating layer 2 at the bottom corners of the gate trench 13; no specific limitation is made here. The material of the insulating layer 2 may include silicon oxide, etc.
[0082] In some embodiments, forming an insulating layer at the bottom, bottom corner, and sidewalls of the gate trench in step S130 includes: The surface of the gate trench 13 is subjected to thermal oxidation treatment to form an insulating layer 2 at the bottom, bottom corner and sidewall of the gate trench 13.
[0083] The thermal oxidation rate of the doped region 16 at the bottom and corner of the gate trench 13 is greater than that at the sidewall of the gate trench 13, which makes the thickness of the insulating layer 2 at the bottom and corner of the gate trench 13 greater than that at the sidewall of the gate trench 13.
[0084] The silicon material (semiconductor body 1) at the bottom, bottom corners and sidewalls of the gate trench 13 is thermally oxidized to form an insulating layer 2. The insulating layer 2 formed by the thermal oxidation process has a tight bond with the surface of the silicon material and a good film quality, reducing the risk of the insulating layer 2 being broken down.
[0085] Since the bottom and corners of the gate trench 13 have doped regions 16, while the sidewalls of the gate trench 13 do not have doped regions, the thermal oxidation rate at the bottom corners of the gate trench 13 is greater than the thermal oxidation rate at the sidewalls of the gate trench 13. That is, the growth rate of the insulating layer at the bottom corners of the gate trench 13 is greater than the growth rate of the insulating layer at the sidewalls of the gate trench 13. Under the condition that the thickness of the insulating layer at the sidewalls of the gate trench 13 meets the predetermined design, the thickness of the insulating layer 2 formed at the bottom and corners of the gate trench 13 is greater.
[0086] Step S140: Fill the gate structure in the gate trench.
[0087] Combination Figure 13As shown, a thin-film deposition process is used to fill the gate trench 13 with the gate structure 3. An insulating layer 2 is located between the gate trench 13 and the gate structure 3, and is used to isolate the gate structure 3 from the semiconductor body 1. The material of the gate structure 3 may include polysilicon, etc.
[0088] In some embodiments, after forming the gate structure 3, the combination Figure 14 As shown, a dielectric layer 6 is formed on the side of the gate structure 3 away from the second surface S2 using a thin-film deposition process, and the dielectric layer 6 covers the gate structure 3. The material of the dielectric layer 6 may include silicon oxide, silicon nitride, etc.
[0089] Step S150: Form a source electrode on the first surface of the semiconductor body.
[0090] Combination Figure 1 As shown, a source electrode 4 is formed on the first surface S1 of the semiconductor body 1 using a thin-film deposition process. The source electrode 4 is in contact with the first region 14 and the second region 15. The source electrode 4 can also be located on the side of the dielectric layer 6 away from the semiconductor body 1, that is, the dielectric layer 6 is located between the source electrode 4 and the gate structure 3, which is used to isolate the source electrode 4 from the gate structure 3. The material of the source electrode 3 can include metals such as aluminum, copper, and nickel.
[0091] Step S160: Form a drain on the second surface of the semiconductor body.
[0092] Combination Figure 1 As shown, a drain 5 is formed on the second surface S2 of the semiconductor body 1 using a thin-film deposition process. The drain 5 can cover the second surface S2 of the semiconductor body 1. The material of the drain 5 can include metals such as aluminum, copper, and nickel.
[0093] In some embodiments, combined with Figure 1 As shown, the fabrication method further includes forming a passivation layer 7 on the side of the source electrode 4 away from the semiconductor body 1. The passivation layer 7 is used to protect the semiconductor device. The material of the passivation layer 7 may include silicon oxide, silicon nitride, PI, etc.
[0094] In some embodiments, the thickness of the insulating layer 2 gradually increases in the direction from the bottom edge of the gate trench 13 toward the bottom center.
[0095] In some embodiments, the interface between the insulating layer 2 at the bottom of the gate trench 13 and the gate structure 3 is a continuous arc surface that bulges toward the first surface S1.
[0096] In some embodiments, the depth of the second region 15 along the thickness direction X is less than or equal to the depth of the gate trench 13 along the thickness direction X.
[0097] According to the semiconductor device fabrication method provided in this application embodiment, by setting doped regions 16 at the bottom and corners of the gate trench 13, the surfaces at the bottom and corners of the gate trench 13 are set as continuous arc surfaces convex in the direction of the second surface S2, avoiding sharp right angles at the corners of the gate trench 13. Furthermore, the setting of the doped regions 16 causes the growth rate of the insulating layer 2 at the bottom and corners of the gate trench 13 to be greater than the growth rate of the insulating layer 2 on the sidewalls of the gate trench 13. This results in the thickness of the insulating layer 2 at the bottom and corners of the gate trench 13 being greater than the thickness of the insulating layer 2 on the sidewalls of the gate trench 13, reducing the electric field strength at the bottom and corners of the gate trench 13, lowering the risk of the insulating layer 2 being broken down, thus better protecting the insulating layer 2 and improving the reliability of the semiconductor device. Moreover, by setting a shallower second region 15, the depth of the second region 15 being less than or equal to the depth of the gate trench 13, the depletion layer width between the second region 15 and the gate trench 13 is reduced, thereby increasing the on-state current and reducing the on-state resistance.
[0098] Accordingly, this application also provides a power module. The power module includes a substrate and the semiconductor device from any of the above embodiments, wherein the substrate is used to support the semiconductor device.
[0099] For example, a power module can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of an electronic device. A power regulator adjusts the power output to meet the needs of a specific application.
[0100] On the other hand, embodiments of this application also provide a power conversion circuit. The power conversion circuit includes a circuit board and the semiconductor device in any of the above embodiments. The semiconductor device is electrically connected to the circuit board, and the power conversion circuit can be used for current conversion, voltage conversion, or power factor correction.
[0101] For example, the power conversion circuit can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.
[0102] On the other hand, embodiments of this application also provide a vehicle. The vehicle includes a load and the power conversion circuit described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load to supply power to the load.
[0103] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.
[0104] In the description of this application, "multiple" means two or more.
[0105] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0106] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A semiconductor device, characterized by, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other along the thickness direction. The semiconductor body includes a first region having a first conductivity type and a well region having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type. The first region is located on the first surface, and the well region is located on the side of the first region away from the first surface. The semiconductor body is provided with a gate trench extending from the first surface into the semiconductor body. The bottom and bottom corner surfaces of the gate trench are continuous arc surfaces convex toward the second surface. An insulating layer is located at the bottom, bottom corner, and sidewall of the gate trench, wherein the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench. A gate structure is filled in the gate trench; The source electrode is located on the first surface of the semiconductor body; The drain is located on the second surface of the semiconductor body.
2. The semiconductor device according to claim 1, characterized in that, The thickness of the insulating layer gradually increases in the direction from the bottom edge of the gate trench toward the bottom center.
3. The semiconductor device according to claim 1, characterized in that, The interface between the insulating layer at the bottom of the gate trench and the gate structure is a continuous arc surface that bulges toward the first surface.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The semiconductor body further includes a second region having a second conductivity type, the second region extending from the first surface into the semiconductor body; The depth of the second region along the thickness direction is less than or equal to the depth of the gate trench along the thickness direction.
5. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other along the thickness direction, the semiconductor body including a first region having a first conductivity type and a well region having a second conductivity type, the first conductivity type being opposite to the second conductivity type, the first region being located on the first surface, and the well region being located on the side of the first region away from the first surface; A gate trench is formed extending from the first surface into the semiconductor body, wherein the bottom and bottom corner surfaces of the gate trench are continuous arc surfaces that convex toward the second surface; An insulating layer is formed at the bottom, bottom corner, and sidewall of the gate trench, wherein the thickness of the insulating layer at the bottom and bottom corner of the gate trench is greater than the thickness of the insulating layer at the sidewall of the gate trench. A gate structure is filled in the gate trench; A source electrode is formed on the first surface of the semiconductor body; A drain electrode is formed on the second surface of the semiconductor body.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The formation of the gate trench extending from the first surface into the semiconductor body includes: An initial gate trench is formed extending from the first surface into the semiconductor body, wherein the bottom surface of the initial gate trench is planar; A doped region is formed covering the bottom and bottom corner of the initial gate trench. The surface of the doped region facing away from the initial gate trench is a continuous arc surface that convexes toward the second surface, forming the surface at the bottom and bottom corner of the gate trench. The sidewall of the initial gate trench forms the sidewall of the gate trench. The formation of an insulating layer at the bottom, bottom corners, and sidewalls of the gate trench includes: The surface of the gate trench is subjected to thermal oxidation treatment to form the insulating layer at the bottom, bottom corners and sidewalls of the gate trench.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The formation of the doped region covering the bottom and bottom corners of the initial gate trench includes: A mask layer is formed on the first surface and the surface of the initial gate trench; The mask layer at the bottom of the initial gate trench is thinned. Ion implantation is performed on the bottom of the initial gate trench using the thinned mask layer to form an initial doped region; Remove the mask layer; Ion diffusion is performed on the initial doped region to form a doped region covering the bottom and bottom corners of the initial gate trench.
8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The ion diffusion process on the initial doped region includes: Thermal oxidation is performed on the surfaces of the first surface and the initial gate trench to form a sacrificial oxide layer, while ion diffusion is performed on the initial doped region. Remove the sacrificial oxide layer.
9. The method for fabricating a semiconductor device according to claim 7, characterized in that, The initial doped region has a doping concentration of 1 x 1017 5 cm - ³~5 x 1017 6 cm - ³.
10. A power module, characterized in that, Including a substrate and as claimed in claim 1 4. Any of the semiconductor devices described above, wherein the substrate is used to support the semiconductor device.
11. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and as claimed in claim 1.
4. The semiconductor device is electrically connected to the circuit board.
12. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 11, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.