Semiconductor device, method of manufacture, power module, conversion circuit and vehicle

Abstract

This application discloses a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body, comprising opposing first and second surfaces; the first surface includes a cell region first surface and a termination region first surface; the semiconductor body further includes a junction extension region and a first region, the first region being configured with a first conductivity type and located on the termination region first surface; the junction extension region being configured with a second conductivity type, located on the termination region first surface and disposed on the outer surface of the first region; the termination region first surface having an isolation trench, the isolation trench penetrating a portion of the thickness of the junction extension region; a filling layer located in the isolation trench; and a dielectric layer located on the termination region first surface, wherein the fixed charge in the dielectric layer has the same polarity as the fixed charge in the first region. While ensuring high withstand voltage, the sensitivity of the JTE termination structure to injected dose is reduced, its resistance to fixed charge interference is improved, and the electric field distribution is optimized to eliminate local electric field spikes.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] For semiconductor power devices, such as insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, the breakdown voltage is one of the key performance indicators. To improve the breakdown voltage, a termination structure is typically designed around the main junction to alleviate the electric field concentration effect at the junction edge, allowing the depletion layer to expand outward more smoothly. Among these, junction termination extension (JTE) structures have become a widely used termination technology in high-voltage power devices due to their high design flexibility and excellent breakdown voltage efficiency.

[0003] JTE termination structures are typically formed by ion implantation around the main junction, creating a doped region with the same doping type but a lower concentration as the main junction. This structure extends outward through a depletion layer connected to the main junction, thereby reducing the curvature effect at the main junction edge and improving the device's breakdown voltage. However, existing JTE termination structures still face a series of technical challenges in practical applications, limiting further performance improvements and process stability. Because JTE termination structures are sensitive to implantation dose, the doping concentration of the JTE region directly affects the depletion layer's expansion capability; both excessively low and high implantation doses can lead to a decrease in breakdown voltage. Furthermore, during device fabrication, packaging, or long-term operation, fixed charges inevitably are introduced or generated within the dielectric layer on the termination structure surface. These charges disrupt the originally designed charge balance of the JTE region, altering the effective doping concentration and subsequently causing a decrease in breakdown voltage or reliability failure. Furthermore, at the JTE region boundary, the JTE termination structure is prone to forming local electric field spikes due to abrupt changes in doping concentration, junction depth variations, and interface states, limiting its breakdown voltage and inherently posing a potential risk of electric field concentration. Deviations in implanted dose and interference from fixed charges further alter the electric field distribution, making the spike position and intensity highly sensitive to process fluctuations. Under reverse bias, this spike is the first to reach the critical breakdown electric field, leading to premature device breakdown. This results in a clear trade-off between device breakdown voltage and long-term reliability (such as high-temperature reverse bias, high-voltage, high-temperature, and high-humidity reverse bias testing).

[0004] Therefore, how to reduce the sensitivity of the JTE terminal structure to the injected dose, improve its resistance to fixed charge interference, and optimize the electric field distribution to eliminate local electric field spikes while ensuring high withstand voltage has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a semiconductor device, fabrication method, power module, conversion circuit, and vehicle to reduce the sensitivity of the JTE terminal structure to injected dose, improve its resistance to fixed charge interference, and optimize the electric field distribution to eliminate local electric field spikes while ensuring high withstand voltage.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other; wherein the first surface includes a cell region first surface and a terminal region first surface; the semiconductor body further includes a junction extension region and a first region, the first region being configured with a first conductivity type and located on the terminal region first surface; the junction extension region being configured with a second conductivity type, located on the terminal region first surface and disposed on the outer surface of the first region; the first conductivity type is different from the second conductivity type; the terminal region first surface has an isolation trench, the isolation trench penetrating a portion of the thickness of the junction extension region; A filling layer is located in the isolation groove, and the filling layer is made of an electrically insulating material; A dielectric layer is located on the first surface of the terminal region; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region.

[0007] Optionally, the semiconductor further includes a main junction region; the main junction region is configured with a second conductivity type and is located on the first surface of the cell region; The main knot region is in contact with the sidewall of the knot extension region; The concentration of second conductivity type doped ions in the main junction region is greater than the concentration of second conductivity type doped ions in the junction extension region.

[0008] Optionally, the number of the first regions is n, where n is an integer greater than or equal to 2; the n first regions are spaced apart in the direction from the main node region to the node extension region. And / or, the number of the isolation slots is m, where m is an integer greater than or equal to 2; the m isolation slots are spaced apart in the direction from the main junction region to the junction expansion region.

[0009] Optionally, in the direction from the main junction region to the junction expansion region, the first region and the isolation groove are alternately arranged in sequence.

[0010] Optionally, the first surface of the cell region includes an adjacent first sub-region surface and a second sub-region surface; All of the first region is located on the surface of the first sub-region, and all of the isolation grooves are located on the surface of the second sub-region.

[0011] Optionally, in the direction from the main junction region to the junction expansion region, the distance between adjacent first regions and the isolation groove gradually decreases; And / or, in the direction from the main junction region to the junction extension region, the width of the first region gradually increases.

[0012] Optionally, the isolation groove is a multi-level groove including at least two sub-grooves; The filling layer is made of undoped polycrystalline silicon.

[0013] Optionally, the semiconductor device further includes: The source electrode is located on the first surface of the cell region; The drain electrode is located on the second surface of the semiconductor body; The semiconductor body includes a substrate, a first epitaxial layer located on one side of the substrate, and a second epitaxial layer located on the side of the first epitaxial layer away from the substrate; the junction expansion region, the first region, and the isolation trench are all disposed in the second epitaxial layer; the first epitaxial layer is used to form a drift region.

[0014] According to another aspect of this application, a method for fabricating a semiconductor device is provided, comprising: A semiconductor body is formed, and an isolation trench is formed on a first surface of a terminal region of the semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other. The first surface includes a cell region first surface and a terminal region first surface. The semiconductor body also includes a junction extension region and a first region. The first region is configured with a first conductivity type and is located on the first surface of the terminal region. The junction extension region is configured with a second conductivity type, is located on the first surface of the terminal region, and is disposed on the outer surface of the first region. The first conductivity type is different from the second conductivity type. The isolation trench penetrates a portion of the thickness of the junction extension region. A filling layer is formed in the isolation groove, and the material of the filling layer is an electrically insulating material; A dielectric layer is formed on the first surface of the terminal region; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region.

[0015] Optionally, forming an isolation trench on the first surface of the terminal region of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; the first epitaxial layer is used to form the drift region of the semiconductor device; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; An initial junction extension region is formed in the second epitaxial layer; A first region is formed in the initial junction expansion region; The isolation trench is formed on at least one side of the first region; the initial junction expansion region is formed by the first region and the region other than the isolation trench.

[0016] Optionally, the isolation groove is formed on at least one side of the first region, including: A first mask layer is formed on the surface of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a first opening that exposes a predetermined position of the isolation trench; Based on the patterned first mask layer, a first-level sub-trench is formed on the surface of the second epitaxial layer on the side away from the substrate; Using the first mask layer as a mask, multiple etching processes are performed sequentially within the second epitaxial layer to form multiple interconnected sub-trenches; wherein, before each etching process, a first barrier layer with a preset thickness is formed on the sidewall of an existing sub-trench to define a new etching area.

[0017] According to another aspect of this application, a power module is provided, including a substrate and at least one semiconductor device as described in any embodiment of this application, the substrate being used to support the semiconductor device.

[0018] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.

[0019] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0020] This application provides a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body comprising a first surface and a second surface disposed opposite to each other; wherein the first surface includes a cell region first surface and a terminal region first surface; the semiconductor body further includes a junction extension region and a first region, the first region being configured with a first conductivity type and located on the terminal region first surface; the junction extension region being configured with a second conductivity type, located on the terminal region first surface and disposed on the outer surface of the first region; the first conductivity type and the second conductivity type are different; the terminal region first surface has an isolation trench that penetrates a portion of the thickness of the junction extension region; a filling layer located in the isolation trench, the filling layer being made of an electrically insulating material; a dielectric layer located on the terminal region first surface; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region. The technical solution provided in this application, by setting an inversion region (first region) with the opposite conductivity type to the junction extension region and an isolation trench in the junction extension region, effectively shields the interference of fixed charge in the dielectric layer on the effective doping concentration of the JTE region. Therefore, the actual electrical characteristics of the JTE region are closer to the design value, and small deviations in the implanted dose do not significantly affect the breakdown voltage, thus reducing the sensitivity of the JTE terminal to the JTE implanted dose and improving the terminal's charge resistance. In addition, the first region and the isolation trench can also adjust the lateral electric field, making the electric field smoother and avoiding single-point high electric fields, resulting in better terminal stability. Therefore, while ensuring high withstand voltage, the sensitivity of the JTE terminal structure to the implanted dose is reduced, its resistance to fixed charge interference is improved, and the electric field distribution is optimized to eliminate local electric field spikes.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a top view of a semiconductor device provided in an embodiment of this application; Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along line AA1 shown. Figure 3 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application; Figure 4 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application; Figure 5 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application; Figure 6 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application; Figure 7 This is a cross-sectional structural diagram corresponding to step S130 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 8 This is a cross-sectional structural diagram corresponding to step S140 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 9 This is a cross-sectional structural diagram corresponding to step S150 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 10 This is a schematic cross-sectional view of step S160 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 11 This is a schematic cross-sectional view of step S1720 in a method for fabricating a semiconductor device provided in this application embodiment; Figures 12-13 This is a schematic cross-sectional view of step S1730 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 14 This is a schematic cross-sectional view of the semiconductor device fabrication method provided in this application after removing the first mask layer and the first barrier layer; Figure 15 This is a schematic cross-sectional view of step S20 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 16 This is a cross-sectional structural diagram corresponding to step S30 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 17 This is a schematic cross-sectional view of the semiconductor device fabrication method provided in this application after the formation of the interlayer dielectric layer. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0026] This application provides a semiconductor device. Figure 1 This is a top view of a semiconductor device provided in an embodiment of this application. Figure 2 yes Figure 1 The diagram shows a cross-sectional view of the structure along line AA1. The semiconductor device includes: The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other; wherein, the first surface 11 includes a cell region first surface and a terminal region first surface; the semiconductor body 1 also includes a junction extension region 31 and a first region 32, the first region 32 is configured with a first conductivity type and is located on the terminal region first surface; the junction extension region 31 is configured with a second conductivity type, is located on the terminal region first surface and covers the outer surface of the first region 32; the first conductivity type and the second conductivity type are different; the terminal region first surface has an isolation trench that penetrates a portion of the thickness of the junction extension region 31; The filling layer 40 is located in the isolation groove, and the material of the filling layer 40 is an electrically insulating material. The dielectric layer 50 is located on the first surface of the terminal region; the dielectric layer 50 contains fixed charges, and the fixed charges in the dielectric layer 50 have the same polarity as the fixed charges in the first region 32.

[0027] The technical solution provided in this application, by setting an inversion region (first region 32) with the opposite conductivity type to the junction extension region 31 and an isolation trench in the junction extension region 31, can prevent the interference of fixed charges in the dielectric layer 50 on the effective doping concentration of the junction extension region 31. Therefore, the actual electrical characteristics of the junction extension region 31 are closer to the design value, and small deviations in the implanted dose will not significantly affect the breakdown voltage. This reduces the sensitivity of the JTE termination structure to the implanted dose in the junction extension region 31, improving the charge immunity of the termination structure. Furthermore, by combining the first region 32 with the isolation trench, the two work synergistically to achieve double shielding against fixed charges, significantly improving the charge immunity of the termination structure. In addition, the first region 32 and the isolation trench can also adjust the lateral electric field, making the electric field smoother and avoiding single-point high electric fields, resulting in better termination stability. Therefore, this application, while ensuring high withstand voltage, reduces the sensitivity of the JTE termination structure to the implanted dose, improves its resistance to fixed charge interference, and optimizes the electric field distribution to eliminate local electric field spikes.

[0028] The above are the core inventive points of this application. The structure of the semiconductor device will be described in detail below with reference to the accompanying drawings.

[0029] The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer formed on one side of the substrate 10.

[0030] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer. In a specific embodiment of this application, both the material of the semiconductor epitaxial layer and the material of the substrate 10 can be SiC. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0031] In the case where the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer, the second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and the first surface 11 is the surface of the semiconductor epitaxial layer furthest from the substrate 10 away from the substrate 10. The semiconductor body 1 includes a cell portion located in a central region and a terminal portion located in an edge region, with the terminal portion surrounding the cell portion. The cell portion of the semiconductor body 1 is used to fabricate SiC power devices, and the terminal portion of the semiconductor body 1 is used to fabricate the termination structure of SiC power devices. The first surface 11 includes a cell region first surface and a terminal region first surface. The first surface 11 located in the cell portion is the cell region first surface, and the first surface 11 located in the terminal portion is the terminal region first surface. Since the terminal portion surrounds the cell portion, the terminal region first surface surrounds the cell region first surface.

[0032] Figure 2 The semiconductor body 1 in the illustrated structure includes: a substrate 10; a first epitaxial layer 20, configured as a first conductivity type, located on one side of the substrate 10; and a second epitaxial layer 30, configured as a first semiconductor type, located on the side of the first epitaxial layer 20 away from the substrate 10; wherein a first region 32, a junction extension region 31, and an isolation trench are disposed on the second epitaxial layer 30. The semiconductor body 1 also includes a drift region 201, located on the first epitaxial layer 20. The second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and the first surface 11 is the surface of the second epitaxial layer 30 away from the substrate 10. By setting two epitaxial layers and using the second epitaxial layer 30 to form the junction extension region 31, the thickness of the junction extension region 31 is not limited by the ion implantation depth, thereby reducing the fabrication difficulty of the junction extension region 31.

[0033] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type. Figure 2In the structure shown, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the conductivity type of the first region 32 is set to N-type and it is located on the first surface 11. The first region 32 can be a heavily doped region. The conductivity type of the junction extension region 31 is set to P-type, located on the side of the first region 32 away from the first surface 11 and on the sidewall of the first region 32, and extends along the sidewall of the first region 32 to the first surface of the terminal region. The first epitaxial layer 20 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The second epitaxial layer 30 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The junction extension region 31 is formed by implanting P-type dopant ions into the second epitaxial layer 30, and the first region 32 is formed by implanting N-type dopant ions into the junction extension region 31. Furthermore, the concentration of N-type doped ions in the second epitaxial layer 30 can be greater than the concentration of N-type doped ions in the first epitaxial layer 20, thereby forming a current extension region 301 in the semiconductor device. The current extension region 301 can be used to reduce the on-resistance of the semiconductor device.

[0034] In semiconductors, when N-type dopant ions (donor dopant ions, such as phosphorus) and P-type dopant ions (acceptor dopant ions, such as boron) are simultaneously doped in the same region, their effects interact through a "compensation effect." Specifically, the charge carriers (electrons and holes) of the N-type and P-type dopant ions cancel each other out. Free electrons provided by N-type dopant ions fill the holes generated by P-type dopant ions, and the final conductivity type of the material depends on the dopant concentration. If the donor concentration (N-type dopant concentration) is greater than the acceptor concentration (P-type dopant concentration), the material behaves as an N-type semiconductor, with the remaining electrons being the majority carriers; if the acceptor concentration (P-type dopant concentration) is greater than the donor concentration (N-type dopant concentration), the material behaves as a P-type semiconductor, with the remaining holes being the majority carriers; if the concentrations of both dopant ions are equal (complete compensation), the material approaches an intrinsic semiconductor with extremely low conductivity.

[0035] Junction Extension Region 31 (JTE region), as a lightly doped P-type region, contains ionized acceptors (immobile negative charges). Under reverse bias, these negative charges cooperate with the ionized donors (immobile positive charges) in Drift Region 201 to jointly establish a lateral depletion layer, bearing the breakdown voltage. When there is a fixed positive charge in the upper dielectric layer 50, some of the immobile negative charges in JTE region 31 will form electric field lines with the positive charges in the upper dielectric layer 50. This reduces the number of effective negative charges in JTE region 31 used for charge balancing with the positive charges in Drift Region 201. The macroscopic effect is a decrease in the equivalent doping concentration of JTE region 31, causing it to deviate from the optimal charge balance state (equivalent to insufficient doping), which in turn leads to a decrease in breakdown voltage and reliability failure. The technical solution provided in this application provides an N-type inversion region (first region 32) in the junction extension region 31 with the opposite conductivity type to the junction extension region 31. The ionized donors (immovable positive charges) in the first region 32 repel the positive charges in the dielectric layer 50, thereby effectively shielding the interference of the positive charges in the dielectric layer 50 on the effective doping concentration of the junction extension region 31. Furthermore, by providing an isolation trench in the junction extension region 31 and a filling layer 40 made of electrically insulating material in the isolation trench, the formation of electric field lines between the positive charges in the dielectric layer 50 and the negative charges in the junction extension region 31 can be blocked, which can also effectively shield the interference of the positive charges in the dielectric layer 50 on the effective doping concentration of the junction extension region 31. Therefore, by utilizing the synergistic effect of the first region 32 and the isolation trench, the actual electrical characteristics of the junction extension region 31 can be made closer to the design value. Small deviations in the injected dose will not significantly affect the breakdown voltage, thereby reducing the sensitivity of the JTE terminal to the injected dose in the junction extension region 31 and improving the terminal's charge resistance. In addition, the first region 32 and the isolation trench can also adjust the transverse electric field, making the electric field smoother and avoiding the occurrence of single-point high electric fields, thus improving the stability of the terminal.

[0036] Based on this, in this application, the first region 32 is disposed on the first surface of the termination region, and the first region 32 (N+ inversion region) is in direct contact with the dielectric layer 50. Compared with the structure in which the first region 32 is completely enclosed within the junction extension region 31, the structure of this application allows the first region 32 to directly establish a potential barrier on the surface, effectively shielding the interference of fixed charges in the dielectric layer 50 on the effective doping concentration of the junction extension region 31. The enclosed structure is equivalent to the barrier being "weakened" by one layer, and the positive charges in the dielectric layer 50 can still form an electric field with the negative charges in the junction extension region 31 located between the first region 32 and the dielectric layer 50, resulting in a decrease in the shielding effect of the first region 32 and an increase in dose sensitivity. In addition, disposing of the first region 32 on the first surface of the termination region can also reduce the fabrication complexity of the device.

[0037] Based on the above embodiments, refer to Figure 2Optionally, the isolation trench is a multi-level trench including at least two sub-trenches. Compared to a single-level trench, the depth of the isolation trench can be increased, which can further block the formation of electric field lines between the positive charges in the dielectric layer 50 and the negative charges in the junction extension region 31, and prevent the positive charges in the dielectric layer 50 from interfering with the effective doping concentration of the junction extension region 31. The material of the filling layer 40 in the isolation trench can be undoped polysilicon.

[0038] Based on the above embodiments, optionally, the semiconductor also includes a main junction region 33, which is configured as a second conductivity type and located on the first surface of the cell region.

[0039] The main junction region 33 is located on one side of the junction extension region 31, and its sidewall is in contact with the sidewall of the junction extension region 31. The concentration of second conductivity type doped ions in the main junction region 33 is greater than that in the junction extension region 31. The main junction region 33 is used to form the main junction of the semiconductor power device with the drift region 201. The main junction is the basic PN junction in the semiconductor power device used to withstand reverse voltage. It is the core structure for the device to achieve voltage withstand capability. When a reverse voltage is applied, the depletion layer extends outward from the edge of the main junction region 33 and gradually enters the JTE region.

[0040] Based on the above embodiments, optionally, the number of first regions 32 is n, where n is an integer greater than or equal to 2; n first regions 32 are spaced apart in the direction from the main junction region 33 to the junction expansion region 31; and / or, the number of isolation slots is m, where m is an integer greater than or equal to 2; m isolation slots are spaced apart in the direction from the main junction region 33 to the junction expansion region 31.

[0041] Specifically, the semiconductor body 1 includes at least two spaced first regions 32; or, the first surface of the terminal region has at least two spaced isolation trenches; or, the semiconductor body 1 includes at least two spaced first regions 32, and the first surface of the terminal region has at least two spaced isolation trenches. Figure 2 The illustrated structure exemplifies the use of three first regions 32 and two isolation trenches. Compared to having only a single first region 32, multiple first regions 32 can control the potential distribution on the surface of the junction extension region 31 over a wider range, reducing the influence of positive charges in the dielectric layer 50 on the doping concentration of the junction extension region 31. Similarly, compared to having only a single isolation trench, multiple isolation trenches can also control the potential distribution on the surface of the junction extension region 31 over a wider range, reducing the influence of positive charges in the dielectric layer 50 on the doping concentration of the junction extension region 31.

[0042] Based on the above embodiments, refer to Figure 2 and Figure 3Optionally, in the direction from the main junction region 33 to the junction extension region 31, the first region 32 and the isolation groove are alternately arranged. Figure 2 An example is shown where the first region 32 is closest to the main junction region 33; Figure 3 An example is shown where the isolation trench is closest to the main junction region 33. In other embodiments of this application, the first surface of the cell region includes an adjacent first sub-region surface and a second sub-region surface; all of the first region 32 is located on the first sub-region surface, and all of the isolation trenches are located on the second sub-region surface; this can be configured according to actual needs.

[0043] Optional, see reference Figure 4 and Figure 5 When the first region 32 and the isolation groove are alternately arranged in sequence, in the direction from the main junction region 33 to the junction expansion region 31, the distance between adjacent first regions 32 and the isolation groove gradually decreases, and / or the width of the first region 32 gradually increases.

[0044] Specifically, in the direction from the main junction region 33 to the junction expansion region 31, the lateral distance between the first region 32 and the isolation trench gradually decreases. That is, near the main junction region 33, the distance between the first region 32 and the trench is larger; near the boundary of the junction expansion region 31, the distance between the first region 32 and the trench is smaller. (Reference) Figure 4 Taking the closest isolation trench to the main junction region 33 as an example, with 3 isolation trenches and 2 first regions 32, the spacing S1 between the first isolation trench and the first first region 32 is smaller than the spacing S2 between the first first region 32 and the second isolation trench; the spacing S2 between the first first region 32 and the second isolation trench is smaller than the spacing S3 between the second isolation trench and the second first region 32; and the spacing S3 between the second isolation trench and the second first region 32 is smaller than the spacing S4 between the second first region 32 and the third isolation trench. Near the main junction region 33, the electric field strength is higher, and the depletion layer expands more violently. The larger spacing allows the junction expansion region 31 sufficient space to buffer the electric field at the edge of the main junction. As the junction expansion region 31 approaches its boundary, the electric field strength gradually decreases. At this point, narrowing the spacing between the inversion region and the trench can progressively compress the lateral width of the potential drop. This gradual spacing design makes the lateral electric field distribution more natural and smooth, reducing the peak electric field.

[0045] In the direction from the main junction region 33 to the junction extension region 31, the width of the first region 32 gradually increases. That is, the first region 32 is narrower near the main junction region 33 and wider near the boundary of the junction extension region 31. (Reference) Figure 5Taking the region closest to the main junction region 33 as the first region 32, and with two isolation slots and three first regions 32, the width W1 of the first first region 32 is smaller than the width W2 of the second first region 32, and the width W2 of the second first region 32 is smaller than the width W3 of the third first region 32. Near the boundary of the junction extension region 31, the depletion layer extends to the end, and the control of the surface potential is particularly important; the wider first region 32 provides a larger shielding area, effectively suppressing potential fluctuations caused by fixed charges or interface states at the boundary; this gradual spacing design can also make the electric field distribution more natural and smooth, reducing the electric field peak.

[0046] Based on the above embodiments, refer to Figures 1-5 Optionally, the semiconductor device also includes: Interlayer insulation layer 60 is located on the side of dielectric layer 50 away from the second surface 12; The source electrode S is located on the first surface of the cell region; The drain electrode D is located on the second surface 12 of the semiconductor body 1.

[0047] This application also provides a method for fabricating a semiconductor device, used to prepare the semiconductor device described in any embodiment of this application. Figure 6 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 6 The methods for fabricating semiconductor devices include: S10. A semiconductor body is formed, and an isolation trench is formed on the first surface of the terminal region of the semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other. The first surface includes a cell region first surface and a terminal region first surface. The semiconductor body also includes a junction extension region and a first region. The first region is configured with a first conductivity type and is located on the first surface of the terminal region. The junction extension region is configured with a second conductivity type, is located on the first surface of the terminal region and is disposed on the outer surface of the first region. The first conductivity type is different from the second conductivity type. The isolation trench penetrates a portion of the thickness of the junction extension region.

[0048] S20. A filling layer is formed in the isolation groove, and the material of the filling layer is an electrically insulating material.

[0049] S30. A dielectric layer is formed on the first surface of the terminal region; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region.

[0050] The technical solution provided in this application forms an inversion region (first region 32) with opposite conductivity type and an isolation trench in the junction extension region 31. The first region 32 and the isolation trench effectively shield the interference of the fixed charge of the dielectric layer 50 on the effective doping concentration of the JTE region. Therefore, the actual electrical characteristics of the JTE region are closer to the design value, and small deviations in the implanted dose do not significantly affect the breakdown voltage. This reduces the sensitivity of the JTE terminal to the JTE implanted dose, improving the terminal's charge immunity. Furthermore, by combining the first region 32 with the isolation trench, the two work synergistically to achieve double shielding against fixed charges, significantly improving the terminal structure's resistance to charge interference. In addition, the first region 32 and the isolation trench can also adjust the transverse electric field, making the electric field smoother and avoiding single-point high electric fields, resulting in better terminal stability. Therefore, while ensuring high withstand voltage, this application reduces the sensitivity of the JTE terminal structure to the implanted dose, improves its resistance to fixed charge interference, and optimizes the electric field distribution to eliminate local electric field spikes.

[0051] Optionally, step S10, forming a semiconductor body, includes forming an isolation trench on the first surface of the terminal region of the semiconductor body, comprising: S110, providing substrate 10.

[0052] S120, A first epitaxial layer 20 is formed on one side of the substrate 10; the first epitaxial layer 20 is configured as a first conductivity type; the first epitaxial layer 20 is used to form a drift region 201 of a semiconductor device.

[0053] For details, please refer to Figure 7 The material of the substrate 10 and the material of the first epitaxial layer 20 may be the same or different. In the embodiments of this application, both the material of the substrate 10 and the material of the first epitaxial layer 20 may be SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the substrate 10, for example, both are N-type. The N-type first epitaxial layer 20 is used to form the drift region 201 of the device.

[0054] S130, a second epitaxial layer 30 is formed on the side of the first epitaxial layer 20 away from the substrate 10; the second epitaxial layer 30 is configured with a first conductivity type.

[0055] For details, please refer to Figure 7 The material of the second epitaxial layer 30 may be the same as or different from the material of the first epitaxial layer 20. In the embodiments of this application, the material of the second epitaxial layer 30 and the first epitaxial layer 20 are both SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the second epitaxial layer 30. The concentration of N-type dopant ions in the second epitaxial layer 30 is greater than the concentration of N-type dopant ions in the first epitaxial layer 20.

[0056] S140, a main junction region 33 is formed in the second epitaxial layer 30.

[0057] For details, please refer to Figure 8 P-type doped ions are implanted into the surface of the second epitaxial layer 30 on the side away from the substrate 10 to form a main junction region 33. The thickness of the main junction region 33 can be greater than the thickness of the second epitaxial layer 30.

[0058] S150, an initial junction extension region 310 is formed in the second epitaxial layer 30.

[0059] For details, please refer to Figure 9 P-type dopant ions are implanted on the surface of the second epitaxial layer 30 away from the substrate 10 to form an initial junction extension region 310. The doping concentration of P-type dopant ions in the initial junction extension region 310 is less than the doping concentration of P-type dopant ions in the main junction region 33. The thickness of the initial junction extension region 310 can be less than the thickness of the second epitaxial layer 30.

[0060] S160, A first region 32 is formed in the initial junction extension region 310.

[0061] For details, please refer to Figure 10 N-type doped ions are implanted into the initial junction extension region 310 to form the first region 32.

[0062] S170, an isolation trench is formed on at least one side of the first region 32; the first region 32 and the region outside the isolation trench in the initial junction expansion region 310 form a junction expansion region 31.

[0063] Optionally, an isolation groove is formed on at least one side of the first region 32, including: S1710, a first mask layer 110 is formed on the surface of the second epitaxial layer 30 away from the substrate 10, and the first mask layer 110 is patterned; the patterned first mask layer 110 includes a first opening that exposes a preset position of the isolation trench.

[0064] S1720, Based on the patterned first mask layer 110, a first sub-trench 71 is formed on the surface of the second epitaxial layer 30 away from the substrate 10.

[0065] For details, please refer to Figure 11 The material of the first mask layer 110 can be silicon dioxide or silicon nitride. A plurality of first openings are formed in the first mask layer 110 by an etching process. Based on the patterned first mask layer 110, at least two spaced first sub-trenches 71 are formed on the surface of the second epitaxial layer 30 away from the substrate 10 by an etching process.

[0066] S1730. Using the first mask layer 110 as a mask, multiple etching operations are performed sequentially within the second epitaxial layer 30 to form multiple interconnected sub-trenches. Before each etching operation, a first barrier layer with a preset thickness is formed on the sidewall of the existing sub-trench to define a new etching area.

[0067] For details, please refer to Figure 12 and Figure 13 An exemplary illustration shows that, using a patterned first mask layer 110 as a mask, one etching is performed within the second epitaxial layer 30 to form an isolation trench with two sub-trenches. (See reference...) Figure 12 Before forming the second-level sub-trench 72, a first barrier layer 101 of a predetermined thickness is formed on the sidewall of the first-level sub-trench 71, thereby defining the etching region of the second-level sub-trench 72. The material of the first barrier layer 101 can be silicon dioxide or silicon nitride. (Reference) Figure 13 The semiconductor body 1 located at the bottom of the first sub-trench 71 is etched to form the second sub-trench 72. The first sub-trench 71 and the second sub-trench 72 located at the bottom of the first sub-trench 71 constitute an isolation trench 70.

[0068] refer to Figure 14 After forming an isolation groove 70 on at least one side of the first region 32, the method further includes: removing the first mask layer 110 and the first barrier layer 101.

[0069] refer to Figure 15 Step S20, which involves forming a filling layer 40 in an isolation trench, includes depositing undoped polysilicon material in the isolation trench 70 to form the filling layer 40.

[0070] refer to Figure 16 Step S30, which involves forming a dielectric layer 50 on the first surface of the terminal region, includes forming a dielectric layer 50 made of silicon oxide on the first surface of the terminal region.

[0071] refer to Figure 17 After forming the dielectric layer 50 on the first surface of the terminal region, the method further includes forming an interlayer dielectric layer 60 on the surface of the dielectric layer 50 away from the semiconductor body 1. The material of the interlayer dielectric layer 60 may be the same as or different from the material of the dielectric layer 50.

[0072] Embodiments of this application also provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. It has the same technical effects and will not be described again here.

[0073] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, wherein the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0074] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load. It has the same technical effects and will not be described again here.

[0075] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other; wherein the first surface includes a cell region first surface and a terminal region first surface; the semiconductor body further includes a junction extension region and a first region, the first region being configured with a first conductivity type and located on the terminal region first surface; the junction extension region being configured with a second conductivity type, located on the terminal region first surface and disposed on the outer surface of the first region; the first conductivity type is different from the second conductivity type; the terminal region first surface has an isolation trench, the isolation trench penetrating a portion of the thickness of the junction extension region; A filling layer is located in the isolation groove, and the filling layer is made of an electrically insulating material; A dielectric layer is located on the first surface of the terminal region; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor further includes a main junction region; the main junction region is configured with a second conductivity type and is located on the first surface of the cell region; The main knot region is in contact with the sidewall of the knot extension region; The concentration of second conductivity type doped ions in the main junction region is greater than the concentration of second conductivity type doped ions in the junction extension region.

3. The semiconductor device according to claim 2, characterized in that, The number of the first regions is n, where n is an integer greater than or equal to 2; the n first regions are spaced apart in the direction from the main node region to the node expansion region; And / or, the number of the isolation slots is m, where m is an integer greater than or equal to 2; the m isolation slots are spaced apart in the direction from the main junction region to the junction expansion region.

4. The semiconductor device according to claim 3, characterized in that, In the direction from the main junction region to the junction expansion region, the first region and the isolation groove are alternately arranged in sequence.

5. The semiconductor device according to claim 3, characterized in that, The first surface of the cell region includes adjacent first sub-region surfaces and second sub-region surfaces; All of the first region is located on the surface of the first sub-region, and all of the isolation grooves are located on the surface of the second sub-region.

6. The semiconductor device according to claim 4, characterized in that, In the direction from the main junction region to the junction expansion region, the distance between adjacent first regions and the isolation groove gradually decreases; And / or, in the direction from the main junction region to the junction extension region, the width of the first region gradually increases.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The isolation trench is a multi-level trench including at least two sub-trenches; The filling layer is made of undoped polycrystalline silicon.

8. The semiconductor device according to claim 7, characterized in that, Also includes: The source electrode is located on the first surface of the cell region; The drain electrode is located on the second surface of the semiconductor body; The semiconductor body includes a substrate, a first epitaxial layer located on one side of the substrate, and a second epitaxial layer located on the side of the first epitaxial layer away from the substrate; the junction expansion region, the first region, and the isolation trench are all disposed in the second epitaxial layer; the first epitaxial layer is used to form a drift region.

9. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is formed, and an isolation trench is formed on a first surface of a terminal region of the semiconductor body. The semiconductor body includes a first surface and a second surface disposed opposite to each other. The first surface includes a cell region first surface and a terminal region first surface. The semiconductor body also includes a junction extension region and a first region. The first region is configured with a first conductivity type and is located on the first surface of the terminal region. The junction extension region is configured with a second conductivity type, is located on the first surface of the terminal region, and is disposed on the outer surface of the first region. The first conductivity type is different from the second conductivity type. The isolation trench penetrates a portion of the thickness of the junction extension region. A filling layer is formed in the isolation groove, and the material of the filling layer is an electrically insulating material; A dielectric layer is formed on the first surface of the terminal region; the dielectric layer contains fixed charges, and the fixed charges in the dielectric layer have the same polarity as the fixed charges in the first region.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The process of forming a semiconductor body, including forming an isolation trench on the first surface of the terminal region of the semiconductor body, comprises: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; the first epitaxial layer is used to form the drift region of the semiconductor device; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; An initial junction extension region is formed in the second epitaxial layer; A first region is formed in the initial junction expansion region; The isolation trench is formed on at least one side of the first region; the initial junction expansion region is formed by the first region and the region other than the isolation trench.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The isolation groove is formed on at least one side of the first region, including: A first mask layer is formed on the surface of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a first opening that exposes a predetermined position of the isolation trench; Based on the patterned first mask layer, a first-level sub-trench is formed on the surface of the second epitaxial layer on the side away from the substrate; Using the patterned first mask layer as a mask, multiple etching operations are performed sequentially within the second epitaxial layer to form multiple interconnected sub-trenches; wherein, before each etching operation, a first barrier layer with a preset thickness is formed on the sidewall of the existing sub-trench to define a new etching area.

12. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 13, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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