A single-gate SiC JFET structure with low on-resistance and its fabrication method

Abstract

This invention relates to the field of semiconductor power device technology, and discloses a single-side-gate SiC JFET structure with low on-resistance and its manufacturing method. The device employs an asymmetric trench structure, with a P+ type gate region on the first sidewall, an undoped second sidewall, and a P+ type bottom gate region at a specific depth at the bottom. During fabrication, the tangent of the tilted ion implantation angle is controlled to be less than the mesa aspect ratio, utilizing the geometric shielding effect to achieve single-side doping of the sidewalls; and an in-situ carbon protective film is used for high-temperature activation annealing to reduce surface contact resistance. The asymmetric structure of this invention eliminates the built-in depletion layer on the second sidewall, increases the effective conductive cross-sectional area of ​​the channel, and reduces the specific on-resistance; simultaneously, it halves the physical overlap area of ​​the gate and drain plates, significantly reducing the Miller capacitance parameter. The deep bottom gate region structure ensures the continuous closure of the internal depletion layer during reverse high-voltage blocking.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, specifically to a single-gate SiCJFET structure with low on-resistance and its manufacturing method. Background Technology

[0002] Silicon carbide junction field-effect transistors (SCTs), as core semiconductor devices for high-frequency, high-power applications, traditionally employ a double-sided symmetrical trench gate structure. In this symmetrical structure, the built-in potential barrier formed by the P-type doped regions on both sides of the trench extends towards the central N-type channel layer. In the on-state, the double-sided built-in depletion layers inevitably compress the effective physical transport channels for charge carriers, resulting in a high specific on-resistance. Simultaneously, the P-type gate regions on both sidewalls and the bottom overlap significantly with the underlying N-type drift region, introducing a high parasitic gate-drain capacitance (Miller capacitance). This double-sided symmetrical physical configuration creates an inherent mutual constraint between the device's static conduction loss and dynamic switching parasitic parameters, making it difficult to achieve a synergistic reduction in various electrical parameters while maintaining or reducing the original platform cell size.

[0003] To overcome this physical constraint, some technical solutions attempt to evolve towards single-side gate or asymmetric gate structures. However, once the P-type doping on one sidewall is removed, relying solely on the reverse turn-off bias applied to that sidewall often results in a lateral depletion layer that cannot completely cover the entire mesa width. Under the influence of the high-voltage electric field at the drain, depletion layer penetration easily occurs in the far-end region of the channel, leaving unclosed intrinsic conductive channels. Ultimately, this leads to the device losing its basic forward voltage blocking capability and triggering a large turn-off leakage current.

[0004] At the semiconductor manufacturing process level, achieving precise single-sided doping within narrow trenches at micrometer depths presents significant technological challenges. Conventional methods require additional high-precision photolithography masking steps to shield specific sidewall regions. This is not only limited by the physical limits of the lithography machine's depth of focus and alignment tolerance, making mask misalignment prone to cause morphological distortion of the doped region, but also extends the process cycle and reduces wafer manufacturing yield. Therefore, how to overcome the physical trade-off between specific on-resistance and Miller capacitance through structural design and process route improvements, while ensuring the device's high-voltage pinch-off capability and simplifying the manufacturing process, is a pressing technical challenge in the field of silicon carbide power devices. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a single-side-gate SiC JFET structure with low on-resistance and its manufacturing method. This solves the problem that physical constraints exist in traditional symmetrical trench silicon carbide junction field-effect transistors regarding specific on-resistance and parasitic Miller capacitance, making it difficult to simultaneously reduce static conduction losses and high-frequency switching parasitic parameters without changing the mesa size.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The first aspect of the present invention provides a single-gate SiC JFET structure with low on-resistance, comprising an N+ type substrate, an N- type drift layer located on the front side of the N+ type substrate, an N- type channel layer located on the N- type drift layer, and an N+ type source layer located on top of the N-type channel layer.

[0007] The N+ type source layer, the N type channel layer, and the N- type drift layer are provided with grooves, which separate the upper part of the device into a surface structure. The groove has a first sidewall, a second sidewall, and a bottom.

[0008] The first sidewall has a P+ type sidewall gate region, and the second sidewall is not P-type doped and remains an N-type semiconductor material.

[0009] The bottom of the groove is provided with a P+ type bottom gate region, the vertical junction depth of the P+ type bottom gate region is 0.5μm-1.5μm, and the vertical junction depth of the P+ type bottom gate region is ≥0.5 times the width of the mesa structure.

[0010] The P+ type bottom gate region extends laterally on one side directly below the first sidewall and the second sidewall, forming a lateral extension region with a width of 0.1μm-0.3μm.

[0011] Regarding specific structural parameters, the thickness of the N-type drift layer is 5.0 μm-15.0 μm, and the nitrogen doping concentration is 1.0 × 10⁻⁶. 15 cm -3 -8.0×10 15 cm -3 The thickness of the N-type channel layer is 0.5 μm-1.5 μm, and the nitrogen doping concentration is 1.0 × 10⁻⁶. 16 cm -3 -5.0×10 16 cm -3 ; The thickness of the N+ type source layer is 0.2 μm-0.5 μm, and the nitrogen doping concentration is 1.0 × 10⁻⁶. 19 cm -3 -1.0×10 20 cm -3 The groove has a depth of 1.5μm-3.5μm and a width of 1.0μm-3.0μm, while the mesa structure has a width of 1.0μm-2.5μm. The angle between the first sidewall and the second sidewall and the bottom of the groove is between 85° and 90°, and the lateral junction depth of the P+ type sidewall gate region within the first sidewall is 0.1μm-0.4μm.

[0012] The mechanism and technical effect of the first aspect of this invention are as follows: Since the second sidewall remains an N-type semiconductor material, when the device is in the on-state, only the P+ type sidewall gate region at the first sidewall generates a depletion layer. This asymmetric physical structure makes the physical width of the conductive channel greater than that of a symmetric structure with P-type doping on both sides, thus reducing the on-resistance. At the same time, the total physical overlap area between the gate region and the drain drift region is reduced compared to a two-sided structure, resulting in a lower Miller capacitance.

[0013] When the device is in the off-bias state, the P+ type bottom gate region, with a vertical junction depth of 0.5μm-1.5μm and extending laterally 0.1μm-0.3μm directly below the mesa, generates a depletion layer from the bottom up. Based on the physical condition that the vertical junction depth of the P+ type bottom gate region is ≥ 0.5 times the width of the mesa structure, the depletion layer from the bottom up physically overlaps spatially with the lateral depletion layer generated by the P+ type sidewall gate region at the first sidewall, cutting off the electron transport path between the N-type channel layer and the N-type drift layer, thus pinching off the operating current.

[0014] A second aspect of the present invention provides a method for manufacturing a single-gate SiC JFET structure with low on-resistance, for manufacturing the single-gate SiC JFET structure provided in the first aspect, comprising the following steps: An N-type drift layer, an N-type channel layer, and an N+ type source layer are epitaxially grown sequentially on the front side of an N+ type substrate.

[0015] A hard mask is deposited and patterned on the surface of the N+ type source layer. Using the hard mask as a barrier layer, an inductively coupled plasma dry etching process is employed to sequentially etch downwards, penetrating the N+ type source layer and the N- type channel layer, and extending into the N- type drift layer, forming grooves and mesa structures separated by the grooves. The etching gas composition includes sulfur hexafluoride and oxygen, wherein the sulfur hexafluoride gas flow rate is 30 sccm-60 sccm, and the oxygen flow rate is 5 sccm-15 sccm. The grooves expose a first sidewall, a second sidewall, and a groove bottom.

[0016] Retaining the hard mask, aluminum ions are vertically implanted at the bottom of the groove, with the implantation direction at 0°-4° to the wafer surface normal. The implantation energy ranges from 30keV to 800keV, and the total implantation dose ranges from 1.0 × 10⁻⁶. 13 cm -2 -5.0×10 14 cm -2The wafer temperature is maintained at 400℃-600℃. This step forms a P+ type bottom gate region with a vertical junction depth of 0.5μm-1.5μm, and under the lateral dispersion of implanted ions, the P+ type bottom gate region extends laterally to the first sidewall and the second sidewall, forming a 0.1μm-0.3μm lateral extension region on one side.

[0017] The hard mask is retained, and aluminum ion unilateral tilting implantation is performed. The incident angle of the aluminum ion unilateral tilting implantation is set to 15°-45°, and the incident angle... satisfy ,in The width of the groove, The depth of the groove. The injection energy range is 30keV-350keV, and the injection dose is controlled at 5.0×10⁻⁶. 12 cm -2 -1.0×10 14 cm -2 The wafer temperature is maintained between 400°C and 600°C. Through the aforementioned incident angle setting, the obliquely incident ion beam is physically shielded by the adjacent mesa structures, ensuring that aluminum ions bombard only the first sidewall to form a P+ type sidewall gate region. The second sidewall is located in the shaded area of ​​the adjacent mesa structures and is not doped. The P+ type sidewall gate region is physically connected to the P+ type bottom gate region formed by vertical implantation.

[0018] Remove the hard mask and spin-coat a polyimide solution onto the device surface to form a polymer film with a thickness of 1.5 μm-3.0 μm; Pre-baking for 5-15 minutes within the range of 150℃-250℃; Under vacuum or argon atmosphere, heat to -800℃ to 1000℃ at a heating rate of 5℃ / min to 10℃ / min and hold for 30min to 60min to synthesize an amorphous graphitized carbon film with a thickness of 30nm to 80nm in situ on the device surface as a carbon protective film.

[0019] Subsequently, an impurity activation annealing process was performed in an argon atmosphere at a temperature of 1600℃-1750℃ for 20-45 minutes. After annealing, the carbon protective film was removed by oxygen plasma ashing at a temperature of 600℃-800℃.

[0020] A silicon dioxide layer with a thickness of 0.5 μm-1.5 μm is deposited on the device surface as an interlayer dielectric, and contact holes are etched to expose the N+ type source layer and the P+ type bottom gate region. A nickel film with a thickness of 50 nm-100 nm is deposited and rapidly thermally annealed at 950 °C-1050 °C for 2 min-5 min under a nitrogen atmosphere to form a nickel silicide ohmic contact layer that contacts the N+ type source layer and the P+ type bottom gate region.

[0021] An aluminum layer or a thick copper alloy layer is deposited on the nickel silicide ohmic contact layer as a front interconnect thickening electrode. After thinning the back side of the N+ type substrate by 100μm-150μm, a stacked electrode system of titanium, nickel and silver layers is deposited sequentially to form the back drain metal layer.

[0022] The mechanism and technical effect of the second aspect of the present invention are as follows: By setting a satisfying relation By determining the incident angle parameters and combining the linear propagation trajectory of the ion beam with the physical height difference of the Mesa mesa, a single-sided sidewall doped structure and a shaded undoped structure are formed in a single tilted implantation step. Through a cascaded energy implantation setup of 30keV-800keV combined with the lateral dispersion physical characteristics under thermal motion, a bottom depletion layer generation region with specific junction depth and lateral extension dimensions is generated, providing the three-dimensional space charge fundamental physical structure required for JFET pinch-off.

[0023] This invention provides a single-gate SiC JFET structure with low on-resistance and its manufacturing method. It offers the following advantages: 1. This invention provides a P+ type sidewall gate region on the first sidewall of the trench while maintaining the second sidewall as an N-type semiconductor material. This results in a space charge depletion layer being generated only at the first sidewall under on-bias conditions. Compared to a double-sided symmetrical P-type doped structure, this asymmetric physical structure increases the effective conductive physical width within the channel, thereby reducing the characteristic on-resistance of the device. Simultaneously, since the second sidewall is free of P-type doping, the total physical overlap area between the gate region and the drain drift region is correspondingly reduced, lowering the gate-drain capacitance (Miller capacitance) of the device.

[0024] 2. This invention provides a P+ type bottom gate region at the bottom of the trench, extending laterally downwards towards the mesa. When a turn-off bias is applied, the depletion layer extending upwards from the bottom gate region, the depletion layer generated by the laterally extended region, and the lateral depletion layer generated by the first sidewall gate region physically close within the channel space. This physical closure mechanism cuts off the electron transport path between the N-type channel layer and the N-type drift layer, enabling the single-sided gate structure to pinch off the operating current and block the drain-source voltage in the turn-off state.

[0025] 3. This invention utilizes the physical height difference of the mesa structure to form a geometric shadow region to block the incident ion beam. By controlling the linear propagation physical trajectory of the ion beam, this process step achieves localized aluminum ion doping of the first sidewall and zero doping of the second sidewall in a single tilting implantation process without adding a sidewall photolithography mask alignment step, thus completing the fabrication of an asymmetric single-sided gate physical structure. Attached Figure Description

[0026] Figure 1 This is a transfer characteristic curve diagram of an embodiment of the present invention; Figure 2 The output characteristic curve of one embodiment of the present invention ( , )picture; Figure 3 This is a graph showing the relationship between gate-drain capacitance and drain-source voltage according to an embodiment of the present invention. Figure 4 This is a graph showing the relationship between the reciprocal of the square of the gate-drain capacitance and the drain-source voltage according to an embodiment of the present invention. Figure 5 This is a comparison diagram of the specific on-resistance of one embodiment of the present invention; Figure 6 This is a comparison diagram of gate-drain capacitance under different drain-source voltages according to an embodiment of the present invention; Figure 7 This is a reverse blocking characteristic curve of an embodiment of the present invention; Figure 8 This is a comparison chart of breakdown voltage values ​​according to an embodiment of the present invention; Figure 9 This is a graph showing the relationship between the square root of the leakage current and the gate-source voltage according to an embodiment of the present invention. Figure 10 The output characteristic curve of one embodiment of the present invention ( )picture; Figure 11 This is a graph showing the linear relationship between pad spacing and total resistance according to an embodiment of the present invention; Figure 12 This is a comparison chart of the extraction ratio and contact resistance values ​​according to an embodiment of the present invention; Figure 13 This is a schematic diagram of a single-gate SiC JFET structure according to an embodiment of the present invention; Figure 14 This is a schematic diagram of a conventional SiC JFET structure according to an embodiment of the present invention; Figure 15 This is a flowchart illustrating the fabrication process of a single-side-gate SiC JFET structure according to an embodiment of the present invention.

[0027] Wherein, Source: refers to the source metal interconnect layer at the top of the device used to connect to external circuits; Drain: The drain electrode refers to the metal interconnect layer on the back of a device used to connect to external circuits. Gate: refers to the metal plate deposited on the surface of the P+ type region to form an ohmic contact; N+: The heavily doped N-type region, located at the top of the structure, serves as a low-impedance contact transition region between the source and the N-type channel layer. N-: N-type lightly doped region, which constitutes the intrinsic conductive channel of the device body, including the vertical channel layer located inside the mesa structure and the epitaxial drift layer below it; P+: P-type heavily doped region, which constitutes the gate physical structure of the device, including the sidewall gate region and the bottom gate region. It is used to form a PN junction and generate a space charge depletion layer under reverse bias to regulate the channel current. Substrate: Semiconductor substrate, usually referring to the high-conductivity N-type silicon carbide wafer substrate at the bottom, serves as the physical support and bottom conductive path for the epitaxial growth of the entire device. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] Preparation Examples 1-3: Preparation Example 1: This preparation example provides a method for preparing an in-situ synthesized carbon protective film, including the following steps: A polyimide precursor solution was spin-coated onto the surface of an N-type silicon carbide single crystal substrate to form a polymer film with a thickness of 1.5 μm. The N-type silicon carbide single crystal substrate with the polymer film attached was placed on a hot plate and pre-baked at 150°C for 5 minutes. The pre-baked N-type silicon carbide single crystal substrate was transferred to a tube furnace and heated to 800°C at a heating rate of 5°C / min under an argon atmosphere. The substrate was then held at 800°C for 30 min to synthesize the polymer film in situ into an amorphous graphitized carbon film. The thickness of the amorphous graphitized carbon film was measured to be 30 nm.

[0030] Preparation Example 2: This preparation example provides a method for preparing an in-situ synthesized carbon protective film, including the following steps: A polyimide precursor solution was spin-coated onto the surface of an N-type silicon carbide single crystal substrate to form a polymer film with a thickness of 2.2 μm. The N-type silicon carbide single crystal substrate with the polymer film attached was placed on a hot plate and pre-baked at 200°C for 10 minutes. The pre-baked N-type silicon carbide single crystal substrate was then transferred to a tube furnace and heated to 900°C at a heating rate of 8°C / min under an argon atmosphere. The temperature was then held at 900°C for 45 minutes to synthesize the polymer film in situ into an amorphous graphitized carbon film. The thickness of the amorphous graphitized carbon film was measured to be 55 nm.

[0031] Preparation Example 3: This preparation example provides a method for preparing an in-situ synthesized carbon protective film, including the following steps: A polyimide precursor solution was spin-coated onto the surface of an N-type silicon carbide single crystal substrate to form a polymer film with a thickness of 3.0 μm. The N-type silicon carbide single crystal substrate with the polymer film attached was placed on a hot plate and pre-baked at 250°C for 15 minutes. The pre-baked N-type silicon carbide single crystal substrate was transferred to a tube furnace and heated to 1000°C at a heating rate of 10°C / min under an argon atmosphere. The substrate was then held at 1000°C for 60 min to synthesize the polymer film in situ into an amorphous graphitized carbon film. The thickness of the amorphous graphitized carbon film was measured to be 80 nm. Examples 1-3: Example 1:

[0032] Reference Figures 13-15 This embodiment provides a method for fabricating a single-gate SiC JFET structure with low on-resistance, including the following steps: An N-type drift layer, an N-type channel layer, and an N+ type source layer were sequentially epitaxially grown on the front side of an N-type silicon carbide single-crystal substrate. The N-type drift layer had a thickness of 5.0 μm and a nitrogen doping concentration of 1.0 × 10⁻⁶. 15 cm -3 ; The N-type channel layer has a thickness of 0.5 μm and a nitrogen doping concentration of 1.0 × 10⁻⁶. 16 cm -3 ; The N+ source layer has a thickness of 0.2 μm and a nitrogen doping concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0033] A 1.0 μm thick silicon dioxide hard mask is deposited and patterned on the surface of the N+ type source layer. Using the silicon dioxide hard mask as a barrier layer, an inductively coupled plasma dry etching process is employed to sequentially etch downwards, penetrating the N+ type source layer and the N- type channel layer, and extending into the N- type drift layer, forming grooves and mesa structures separated by the grooves. The etching gas composition includes sulfur hexafluoride and oxygen, with a sulfur hexafluoride flow rate of 30 sccm and an oxygen flow rate of 5 sccm. The formed grooves have a depth of 1.5 μm and a width of 1.0 μm, the mesa structures have a width of 1.0 μm, and the angle between the first and second sidewalls and the bottom of the groove is 85°.

[0034] Retaining the silicon dioxide hard mask, and with the wafer temperature maintained at 400°C, aluminum ions are vertically implanted into the bottom of the groove, with the implantation direction at 0° to the wafer surface normal. The implantation energy is cascaded from 30keV to 300keV, with a total implantation dose of 1.0 × 10⁻⁶. 13 cm -2 A P+ type bottom gate region with a vertical junction depth of 0.5 μm is formed (satisfying the numerical relationship of 0.5 μm ≥ 0.5 × 1.0 μm), and under the lateral dispersion of implanted ions, the P+ type bottom gate region extends laterally to the lower side of the first and second sidewalls to form a 0.1 μm unilateral lateral extension region.

[0035] While retaining the silicon dioxide hard mask, aluminum ion single-sided tilt implantation was performed under the condition that the wafer temperature was maintained at 400°C. The incident angle for aluminum ion single-sided tilt implantation was set to 15°, the implantation energy was cascaded implantation from 30keV to 150keV, and the implantation dose was 5.0 × 10⁻⁶. 12 cm -2 The obliquely incident ion beam is physically shielded by the adjacent mesa structure. Aluminum ions bombard only the first sidewall to form a P+ type sidewall gate region with a lateral junction depth of 0.1 μm. The second sidewall is in the shaded area of ​​the adjacent mesa structure and is not doped. The P+ type sidewall gate region is connected to the P+ type bottom gate region formed by vertical implantation.

[0036] The silicon dioxide hard mask was removed, and an amorphous graphitized carbon film with a thickness of 30 nm was synthesized in situ on the device surface as a carbon protective film using the method of Preparation Example 1. Subsequently, an impurity activation annealing process was performed in an argon atmosphere at a temperature of 1600 °C for 20 min. After annealing, the carbon protective film was removed by oxygen plasma ashing at 600 °C.

[0037] A 0.5 μm thick silicon dioxide layer was deposited on the device surface as an interlayer dielectric, and contact holes were etched to expose the N+ type source layer and the P+ type bottom gate region. A 50 nm thick nickel film was deposited and rapidly thermally annealed at 950 °C for 2 min under a nitrogen atmosphere to form a nickel silicide ohmic contact layer that contacts the N+ type source layer and the P+ type bottom gate region. A 2.0 μm thick aluminum layer was deposited on the nickel silicide ohmic contact layer as a front interconnect thickening electrode. After thinning the back side of the N-type silicon carbide single crystal substrate to 100 μm, a 50 nm thick titanium layer, a 100 nm thick nickel layer, and a 500 nm thick silver layer were sequentially deposited to form the back drain metal layer. Example 2:

[0038] This embodiment provides a method for fabricating a single-gate SiC JFET structure with low on-resistance, including the following steps: An N-type drift layer, an N-type channel layer, and an N+ type source layer were sequentially epitaxially grown on the front side of an N-type silicon carbide single crystal substrate. The N-type drift layer had a thickness of 10.0 μm and a nitrogen doping concentration of 4.0 × 10⁻⁶. 15 cm -3 The N-type channel layer has a thickness of 1.0 μm and a nitrogen doping concentration of 3.0 × 10⁻⁶. 16 cm -3 The N+ source layer has a thickness of 0.35 μm and a nitrogen doping concentration of 5.0 × 10⁻⁶. 19 cm -3 .

[0039] A 1.5 μm thick silicon dioxide hard mask is deposited and patterned on the surface of the N+ type source layer. Using the silicon dioxide hard mask as a barrier layer, an inductively coupled plasma dry etching process is employed to sequentially etch downwards, penetrating the N+ type source layer and the N- type channel layer, and extending into the N- type drift layer, forming grooves and mesa structures separated by the grooves. The etching gas composition includes sulfur hexafluoride and oxygen, with a sulfur hexafluoride flow rate of 45 sccm and an oxygen flow rate of 10 sccm. The formed grooves have a depth of 2.5 μm and a width of 2.0 μm, the mesa structures have a width of 1.8 μm, and the angle between the first and second sidewalls and the bottom of the groove is 88°.

[0040] Retaining the silicon dioxide hard mask, and with the wafer temperature maintained at 500°C, aluminum ions are vertically implanted into the bottom of the groove, with the implantation direction at 2° to the wafer surface normal. The implantation energy is cascaded from 30keV to 500keV, with a total implantation dose of 1.0 × 10⁻⁶. 14 cm -2A P+ type bottom gate region with a vertical junction depth of 1.0 μm is formed (satisfying the numerical relationship of 1.0 μm ≥ 0.5 × 1.8 μm), and under the lateral dispersion of implanted ions, the P+ type bottom gate region extends laterally by 0.2 μm to the lower side of the first and second sidewalls, forming a single-sided lateral extension region.

[0041] While retaining the silicon dioxide hard mask, aluminum ion single-sided tilt implantation was performed under the condition that the wafer temperature was maintained at 500°C. The incident angle for aluminum ion single-sided tilt implantation was set to 30°, the implantation energy was cascaded implantation from 30keV to 250keV, and the implantation dose was 5.0 × 10⁻⁶. 13 cm -2 The obliquely incident ion beam is physically shielded by the adjacent mesa structure. Aluminum ions bombard only the first sidewall to form a P+ type sidewall gate region with a lateral junction depth of 0.25 μm. The second sidewall is in the shaded area of ​​the adjacent mesa structure and is not doped. The P+ type sidewall gate region is connected to the P+ type bottom gate region formed by vertical implantation.

[0042] The silicon dioxide hard mask was removed, and an amorphous graphitized carbon film with a thickness of 55 nm was synthesized in situ on the device surface as a carbon protective film using the method of Preparation Example 2. Subsequently, an impurity activation annealing process was performed in an argon atmosphere at a temperature of 1680 °C for 30 min. After annealing, the carbon protective film was removed by oxygen plasma ashing at 700 °C.

[0043] A 1.0 μm thick silicon dioxide layer was deposited on the device surface as an interlayer dielectric, and contact holes were etched to expose the N+ type source layer and the P+ type bottom gate region. A 75 nm thick nickel film was deposited and rapidly thermally annealed at 1000 °C for 3 min under a nitrogen atmosphere to form a nickel silicide ohmic contact layer that contacts the N+ type source layer and the P+ type bottom gate region. A 3.0 μm thick aluminum layer was deposited on the nickel silicide ohmic contact layer as a front interconnect thickening electrode. After thinning the back side of the N-type silicon carbide single crystal substrate to 125 μm, a 75 nm thick titanium layer, a 200 nm thick nickel layer, and a 750 nm thick silver layer were sequentially deposited to form the back drain metal layer. Example 3:

[0044] This embodiment provides a method for fabricating a single-gate SiC JFET structure with low on-resistance, including the following steps: An N-type drift layer, an N-type channel layer, and an N+ type source layer were sequentially epitaxially grown on the front side of an N-type silicon carbide single-crystal substrate. The N-type drift layer had a thickness of 15.0 μm and a nitrogen doping concentration of 8.0 × 10⁻⁶. 15 cm -3 The N-type channel layer has a thickness of 1.5 μm and a nitrogen doping concentration of 5.0 × 10⁻⁶. 16cm -3 The N+ source layer has a thickness of 0.5 μm and a nitrogen doping concentration of 1.0 × 10⁻⁶. 20 cm -3 .

[0045] A 2.0 μm thick silicon dioxide hard mask is deposited and patterned on the surface of the N+ type source layer. Using the silicon dioxide hard mask as a barrier layer, an inductively coupled plasma dry etching process is employed to sequentially etch downwards, penetrating the N+ type source layer and the N- type channel layer, and extending into the N- type drift layer, forming grooves and mesa structures separated by the grooves. The etching gas composition includes sulfur hexafluoride and oxygen, with a sulfur hexafluoride flow rate of 60 sccm and an oxygen flow rate of 15 sccm. The formed grooves have a depth of 3.5 μm and a width of 3.0 μm, the mesa structures have a width of 2.5 μm, and the angle between the first and second sidewalls and the bottom of the groove is 90°.

[0046] Retaining the silicon dioxide hard mask, and with the wafer temperature maintained at 600°C, aluminum ions are vertically implanted into the bottom of the groove, with the implantation direction at a 4° angle to the wafer surface normal. The implantation energy is cascaded from 30keV to 800keV, with a total implantation dose of 5.0 × 10⁻⁶. 14 cm -2 A P+ type bottom gate region with a vertical junction depth of 1.5 μm is formed (satisfying the numerical relationship of 1.5 μm ≥ 0.5 × 2.5 μm), and under the lateral dispersion effect of implanted ions, the P+ type bottom gate region extends laterally by 0.3 μm to the lower side of the first and second sidewalls, forming a single-sided lateral extension region.

[0047] While retaining the silicon dioxide hard mask, aluminum ion single-sided tilt implantation was performed at a wafer temperature maintained at 600°C. The incident angle for aluminum ion single-sided tilt implantation was set to 40°, the implantation energy was cascaded implantation from 30keV to 350keV, and the implantation dose was 1.0 × 10⁻⁶. 14 cm -2 The obliquely incident ion beam is physically shielded by the adjacent mesa structure. Aluminum ions bombard only the first sidewall to form a P+ type sidewall gate region with a lateral junction depth of 0.4 μm. The second sidewall is in the shaded area of ​​the adjacent mesa structure and is not doped. The P+ type sidewall gate region is connected to the P+ type bottom gate region formed by vertical implantation.

[0048] The silicon dioxide hard mask was removed, and an amorphous graphitized carbon film with a thickness of 80 nm was synthesized in situ on the device surface as a carbon protective film using the method described in Example 3. Subsequently, an impurity-activated annealing process was performed in an argon atmosphere at a temperature of 1750 °C for 45 min. After annealing, the carbon protective film was removed by oxygen plasma ashing at 800 °C.

[0049] A 1.5 μm thick silicon dioxide layer was deposited on the device surface as an interlayer dielectric, and contact holes were etched to expose the N+ type source layer and the P+ type bottom gate region. A 100 nm thick nickel film was deposited and rapidly thermally annealed at 1050 °C for 5 min under a nitrogen atmosphere to form a nickel silicide ohmic contact layer that contacts the N+ type source layer and the P+ type bottom gate region. A 4.0 μm thick aluminum layer was deposited on the nickel silicide ohmic contact layer as a front interconnect thickening electrode. After thinning the back side of the N-type silicon carbide single crystal substrate to 150 μm, a 100 nm thick titanium layer, a 300 nm thick nickel layer, and a 1000 nm thick silver layer were sequentially deposited to form the back drain metal layer.

[0050] Comparative Examples 1-4: Comparative Example 1: Compared with Example 2, the difference is that the single-sided tilted implantation of aluminum ions is changed to the symmetrical tilted implantation of aluminum ions on both sides, so that a P+ type sidewall gate region with a lateral junction depth of 0.25 μm is formed in both the first and second sidewalls. All other aspects are the same.

[0051] Comparative Example 2: Compared with Example 2, the difference is that the cascade implantation energy for vertical aluminum ion implantation at the bottom of the groove is reduced, so that the vertical junction depth of the formed P+ type bottom gate region is 0.2 μm, which does not meet the numerical relationship that the vertical junction depth is ≥ 0.5 times the width of the mesa structure. All other aspects are the same.

[0052] Comparative Example 3: Compared with Example 1, the difference is that the incident angle for unilateral tilting implantation of aluminum ions is set to 50°, so that the incident angle does not satisfy the physical shielding relationship, resulting in aluminum ion doping on the second sidewall. All other aspects are the same.

[0053] Comparative Example 4: Compared with Example 2, the difference is that the steps of in-situ synthesis of amorphous graphitized carbon film on the device surface using the method of Example 2 and the step of oxygen plasma ashing to remove the carbon protective film after annealing are omitted. Instead, the impurity activation annealing process is performed directly without a surface protective film covering. All other aspects are the same.

[0054] Test Examples 1-6: Test Example 1: The single-side gate SiC JFET device wafers prepared in Examples 1, 2 and 3 were placed on the vacuum chuck of the semiconductor probe station, and the working environment temperature of the probe station was set to 25°C.

[0055] Operate the microprobe system to establish ohmic contacts between the three test probes and the thickened aluminum interconnect electrode (source) on the device surface, the test pad extending from the exposed P+ type bottom gate region (gate), and the silver layer (drain) on the back of the wafer. The probes are connected to a semiconductor parameter analyzer via coaxial cables.

[0056] Set up and run the transfer characteristic test program. Set a constant drain-source voltage in the semiconductor parameter analyzer. Set the gate-source voltage to 5.0V. The scan range is -15.0V to 2.0V, and the scan step size is set to 0.1V. Start the test and record the data. Varying leakage current The threshold voltage of the device is calculated by extracting the horizontal intercept of the linear region of the leakage current versus gate-source voltage curve. .

[0057] Set up and run the output characteristic test program. Set the gate-source voltage to 0V and the drain-source current scan range to 0V to 15.0V. Start the test and record the leakage current response data. Extract the voltage and current data in the linear region (drain-source voltage = 2.0V) and calculate the specific on-resistance (mΩ·cm) based on the effective operating area of ​​the device. 2） The stable constant current value under high drain-source voltage is extracted as the saturation leakage current (mA / mm).

[0058] Table 1. Record of key electrical parameters of static characteristics in Examples 1 to 3 in conclusion: Figure 1 This illustrates the physical transfer process of the device's leakage current as it continuously changes with the gate-source voltage. The intercept of the curves with the horizontal axis characterizes the pinch-off voltage required for the device to achieve complete channel depletion. The figure shows that Example 1 has the smallest absolute pinch-off voltage, while the pinch-off voltages of Examples 2 and 3 extend in the negative direction sequentially. This lateral shift in the intercept reflects the ability to intervene in the expansion process of the space charge region inside the channel by adjusting the physical parameters of the single-sided gate structure, thereby changing the external electric field strength required to cut off the conductive channel. Furthermore, in the zero-bias and positive-bias regions, the slope of the curve for Example 1 is higher than the other two, demonstrating a stronger ability to control channel carriers under these structural parameters.

[0059] Figure 2The current output capability of the device in the zero gate bias, i.e., normal conduction state, is demonstrated. In the linear operating region with low drain-source voltage, the curve of Example 1 exhibits the largest rising slope, directly corresponding to the lowest forward ratio on-resistance; the slopes of Examples 2 and 3 decrease stepwise, indicating a difference in their internal effective conductive cross-sectional area. As the drain-source voltage continues to increase and enters the saturation operating region, the saturation leakage current of Example 1 remains at the highest level, while the saturation leakage current values ​​of Examples 2 and 3 decrease in a stepwise manner. The comparative test results of the two sets of curves confirm from a macroscopic electrical perspective that the single-sided asymmetric gate structure design of this invention can construct a stable and continuous electron drift channel, and that precise control of the device's on-resistance and upper limit of output current can be achieved by adjusting the structural parameters.

[0060] According to the data in Table 1, the single-gate SiC JFET devices of Examples 1 to 3 all exhibited negative threshold voltages, ranging from -5.83V to -12.16V, consistent with the physical characteristics of a junction field-effect transistor under normal conduction. This test result demonstrates that the N-type channel layer of the single-sided asymmetric physical structure with no P-type doping on the second sidewall can maintain effective electron transport when zero gate bias is applied, and the measured specific on-resistance confirms the conduction function of the physical channel. Under the condition of applying a negative bias to the gate, Examples 1 to 3 can all achieve physical pinch-off of the current channel, and the absolute value of the threshold voltage increases regularly with proportional scaling of the mesa width and trench depth.

[0061] This parameter performance verifies the physical mechanism of the synergistic effect between the P+ type bottom gate region with a vertical junction depth ≥ 0.5 times the width of the mesa structure and the P+ type sidewall gate region at the first sidewall. Under a given negative bias, the bottom-up depletion layer and the single-sided depletion layer can completely overlap the space charge region at the interface between the N-type channel layer and the N-type drift layer, effectively cutting off the electron drift path between the drain and source. Saturation leakage current data shows that, with adjustments to the device's physical dimensions, the single-sided gate structure can continuously provide a stable output current during operation, verifying the electrical feasibility of the single-sided gate combined with the bottom deep injection structure in this invention at the operational level of actual semiconductor devices.

[0062] Test Example 2: The single-side gate SiC JFET device wafers prepared in Examples 1, 2 and 3 were placed on the test chuck of the semiconductor probe station, and the ambient temperature was set to 25°C.

[0063] Using a microscopic test probe with a coaxial shielded cable, establish physical contact with the front interconnect thickened electrode (source), the test pad extending from the P+ type bottom gate region (gate), and the back drain metal layer on the device surface. Connect the end of the probe cable to the corresponding input port of the LCR impedance meter.

[0064] In the control interface of the LCR impedance tester, the frequency of the AC test signal is set to 1MHz, and the voltage amplitude of the AC signal is set to 50mV.

[0065] Set the DC bias scan sequence and fix the gate-source voltage output at -15.0V to ensure the device is in a channel-pinch-off physical state. Set the DC scan range of the drain-source voltage to 0V to 30.0V and the scan step size to 1.0V.

[0066] Start the capacitance and voltage test program, extract the imaginary part of the AC impedance between the gate and drain of the device under different drain-source voltage nodes, and calculate and record the corresponding gate-drain capacitance (pF / mm) value.

[0067] Table 2. Record of key electrical parameters for dynamic capacitance characteristics in Examples 1 to 3 in conclusion: Figure 3 The nonlinear decay physical trend of the gate-drain capacitance values ​​in Examples 1 to 3 within the drain-source voltage range of 0V to 30.0V is shown. These test curves directly correspond to the discrete test node data in Table 2 above, reflecting the physical process of the increase in the equivalent capacitor plate spacing caused by the widening of the depletion layer towards the N-type drift region. The stepwise increase in the vertical axis values ​​of the curves in Examples 1 to 3 verifies the direct impact of the proportional scaling of the structural mesa width and trench depth on the parasitic capacitance values.

[0068] Figure 4 The diagram shows that by extracting the reciprocal of the square of the gate-drain capacitance, the value increases approximately linearly with increasing drain-source voltage. This trend conforms to the expansion law of the single-sided space charge region of the abrupt junction, verifying from an electrical testing perspective that an effective single-sided PN junction structure is formed between the P+ type sidewall gate region and the N- type drift layer using a single tilted injection, thus proving the physical feasibility of the asymmetric single-sided doping mechanism of this invention.

[0069] According to the data in Table 2, the devices in Examples 1 to 3 all output clear gate-drain capacitance parasitic parameter extraction values ​​at an AC test frequency of 1MHz. As the drain-source voltage increases from 0V to 30.0V, the Miller capacitance values ​​in all three examples exhibit a non-linear, stepwise decay. This test data conforms to the physical law that the width of the space charge depletion layer of a semiconductor PN junction widens towards the N-type drift region with increasing reverse bias, leading to an increase in the equivalent plate spacing.

[0070] At the same drain-source voltage node, the capacitance values ​​of Examples 1 to 3 show a corresponding increase as the physical dimensions of the device recess and mesa are scaled up proportionally. Test results demonstrate that, because the second sidewall in the structure is not P-type doped and remains an N-type semiconductor material, the device physically eliminates the parasitic capacitance plate surface present in this region. The physical overlap between the gate structure and the N-type drift region is only retained in the P+ type sidewall gate region of the first sidewall and the bottom P+ type bottom gate region. This unilateral asymmetric doping design limits the total area of ​​effective charge charging and discharging in terms of electrical mechanism, proving that the unilateral gate physical structure of the present invention has the electrical function of reducing the device's Miller parasitic capacitance while maintaining channel pinch-off characteristics.

[0071] Test Example 3: The wafers of the single-side gate SiC JFET device and the symmetrical double-side gate SiC JFET device prepared in Example 2 and Comparative Example 1 were placed on the carrier plate of the semiconductor probe station, and the test environment temperature was stabilized at 25°C using the temperature control system built into the probe station.

[0072] A high-precision microprobe holder is used to allow the probe tip to penetrate the native oxide layer on the device surface, forming stable ohmic contacts with the source metal pad, gate test pad, and back drain metal layer, respectively. The output of the probe system is connected to a semiconductor parameter analyzer and an LCR impedance meter via an RF coaxial switch matrix.

[0073] Static extraction of forward conduction characteristics is performed using a semiconductor parameter analyzer. The gate-source voltage is then... Set to 0V to make the drain-source voltage Perform a stepped scan within the linear region from 0V to 2.0V, with a scan step size of 0.05V. Record the source and drain currents under this bias condition. ,extract The current data at that time, combined with the effective physical area of ​​the measured device, is used to calculate and record the specific on-resistance. The specific value.

[0074] Switch the RF coaxial switch matrix and connect the probe path to the LCR impedance meter to perform dynamic parasitic capacitance extraction. Set the AC excitation signal frequency to 1MHz and the amplitude to 50mV. Set the gate-source voltage in the DC bias module. To ensure the channel is fully pinched off, a drain-source voltage of -15.0V is applied sequentially: 0V, 5.0V, 15.0V, and 30.0V. At each bias node, read the impedance imaginary part network parameters output by the test instrument, calculate and extract the corresponding gate-drain Miller capacitance. Numerical value.

[0075] Table 3. Comparison of static on-resistance and dynamic capacitance parameters between Example 2 and Comparative Example 1 in conclusion: Figure 5 The difference in on-resistance values ​​between the single-sided asymmetric gate structure of Example 2 and the double-sided symmetric gate structure of Comparative Example 1 is visually presented, corresponding to the physical behavior of static conduction loss.

[0076] Figure 6 The Miller capacitance values ​​of the two types of device structures at various drain-source voltages are shown by grouped bar charts, reflecting the direct impact of doping on the area of ​​parasitic capacitor plates on the second sidewall. The changes in the data ratio are consistent with the physical mechanism of the effective overlapping area on one side being halved.

[0077] Based on the data in Table 3, Under forward conduction conditions, the specific on-resistance measured for the double-sided symmetrical gate structure in Comparative Example 1 is 3.14 mΩ·cm. 2 The on-resistance of the single-sided asymmetric gate structure in Example 2 is 1.87 mΩ·cm. 2 This significant numerical difference is determined by the distribution mechanism of the space charge depletion layer within the channel region. In Comparative Example 1, both the first and second sidewalls are P+ type doped. Under zero bias, the depletion layer generated by the built-in electric field of the PN junctions on both sides simultaneously extends laterally into the N-type channel layer, physically compressing the effective conductive channel width for electrons from both sides. Example 2 maintains the undoped state of the second sidewall, eliminating the built-in electric field and depletion layer on that side, thus relatively increasing the effective conductive physical cross-sectional area of ​​the N-type channel layer, resulting in a significant reduction in specific on-resistance in macroscopic electrical tests.

[0078] Furthermore, regarding dynamic capacitance parameters, the gate-drain capacitance values ​​in Example 2 at each drain-source voltage node are approximately half the values ​​measured in Comparative Example 1. The magnitude of the Miller capacitance is directly limited by the physical overlap area between the gate and drain drift regions. In Comparative Example 1, the dual-sided P+ type sidewall gate regions spatially constitute a capacitor plate with twice the area. Example 2 achieves zero doping of the second sidewall in the tilted implantation process through the geometric shadowing effect, directly eliminating the sidewall overlap area of ​​half a trench depth at the device's physical structure level. Test data confirms that the single-sided asymmetric physical structure can achieve a geometrically proportional decrease in Miller capacitance parameters by reducing the parasitic plate area, demonstrating the physical effectiveness of the present invention in simultaneously optimizing device conduction characteristics and high-frequency switching performance without changing the mesa spacing.

[0079] Test Example 4: The single-side gate SiC JFET device wafers prepared in Example 2 and Comparative Example 2 were placed on the carrier disk of the high-voltage semiconductor probe stage. Fluoride liquid was dropped onto the wafer surface and the probe contact area to prevent air breakdown and surface arcing during the high-voltage test. The test environment temperature was controlled at 25°C.

[0080] Establish contact between the high-voltage test probe and the front interconnect thickened electrode (source), the P+ type bottom gate region test pad (gate), and the back drain metal layer on the device surface. Connect the probe to a semiconductor parameter analyzer equipped with a high-voltage test module.

[0081] In the parameter analyzer, set the device's turn-off bias condition and fix the gate-source voltage output at -15.0V to put the PN junction inside the device in a reverse bias state.

[0082] Set the drain-source voltage scan program, with the starting voltage set to 0V, the stopping voltage set to 2000V, and the voltage step value set to 5.0V. Set the system protection current (i.e., the breakdown threshold) to 1.0mA / mm.

[0083] Initiate the high-voltage blocking characteristic test, and the system synchronously records the leakage current data during the test. Extract the turn-off leakage current values ​​when the leakage-source voltage is 100V and 400V respectively, and record the leakage-source voltage corresponding to the leakage current reaching the threshold of 1.0mA / mm as the breakdown voltage of the device.

[0084] Table 4. Record of key electrical parameters for reverse blocking characteristics of Example 2 and Comparative Example 2 in conclusion: Figure 7 The nonlinear evolution of the leakage current as a function of drain-source voltage in the blocking state is illustrated using a semi-logarithmic coordinate system. The curve in Example 2 remains at 10 over a wide bias range. -2 The low current level, on the order of μA / mm, precisely corresponds to the extracted data from the 100V and 400V nodes in the table; while the curve in Comparative Example 2 shows severe leakage at the low voltage stage and rapidly rises to 10. 4 μA / mm or higher directly reflects the physical failure characteristics of the internal depletion layer not closing due to the shallow junction bottom gate.

[0085] Figure 8 The critical voltages for avalanche breakdown of the two structures were compared in the form of histograms. The macroscopic electrical difference was presented in which the overall voltage blocking capability of the device increased from 416V to 1582V after the vertical junction depth parameter was increased from 0.2μm to 1.0μm, which verified the necessity of deep level injection for building a continuous potential barrier.

[0086] According to the data in Table 4, under the same -15.0V gate-source voltage turn-off condition, the device in Comparative Example 2 exhibited a higher turn-off leakage current, reaching 18450 μA / mm at a drain-source voltage of only 100V, and its breakdown voltage plummeted to 416V, demonstrating significant blocking failure characteristics. In contrast, Example 2 showed a turn-off leakage current of only 0.037 μA / mm at a drain-source voltage of 400V, with a breakdown voltage reaching 1582V, demonstrating stable high-voltage turn-off and blocking capabilities. The difference in electrical parameters between the two devices stems from the physical determinant effect of the bottom gate vertical junction depth on the spatial distribution of the internal depletion layer. In Comparative Example 2, the vertical junction depth of the P+ type bottom gate region formed by shallow injection at the bottom is only 0.2 μm, which does not meet the design requirement of being greater than or equal to 0.5 times the mesa structure width (i.e., 0.9 μm).

[0087] When a reverse turn-off bias is applied, the vertical depletion layer extending upwards from the bottom gate region cannot physically overlap and close with the lateral depletion layer extending laterally from the sidewall gate region. This results in an undepleted intrinsic conductive channel remaining at the interface between the N-type channel layer and the N-type drift layer. Electrons driven by the high voltage directly penetrate this unclosed region, forming a macroscopic leakage current. Simultaneously, the drastic change in the cross-section of the physical channel causes severe local electric field concentration, inducing premature breakdown of the device at low voltage.

[0088] Example 2 utilizes a deep-level cascade implantation process to achieve a vertical junction depth of 1.0 μm, which geometrically reduces the physical distance between the bottom gate region and the top source and sidewall gate regions. Under turn-off bias, the vertical depletion layer generated by the deep junction structure effectively covers the central region of the mesa width and completely merges with the lateral depletion layer of the single sidewall to form a continuous potential barrier, physically cutting off the electron drift path. The test results, based on the actual blocking electrical performance of the device, confirm the necessity of setting a vertical junction depth greater than or equal to 0.5 times the mesa structure width for reliable pinch-off in single-gate asymmetric structures.

[0089] Test Example 5: The single-gate SiC JFET device wafers prepared in Example 1 and Comparative Example 3 were fixed on the vacuum carrier disk of the semiconductor probe station, and the test environment temperature was set and maintained at 25°C.

[0090] Three sets of DC test probes are moved using a micromanipulator to establish electrical contacts between the probe tips and the source metal interconnect layer on the device surface, the P+ type bottom gate extended test pad, and the drain metal layer on the back of the wafer, respectively. The probe ends are connected to the corresponding test units of the semiconductor parameter analyzer via low-noise coaxial cables.

[0091] Establish a transfer characteristic test sequence in the semiconductor parameter analyzer control software. Set the drain-source voltage to a constant 5.0V, the gate-source voltage scan start point to -12.0V, the cutoff point to 2.0V, and the voltage step size to 0.1V. Run the test sequence to acquire leakage current test data, and extract the horizontal intercept of the square root of the leakage current versus the gate-source voltage curve to calculate the device threshold voltage.

[0092] Establish an output characteristic test sequence. Set the gate-source voltage to 0V to put the device in its normal conduction state. Set the drain-source voltage scan range to 0V to 10.0V, with a step size of 0.05V. Run the test program to record the leakage current values ​​at different drain-source voltages. Extract the current data when the drain-source voltage is 2.0V, and calculate the forward ratio on-resistance based on the effective operating area of ​​the device. Simultaneously record the saturation leakage current value at high drain-source voltages.

[0093] Table 5. Record of electrical parameters affected by tilt injection angle in Example 1 and Comparative Example 3 in conclusion: Figure 9 The process of extracting the device transfer characteristics and threshold voltage is demonstrated. The intercept of the curve in Example 1 on the horizontal axis is -5.78V, while the intercept of the curve in Comparative Example 3 shifts positively to -2.42V. This change in intercept directly reflects that in Comparative Example 3, the excessively large injection angle led to unexpected doping of the second sidewall, which in turn compressed the initial channel width at zero bias, reducing the external reverse bias required to achieve channel pinch-off.

[0094] Figure 10 The current output capability of the device in the on-state is presented. At the node with a drain-source voltage of 5.0V, the saturation leakage current of Example 1 reaches 421.3mA / mm, while the saturation leakage current of Comparative Example 3 decreases to 198.7mA / mm; at the same time, in the linear region, the slope of the curve of Example 1 is significantly greater than that of Comparative Example 3, corresponding to the on-resistance in Table 5 starting from 1.164mΩ·cm. 2 Increased to 2.893 mΩ·cm 2 The physical properties of the sample verified the direct reduction effect of spatial geometric occlusion failure on the cross-sectional area of ​​the conductive channel.

[0095] According to the data in Table 5, the threshold voltage of Example 1 is -5.78V, and the specific on-resistance is 1.164mΩ·cm. 2 In Comparative Example 3, the threshold voltage exhibits a positive drift, with a extracted value of -2.42V, and the on-resistance increases to 2.893 mΩ·cm. 2The saturation leakage current decreased from 421.3 mA / mm to 198.7 mA / mm. The difference in electrical parameters is determined by the spatial geometric shielding mechanism in the tilted implantation process. In Example 1, the ratio of mesa width to groove depth was set to 1.0 / 1.5, and the implantation angle of 15° satisfied the spatial geometric relationship that the tangent value was less than this ratio. Under these conditions, the straight-line transmission path of the ion beam was physically blocked by the adjacent mesa structure, preventing it from reaching the second sidewall surface and maintaining the undoped state of the second sidewall, thus ensuring the effective physical width of the N-type channel layer.

[0096] Comparative Example 3 changed the injection angle to 50°, with a tangent of 1.19 greater than the ratio of mesa width to trench depth (0.67). The ion beam crossed the top shielding region of the adjacent mesa structure, directly bombarding the second sidewall and forming an unintended P-type doping in this region. The unintended doping generated an additional PN junction structure on the second sidewall. Under zero bias, the built-in electric field of this additional PN junction caused the depletion layer to extend into the N-type channel layer, physically reducing the cross-sectional area of ​​the conductive channel, resulting in an increase in specific on-resistance and a decrease in saturation leakage current. When a negative gate bias was applied, since the initial effective width of the channel had been compressed by the unintended depletion layer, only a small external reverse voltage was needed to completely close the space charge region within the channel, resulting in a decrease in the absolute value of the threshold voltage and a drift towards zero voltage. The data comparison of this test example verifies the geometrical constraint that the ion beam incident angle tangent must be less than or equal to the ratio of trench width to trench depth, which is a necessary technical parameter for achieving unilateral lateral doping and ensuring that the device achieves the designed conduction performance.

[0097] Test Example 6: The transmission line model (TLM) test pattern area reserved on the wafer prepared in Example 2 and Comparative Example 4 was placed on the stage of the semiconductor probe station. The system vacuum adsorption function was turned on to fix the wafer, and the ambient temperature of the probe station was set to 25°C.

[0098] Operate the microprobe system to establish physical connections between the tips of the four test probes and adjacent rectangular nickel silicide metal contact pads in the TLM test structure. The other ends of the probes are bridged to the source test unit of the semiconductor parameter analyzer via a matrix switch.

[0099] Set the constant current source scanning mode in the parameter analyzer. Apply a DC test current between two adjacent metal contact pads, setting the current scan range to -10.0mA to 10.0mA and the scan step size to 0.5mA. Start the test, simultaneously measure and record the voltage drop between the two pads, and extract the slope of the current-voltage curve to obtain the total resistance value between the two pads.

[0100] The probe contacts different pad pairs sequentially, and the total resistance is measured for pad spacing of 5μm, 10μm, 15μm, 20μm, and 25μm. The discrete resistance data for each spacing node is recorded. 5. Contact parameters are extracted using the transmission line model formula. A linear fit is performed with pad spacing as the x-axis and total resistance as the y-axis. The contact resistance is calculated by extracting the y-intercept of the fitted line. ), combined with the set physical width of the contact pads and the extracted sheet resistance of the semiconductor layer ( ), which is converted to the contact resistance ( The specific value of ).

[0101] Table 6. Record of TLM contact resistance test parameters for Example 2 and Comparative Example 4 in conclusion: Figure 11 The results demonstrate the linear distribution of discrete total resistance data recorded during the testing process as the pad spacing increases. In Example 2, the data points, the slope of the fitted line, and the y-intercept are all at relatively low levels, reflecting the protective effect of the in-situ carbon protective film process on the sheet resistance of the semiconductor surface and the metal-semiconductor contact resistance. In Comparative Example 4, the slope of the fitted line is significantly increased, and the y-intercept is significantly higher, corresponding to the physical manifestations of surface lattice damage and high contact barriers caused by annealing without a protective film.

[0102] Figure 12 A semi-logarithmic coordinate system was used to visually quantify the difference in specific contact resistance between the two types of device structures. The specific contact resistance in Example 2 was maintained at 10. -5 Ω·cm 2 The excellent ohmic contact standard is on the order of magnitude, while the standard of 4 deteriorates to 10. -3 Ω·cm 2 The chart, at the macroscopic electrical parameter level, confirms the necessity of maintaining the stoichiometry of the silicon carbide surface for reducing the interface state density and forming low-resistivity contact plates.

[0103] Based on the data in Table 6, the specific contact resistance extracted in Example 2 is 5.37 × 10⁻⁶. -5 Ω·cm 2 The specific contact resistance measured in Comparative Example 4 was 8.62 × 10⁻⁶. -3 Ω·cm 2The two exhibit a difference of more than two orders of magnitude in contact resistance. This drastic change in contact resistance is dominated by the physical mechanism of material composition and morphological evolution on the wafer surface during high-temperature activated annealing. In Example 2, a carbon protective film was synthesized in situ on the wafer surface before ion implantation activated annealing. During the annealing thermodynamic process at higher temperatures (e.g., above 1600°C), this carbon protective film physically blocks the outward sublimation pathway of silicon atoms in the silicon carbide material, maintains the original stoichiometry of silicon and carbon on the wafer surface, and protects the lattice integrity and flatness of the surface.

[0104] After depositing nickel metal on this high-quality surface, a uniform and dense nickel silicide (Ni2Si) alloy layer can be formed, thereby establishing a low-barrier ohmic contact on the physical contact surface, corresponding to a lower specific contact resistance extraction value. Comparative Example 4 was directly subjected to high-temperature annealing without a carbon protective film. Thermodynamic drive caused a large number of silicon atoms to escape from the surface, leaving excessive carbon atoms on the surface and forming a graphitization layer, accompanied by severe macroscopic morphological damage such as step clustering.

[0105] The imbalance in surface stoichiometry and the sharp increase in lattice defect density severely hindered the subsequent full alloying reaction between nickel and silicon atoms, leading to the formation of high-density interface state traps and Schottky barriers at the interface. Macroscopic electrical tests directly manifested this as a significant increase in the total resistance at each spacing node, and a marked degradation in the calculated specific contact resistance. This comparative data demonstrates that, in the fabrication process of this example, the in-situ synthesis of a carbon protective film is a necessary technique for suppressing surface silicon sublimation, maintaining the physicochemical properties of the device electrode contact area, and achieving low-impedance ohmic contacts.

Claims

1. A single-gate SiC JFET structure with low on-resistance, characterized in that, It includes an N+ type substrate, an N- type drift layer located on the front side of the N+ type substrate, an N- type channel layer located on the N- type drift layer, and an N+ type source layer located on top of the N-type channel layer; The N+ type source layer, the N type channel layer and the N- type drift layer are provided with grooves, which separate the upper part of the device into a surface structure; The groove has a first sidewall, a second sidewall, and a bottom. The first sidewall has a P+ type sidewall gate region, and the second sidewall is not P-type doped and remains an N-type semiconductor material; The bottom of the groove is provided with a P+ type bottom gate region, and the vertical junction depth of the P+ type bottom gate region is 0.5μm-1.5μm; The vertical junction depth of the P+ type bottom gate region is ≥ 0.5 times the width of the mesa structure; The P+ type bottom gate region extends laterally on one side directly below the first sidewall and the second sidewall, forming a lateral extension region with a width of 0.1μm-0.3μm.

2. The single-gate SiC JFET structure with low on-resistance according to claim 1, characterized in that, The thickness of the N-type drift layer is 5.0-15.0 μm, the nitrogen doping concentration is 1.0 x 10 15 cm -3 -8.0 x 10 15 cm -3 ; The thickness of the N-type channel layer is 0.5-1.5 μm, the nitrogen doping concentration is 1.0x1018-5.0x1018 cm-3. 16 cm -3 -5.0x1018 cm-3. 16 cm -3 ; The thickness of the N+ type source layer is 0.2 μm-0.5 μm, and the nitrogen doping concentration is 1.0 × 10⁻⁶. 19 cm -3 -1.0×10 20 cm -3 .

3. The single-gate SiC JFET structure with low on-resistance according to claim 1, characterized in that, The groove has a depth of 1.5μm-3.5μm, a width of 1.0μm-3.0μm, and a platform structure width of 1.0μm-2.5μm. The angle between the first sidewall and the second sidewall and the bottom of the groove is between 85° and 90°; the lateral junction depth of the P+ type sidewall gate region within the first sidewall is 0.1μm-0.4μm.

4. A method for manufacturing a single-gate SiC JFET structure with low on-resistance, characterized in that, Fabricating a single-gate SiC JFET structure with low on-resistance as described in any one of claims 1-3 includes the following steps: An N-type drift layer, an N-type channel layer, and an N+ type source layer are epitaxially grown sequentially on the front side of an N+ type substrate. A hard mask is deposited and patterned on the surface of the N+ type source layer. Using the hard mask as a barrier layer, the N+ type source layer and the N- type channel layer are sequentially etched downwards and penetrated into the N- type drift layer to form a groove and a mesa structure separated by the groove. The groove exposes a first sidewall, a second sidewall and a bottom of the groove. The hard mask is retained, and aluminum ions are vertically implanted at the bottom of the groove to form a P+ type bottom gate region with a vertical junction depth of 0.5μm-1.5μm. Under the lateral dispersion of the implanted ions, the P+ type bottom gate region extends laterally to the first sidewall and the second sidewall to form a 0.1μm-0.3μm unilateral lateral extension region. The hard mask is retained, and aluminum ion single-sided tilt implantation is performed. The incident angle of the aluminum ion single-sided tilt implantation is set to 15°-40°, and the incident angle is adjusted according to the width and depth of the groove formed by etching, so that the tilted incident ion beam is blocked by the adjacent mesa structure, so that the aluminum ions only bombard the first sidewall to form a P+ type sidewall gate region, and the second sidewall is completely in the shadow area of ​​the adjacent mesa structure without doping. The P+ type sidewall gate region is connected to the P+ type bottom gate region formed by the aforementioned vertical implantation. Remove the hard mask and synthesize a carbon protective film in situ on the device surface having the P+ type bottom gate region and the P+ type sidewall gate region. Then perform an impurity activation annealing process to activate the aforementioned vertically implanted and unilaterally tilted implanted aluminum ions. After annealing, remove the carbon protective film by ashing. Interlayer dielectric is deposited on the device surface and contact holes are etched to expose the N+ type source layer and the P+ type bottom gate region, followed by metallization to obtain the electrode.

5. The method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, When performing vertical implantation of aluminum ions at the bottom of the groove, the implantation direction is at an angle of 0°-4° to the normal of the wafer surface, the implantation energy ranges from 30keV to 800keV, and the total implantation dose ranges from 1.0×10⁻⁶. 13 cm -2 -5.0×10 14 cm -2 During the implantation process, the wafer temperature is maintained at 400℃-600℃.

6. A method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, When performing unilateral tilted implantation of aluminum ions, the implantation energy range is 30keV-350keV, and the implantation dose is controlled at 5.0×10⁻⁶. 12 cm -2 -1.0×10 14 cm -2 During the implantation process, the wafer temperature is maintained at 400℃-600℃.

7. The method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, The in-situ synthesis of the carbon protective film on the device surface includes: A polyimide solution is spin-coated onto the wafer surface to form a polymer film with a thickness of 1.5 μm to 3.0 μm; Pre-baking for 5-15 minutes within the range of 150℃-250℃; Amorphous graphitized carbon films with a thickness of 30nm-80nm were synthesized in situ by heating to 800℃-1000℃ at a heating rate of 5℃ / min-10℃ / min and holding for 30min-60min under an argon atmosphere.

8. A method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, The impurity activation annealing process is carried out in an argon atmosphere, with an annealing temperature of 1600℃-1750℃ and a holding time of 20min-45min. The removal of the carbon protective film by ashing is carried out by introducing oxygen plasma at a temperature of 600℃-800℃.

9. A method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, When etching downwards sequentially through the N+ type source layer and the N type channel layer and into the N- type drift layer, an inductively coupled plasma dry etching process is used. The etching gas components include sulfur hexafluoride and oxygen, wherein the sulfur hexafluoride gas flow rate is 30 sccm-60 sccm and the oxygen flow rate is 5 sccm-15 sccm.

10. A method for manufacturing a single-gate SiC JFET structure with low on-resistance according to claim 4, characterized in that, The specific steps of obtaining the electrode through metallization include: A nickel film with a thickness of 50nm-100nm was deposited and then rapidly thermally annealed at 950℃-1050℃ for 2min-5min under a nitrogen atmosphere to form a nickel silicide ohmic contact layer. An aluminum layer is deposited on the nickel silicide ohmic contact layer as a front interconnect thickening electrode; After thinning the back side of the N+ type substrate to 100μm-150μm, a stacked electrode system of titanium, nickel and silver layers is sequentially deposited to form the back drain metal layer.

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