Switching element and method for manufacturing the same

Abstract

A switching element and a method for manufacturing the same are disclosed. The switching element comprises: a semiconductor substrate having a plurality of dummy trenches spaced apart on its upper surface and extending along a first direction; a gate insulating film in contact with a portion sandwiched between the plurality of dummy trenches, i.e., a device region; a gate electrode; and a source electrode in contact with the device region. The semiconductor substrate comprises: a source region disposed within the device region; a body region disposed within the device region; a drift region distributed from the device region to a position lower than each of the dummy trenches; an intermediate second conductivity type region extending linearly within the drift region along a second direction intersecting the first direction; and a plurality of second conductivity type connection regions adjacent to each of the dummy trenches, connecting each of the intermediate second conductivity type regions to the source electrode.

Description

Technical Field

[0001] The technology disclosed in this specification relates to switching elements and their manufacturing methods. Background Technology

[0002] Patent Document 1 discloses a gate-type switching element. Furthermore, in this specification, switching elements include MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and the like.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2023-027360 Summary of the Invention

[0004] When a switching element turns off at high speed, a surge voltage is generated, which may sometimes lead to avalanche current in the drift region. This avalanche current flows through the interior of the semiconductor substrate to the source electrode. At this time, when the avalanche current flows near the gate, the gate insulating film may degrade due to the heat generated by the avalanche current. This specification proposes techniques to suppress the degradation of the gate insulating film when avalanche current is generated.

[0005] The switching element disclosed in this specification includes: a semiconductor substrate having a plurality of dummy trenches extending along a first direction at intervals on its upper surface in a direction orthogonal to the first direction; a gate insulating film in contact with a portion of the semiconductor substrate sandwiched by the plurality of dummy trenches, i.e., a device region; a gate electrode in contact with the gate insulating film and insulated from the semiconductor substrate by the gate insulating film; and a source electrode in contact with the device region. The semiconductor substrate has a source region, a body region, a drift region, an intermediate second conductivity type region, and a plurality of connection regions. The source region is disposed within the device region and is a first conductivity type region in contact with the source electrode and the gate insulating film. The body region is disposed within the device region and is a second conductivity type region in contact with the source region and the gate insulating film. The drift region extends from within the device region to a position lower than each of the dummy trenches and is in contact with the body region and the gate insulating film within the device region. The plurality of intermediate second conductive regions are second conductive regions that extend linearly along a second direction intersecting the first direction and are spaced apart in a direction orthogonal to the second direction within the drift region. The lower ends of each intermediate second conductive region are positioned lower than the lower ends of each dummy trench. The plurality of connection regions are adjacent to each dummy trench and are second conductive regions that connect each intermediate second conductive region to the source electrode.

[0006] In this specification, one of the first conductivity type and the second conductivity type means n-type and the other means p-type.

[0007] Furthermore, in this specification, the drift region is the area where current flows when the switching element is turned on and is depleted when the switching element is turned off.

[0008] In this switching element, an intermediate second conductivity region is provided within the drift region. This intermediate second conductivity region is connected to the source electrode via a connection region, thus having approximately the same potential as the source electrode. Therefore, when an avalanche current is generated in the drift region, the avalanche current flows into the intermediate second conductivity region. The avalanche current flowing into the intermediate second conductivity region flows to the source electrode via the connection region. Furthermore, the connection region is adjacent to dummy trenches disposed at both ends of the element region, and is therefore located away from the gate insulating film. Therefore, even if the connection region generates heat due to the flow of avalanche current, the heat is difficult to transfer to the gate insulating film. Thus, degradation of the gate insulating film can be suppressed. Attached Figure Description

[0009] Figure 1 This is a perspective view of the switching element in Embodiment 1.

[0010] Figure 2This is a perspective view of the switching element in Embodiment 1 (the source electrode is omitted).

[0011] Figure 3 This is a perspective view showing a modified example of Example 1 (the source electrode is omitted).

[0012] Figure 4 This is a perspective view showing a modified example of Example 1 (the source electrode is omitted).

[0013] Figure 5 This is a perspective view showing a modified example of Example 1 (the source electrode is omitted).

[0014] Figure 6 This is a perspective view of the switching element in Embodiment 2 (the source electrode is omitted).

[0015] Figure 7 This is a perspective view of a modified example of Example 2 (the source electrode is omitted).

[0016] Figure 8 This is a perspective view of the switching element in Embodiment 3 (the source electrode is omitted).

[0017] Figure 9 This is a perspective view of a modified example of Example 3 (the source electrode is omitted).

[0018] Figure 10 This is an explanatory diagram illustrating the manufacturing method of the switching element in Example 3.

[0019] Figure 11 This is an explanatory diagram illustrating the manufacturing method of the switching element in Example 3.

[0020] Figure 12 This is an explanatory diagram illustrating the manufacturing method of the switching element in Example 3.

[0021] Figure 13 This is an explanatory diagram illustrating the manufacturing method of the switching element in Example 3.

[0022] Figure 14 This is an explanatory diagram illustrating the manufacturing method of the switching element in Example 3.

[0023] Figure 15 This is an illustrative diagram illustrating a variation of the groove configuration pattern.

[0024] Figure 16 This is an illustrative diagram illustrating a variation of the groove configuration pattern.

[0025] Figure 17 This is an illustrative diagram illustrating a variation of the groove configuration pattern.

[0026] Figure 18 This is an illustrative diagram illustrating a variation of the groove configuration pattern.

[0027] Figure 19 This is a diagram showing a variation of the internal structure of a fictitious trench.

[0028] Figure 20 This is a diagram showing a variation of the connection region.

[0029] Figure 21 This is a diagram showing a variation of the connection region.

[0030] Figure 22 This is a perspective view showing an embodiment of a planar switching element. Detailed Implementation

[0031] [Example 1] Figure 1 , Figure 2 The switching element 10 in Embodiment 1 shown is a MOSFET. The switching element 10 has a semiconductor substrate 12, a source electrode 14, and a drain electrode 16. Furthermore, in Figure 2 The source electrode 14 is omitted from the diagram. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 can also be made of other semiconductor materials such as Si and GaN. Figure 1 As shown, the source electrode 14 covers the upper surface 12a of the semiconductor substrate 12. Figure 1 , Figure 2 As shown, the drain electrode 16 covers the lower surface 12b of the semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction, a direction in a plane perpendicular to the z-direction will be referred to as the x-direction, and a direction in the plane orthogonal to the x-direction will be referred to as the y-direction.

[0032] A plurality of gate trenches 20 and a plurality of dummy trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. The gate trenches 20 function as the gates of MOSFETs and form channels along the sides of the MOSFETs when they are turned on. The dummy trenches 22 do not function as the gates of MOSFETs and do not form channels along the sides of the MOSFETs when they are turned on. The gate trenches 20 and the dummy trenches 22 extend linearly along the y-direction on the upper surface 12a. The depths of the gate trenches 20 and the dummy trenches 22 are approximately equal.

[0033] The dummy trenches 22 are arranged at intervals in the x-direction. At some locations, a spacer C1 is provided between the dummy trenches 22 along the x-direction, and at other locations, a spacer C2 is provided between the dummy trenches 22 along the x-direction. Spacer C2 is longer than spacer C1. Multiple dummy trenches 22 are arranged in the x-direction with alternating spaces C1 and C2. Hereinafter, the portion of the semiconductor substrate 12 sandwiched between two dummy trenches 22 separated by a spacer C2 is referred to as the device region 26. Each gate trench 20 is disposed within the device region 26. Multiple (two in this embodiment) gate trenches 20 are disposed within each device region 26. Therefore, these trenches are arranged in a manner where two dummy trenches 22 and two gate trenches 20 alternately and repeatedly in the x-direction.

[0034] A gate insulating film 20a and a gate electrode 20b are disposed within each gate trench 20. The gate insulating film 20a covers the inner surface of the gate trench 20. The gate electrode 20b is disposed at a position surrounded by the gate insulating film 20a. The gate electrode 20b is insulated from the semiconductor substrate 12 through the gate insulating film 20a. The upper surface of the gate electrode 20b is covered by an interlayer insulating film 20c. The gate electrode 20b is insulated from the source electrode 14 through the interlayer insulating film 20c. Each gate electrode 20b is connected to a gate pad disposed at a position not shown. The potential of each gate electrode 20b is controlled by the gate pad.

[0035] An insulating film 22a and a dummy electrode 22b are disposed within each dummy trench 22. The insulating film 22a covers the inner surface of the dummy trench 22. The dummy electrode 22b is disposed at a position surrounded by the insulating film 22a. No interlayer insulating film is disposed on the upper surface of the dummy electrode 22b, and the dummy electrode 22b is connected to the source electrode 14 on its upper surface. In addition, the dummy electrode 22b is insulated from the gate electrode 20b. Therefore, the potential of the gate electrode 20b is controlled independently of the potential of the dummy electrode 22b.

[0036] The semiconductor substrate 12 has multiple n-type source regions 30, multiple p-type contact regions 32, a p-type body region 34, multiple intermediate p-type regions 36, multiple p-type connection regions 38, an n-type drift region 40, and an n-type drain region 42.

[0037] Source region 30 is an n-type region with a high n-type impurity concentration. Source region 30 is disposed within device region 26. Source region 30 is disposed in the area sandwiched between two gate trenches 20, and in the area sandwiched between the gate trenches 20 and a dummy trench 22. Each source region 30 is disposed within the area including the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the source electrode 14. Each source region 30 is connected to the gate insulating film 20a at the upper end of the side of the gate trench 20. Each source region 30 extends linearly along the y-direction.

[0038] Contact region 32 is a p-type region with a high p-type impurity concentration. Contact region 32 is disposed within device region 26. Contact region 32 is disposed in the area sandwiched between two gate trenches 20, and in the area sandwiched between the gate trenches 20 and dummy trenches 22. Each contact region 32 is disposed adjacent to the source region 30. Each contact region 32 is disposed in the area including the upper surface 12a of the semiconductor substrate 12, and is in ohmic contact with the source electrode 14. Each contact region 32 extends linearly along the y-direction. Furthermore, contact region 32 may also be disposed in the area sandwiched between two dummy trenches 22.

[0039] Body region 34 is a p-type region with a lower p-type impurity concentration compared to contact region 32. Body region 34 is distributed across a region sandwiched by two gate trenches 20, a region sandwiched by gate trench 20 and dummy trench 22, and a region sandwiched by two dummy trenches 22. Body region 34 is connected from below within element region 26 relative to source region 30 and contact region 32. Body region 34 is connected to source electrode 14 via contact region 32. Body region 34 is connected to gate insulating film 20a below source region 30.

[0040] The drift region 40 is the region where electrons flow when the switching element is turned on and are depleted when the switching element is turned off. In this embodiment, the drift region 40 is an n-type region with a lower n-type impurity concentration than the source region 30. The drift region 40 is distributed across the range sandwiched by each trench (i.e., the range sandwiched by the two gate trenches 20, the range sandwiched by the gate trench 20 and the dummy trench 22, and the range sandwiched by the two dummy trenches 22). Furthermore, the drift region 40 is distributed from the range sandwiched by each trench to a position lower than the lower end of the gate trench 20 and the lower end of the dummy trench 22. The drift region 40 is distributed from the range sandwiched by each trench to a position near the lower surface 12b of the semiconductor substrate 12. The drift region 40 is connected to the body region 34 from the bottom within the device region 26. The drift region 40 is separated from each source region 30 by the body region 34. The drift region 40 is connected to the gate insulating film 20a on the lower side of the body region 34.

[0041] The intermediate p-type region 36 is a p-type region with a lower p-type impurity concentration than the contact region 32 and a higher concentration than the body region 34. Each intermediate p-type region 36 extends linearly along the x-direction inside the drift region 40. The plurality of intermediate p-type regions 36 are arranged spaced apart by a gap C3 in the y-direction. The drift region 40 is distributed within the gap C3. In other words, the drift region 40 is distributed from the upper side to the lower side of the intermediate p-type region 36 via the gap C3. Each intermediate p-type region 36 is in contact with the drift region 40 on its upper surface, lower surface, and side surface. The intermediate p-type region 36 is positioned lower than the lower end of the gate trench 20 and the lower end of the dummy trench 22. That is, both the upper and lower ends of the intermediate p-type region 36 are positioned lower than the lower ends of the gate trench 20 and the lower ends of the dummy trench 22.

[0042] The connection region 38 is a p-type region with a lower p-type impurity concentration than the contact region 32 and a higher concentration than the body region 34. The connection region 38 is disposed in the region adjacent to the corresponding dummy trench 22. More specifically, the connection region 38 is disposed from the region adjacent to the side of the corresponding dummy trench 22 to the region adjacent to the bottom surface. The connection region 38 extends linearly along the corresponding dummy trench 22 in the y-direction. The connection region 38 is connected to the source electrode 14 at its upper end. The connection region 38 is connected to each intermediate p-type region 36 at its lower end. Therefore, each intermediate p-type region 36 is connected to the source electrode 14 via the connection region 38.

[0043] Drain region 42 is an n-type region with a higher n-type impurity concentration than drift region 40. Drain region 42 is disposed below drift region 40 and is in contact with drift region 40. Drain region 42 is in ohmic contact with drain electrode 16 on the lower surface 12b of semiconductor substrate 12.

[0044] Next, the operation of the switching element 10 will be explained. The switching element 10 is used when a higher potential than the source electrode 14 is applied to the drain electrode 16. When a potential higher than the gate threshold is applied to the gate electrode 20b, a channel is formed in the body region 34 adjacent to the gate insulating film 20a. That is, the channel is formed in the body region 34 within the element region 26. The source region 30 is connected to the drift region 40 through the channel. Thus, electrons flow from the source electrode 14 through the source region 30 and the channel into the drift region 40. Within the drift region 40, electrons flow from the upper part of the intermediate p-type region 36 through the spacer C3 to the lower part of the intermediate p-type region 36. Electrons flowing to the lower end of the drift region 40 flow to the drain electrode 16 through the drain region 42. With the flow of electrons in this way, current flows from the drain electrode 16 to the source electrode 14. That is, the switching element 10 is turned on.

[0045] When the potential of the gate electrode 20b is reduced to a level below the gate threshold, the channel disappears and the current stops. That is, the switching element 10 is turned off. When the switching element 10 is turned off, the potential of the drift region 40 rises. Since the body region 34 has approximately the same potential as the source electrode 14, a reverse voltage is applied to the pn junction at the interface between the body region 34 and the drift region 40 when the potential of the drift region 40 rises. Therefore, the depletion layer extends from the body region 34 to the drift region 40. In addition, the intermediate p-type region 36 is connected to the source electrode 14 via the connection region 38, and therefore the intermediate p-type region 36 has approximately the same potential as the source electrode 14. Therefore, when the potential of the drift region 40 rises, a reverse voltage is also applied to the pn junction at the interface between the intermediate p-type region 36 and the drift region 40. Therefore, the depletion layer extends from the intermediate p-type region 36 to the drift region 40. If the switching element 10 is turned off in this way, the depletion layer extends from the body region 34 and the intermediate p-type region 36 to the drift region 40. The electric field generated at the lower end of the gate trench 20 is suppressed by extending the depletion layer from the intermediate p-type region 36 to the drift region 40. In particular, since the intermediate p-type region 36 has approximately the same potential as the source electrode 14, the electric field generated at the lower end of the gate trench 20 is effectively suppressed. Therefore, the concentration of the electric field towards the gate insulating film 20a covering the lower end of the gate trench 20 is suppressed.

[0046] Furthermore, in the switching element 10, by providing an intermediate p-type region 36 at the lower part of the gate electrode 20b, the capacitance (i.e., the feedback capacitance) between the gate electrode 20b and the drain electrode 16 is reduced. Therefore, the switching element 10 can switch at high speed.

[0047] Furthermore, when the switching element 10 is turned off, the current flowing through the switching element 10 decreases sharply, thus applying a high surge voltage to the switching element 10. This sometimes generates a high electric field within the drift region 40, resulting in an avalanche current. The avalanche current flows from the drift region 40 to the source electrode 14. When the avalanche current flows near the gate insulating film 20a, the gate insulating film 20a is sometimes exposed to high temperatures and degrades. Additionally, if the avalanche current flows near the gate insulating film 20a, hot carriers are captured by the gate insulating film 20a, sometimes causing fluctuations in the gate threshold. However, in this embodiment, as explained below, the flow of avalanche current to the vicinity of the gate insulating film 20a is prevented by the intermediate p-type region 36 and the connection region 38. As described above, in this embodiment, the intermediate p-type region 36 has approximately the same potential as the source electrode 14. Therefore, when an avalanche current is generated within the drift region 40, the avalanche current flows into the intermediate p-type region 36. The avalanche current flowing into the intermediate p-type region 36 flows to the source electrode 14 via the connection region 38. For example... Figure 1 , Figure 2As shown, connection regions 38 are disposed at both ends of element region 26, located away from gate insulating film 20a. That is, avalanche current flows to source electrode 14 through a location away from gate insulating film 20a. Therefore, in this embodiment, the degradation of gate insulating film 20a caused by avalanche current is suppressed.

[0048] Furthermore, in the above-described embodiment 1, the contact area 32 extends linearly along the y-direction (i.e., the direction parallel to each trench). However, as... Figure 3 As illustrated, the contact area 32 can also extend linearly along the direction intersecting with each groove. Furthermore, the angle at which the contact area 32 intersects with each groove can be 90 degrees or other angles.

[0049] Furthermore, in Example 1 described above, the drift region 40 has a substantially fixed concentration of n-type impurities. However, as... Figure 4 As shown, the drift region 40a, which is above each intermediate p-type region 36, may have a higher n-type impurity concentration than the drift region 40b, which is below each intermediate p-type region 36. With this configuration, the resistance of the drift region 40 can be reduced within the area sandwiched by the trench (i.e., the area with a narrower current path), thereby reducing the on-resistance of the switching element.

[0050] Furthermore, in the above-described embodiment 1, the upper end of the intermediate p-shaped region 36 is positioned lower than the lower ends of the trenches 20 and 22. However, as... Figure 5 As shown, the upper end of the intermediate p-shaped region 36 can also be positioned above the lower ends of the grooves 20 and 22. That is, the intermediate p-shaped region 36 can also be positioned to overlap with the lower ends of the grooves 20 and 22 in the z-direction.

[0051] also, Figure 3 , Figure 4 , Figure 5 The configuration can also be combined with other embodiments described later.

[0052] [Example 2] Figure 6The switching element of Embodiment 2 shown has a plurality of low-concentration intermediate p-type regions 37. Each low-concentration intermediate p-type region 37 is a p-type region having a lower p-type impurity concentration than the intermediate p-type region 36 and the connecting region 38. Each low-concentration intermediate p-type region 37 is disposed below the corresponding intermediate p-type region 36. Each low-concentration intermediate p-type region 37 extends linearly along the intermediate p-type region 36 in the x-direction. Each low-concentration intermediate p-type region 37 is connected to the corresponding intermediate p-type region 36 from below. The plurality of low-concentration intermediate p-type regions 37 are arranged with a gap C3 in the y-direction. The drift region 40 above the intermediate p-type region 36 is connected to the drift region 40 below the low-concentration intermediate p-type region 37 via the gap C3. Furthermore, in Embodiment 2, the connecting region 38 extends from the upper surface 12a into the interior of the low-concentration intermediate p-type region 37. That is, the connecting region 38 penetrates the intermediate p-type region 36. The lower end of the connecting region 38 is disposed inside the low-concentration intermediate p-type region 37. Except for the points mentioned above, Example 2 is the same as Example 1.

[0053] When the switching element in Example 2 is turned off, the depletion layer extends into the low-concentration intermediate p-type region 37, where the p-type impurity concentration is lower. Therefore, the withstand voltage of the switching element 10 is further improved.

[0054] Furthermore, in Embodiment 2, the connection region 38 extends through the intermediate p-type region 36 and into the interior of the low-concentration intermediate p-type region 37. Therefore, when the switching element is turned off, the low-concentration intermediate p-type region 37 near the lower end of the connection region 38 is less likely to be depleted compared to other portions of the low-concentration intermediate p-type region 37. Consequently, electric field concentration easily occurs near the lower end of the connection region 38. Therefore, in the event of a high surge voltage applied to the switching element due to turn-off, avalanche breakdown occurs near the lower end of the connection region 38. Therefore, avalanche current easily flows through the connection region 38, and the flow of avalanche current near the gate insulating film 20a can be more reliably suppressed. Thus, the degradation of the gate insulating film 20a can be more effectively suppressed.

[0055] Furthermore, due to the high p-type impurity concentration in the connection region 38, the crystal defect density within the connection region 38 is also high. When the connection region 38, with its high crystal defect density, is depleted and an electric field is applied, leakage current may occur. However, in Embodiment 2, the connection region 38 does not penetrate the low-concentration intermediate p-type region 37, and the lower end of the connection region 38 is located inside the low-concentration intermediate p-type region 37. Therefore, when the switching element is turned off, the expansion of the depletion layer into the interior of the connection region 38 is prevented. Consequently, leakage current is suppressed.

[0056] Furthermore, in Example 2 described above, the low-concentration intermediate p-type region 37 extends linearly along the intermediate p-type region 36. However, as... Figure 7As shown, the low-concentration intermediate p-type region 37 can also extend linearly along the direction intersecting with the intermediate p-type region 36. In this configuration, a grid-like p-type region is formed by the intermediate p-type region 36 and the low-concentration intermediate p-type region 37. This configuration can also improve the withstand voltage of the switching element. In addition, the angle at which the low-concentration intermediate p-type region 37 intersects with the intermediate p-type region 36 can be 90 degrees or other angles. Thus, as long as the intermediate p-type region 36 extends linearly along the direction intersecting with the trench, the shape of the p-type region attached to the intermediate p-type region 36 (i.e., the low-concentration intermediate p-type region 37, etc.) is not particularly limited.

[0057] [Example 3] Figure 8 The switching element of Embodiment 3 shown has a drift region 40 with a different configuration than that of Embodiment 2. Except for the drift region 40, Embodiment 3 is the same as Embodiment 2.

[0058] like Figure 8 As shown, in Example 3, the drift region 40 at the lower part of the low-concentration intermediate p-type region 37 is composed of a superjunction layer 40s. The superjunction layer 40s has a superstructure in which multiple p-type layers 40p and multiple n-type layers 40n are alternately arranged in the x-direction. Each p-type layer 40p and each n-type layer 40n extends linearly in the y-direction. Each p-type layer 40p and each n-type layer 40n contacts the low-concentration intermediate p-type region 37 at its upper end. Above the intermediate p-type region 36, the drift region 40 is composed of an n-type layer 40c. The n-type layer 40c and Figure 4 Similarly, drift region 40a has a relatively high concentration of n-type impurities. n-type layer 40c has a higher concentration of n-type impurities than n-type layer 40n. Furthermore, n-type layer 40c can also be combined with... Figure 2 The drift region 40 also has a low concentration of n-type impurities. Furthermore, within the spacer C3, the drift region 40 is composed of an n-type layer with a low concentration similar to that of the n-type layer 40n. Additionally, the drift region 40 located below the superjunction layer 40s is composed of an n-type layer 40d with a low concentration similar to that of the n-type layer 40n. The n-type layer 40d is connected from below to the p-type layer 40p and the n-type layer 40n, and from above to the drain region 42.

[0059] When the switching element in Embodiment 3 is turned off, the depletion layer extends from the interfaces between the n-type layer 40n and the p-type layer 40p towards both the n-type layer 40n and the p-type layer 40p. Therefore, the superjunction layer 40s is easily depleted. Thus, according to the configuration of Embodiment 3, the withstand voltage of the switching element can be further improved.

[0060] Furthermore, in embodiment 3, the p-type layer 40p and the n-type layer 40n are alternately arranged in the x-direction, but it can also be arranged as follows: Figure 9As shown, p-type layer 40p and n-type layer 40n are arranged alternately in the y-direction. Alternatively, p-type layer 40p and n-type layer 40n can also be arranged alternately in other directions.

[0061] In Example 3, the p-type layer 40p and the n-type layer 40n are connected to the low-concentration intermediate p-type region 37. However, for example, in... Figure 2 In the case of using a superjunction layer in a switching element that does not have a low-concentration intermediate p-type region 37, the p-type layer 40p and the n-type layer 40n can also be connected to the intermediate p-type region 36.

[0062] Next, the manufacturing method of the switching element in the embodiment will be described. Here, as an example, the manufacturing method of the switching element in Embodiment 3 will be described. First, an n-type layer 40d and an n-type layer 40n are epitaxially grown on the drain region 42. Next, as... Figure 10 As shown, by implanting p-type impurities into the n-type layer 40n, a p-type layer 40p, a low-concentration intermediate p-type region 37, and an intermediate p-type region 36 are formed. Next, as... Figure 11 As shown, an n-type layer 40c, a body region 34, a contact region 32, and a source region 30 are formed by epitaxially growing a low-concentration semiconductor layer on a semiconductor substrate 12 and then performing ion implantation on the semiconductor layer. Next, as... Figure 12 As shown, by selectively etching the upper surface 12a of the semiconductor substrate 12, a gate trench 20 and a dummy trench 22 are simultaneously formed on the upper surface 12a. When the gate trench 20 and the dummy trench 22 are formed simultaneously in this way, the depth of the gate trench 20 is approximately equal to the depth of the dummy trench 22. Next, as... Figure 13 As shown, with the upper surface 12a and the gate trench 20 covered by the mask 60, p-type impurities are ion-implanted into the dummy trench 22. Here, p-type impurities are implanted into one side of the dummy trench 22 by irradiating the p-type impurities at an angle tilted relative to the thickness direction of the semiconductor substrate 12. Similarly, p-type impurities are implanted into the other side of the dummy trench 22. Furthermore, p-type impurities are also implanted into the bottom surface of the dummy trench 22. By implanting p-type impurities into the dummy trench 22 in this manner, as shown... Figure 14 The connection region 38 is formed as shown. Next, by forming the gate electrode 20b, dummy electrode 22b, source electrode 14, drain electrode 16, etc., the connection is completed. Figure 8 The switching element of Embodiment 3 is shown.

[0063] According to this manufacturing method, since the gate trench 20 and the dummy trench 22 are formed simultaneously, switching elements can be manufactured efficiently. Furthermore, according to this manufacturing method, since the connection region 38 is formed by ion implantation into the dummy trench 22, the connection region 38 can be formed with lower implantation energy. Therefore, the connection region 38 can be formed with a short ion implantation time, enabling efficient manufacturing of switching elements. Additionally, the connection region 38 can be formed stably, thus suppressing deviations in the characteristics of the switching element. Furthermore, the connection region 38 can also be formed by other formation methods. For example, the connection region 38 can be formed by deeper ion implantation into the upper surface 12a of the semiconductor substrate 12.

[0064] The following describes variations that can be used in the above embodiments.

[0065] Figures 15-18 A modified example of the configuration pattern of the gate trench 20 and the dummy trench 22 is shown. Additionally, in Figures 15-18 Only the trenches and connection region 38 are shown in the diagram; other parts are omitted. In embodiments 1-3 described above, two gate trenches 20 are arranged within a single element region 26. However, as... Figure 15 As shown, a gate trench 20 can also be configured within a single device region 26. Furthermore, three or more gate trenches 20 can be configured within a single device region 26. Additionally, in the above embodiment, two dummy trenches 22 are configured in the region between two device regions 26, but this can also be done as described above. Figure 16 As shown, a dummy trench 22 is configured in the area between the two component areas 26. Alternatively, three or more dummy trenches 22 can be configured in the area between the two component areas 26. Alternatively, as shown... Figure 17 As shown, a gate trench 20 and a dummy trench 22 are alternately configured. Additionally, as... Figure 18 As shown, the configuration pattern of the gate trench 20 and the dummy trench 22 can also vary depending on their positions.

[0066] In the above embodiments, an insulating film 22a and a dummy electrode 22b are disposed within the dummy trench 22. However, as... Figure 19 As shown, the dummy trench 22 can also be filled by the insulating layer 50. The dummy trench 22 can be any structure as long as it does not form a channel on the side.

[0067] In the above embodiments, the connecting area 38 is provided in a manner that covers the entire side and bottom surfaces of the dummy trench 22, but the connecting area 38 can also be provided partially relative to the dummy trench 22. For example, as Figure 20 As shown, a connection area 38 can also be provided only on one side of the dummy trench 22. Additionally, as... Figure 21As shown, the virtual trench 22 can also be alternately provided with a portion having a connection area 38 and a portion without a connection area 38 along its length direction (i.e., the y direction).

[0068] Furthermore, in the above embodiments, although the gate trench 20 and the dummy trench 22 have the same depth, the depths of the gate trench 20 and the dummy trench 22 may also be different.

[0069] In the above embodiment, a trench-type gate electrode 20b is provided in the element region 26. However, as... Figure 22 As shown, a planar gate electrode 20b can also be provided in the component area 26. Figure 22 In this configuration, a gate insulating film 20a is disposed covering the upper surface 12a, and a gate electrode 20b is disposed on the gate insulating film 20a. Furthermore, the source region 30, the body region 34, and the drift region 40 are in contact with the gate insulating film 20a on the upper surface 12a. This structure can suppress avalanche current flowing near the gate insulating film 20a and can also suppress the degradation of the gate insulating film 20a.

[0070] In the above embodiments, the switching element is a MOSFET, but it can also be an IGBT. In a MOSFET, an IGBT structure can be obtained by replacing the n-type drain region 42 with a p-type collector region. In this case, the source and drain can be referred to as the emitter and collector, respectively.

[0071] The technical components disclosed in this specification are listed below.

[0072] (Component 1) A switching element includes: a semiconductor substrate having a plurality of dummy trenches spaced apart on its upper surface in a direction orthogonal to a first direction and extending along the first direction; a gate insulating film connected to a portion of the semiconductor substrate sandwiched by the plurality of dummy trenches, i.e., a device region; a gate electrode connected to the gate insulating film and insulated from the semiconductor substrate through the gate insulating film; and a source electrode connected to the device region. The semiconductor substrate has: a source region of a first conductivity type disposed within the device region and connected to the source electrode and the gate insulating film; and a body region of a second conductivity type disposed within the device region and connected to... The source region and the gate insulating film are connected; a drift region is distributed from the element region to a position lower than each of the dummy trenches, and is connected to the body region and the gate insulating film within the element region; and a plurality of intermediate second conductivity type regions extend linearly inside the drift region along a second direction intersecting the first direction, and are spaced apart in a direction orthogonal to the second direction, with the lower end of each intermediate second conductivity type region located lower than the lower end of each of the dummy trenches; and a plurality of second conductivity type connection regions are adjacent to each of the dummy trenches, connecting each intermediate second conductivity type region to the source electrode.

[0073] (Component 2) According to the switching element of configuration 1, it further has a low-concentration intermediate second conductivity region, which has a lower concentration of second conductivity impurities compared to the plurality of intermediate second conductivity regions, and is connected to the plurality of intermediate second conductivity regions from below.

[0074] (Component 3) According to the switching element comprising 1 or 2, each of the connection regions has a higher concentration of second conductivity type impurities than each of the low-concentration intermediate second conductivity type regions, and the lower end of each of the connection regions is located at a position lower than the lower end of each of the intermediate second conductivity type regions.

[0075] (Component 4) According to the switching element described in configuration 3, the lower end of each of the connection regions is located above the lower end of the low-concentration intermediate second conductivity region.

[0076] (Component 5) According to any one of the following configurations of the switching element, a gate trench extending along the first direction is provided on the upper surface of the semiconductor substrate in the element region, the gate insulating film covers the inner surface of the gate trench, and the gate electrode is disposed in the gate trench.

[0077] (Composition 6) According to the switching element described in configuration 5, a plurality of gate trenches are provided at intervals on the upper surface of the semiconductor substrate within the element region in a direction orthogonal to the first direction.

[0078] (Component 7) According to the switching element described in configuration 6, a second conductivity type contact area is provided in the portion of the element region that is sandwiched between the plurality of gate trenches, for connecting the source electrode and the body region.

[0079] (Composition 8) According to any one of the switching elements comprising 1 to 7, each of the dummy trenches is provided with: an insulating film covering the inner surface of the dummy trench; and a dummy electrode that is insulated from the semiconductor substrate and from the gate electrode through the insulating film.

[0080] (Composition 9) According to the switching element described in configuration 8, the dummy electrode is electrically connected to the source electrode.

[0081] (Composition 10) According to any one of the switching elements comprising 1 to 9, the drift region is a first conductivity type region.

[0082] (Composition 11) According to any one of the following configurations, the drift region above each of the intermediate second conductive regions is a first conductive region, and the drift region below each of the intermediate second conductive regions has a superstructure formed by the alternating arrangement of the second conductive region and the first conductive region in the lateral direction.

[0083] (Composition 12) A method for manufacturing a switching element comprising any one of 1 to 11, comprising: a step of forming a plurality of said dummy trenches by etching the upper surface of the semiconductor substrate; and a step of forming a plurality of said connection regions by ion implanting a second type of conductivity impurity into the sidewalls of the plurality of said dummy trenches.

[0084] (Composition 13) A method for manufacturing a switching element comprising any one of 5 to 7, comprising: a step of simultaneously forming the gate trench and a plurality of the dummy trenches by etching the upper surface of the semiconductor substrate; and a step of forming a plurality of the connection regions by ion implanting a second conductivity type impurity into the sidewalls of the plurality of the dummy trenches.

[0085] According to configuration 2, since the depletion layer extends into the low-concentration intermediate second conductivity region when the switching element is turned off, the withstand voltage of the switching element can be improved.

[0086] According to configuration 3, the electric field tends to concentrate near the lower end of the connection region compared to its surroundings, thus avalanche currents are more likely to be generated near the lower end of the connection region. Therefore, by confining the path of the avalanche current to the vicinity of the connection region, the degradation of the gate insulating film can be suppressed more effectively.

[0087] According to configuration 4, leakage current can be suppressed because it is possible to suppress the depletion of the connection region.

[0088] According to configuration 5, the electric field on the gate insulating film at the lower end of the gate trench can be reduced through the intermediate second conductivity region.

[0089] According to configuration 7, the potential of the body region can be stabilized.

[0090] According to configuration 9, the potential of the dummy trench can be stabilized.

[0091] According to configuration 11, the withstand voltage of the switching element can be improved.

[0092] Based on composition 12, connecting regions can be easily formed.

[0093] According to configuration 13, gate trenches and dummy trenches can be formed efficiently.

[0094] The embodiments have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. The technical elements illustrated in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. A switching element, characterized in that, have: A semiconductor substrate having a plurality of dummy trenches spaced apart on its upper surface in a direction orthogonal to a first direction and extending along the first direction. A gate insulating film, which is in contact with the portion of the semiconductor substrate sandwiched by the plurality of dummy trenches, namely the element region; A gate electrode, which is connected to the gate insulating film and insulated from the semiconductor substrate through the gate insulating film; and The source electrode is connected to the device region. The semiconductor substrate has: The source region of the first conductivity type is disposed within the device region and is connected to the source electrode and the gate insulating film; The body region of the second conductivity type is disposed within the element region and is connected to the source region and the gate insulating film; A drift region is distributed from within the element region to a position lower than each of the dummy trenches, and is in contact with the body region and the gate insulating film within the element region; Multiple intermediate second conductive regions extend linearly within the drift region along a second direction intersecting the first direction and are spaced apart in a direction orthogonal to the second direction. The lower end of each intermediate second conductive region is located below the lower end of each dummy trench. as well as Multiple second conductivity type connection regions, each adjacent to a dummy trench, connect each intermediate second conductivity type region to the source electrode.

2. The switching element according to claim 1, characterized in that, It also has a low-concentration intermediate second conductivity region, which has a lower concentration of second conductivity impurities compared to the plurality of intermediate second conductivity regions, and is connected to the plurality of intermediate second conductivity regions from below.

3. The switching element according to claim 2, characterized in that, Each of the aforementioned connection regions has a higher concentration of second conductivity type impurities than the low-concentration intermediate second conductivity type region. The lower end of each of the connection regions is located below the lower end of each of the intermediate second conductive regions.

4. The switching element according to claim 3, characterized in that, The lower end of each of the connection regions is located above the lower end of the low-concentration intermediate second conductivity region.

5. The switching element according to any one of claims 1 to 4, characterized in that, A gate trench extending along the first direction is provided on the upper surface of the semiconductor substrate within the component region. The gate insulating film covers the inner surface of the gate trench. The gate electrode is disposed within the gate trench.

6. The switching element according to claim 5, characterized in that, On the upper surface of the semiconductor substrate within the element region, a plurality of gate trenches are provided at intervals in a direction orthogonal to the first direction.

7. The switching element according to claim 6, characterized in that, In the portion of the element region sandwiched by the plurality of gate trenches, a second conductivity contact region is provided for connecting the source electrode to the body region.

8. The switching element according to any one of claims 1 to 4, characterized in that, Each of the aforementioned dummy trenches is equipped with: An insulating film covering the inner surface of the dummy trench; and A dummy electrode that is insulated from the semiconductor substrate and from the gate electrode by the insulating film.

9. The switching element according to claim 8, characterized in that, The dummy electrode is electrically connected to the source electrode.

10. The switching element according to any one of claims 1 to 4, characterized in that, The drift region is the first conductivity type region.

11. The switching element according to any one of claims 1 to 4, characterized in that, The drift region located above the intermediate second conductivity region is the first conductivity region. The drift region located below each of the intermediate second conductive regions has a superstructure formed by the alternating arrangement of the second conductive region and the first conductive region in the lateral direction.

12. A method for manufacturing a switching element, as described in any one of claims 1 to 4, characterized in that, have: The process of forming a plurality of dummy trenches by etching the upper surface of the semiconductor substrate; and The process of forming multiple connection regions by ion implanting a second type of conductive impurity into the sidewalls of multiple dummy trenches.

13. A method for manufacturing a switching element, which is the method for manufacturing the switching element according to claim 5, characterized in that, have: The process of simultaneously forming the gate trench and a plurality of dummy trenches by etching on the upper surface of the semiconductor substrate; and The process of forming multiple connection regions by ion implanting a second type of conductive impurity into the sidewalls of multiple dummy trenches.

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