Methods for forming metal silicides

Abstract

This application discloses a method for forming metal silicides, comprising: S1: providing a substrate, wherein a polysilicon gate is formed on the surface of the substrate, and a first sidewall is formed on both sides of the polysilicon gate. The first sidewall includes a first oxide layer and a first nitride layer from the inside to the outside, and a lightly doped region is formed in the substrate; S2: removing the first nitride layer; S3: forming a second sidewall outside the first oxide layer, wherein the second sidewall includes a second oxide layer and a second nitride layer from the inside to the outside; S4: performing a source / drain ion implantation process on the surface layer of the lightly doped region to form a source region and a drain region; S5: forming a metal silicide barrier layer; S6: performing a pre-silicide formation cleaning process; S7: forming metal silicides on the surface layer of the polysilicon gate, the surface layer of the source region, and the surface layer of the drain region through metal deposition and annealing processes. This application, through the above scheme, can increase the thickness of the metal silicide at the gate and reduce the sheet resistance.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically to a method for forming metal silicides. Background Technology

[0002] Salicide (self-aligned silicide) is a key process in semiconductor manufacturing. As semiconductor process nodes enter the nanoscale, the contact resistance of the source, drain, and gate increases significantly, making it difficult to meet the requirements of high speed and low power consumption. Salicide effectively reduces contact resistance and parasitic resistance by forming low-resistance metal silicides (such as NiSi and CoSi2).

[0003] Salicide forms silicides only in silicon regions (such as source / drain and gate) through metal deposition and annealing, while insulating regions (such as SiO2) remain unreacted. This self-aligned characteristic eliminates the need for additional photolithography steps, simplifying the process flow, reducing costs, and avoiding mask alignment errors, thereby increasing device integration density. The Salicide contact resistance Rs directly determines device performance and is mainly affected by factors such as metal materials, annealing processes, and silicon surface states.

[0004] Currently, in the mid-stage process, due to the protection of the first sidewall oxide and nitride layer (the final sidewall adopts an "oxide-nitride-oxide-nitride" (ONON) multilayer structure), the actual contact area between the NiPt metal layer and the top polysilicon layer is relatively small. This structural limitation results in a lower effective thickness of the NiSi salicide formed in the gate region after annealing, ultimately leading to a higher sheet resistance (Rs) value, which adversely affects the electrical performance of the device. Summary of the Invention

[0005] This application provides a method for forming metal silicides, which can increase the thickness of the metal silicide at the gate and reduce the chip resistance.

[0006] This application provides a method for forming a metal silicide, including: S1: A substrate is provided, on the surface of which a polysilicon gate is formed, and a first sidewall is formed on both sides of the polysilicon gate. The first sidewall includes a first oxide layer and a first nitride layer from the inside to the outside. A lightly doped region is formed in the substrate, and the polysilicon gate is located between the two lightly doped regions. S2: Remove the first nitride layer; S3: A second sidewall is formed on the outside of the first oxide layer. The second sidewall includes a second oxide layer and a second nitride layer from the inside to the outside. The second oxide layer, the second nitride layer and the first oxide layer together constitute the sidewall structure. S4: Perform source and drain ion implantation on the surface of the lightly doped region to form source and drain regions; S5: Form a metal silicide barrier layer, the metal silicide barrier layer covering the substrate surface except for a predetermined region, the predetermined region including the source region surface and the drain region surface; S6: Perform a pre-silicide cleaning process, in which the tops of the first oxide layer and the second oxide layer are partially removed; S7: Perform a metal silicide deposition process, wherein the metal silicide covers the exposed polysilicon gate surface, source surface, and drain surface.

[0007] In some embodiments, in step S2, the first nitride layer is removed by a wet cleaning process.

[0008] In some embodiments, the thickness of the first oxide layer is 30 to 100 angstroms, and the thickness of the first nitride layer is 130 to 300 angstroms.

[0009] In some embodiments, step S3 includes: The second oxide layer and the second nitride layer are deposited sequentially; The second oxide layer and the second nitride layer in the horizontal direction are removed by a plasma dry etching process, and the remaining second oxide layer and the second nitride layer in the vertical direction constitute the second sidewall.

[0010] In some embodiments, in step S4, the thickness of the second oxide layer in the formed sidewall structure is 50-150 angstroms, and the thickness of the second nitride layer is 300-600 angstroms.

[0011] In some embodiments, the thickness of the metal silicide is 150 to 400 angstroms.

[0012] The technical solution of this application has at least the following advantages: 1. By removing the first nitride layer and increasing the thickness of the second oxide layer, the final sidewall structure is a composite structure of "oxide layer + nitride layer". During the subsequent cleaning process before silicide formation, the first oxide layer and the second oxide layer on the top sidewall of the polysilicon gate are partially removed due to the lack of protection from the first nitride layer, exposing the top edge of the polysilicon gate and increasing the overall exposed area of ​​the polysilicon gate. Then, metal deposition and annealing processes are performed. During the metal deposition process, the effective contact area between the deposited alloy and the polysilicon gate increases, thereby increasing the thickness of the metal silicide formed on the surface of the polysilicon gate and ultimately reducing the sheet resistance. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a method for forming metal silicides provided in an exemplary embodiment of this application; Figures 2-7 This is a schematic diagram of the device structure during the implementation of a method for forming metal silicides provided in an exemplary embodiment of this application.

[0015] Explanation of reference numerals in the attached figures: 1. Substrate; 11. Lightly doped region; 12. Source region; 13. Drain region; 2. Polysilicon gate; 3. First oxide layer; 4. First nitride layer; 5. Second oxide layer; 6. Second nitride layer; 7. Metal silicide. Detailed Implementation

[0016] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0019] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0020] This application provides a method for forming metal silicides, referring to... Figure 1 The method includes the following steps: S1: A substrate is provided, on the surface of which a polysilicon gate is formed, and a first sidewall is formed on both sides of the polysilicon gate. The first sidewall includes a first oxide layer and a first nitride layer from the inside to the outside. A lightly doped region is formed in the substrate, and the polysilicon gate is located between the two lightly doped regions.

[0021] For example, refer to Figure 2 A semiconductor substrate 1 is provided. A polysilicon gate 2 is formed on the surface of an active region 12 of the substrate 1. A gate oxide layer is formed between the polysilicon gate 2 and the substrate 1. First sidewalls are formed on both sides of the polysilicon gate 2. The first sidewalls include a first oxide layer 3 and a first nitride layer 4 from the inside to the outside. The first oxide layer 3 is made of silicon dioxide, and the first nitride layer 4 is made of silicon nitride. Lightly doped regions 11 are formed in the substrate 1, and the polysilicon gate 2 is located between two lightly doped regions 11.

[0022] Furthermore, the thickness of the first oxide layer can be 30 to 100 angstroms, and the thickness of the first nitride layer 4 can be 130 to 300 angstroms.

[0023] S2: Remove the first nitride layer.

[0024] For example, refer to Figure 3 The first nitride layer 4 can be removed by a wet cleaning process. For example, a cleaning solution containing phosphoric acid can be used to remove the first nitride layer 4.

[0025] S3: A second sidewall is formed on the outside of the first oxide layer. The second sidewall consists of a second oxide layer and a second nitride layer from the inside to the outside. The second oxide layer, the second nitride layer and the first oxide layer together constitute the sidewall structure.

[0026] For example, refer to Figure 5 A second sidewall is formed outside the first oxide layer 3. The second sidewall comprises, from the inside out, a second oxide layer 5 and a second nitride layer 6. The second oxide layer 5, the second nitride layer 6, and the first oxide layer 3 together constitute the sidewall structure. Since the first nitride layer 4 is removed in the preceding step, the thickness of the second oxide layer 5 formed in this step is increased compared to existing technologies to ensure that the overall thickness of the sidewall structure meets process requirements.

[0027] Furthermore, step S3 may include the following processing: S31: Sequentially deposit the second oxide layer and the second nitride layer.

[0028] For example, refer to Figure 4 First, a silicon dioxide layer can be deposited using plasma-enhanced chemical vapor deposition (PECVD) as the second oxide layer 5. The second oxide layer 5 covers the surface of the polysilicon gate 2, the outer side of the first oxide layer 3, and the surface of the substrate 1. Then, a silicon nitride layer can be deposited on the surface of the second oxide layer 5 using PECVD as the second nitride layer 6.

[0029] S32: The second oxide layer and the second nitride layer in the horizontal direction are removed by plasma dry etching process, and the remaining second oxide layer and the second nitride layer in the vertical direction form the second sidewall.

[0030] For example, refer to Figure 5 Anisotropic etching can be performed using plasma dry etching process to sequentially remove the second oxide layer 5 and the second nitride layer 6 in the horizontal direction. The remaining second oxide layer 5 and the second nitride layer 6 in the vertical direction cover the outside of the first oxide layer 3, forming the second sidewall.

[0031] Furthermore, in step S3 above, the thickness of the second oxide layer 5 in the formed sidewall structure is 50-150 angstroms, and the thickness of the second nitride layer 6 is 300-600 angstroms.

[0032] S4: Perform source and drain ion implantation on the surface of the lightly doped region to form the source and drain regions.

[0033] For example, refer to Figure 6 Ion implantation of source and drain regions 13 is performed on the surface of two lightly doped regions 11, thereby forming a source region 12 on the surface of one lightly doped region 11 and a drain region 13 on the surface of the other lightly doped region 11.

[0034] S5: Form a metal silicide barrier layer, which covers the substrate surface except for a predetermined area, including the source region surface and the drain region surface.

[0035] For example, a metal silicide barrier layer can be formed on the surface of substrate 1 through steps such as deposition, image formation, and etching. The metal silicide barrier layer covers areas other than a predetermined area, including the surface of source region 12 and the surface of drain region 13, and is used to define the formation area of ​​metal silicide 7 on substrate 1.

[0036] S6: Perform a cleaning process before silicide formation, during which the tops of the first oxide layer and the second oxide layer are partially removed.

[0037] For example, refer to Figure 7 The surface of the predetermined area can be ensured by a pre-cleaning process before silicide formation. At the same time, the top of the first oxide layer 3 and the second oxide layer 5 are also partially removed, so that the top edge of the polysilicon gate 2 is exposed and the overall exposed area is increased.

[0038] S7: Metal silicides are formed on the surface of the polysilicon gate, source, and drain regions through metal deposition and annealing processes.

[0039] For example, refer to Figure 7 A metal deposition process can be used to deposit a corresponding alloy, such as NiPt, on the substrate surface and the polysilicon gate surface. Following this, an annealing process is performed. During annealing, the exposed polysilicon gate 2 surface layer, source region 12 surface layer, and drain region 13 surface layer react with the alloy to form metal silicide 7. The unreacted alloy is removed in subsequent processes. In the pre-processing step, because the top edge of the polysilicon gate 2 is exposed and the overall exposed area of ​​the polysilicon gate 2 is increased, the effective contact area between the deposited alloy and the polysilicon gate 2 increases during metal deposition. This, in turn, increases the thickness of the metal silicide 7 formed on the surface of the polysilicon gate 2 during annealing, ultimately reducing the sheet resistance.

[0040] Furthermore, the material of metal silicide 7 can be NiSi, CoSi2, etc.

[0041] Furthermore, the thickness of the formed metal silicide 7 is 150~400 angstroms.

[0042] The method for forming metal silicides provided in this application removes the first nitride layer and increases the thickness of the second oxide layer, resulting in a final sidewall structure that is a composite structure of "oxide layer + nitride layer". During the subsequent cleaning process before silicide formation, the first oxide layer and the second oxide layer on the top sidewall of the polysilicon gate are partially removed due to the lack of protection from the first nitride layer, exposing the top edge of the polysilicon gate and increasing the overall exposed area of ​​the polysilicon gate. Then, metal deposition and annealing processes are performed. During the metal deposition process, the effective contact area between the deposited alloy and the polysilicon gate increases, thereby increasing the thickness of the metal silicide formed on the surface of the polysilicon gate during annealing, ultimately reducing the sheet resistance.

[0043] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for forming a metal silicide, characterized in that, include: S1: A substrate is provided, on the surface of which a polysilicon gate is formed, and a first sidewall is formed on both sides of the polysilicon gate. The first sidewall includes a first oxide layer and a first nitride layer from the inside to the outside. A lightly doped region is formed in the substrate, and the polysilicon gate is located between the two lightly doped regions. S2: Remove the first nitride layer; S3: A second sidewall is formed on the outside of the first oxide layer. The second sidewall includes a second oxide layer and a second nitride layer from the inside to the outside. The second oxide layer, the second nitride layer and the first oxide layer together constitute the sidewall structure. S4: Perform source and drain ion implantation on the surface of the lightly doped region to form source and drain regions; S5: Form a metal silicide barrier layer, the metal silicide barrier layer covering the substrate surface except for a predetermined region, the predetermined region including the source region surface and the drain region surface; S6: Perform a pre-silicide cleaning process, in which the tops of the first oxide layer and the second oxide layer are partially removed; S7: Metal silicides are formed on the polysilicon gate surface, source surface, and drain surface through metal deposition and annealing processes.

2. The method for forming metal silicides according to claim 1, characterized in that, In step S2, the first nitride layer is removed by a wet cleaning process.

3. The method for forming metal silicides according to claim 1, characterized in that, The thickness of the first oxide layer is 30-100 angstroms, and the thickness of the first nitride layer is 130-300 angstroms.

4. The method for forming metal silicides according to claim 1, characterized in that, Step S3 includes: The second oxide layer and the second nitride layer are deposited sequentially; The second oxide layer and the second nitride layer in the horizontal direction are removed by a plasma dry etching process, and the remaining second oxide layer and the second nitride layer in the vertical direction constitute the second sidewall.

5. The method for forming metal silicides according to claim 3, characterized in that, In step S4, the thickness of the second oxide layer in the formed sidewall structure is 50-150 angstroms, and the thickness of the second nitride layer is 300-600 angstroms.

6. The method for forming metal silicides according to claim 4, characterized in that, The thickness of the metal silicide is 150 to 400 angstroms.

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