A semiconductor device and its fabrication method

Abstract

This application discloses a semiconductor device and its fabrication method, relating to the field of semiconductor technology. The semiconductor device includes a substrate; a deep trench isolation structure disposed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and buffer regions disposed on opposite sides of the active region, a dummy device disposed within the buffer regions, and a multi-finger gate transistor disposed within the active region, with multiple gates of the multi-finger gate transistor arranged along a first direction. The dummy devices are disposed on both sides of the multi-finger gate transistor along the first direction, and the dummy devices are used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor. This semiconductor device and its fabrication method can eliminate the proximity effect of BCD devices, improving device reliability and stability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In modern power integrated circuit design, the BCD (Bipolar-CMOS-DMOS) process has become the mainstream manufacturing platform in automotive electronics, industrial control, power management, and intelligent power drives due to its ability to integrate high-precision analog devices, high-density digital logic units, and high-voltage, high-current power devices onto the same silicon substrate. To ensure good electrical isolation between different types of devices, especially in scenarios where high-voltage and low-voltage regions coexist, the industry commonly employs deep trench isolation (DTI) technology. DTI achieves excellent lateral electrical isolation by etching trenches several micrometers deep into the silicon substrate and filling them with a highly insulating dielectric material, significantly suppressing high-voltage crosstalk, parasitic bipolar effects, and latch-up risks.

[0003] However, as process nodes continue to shrink and device integration density increases, the physical distance between the DTI structure and adjacent active regions is constantly decreasing. The resulting proximity effect is increasingly becoming a key bottleneck restricting device performance and long-term reliability. This effect is mainly manifested in the following two aspects: First, mechanical stress-induced drift in electrical parameters. The DTI filling material (such as SiO2) and the single-crystal silicon substrate have significantly different coefficients of thermal expansion. During the cooling process after subsequent high-temperature processing, this thermal mismatch introduces a localized non-uniform mechanical stress field in the silicon lattice near the DTI sidewalls. This stress modulates the band structure of silicon, altering the effective quality of the conduction and valence bands, thereby affecting the mobility of electrons and holes. For devices highly sensitive to carrier transport, such as LDMOS or CMOS, this directly leads to uncontrollable drift in key parameters such as threshold voltage, transconductance, and on-resistance, severely affecting circuit matching and functional stability. Second, reliability degradation caused by interface trap states. During the high aspect ratio etching process of DTI, even with advanced plasma etching techniques, it is still difficult to completely avoid lattice damage to the silicon sidewalls. Furthermore, subsequent oxidation, filling, and chemical mechanical polishing steps may introduce defects such as dangling bonds and oxygen vacancies at the Si / SiO2 interface. These defects form a high density of interface trap states in the bandgap, effectively trapping charge carriers in the channel. This leads to performance degradation of LDMOS devices over time, affecting device reliability. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and a method for fabricating the same, which can eliminate the proximity effect of BCD devices and improve device reliability and stability.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a semiconductor device, including a substrate; a deep trench isolation structure disposed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and buffer regions disposed on opposite sides of the active region, a virtual device disposed in the buffer region, a multi-finger gate transistor disposed in the active region, and a plurality of gates of the multi-finger gate transistor arranged along a first direction, the virtual device being disposed on both sides of the multi-finger gate transistor along the first direction, the virtual device being used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor.

[0006] As one possible implementation, the virtual device includes a gate, a source, a drain, and a body region connection portion, wherein the gate, source, drain, and body region connection portion are interconnected to form an equipotential.

[0007] As one possible implementation method, the equipotential is 0 potential or a preset potential.

[0008] In one possible implementation, the source and drain of the virtual device are located in the substrate on both sides of the gate of the virtual device, and the body region connection of the virtual device is located in the substrate on the side of the source of the virtual device away from the drain.

[0009] In one possible implementation, a P-well region and an N-drift region are alternately arranged sequentially along a first direction within the device region. Multiple gates are respectively disposed on the interface between the P-well region and the N-drift region and are in contact with the P-well region and the N-drift region. A first N-type heavily doped region and a P-type heavily doped region are formed in the P-well region. The first N-type heavily doped region and the P-type heavily doped region serve as the source and body region connection, respectively. A second N-type heavily doped region is formed in the N-drift region and serves as the drain.

[0010] As one possible implementation, the buffer region includes at least one P-well region and at least one N-drift region. Within the buffer region, a first N-type heavily doped region, a P-type heavily doped region, a second N-type heavily doped region, and a gate located within the buffer region are connected.

[0011] As one possible implementation, shallow trench isolation structures are provided on both sides of the second N-type heavily doped region.

[0012] As one possible implementation, within the active region, the first N-type heavily doped region comprises two regions, which are located on either side of the P-type heavily doped region.

[0013] As one possible implementation, the gate includes a dielectric layer and a polysilicon layer.

[0014] A second aspect of this application provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a deep trench isolation structure on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and buffer regions disposed on opposite sides of the active region; forming a multi-finger gate transistor on the active region, and forming a dummy device in the buffer region, wherein a plurality of gates of the multi-finger gate transistor are arranged along a first direction, and the dummy device is disposed on both sides of the active region along the first direction, the dummy device being used to buffer stress between the deep trench isolation structure and the multi-finger gate transistor.

[0015] As one possible implementation, a multi-finger gate transistor is formed on an active region, and a virtual device is formed in a buffer region, including: forming a P-well region and an N-drift region alternately arranged along a first direction on a substrate; forming a gate at the interface of each adjacent P-well region and N-drift region; performing N-type ion implantation and P-type ion implantation respectively to form a first N-type heavily doped region and a P-type heavily doped region in the P-well region, and a second N-type heavily doped region in the N-drift region, wherein the first N-type heavily doped region, the P-type heavily doped region, and the second N-type heavily doped region serve as the source, the body region connection portion, and the drain, respectively; forming a passivation layer on the upper surface of the substrate, wherein connection holes are formed in the passivation layer corresponding to each source, drain, body region connection portion, and gate, respectively; forming a metal material on the passivation layer, wherein the metal material also fills the connection holes, wherein the metal material serves as the lead-out terminals of each source, body region connection portion, drain, and gate, and the metal material on the buffer region is also used to interconnect the source, drain, body region connection portion, and gate within the buffer region.

[0016] The beneficial effects of the embodiments of this application include: The semiconductor device provided in this application constructs a stress buffer barrier by setting a buffer region and virtual devices between the active region and the DTI (Distributed Tunneling Interface). This blocks the direct transmission of DTI stress to the multi-finger gate transistor, fundamentally solving the proximity effect problem caused by the reduced distance between the DTI and the active region. It avoids performance problems such as transistor threshold voltage drift, decreased carrier mobility, and deteriorated switching characteristics caused by the proximity effect, thus eliminating the proximity effect in BCD devices. Furthermore, the buffering effect of the virtual devices protects the core transistor from stress shocks, reducing the risk of long-term device failure due to stress accumulation. Simultaneously, the isolation effect of the DTI avoids electrical crosstalk between adjacent device regions, further reducing the probability of device failure and significantly improving the long-term reliability of the device. The multi-finger gate transistor operates in a stress-free environment, resulting in significantly improved consistency and stability of its electrical parameters. This ensures stable output performance under different operating conditions, avoiding performance fluctuations caused by the proximity effect and improving device stability. Therefore, the semiconductor device in this application can eliminate the proximity effect of BCD devices and improve device reliability and stability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of a semiconductor device provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 3 A semiconductor device and a prior art on-resistance curve are provided for embodiments of this application; Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0019] Icons: 100 - Semiconductor device; 110 - Substrate; 120 - Deep trench isolation structure; 121 - Active region; 122 - Buffer region; 131 - Multi-finger gate transistor; 132 - Virtual device; 141 - Gate; 142 - Source; 143 - Drain; 144 - Body region connection; 151 - P-well region; 152 - N-drift region; 161 - Shallow trench isolation structure. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0021] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0023] Please refer to the reference. Figure 1 and Figure 2 This application provides a semiconductor device 100, which may include a substrate 110; a deep trench isolation structure 120 disposed on the substrate 110, the deep trench isolation structure 120 enclosing a device region, the device region including an active region 121 and buffer regions 122 disposed on opposite sides of the active region 121, a virtual device 132 disposed in the buffer region 122, a multi-finger gate transistor 131 disposed in the active region 121, and a plurality of gates 141 of the multi-finger gate transistor 131 arranged along a first direction, the virtual device 132 disposed on both sides of the multi-finger gate transistor 131 along the first direction, the virtual device 132 being used to buffer the stress between the deep trench isolation structure 120 and the multi-finger gate transistor 131.

[0024] The semiconductor device 100 in this embodiment is a part of a BCD device. Specifically, the BCD device may include multiple high-voltage devices and low-voltage devices, and the deep trench isolation structure 120 is used to isolate the high-voltage devices and low-voltage devices.

[0025] In this embodiment, the substrate 110 is the basic support layer of the semiconductor device 100, providing support for all subsequent structures; the deep trench isolation structure 120 is disposed on the substrate 110, and its core function is to achieve physical isolation between different device regions and avoid electrical interference between adjacent device regions.

[0026] Specifically, the deep trench isolation structure 120 forms an independent device region by creating trenches on the substrate 110 and filling them with isolation material. This physically isolates the device region from other device regions on the substrate 110, avoiding electrical crosstalk between devices in different regions and providing a basic environment for the stable operation of the active region 121. The isolation material is typically silicon dioxide.

[0027] In this embodiment, the deep trench isolation structure 120 encloses and forms a device region, which is divided into an active region 121 and a buffer region 122. The active region 121 is the core functional implementation area, containing multi-finger gate transistors 131. The multiple gates 141 of the multi-finger gate transistors 131 are arranged along a first direction, and are the core components for the semiconductor device 100 to achieve specific electrical performance. The buffer region 122 is located on opposite sides of the active region 121, between the active region 121 and the DTI (Damping Transition Induction), i.e., the buffer region 122 is equivalent to the transition region between the active region 121 and the DTI, and contains virtual devices 132.

[0028] By adding a virtual device 132 as a buffer layer between the active region 121 and the DTI, direct adjacency between the active region 121 and the DTI is avoided. Simultaneously, the virtual device 132 provides stress buffering, structurally blocking the conduction path of the proximity effect. The virtual device 132 is disposed on both sides of the multi-finger gate transistor 131 along a first direction, buffering the stress between the DTI and the multi-finger gate transistor 131, and is the core component for eliminating the proximity effect. It is equivalent to constructing a stress absorption and buffer barrier between the DTI and the multi-finger gate transistor 131. When the stress generated by the DTI is conducted to the active region 121, it first acts on the virtual device 132. The structure of the virtual device 132 can disperse and absorb some of the stress, reducing the intensity of stress conduction. Furthermore, the interface between the virtual device 132 and the DTI and the active region 121 can adjust the stress distribution, preventing stress concentration in the multi-finger gate transistor 131 region, thereby blocking or significantly weakening the conduction path of the proximity effect. Under the buffer protection of the virtual device 132, the multi-finger gate transistor 131 in the active region 121 can get rid of the interference of DTI stress, and its multiple gates 141 arranged along the first direction can normally realize core electrical functions such as charge control and current amplification, ensuring the normal operation performance of the device.

[0029] In this embodiment, the virtual device 132 may have the same or similar gate-source-drain structure as the multi-finger gate transistor 131, but does not participate in the actual electrical function.

[0030] Specifically, the substrate 110 in this embodiment can be a silicon-on-insulator (SOI) substrate, which is particularly suitable for fabricating components such as switches, low-noise amplifiers, or signal generators required for millimeter-wave bands in 5G communication network systems.

[0031] In this embodiment, the substrate 110 may include a silicon oxide layer and a silicon layer located on the silicon oxide layer. The thickness of the silicon oxide layer may be approximately 200–400 nm, and the thickness of the silicon layer may be approximately 50–200 nm.

[0032] In the above embodiments, the silicon oxide layer serves as a buried oxide isolation layer of the SOI substrate 110. It reduces the capacitance between the field-effect transistor (FET) and the substrate 110 to improve its operating speed and prevents leakage to reduce power consumption. The silicon layer is preferably a high-resistivity monocrystalline silicon layer, which serves as the active layer of the device and can form various doped regions therein. Below the silicon oxide layer is a relatively thick silicon substrate. In some embodiments, a polycrystalline silicon trapping layer may be disposed between the silicon oxide layer and the silicon substrate to trap electrons dissipated into the device during high-frequency applications, thereby improving the performance of the RF device. In some other embodiments, the substrate 110 may also be a gallium nitride-coated silicon substrate or a gallium nitride-coated silicon carbide substrate.

[0033] In summary, by setting a buffer region 122 and a virtual device 132 between the active region 121 and the DTI, a stress buffer barrier is constructed, blocking the direct transmission of DTI stress to the multi-finger gate transistor 131 (the core transistor). This fundamentally solves the proximity effect problem caused by the reduced distance between the DTI and the active region 121, avoiding performance problems such as transistor threshold voltage drift, decreased carrier mobility, and deteriorated switching characteristics caused by the proximity effect, thus eliminating the proximity effect of the BCD device. Furthermore, the buffering effect of the virtual device 132 protects the core transistor from stress impact, reducing the risk of long-term device failure due to stress accumulation. Simultaneously, the isolation effect of the DTI avoids electrical crosstalk between adjacent device regions, further reducing the probability of device failure and significantly improving the long-term reliability of the device. The multi-finger gate transistor 131 operates in a stress-free environment, with significantly improved consistency and stability of its electrical parameters, ensuring stable output performance under different operating conditions, avoiding performance fluctuations caused by the proximity effect, and improving the device's operational stability. Therefore, the semiconductor device 100 of this application embodiment can eliminate the proximity effect of BCD devices and improve device reliability and stability.

[0034] To demonstrate the beneficial effects of the embodiments of this application, the applicant measured the change in on-resistance of a semiconductor device without the added virtual device 132 and a semiconductor device with the added virtual device under stress-time conditions. The results are as follows: Figure 3 As shown, by Figure 3 It can be seen that the change in on-resistance under stress time is reduced, the degree of device degradation is reduced, and the reliability and stability of semiconductor devices are improved.

[0035] Optional, please continue to refer to Figure 2 As shown, the virtual device 132 may include a gate 141, a source 142, a drain 143, and a body region connection portion 144. The gate 141, the source 142, the drain 143, and the body region connection portion 144 are interconnected to form an equipotential.

[0036] As described above, the virtual device 132 is used to buffer the stress between the deep trench isolation structure 120 and the multi-finger gate transistor 131, and does not participate in the actual electrical function. In this embodiment, the gate 141, source 142, drain 143, and body region connection portion 144 of the virtual device 132 are interconnected to form an equipotential, so that all PN junctions in the virtual device 132 are in a zero-bias state, suppressing parasitic conduction, clamping the body region potential, and avoiding charge accumulation. In addition, after all terminals are shorted, the virtual device 132 becomes an electrically continuous metal-semiconductor composite shield, which can effectively suppress the electric field abrupt change at the DTI edge and shield noise coupling from the substrate 110 or the isolation medium.

[0037] Therefore, the virtual device 132 not only prevents the virtual device 132 itself from becoming a reliability hazard, but also transforms it into a stable stress buffer and electromagnetic shielding unit, thereby more effectively protecting the adjacent multi-finger gate transistor 131 from the negative effects of the DTI proximity effect.

[0038] As an feasible approach, the equipotential is 0 potential or a preset potential.

[0039] In this embodiment, the equipotential is 0, meaning all terminals (gate, source, drain, and body region) of the virtual device 132 are connected to the chip's global reference ground (GND), keeping its potential constant at 0 V. This completely eliminates any possible potential fluctuations and ensures that the virtual device 132 is in a completely passive state. In BCD technology, ground is typically a low-impedance, large-area distributed network that effectively absorbs stray charges. The equipotential is a preset potential, i.e., connected to a non-zero but fixed bias voltage, which is predetermined by the circuit design. In some high-voltage DMOS structures, if the DTI region is in a high-potential drift region, biasing the virtual device 132 to a similar potential (such as 1 / 2 VDD) can minimize the electric field gradient. In RF or high-precision analog circuits, to avoid ground noise coupling, the virtual device 132 can be biased to a quiet bias rail (such as a bandgap reference output). In SOI or FD-SOI processes, a specific back gate bias voltage needs to be applied to the body region to control the threshold voltage. In this case, the virtual device 132 should also follow this bias, allowing the virtual device 132 to adapt to more scenarios.

[0040] Those skilled in the art can connect each terminal of the virtual device 132 to the required potential according to the actual situation.

[0041] As one possible approach, the source and drain of the virtual device are located in the substrate on both sides of the gate of the virtual device, and the body connection portion of the virtual device is located in the substrate on the side of the source of the virtual device away from the drain.

[0042] Specifically, the virtual device is configured to include a gate, source, drain, and body region connection, meaning that the virtual device has the same structure as the normal device, which facilitates the subsequent fabrication of semiconductor devices.

[0043] Optionally, a P-well region 151 and an N-drift region 152 are alternately arranged in sequence along the first direction within the device region, and a plurality of gates 141 are respectively disposed on the interface between the P-well region 151 and the N-drift region 152 and in contact with the P-well region 151 and the N-drift region 152.

[0044] In this embodiment, a first N-type heavily doped region and a P-type heavily doped region are formed in the P-well region 151. The first N-type heavily doped region and the P-type heavily doped region serve as the source 142 and the body region connection 144, respectively. A second N-type heavily doped region is formed in the N-drift region 152. The second N-type heavily doped region serves as the drain 143.

[0045] In the above embodiments, P-well regions 151 and N-drift regions 152 are alternately arranged along the first direction within the device region, with each P-well region 151 and N-drift region 152 constituting a cell; multiple gates 141 are respectively located at the interface between the P-well and N-drift regions 152 and are in contact with both; the upper surface of the P-well region 151 is ion-implanted to form a first N-type heavily doped region as the source 142; the upper surface of the P-well region 151 is ion-implanted to form a P-type heavily doped region as the body region connection portion 144; the upper surface of the N-drift region 152 is ion-implanted to form a second P-type heavily doped region as the drain 143, forming a multi-finger gate transistor 131, with each finger consisting of a P-well region 151, an N-drift region 152, and a gate 141. Multiple fingers are connected in parallel, i.e., multiple cells are connected in parallel, which effectively increases the channel width and reduces the on-resistance; the current path is dispersed, the heat distribution is more uniform, and local hot spots are avoided; the gates 141 are arranged along the first direction, which facilitates metal interconnect wiring and improves layout efficiency.

[0046] As one possible implementation, the buffer region 122 may include at least one P-well region 151 and at least one N-drift region 152. Within the buffer region 122, a first N-type heavily doped region, a P-type heavily doped region, a second N-type heavily doped region, and a gate 141 located within the buffer region 122 are connected.

[0047] In the above embodiments, the buffer region 122 completely replicates the structure of the multi-finger gate transistor 131 cell at the layout and process levels, but its electrical function is turned off. That is, the first N-type heavily doped region, the P-type heavily doped region, the second N-type heavily doped region and the gate 141 located in the buffer region 122 are connected to form a closed cell with equal potential and no internal potential difference.

[0048] The lattice stress field generated at the edge of the DTI has directionality and attenuation characteristics. The buffer region 122 adopts the same doping type, well depth, dielectric coverage and metal density as the active region 121, so its mechanical response characteristics (such as Young's modulus and thermal expansion coefficient) are highly matched with the real device. The stress will not be reflected or focused due to the material abrupt change when passing through the buffer, but will be smoothly attenuated, avoiding the formation of new stress concentration points at the boundary of the active region 121.

[0049] Furthermore, since the buffer region 122 completely replicates the structure of the multi-finger gate transistor 131 cell at the layout and process levels, the process of fabricating the semiconductor device 100 does not require adding a mask layer or special process steps, and the process of the multi-finger gate transistor 131 can be completely reused; and the layout density and pattern complexity are consistent with the active region 121, which is beneficial for photolithography focus control, etching uniformity, and CMP planarization, thereby simplifying the fabrication of the semiconductor device 100.

[0050] Optionally, shallow trench isolation structures 161 (STI) are provided on both sides of the second N-type heavily doped region.

[0051] The second heavily doped N-type region is located on the surface of the N-drift region 152, serving as the contact region for the drain 143. It is typically a high-concentration N-type implant (such as As or P) to form a low-resistance ohmic contact. Shallow trench isolation structures 161 are respectively formed on both sides of the second heavily doped N-type region along the first direction. The shallow trench isolation structures 161 are shallow trenches filled with SiO2, used to achieve localized isolation of the active region 121. The depth of the shallow trench isolation structures 161 is between 0.2 and 0.5 μm.

[0052] SiO2 in STI has high dielectric strength and low dielectric constant, which can effectively stretch electric field lines, making the electric field distribution more uniform. The STI boundary forms a physical step, forcing the depletion region to extend into the N drift region 152, avoiding the electric field from concentrating at the edge of the drain contact; achieving a local RESURF effect and improving the surface breakdown voltage.

[0053] STI is used for fine isolation within local active regions 121, such as the separation between source / drain fingers and the definition of drain contact boundaries. DTI is used for isolation of large-scale device regions, such as between high-voltage regions and low-voltage logic regions, with a depth of up to several micrometers.

[0054] As one possible approach, within the active region 121, the first N-type heavily doped region may include two regions, located on either side of the P-type heavily doped region.

[0055] In the above embodiment, two N-type heavily doped regions are symmetrically distributed on the left and right sides of the P-type heavily doped region, forming an “N + –P + –N+ The layout employs a sandwich-like configuration. The heavily P-type doped region serves as the body contact. By placing the body contact between the two N-type heavily doped source regions 142, the lateral distance from the source 142 to the body region is shortened, significantly reducing the lateral resistance of the P-well. This ensures a highly uniform P-well potential across the entire channel width, preventing localized potential rise. Furthermore, it greatly weakens the base drive capability of the parasitic BJT, effectively suppressing its turn-on. Additionally, the N... + –P + –N + The layout allows the body contacts to be close to both sides of the channel, enabling holes to be quickly collected by the heavily doped P-type region and discharged to ground, achieving efficient hole extraction and stable body potential.

[0056] Optionally, gate 141 may include a dielectric layer and a polysilicon layer.

[0057] In the above embodiment, the dielectric layer, located between the gate 141 and the silicon substrate 110, is an insulating layer made of silicon dioxide. A polysilicon layer, serving as the gate electrode material, covers the dielectric layer and is used to apply the control voltage. In high-voltage BCDs or power devices, polysilicon gates remain the mainstream choice because they can withstand the high-temperature processes required for high-voltage devices; they have good compatibility with thick gate oxide / field oxide processes; and their work function can be adjusted through doping, among other advantages.

[0058] This application also provides a method for fabricating a semiconductor device 100, used to fabricate the aforementioned semiconductor device 100, such as... Figure 4 As shown, it may include: S100: Provides substrate 110.

[0059] S200: A deep trench isolation structure 120 is formed on the substrate 110. The deep trench isolation structure 120 encloses and forms a device region, which includes an active region 121 and buffer regions 122 disposed on opposite sides of the active region 121.

[0060] The substrate 110 may be silicon-on-insulator.

[0061] Specifically, the formation process of the deep trench isolation structure 120 is as follows: photolithography defines the DTI pattern, specifically, the DTI pattern surrounds the target device area; then, high aspect ratio dry etching (such as RIE) is used to etch trenches with a depth of 2–5 μm; then, the inner wall is thermally oxidized to form a pad oxide layer; then, SiO2 is deposited by CVD to fill the trench; finally, CMP is used to planarize the surface to complete the fabrication of the deep trench isolation structure 120.

[0062] S300: A multi-finger gate transistor 131 is formed on the active region 121, and a virtual device 132 is formed in the buffer region 122. The multiple gates 141 of the multi-finger gate transistor 131 are arranged along a first direction. The virtual device 132 is disposed on both sides of the active region 121 along the first direction. The virtual device 132 is used to buffer the stress between the deep trench isolation structure 120 and the multi-finger gate transistor 131.

[0063] As one possible implementation, forming a multi-finger gate transistor 131 on the active region 121 and forming a dummy device 132 in the buffer region 122 may include: S210: A P-well region 151 and an N-drift region 152 are alternately arranged along a first direction on a substrate 110.

[0064] In this embodiment, the P-well implantation window can be defined by photolithography, and the P-well can be formed by high-energy boron (B) or BF2 implantation. The N-drift region 152 can be formed by low-dose phosphorus / arsenic implantation. The P-well region 151 and the N-drift region 152 are arranged alternately along the first direction to form multiple cells.

[0065] In this embodiment, the P-well region 151 and the N-drift region 152 simultaneously cover the active region 121 and the buffer regions on both sides 122 to ensure structural consistency.

[0066] S220: Gate 141 is formed on the interface of each adjacent P-well region 151 and N-drift region 152.

[0067] In this embodiment, a gate dielectric layer can be deposited by CVD, and then polysilicon can be deposited on the dielectric layer; polysilicon gates arranged along the first direction can be formed by photolithography and dry etching, and each gate 141 is connected to a P-well / N-drift junction.

[0068] S230: Perform N-type ion implantation and P-type ion implantation respectively to form a first N-type heavily doped region and a P-type heavily doped region in the P-well region 151, and a second N-type heavily doped region in the N-drift region 152. The first N-type heavily doped region, the P-type heavily doped region and the second N-type heavily doped region serve as the source, the body region connection and the drain respectively.

[0069] In this embodiment, within the P-well region 151, a high-dose As / P implantation forms a first heavily doped N-type region as the source 142; a high-dose B implantation forms a heavily doped P-type region as the body contact; and within the N-drift region 152, a high-dose As implantation forms a second heavily doped N-type region as the drain 143.

[0070] It should be noted that the injection is completed simultaneously in the active region 121 and the buffer, and the active region 121 and the buffer have the same structure.

[0071] S240: A passivation layer is formed on the upper surface of the substrate 110, and connection holes are formed in the passivation layer to each source, drain, body region and gate respectively.

[0072] In this embodiment, the passivation layer can be a Si3N4 / SiO2 stack, which serves to protect the chip surface, suppress sodium ion contamination, and provide mechanical support, among other functions.

[0073] S250: A metal material is formed on the passivation layer, and the metal material also fills the connection holes. The metal material serves as the lead-out terminals of each source 142, body region connection portion 144, drain 143 and gate 141, and the metal material on the buffer region 122 is also used to connect the source, drain, body region connection portion and gate 141 in the buffer region to each other.

[0074] In this embodiment, metal interconnects are formed by sputtering a Ti / TiN adhesion layer, filling with W or Al / Cu, and etching. Within the active region 121, the metal interconnects are connected to the first heavily doped N-type region, the heavily doped P-type region, and the second heavily doped N-type region through the metal material in the connection holes, respectively, serving as the source 142, the body region connection portion 144, and the drain 143. Simultaneously, within the buffer zone, the metal interconnects connect the source, drain, body region connection portion, and gate 141 within the buffer zone.

[0075] The semiconductor device 100 of this application embodiment is fabricated without increasing process complexity, and includes a virtual device 132, thereby achieving systematic suppression of the DTI proximity effect.

[0076] It should be noted that the specific structure and beneficial effects of the semiconductor device 100 prepared by the method for preparing the semiconductor device 100 have been described in detail in the foregoing embodiments, and will not be repeated here.

[0077] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0078] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A semiconductor device, characterized in that, include: Substrate; A deep trench isolation structure is disposed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and buffer regions disposed on opposite sides of the active region, a virtual device is disposed in the buffer region, a multi-finger gate transistor is disposed in the active region, and a plurality of gates of the multi-finger gate transistor are arranged along a first direction, the virtual device is disposed on both sides of the multi-finger gate transistor along the first direction, the virtual device is used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor.

2. The semiconductor device according to claim 1, characterized in that, The virtual device includes a gate, a source, a drain, and a body region connection portion, wherein the gate, the source, the drain, and the body region connection portion are interconnected to form an equipotential.

3. The semiconductor device according to claim 2, characterized in that, The equipotential is 0 potential or a preset potential.

4. The semiconductor device according to claim 2, characterized in that, The source and drain of the virtual device are located in the substrate on both sides of the gate of the virtual device, and the body connection portion of the virtual device is located in the substrate on the side of the source of the virtual device away from the drain.

5. The semiconductor device according to claim 1, characterized in that, P-well regions and N-drift regions are alternately arranged along a first direction within the device region. A plurality of gates are respectively disposed on the interface between the P-well regions and the N-drift regions and are in contact with the P-well regions and the N-drift regions. A first N-type heavily doped region and a P-type heavily doped region are formed in the P-well region. The first N-type heavily doped region and the P-type heavily doped region serve as the source and body region connection portions, respectively. A second N-type heavily doped region is formed in the N-drift region and serves as the drain.

6. The semiconductor device according to claim 5, characterized in that, The buffer region includes at least one P-well region and at least one N-drift region, wherein the first N-type heavily doped region, the P-type heavily doped region, the second N-type heavily doped region, and the gate located within the buffer region are connected.

7. The semiconductor device according to claim 5, characterized in that, Shallow trench isolation structures are provided on both sides of the second N-type heavily doped region.

8. The semiconductor device according to claim 5, characterized in that, Within the active region, the first N-type heavily doped region within the P-well region comprises two regions, located on either side of the P-type heavily doped region.

9. A method for fabricating a semiconductor device, characterized in that, For preparing the semiconductor device according to any one of claims 1-8, comprising: Provide substrate; A deep trench isolation structure is formed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and buffer regions disposed on opposite sides of the active region; A multi-finger gate transistor is formed on the active region, and a virtual device is formed in the buffer region. The multiple gates of the multi-finger gate transistor are arranged along a first direction, and the virtual device is disposed on both sides of the active region along the first direction. The virtual device is used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The process of forming a multi-finger gate transistor on the active region and forming a virtual device in the buffer region includes: P-well regions and N-drift regions are formed alternately along a first direction on the substrate; A gate is formed at the interface between each adjacent P-well region and the N-drift region; N-type ion implantation and P-type ion implantation are performed respectively to form a first N-type heavily doped region and a P-type heavily doped region in the P-well region, and a second N-type heavily doped region in the N-drift region. The first N-type heavily doped region, the P-type heavily doped region and the second N-type heavily doped region serve as the source, the body region connection and the drain, respectively. A passivation layer is formed on the upper surface of the substrate, and connection holes corresponding to each source, drain, body region connection portion and gate are formed in the passivation layer; A metal material is formed on the passivation layer, and the metal material also fills the connection hole. The metal material serves as the lead-out terminals of each source, body region connection, drain and gate, and the metal material on the buffer region is also used to connect the source, drain, body region connection and gate in the buffer region to each other.

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