A semiconductor device and its fabrication method

Abstract

This application discloses a semiconductor device and its fabrication method, relating to the field of semiconductor technology. The semiconductor device includes a substrate and a deep trench isolation structure disposed on the substrate. The deep trench isolation structure encloses a device region, which includes an active region and terminal regions disposed on opposite sides of the active region along a second direction. A multi-finger gate transistor is disposed within the active region, and the gates of the multi-finger gate transistor are arranged along a first direction. A stress buffer structure is formed within the terminal regions to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor. The first direction is perpendicular to the second direction. This semiconductor device and its fabrication method can eliminate the proximity effect of BCD devices, improving device reliability and stability.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In modern power integrated circuit design, the BCD (Bipolar-CMOS-DMOS) process has become the mainstream manufacturing platform in automotive electronics, industrial control, power management, and intelligent power drives due to its ability to integrate high-precision analog devices, high-density digital logic units, and high-voltage, high-current power devices onto the same silicon substrate. To ensure good electrical isolation between different types of devices, especially in scenarios where high-voltage and low-voltage regions coexist, the industry commonly employs deep trench isolation (DTI) technology. DTI achieves excellent lateral electrical isolation by etching trenches several micrometers deep into the silicon substrate and filling them with a highly insulating dielectric material, significantly suppressing high-voltage crosstalk, parasitic bipolar effects, and latch-up risks.

[0003] However, as process nodes continue to shrink and device integration density increases, the physical distance between the DTI structure and adjacent active regions is constantly decreasing. The resulting proximity effect is increasingly becoming a key bottleneck restricting device performance and long-term reliability. This effect is mainly manifested in the following two aspects: First, mechanical stress-induced drift in electrical parameters. The DTI filling material (such as SiO2) and the single-crystal silicon substrate have significantly different coefficients of thermal expansion. During the cooling process after subsequent high-temperature processing, this thermal mismatch introduces a localized non-uniform mechanical stress field in the silicon lattice near the DTI sidewalls. This stress modulates the band structure of silicon, altering the effective quality of the conduction and valence bands, thereby affecting the mobility of electrons and holes. For devices highly sensitive to carrier transport, such as LDMOS or CMOS, this directly leads to uncontrollable drift in key parameters such as threshold voltage, transconductance, and on-resistance, severely affecting circuit matching and functional stability. Second, reliability degradation caused by interface trap states. During the high aspect ratio etching process of DTI, even with advanced plasma etching techniques, it is still difficult to completely avoid lattice damage to the silicon sidewalls. Furthermore, subsequent oxidation, filling, and chemical mechanical polishing steps may introduce defects such as dangling bonds and oxygen vacancies at the Si / SiO2 interface. These defects form a high density of interface trap states in the bandgap, effectively trapping charge carriers in the channel. This leads to performance degradation of LDMOS devices over time, affecting device reliability. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and a method for fabricating the same, which can eliminate the proximity effect of BCD devices and improve device reliability and stability.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a semiconductor device, including a substrate; a deep trench isolation structure disposed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and terminal regions disposed on opposite sides of the active region along a second direction, a multi-finger gate transistor disposed in the active region, and a plurality of gates of the multi-finger gate transistor being arranged along a first direction, a stress buffer structure being formed in the terminal region, the stress buffer structure being used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor, the first direction being perpendicular to the second direction.

[0006] In one possible implementation, a P-well region and an N-drift region are alternately arranged sequentially along a first direction in the active region, and the P-well region and the N-drift region extend into the terminal region along a second direction; multiple gates are respectively disposed on the interface between the P-well region and the N-drift region and are in contact with the P-well region and the N-drift region; a first connection region and a second connection region are formed by ion implantation on the upper surface of the P-well region; a third connection region is formed in the N-drift region; wherein the first connection region and the second connection region in the terminal region are both first P-type heavily doped regions; the third connection region in the terminal region is a first N-type heavily doped region; and the gate in the terminal region is a pseudo-gate structure.

[0007] As one possible implementation, the gate in the terminal region includes a first gate region and a second gate region, the second gate region being close to the first P-type heavily doped region and the second gate region being the second P-type heavily doped region; the first P-type heavily doped region and the second P-type heavily doped region are connected to form a stress buffer structure in the terminal region.

[0008] As one possible approach, the first gate region can be a second N-type heavily doped region or an undoped region.

[0009] As one possible implementation, within the active region, there are two second connection regions, which are respectively located on both sides of the first connection region.

[0010] In one possible implementation, within the active region, the first connection region is a first P-type heavily doped region serving as a body region connection portion, the second connection region is a third N-type heavily doped region serving as a source, the third connection region is a first N-type heavily doped region serving as a drain, and the gate is a second N-type heavily doped region.

[0011] A second aspect of this application provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a deep trench isolation structure on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and terminal regions disposed on opposite sides of the active region along a second direction; forming a multi-finger gate transistor on the active region, forming a stress buffer structure in the terminal regions, wherein a plurality of gates of the multi-finger gate transistor are arranged along a first direction, the first direction being perpendicular to the second direction.

[0012] As one possible implementation, a multi-finger gate transistor is formed on an active region, and a stress buffer structure is formed in a terminal region. This includes: forming alternating P-well regions and N-drift regions on a substrate, the P-well regions and N-drift regions being located within the active region and extending to the terminal region; forming multiple gate materials at the interface between two adjacent P-well regions and N-drift regions; performing ion implantation on the P-well regions, N-drift regions, and gate materials to form a first connection region and a second connection region on the upper surface of the P-well region, a third connection region on the upper surface of the N-drift region, and a gate located at the interface between the P-type region and the N-drift region; wherein the first connection region and the second connection region in the terminal region are both first heavily doped P-type regions, the third connection region in the terminal region is a first heavily doped N-type region, and the gate in the terminal region is a pseudo-gate structure, comprising a first gate region and a second gate region, the second gate region being close to the first heavily doped P-type region and being a second heavily doped P-type region, and the first and second heavily doped P-type regions being connected to form a stress buffer structure in the terminal region.

[0013] As one possible implementation, ion implantation is performed on the P-well region, the N-drift region, and the gate material, including: performing P-type ion implantation and N-type ion implantation on the P-well region, the N-drift region, and the gate material, respectively; the P-type ion implantation region includes the P-well region in the active region away from the gate, the P-well region in the terminal region, and the gate material on the P-well region in the terminal region; the N-type ion implantation region includes the N-type drift region, the P-well region in the active region close to the gate, and the gate material in the active region.

[0014] As one possible implementation, the method for fabricating a semiconductor device further includes: forming a passivation layer covering a substrate and a gate surface, and etching the passivation layer to form a connection hole; forming a metal material on the surface of the passivation layer, the metal material also filling the connection hole, and the metal material leading out the first connection region, the second connection region, the third connection region and the gate in the active region to serve as the drain, the body connection portion, the source and the gate respectively, forming a multi-finger gate transistor.

[0015] The beneficial effects of the embodiments of this application include: The semiconductor device provided in this application embodiment, by adding a stress buffer structure between the active region and the DTI, avoids direct adjacency between the active region and the DTI. Simultaneously, the stress buffer structure achieves stress buffering, structurally blocking the conduction path of the proximity effect. This fundamentally solves the proximity effect problem caused by the reduced distance between the DTI and the active region, avoiding performance problems such as transistor threshold voltage drift, decreased carrier mobility, and deteriorated switching characteristics caused by the proximity effect, thus eliminating the proximity effect in BCD devices. Furthermore, the buffering effect of the stress buffer structure protects the core transistor from stress shocks, reducing the risk of long-term device failure due to stress accumulation. At the same time, the isolation effect of the DTI avoids electrical crosstalk between adjacent device regions, further reducing the probability of device failure and significantly improving the long-term reliability of the device. The multi-finger gate transistor operates in a stress-free environment, significantly improving the consistency and stability of its electrical parameters, ensuring stable output performance under different operating conditions, avoiding performance fluctuations caused by the proximity effect, and improving device operational stability. Therefore, the semiconductor device in this application embodiment can eliminate the proximity effect of BCD devices and improve device reliability and stability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the schematic diagrams of a semiconductor device provided in the embodiments of this application; Figure 2 This is a schematic diagram of a region of a semiconductor device provided in an embodiment of this application; Figure 3 for Figure 1 Schematic diagram of the cross section along AA; Figure 4 for Figure 1 Schematic diagram of the cross section along BB; Figure 5 This is a second schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 6 for Figure 5 Schematic diagram of the cross section along AA; Figure 7 for Figure 5 Schematic diagram of the cross section along BB; Figure 8A semiconductor device and a prior art on-resistance curve are provided for embodiments of this application; Figure 9 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0018] Icons: 100 - Semiconductor device; 110 - Substrate; 120 - Deep trench isolation structure; 131 - Active region; 132 - Termination region; 141 - P-well region; 142 - N-drift region; 143 - Gate; 144 - Third connection region; 146 - First connection region; 147 - Second connection region; 151 - First gate region; 152 - Second gate region; 161 - First heavily P-type doped region. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0020] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Please refer to the reference. Figures 1 to 7This application provides a semiconductor device 100, which may include a substrate 110; a deep trench isolation structure 120 disposed on the substrate 110, the deep trench isolation structure 120 enclosing a device region, the device region including an active region 131 and terminal regions 132 disposed on opposite sides of the active region 131 along a second direction, a multi-finger gate transistor disposed in the active region 131, and a plurality of gates 143 of the multi-finger gate transistor arranged along a first direction, a stress buffer structure formed in the terminal region 132, the stress buffer structure being used to buffer the stress between the deep trench isolation structure 120 and the multi-finger gate transistor, the first direction being perpendicular to the second direction.

[0023] The semiconductor device 100 in this embodiment is a part of a BCD device. Specifically, the BCD device may include multiple high-voltage devices and low-voltage devices, and the deep trench isolation structure 120 is used to isolate the high-voltage devices and low-voltage devices.

[0024] Specifically, the substrate 110 is the basic support layer of the semiconductor device 100, providing support for all subsequent structures; the deep trench isolation structure 120 is disposed on the substrate 110, and its core function is to achieve physical isolation between different device regions and avoid electrical interference between adjacent device regions.

[0025] In this embodiment, the deep trench isolation structure 120 forms an independent device region by creating trenches on the substrate 110 and filling them with isolation material. This physically isolates the device region from other device regions on the substrate 110, avoiding electrical crosstalk between devices in different regions and providing a basic environment for the stable operation of the active region 131. The isolation material is typically silicon dioxide.

[0026] In this embodiment, as Figure 2 As shown, the deep trench isolation structure 120 encloses and forms a device region, which is divided into an active region 131 and a terminal region 132.

[0027] The active region 131 is the core function implementation region, which contains a multi-finger gate transistor. The multiple gates 143 of the multi-finger gate transistor are arranged along a first direction (e.g., Figure 1 and Figure 5 The arrangement (as shown in the C direction) is the core component for the semiconductor device 100 to achieve specific electrical performance.

[0028] In this embodiment, the terminal region 132 is disposed on both sides of the active region 131, located between the active region 131 and the DTI. That is, the terminal region 132 corresponds to the transition region between the active region 131 and the DTI, and a stress buffer structure is disposed internally. Specifically, the terminal region 132 is located along the second direction (e.g., Figure 1 and Figure 5The D direction shown is disposed on opposite sides of the active region 131. The second direction is perpendicular to the surface of the substrate 110 and parallel to the first direction, and the second direction is perpendicular to the first direction.

[0029] By adding a stress buffer structure between the active region 131 and the DTI, direct adjacency between them is avoided. Simultaneously, the stress buffer structure provides stress buffering, structurally blocking the conduction path of the proximity effect. The stress buffer structure is positioned along the second direction on both sides of the multi-finger gate transistor, buffering the stress between the DTI and the multi-finger gate transistor. It is the core component for eliminating the proximity effect. Essentially, a stress absorption and buffer barrier is constructed between the DTI and the multi-finger gate transistor. When the stress generated by the DTI is conducted to the active region 131, it first acts on the stress buffer structure. The stress buffer structure can disperse and absorb some of the stress, reducing the intensity of stress conduction. Furthermore, the interface between the stress buffer structure, the DTI, and the active region 131 can adjust the stress distribution, preventing stress concentration in the multi-finger gate transistor region, thereby blocking or significantly weakening the conduction path of the proximity effect. Under the buffer protection of the stress buffer structure, the multi-finger gate transistor in the active region 131 can get rid of the interference of DTI stress, and its multiple gates 143 arranged along the first direction can normally realize core electrical functions such as charge control and current amplification, ensuring the normal operation performance of the device.

[0030] Among them, the stress buffer structure can have the same or similar gate-source-drain structure as the multi-finger gate transistor, but it does not have gate-source-drain function and does not participate in the actual electrical function.

[0031] The substrate 110 in this embodiment can be a silicon-on-insulator (SOI) substrate. Specifically, as shown... Figure 3 As shown, the substrate 110 may include a silicon oxide layer and a silicon layer located on the silicon oxide layer. The thickness of the silicon oxide layer may be approximately 200–400 nm, and the thickness of the silicon layer may be approximately 50–200 nm.

[0032] In the above embodiments, the silicon oxide layer serves as a buried oxide isolation layer of the SOI substrate 110. It reduces the capacitance between the field-effect transistor (FET) and the substrate 110 to improve its operating speed and prevents leakage to reduce power consumption. The silicon layer is preferably a high-resistivity monocrystalline silicon layer, which serves as the active layer of the device and can form various doped regions therein. Below the silicon oxide layer is a relatively thick silicon substrate. In some embodiments, a polycrystalline silicon trapping layer may be disposed between the silicon oxide layer and the silicon substrate to trap electrons dissipated into the device during high-frequency applications, thereby improving the performance of the RF device. In some other embodiments, the substrate 110 may also be a gallium nitride-coated silicon substrate or a gallium nitride-coated silicon carbide substrate.

[0033] In summary, by setting a termination region 132 and a stress buffer structure between the active region 131 and the DTI, a stress buffer barrier is constructed, blocking the direct transmission of DTI stress to the multi-finger gate transistor (core transistor). This fundamentally solves the proximity effect problem caused by the reduced distance between the DTI and the active region 131, avoiding performance problems such as threshold voltage drift, decreased carrier mobility, and deteriorated switching characteristics of the multi-finger gate transistor caused by the proximity effect, thus eliminating the proximity effect of the BCD device. Furthermore, the buffering effect of the stress buffer structure protects the core transistor from stress impact, reducing the risk of long-term device failure due to stress accumulation. Simultaneously, the isolation effect of the DTI avoids electrical crosstalk between adjacent device regions, further reducing the probability of device failure and significantly improving the long-term reliability of the device. The multi-finger gate transistor operates in a stress-free environment, resulting in significantly improved consistency and stability of its electrical parameters. This ensures stable output performance under different operating conditions, avoiding performance fluctuations caused by the proximity effect and improving device stability. Therefore, the semiconductor device 100 of this embodiment can eliminate the proximity effect of the BCD device and improve device reliability and stability.

[0034] To demonstrate the beneficial effects of the embodiments of this application, the applicant measured the changes in the on-resistance of a semiconductor device 100 without a stress buffer structure and a semiconductor device 100 with a stress buffer structure under stress time. The results are as follows: Figure 8 As shown, by Figure 8 It can be seen that the change in on-resistance under stress time is reduced, the degree of device degradation is reduced, and the reliability and stability of semiconductor device 100 are improved.

[0035] Optional, such as Figures 1 to 7 As shown, P-well region 141 and N-drift region 142 are alternately arranged in the active region 131 along the first direction, and P-well region 141 and N-drift region 142 extend into the terminal region 132 along the second direction.

[0036] In this embodiment, a plurality of gates 143 are respectively disposed on the interface between the P-well region 141 and the N-drift region 142, and are in contact with the P-well region 141 and the N-drift region 142.

[0037] In this embodiment, a first connection region 146 and a second connection region 147 are formed in the P-well region 141, and a third connection region 144 is formed in the N-drift region 142.

[0038] In the terminal region 132, the first connection region 146 and the second connection region 147 are both first P-type heavily doped regions, the third connection region 144 in the terminal region 132 is a first N-type heavily doped region, and the gate in the terminal region 132 is a pseudo-gate structure.

[0039] Specifically, the P-well region 141 and the N-drift region 142 extend along the second direction into the terminal region 132, meaning that the terminal region 132 is connected to the active region 131 in terms of material properties, sharing the same P-well region 141 and N-drift region 142. On the surface of the P-well region 141 of the active region 131, a first connection region 146 and a second connection region 147 are formed by ion implantation; a third connection region 144 is formed within the N-drift region 142.

[0040] Corresponding to the first connection region 146, the second connection region 147, and the third connection region 144 of the active region 131, corresponding heavily doped regions are also formed at their respective positions extending into the terminal region 132. Specifically, the first connection region 146 and the second connection region 147 extend into the terminal region 132 to form a first P-type heavily doped region, and the third connection region 144 extends into the terminal region 132 to form a first N-type heavily doped region. Corresponding to the gate of the active region 131, a gate-shaped structure, called a pseudo-gate structure, is also formed within the terminal region 132. The pseudo-gate structure is not connected to the drive signal, does not participate in normal switching operations, and exists only as a physical structure.

[0041] Understandably, the first connection region 146, the second connection region 147, and the third connection region 144 within the active region 131 extend into the terminal region 132, giving the terminal region 132 a structure similar to that of the active region 131. However, it cannot form cells and does not participate in actual electrical functions. Since the terminal region 132 uses the same doping type, well depth, dielectric coverage, and metal density as the active region 131, its mechanical response characteristics (such as Young's modulus and coefficient of thermal expansion) are highly matched to those of the actual device. Stress passing through the buffer zone will not be reflected or focused due to abrupt material changes, but will instead attenuate smoothly, avoiding the formation of new stress concentration points at the boundary of the active region 131.

[0042] When the stress wave generated by DTI propagates to the terminal region 132, the heavily doped structure and the pseudo-gate structure of the terminal region 132 work together to flatten the stress gradient that might have been concentrated at the edge of the active region 131, so that the stress is dissipated by the buffer structure before it reaches the effective channel of the active region 131.

[0043] Furthermore, the pseudo-gate structure provides the same physical coverage and material stacking as the gate in the active region 131 in the termination region 132. This prevents steps or material gaps at the edge of the active region 131, avoids chemical mechanical polishing inhomogeneities caused by abrupt changes in pattern density, and thus reduces the resulting local stress concentration. Additionally, the first P-type heavily doped region and the first N-type heavily doped region within the termination region 132 effectively constitute a protective structure for the active region 131. They can collect minority carriers, i.e., leakage current, from the DTI interface or deep within the substrate 110, preventing these stray carriers from being injected into the sensitive channel of the active region 131, thereby suppressing latch-up effects or an increase in leakage current.

[0044] As an feasible approach, such as Figure 4 and Figure 7 As shown, the gate in the terminal region 132 may include a first gate region 151 and a second gate region 152. The second gate region 152 is close to the first P-type heavily doped region and is the second P-type heavily doped region. The first P-type heavily doped region 161 and the second P-type heavily doped region are connected to form a stress buffer structure in the terminal region 132.

[0045] In this embodiment, in the terminal region 132, the gate is divided into a first gate region 151 and a second gate region 152, which are attached together. The second gate region 152 is a second P-type heavily doped region, which is located near the first P-type heavily doped region and connected to it. As mentioned above, the gate is located above the interface between the P-well region 141 and the N-drift region 142, and the first P-type heavily doped region is formed by ion implantation on the upper surface of the P-well region 141. Therefore, the first P-type heavily doped region and the second P-type heavily doped region are connected in the vertical direction.

[0046] In this embodiment, the first P-type heavily doped region and the second P-type heavily doped region are connected to form a buffer wall, which actively intercepts and redistributes stress, completely blocking the non-uniform stress field induced by DTI from entering the active region 131.

[0047] Optionally, the first gate region 151 is a second N-type heavily doped region or an undoped region.

[0048] like Figure 4 As shown, when the first gate region 151 is the second N-type heavily doped region, it forms a PN structure with the second P-type heavily doped region of the second gate region 152. The second N-type heavily doped region can serve as an electron collection region. Together with the second P-type heavily doped region, it forms a more complete protection ring network, which collects minority carriers from the DTI interface in all directions.

[0049] like Figure 7As shown, when the first gate region 151 is an undoped region, the undoped region has a complete lattice structure, which can absorb and release shear stress from the DTI direction through small elastic deformation, preventing stress from being directly transmitted to the active region 131. Furthermore, if the region is entirely heavily doped, lattice mismatch at the interfaces of different doping types may lead to new stress concentration points. Introducing an undoped region can break this continuous chain of lattice mismatches, acting as a stress isolation band.

[0050] Optional, such as Figure 1 , Figure 3 and Figure 4 As shown, within the active region 131, there are two second connection regions, and the two second connection regions 147 are respectively disposed on both sides of the first connection region 146.

[0051] Specifically, within the active region 131, the first connection region 146 is a first P-type heavily doped region serving as a body region connection, and the second connection region 147 is a third N-type heavily doped region serving as a source. The first connection region 146 includes two regions respectively disposed on both sides of the second connection region 147, that is, the third N-type heavily doped region is disposed on both sides of the first P-type heavily doped region, forming a body-source-body interdigitated layout, which is used to reduce the body resistance and suppress the floating body effect.

[0052] As an feasible approach, such as Figure 1 , Figure 3 and Figure 4 As shown, within the active region 131, the first connection region 146 is a first P-type heavily doped region, serving as a body region connection portion; the second connection region 147 is a third N-type heavily doped region, serving as a source; the third connection region 144 is a first N-type heavily doped region, serving as a drain; and the gate is a second N-type heavily doped region.

[0053] A first connection region 146 and a second connection region 147 are formed on the upper surface of the P-well region 141, serving as the source and body region connection, respectively. Specifically, the first connection region 146 can be formed by ion implantation on the upper surface of the P-well region 141, serving as the body region connection; the second connection region 147 can be formed by ion implantation on the upper surface of the P-well region 141, serving as the source; the upper surface of the N-drift region 142 is formed by ion implantation, serving as the drain. The whole structure forms a multi-finger gate transistor, where each finger consists of a P-well region 141, an N-drift region 142, and a gate 143. Multiple fingers are connected in parallel, i.e., multiple cells are connected in parallel, which effectively increases the channel width and reduces the on-resistance; the current path is dispersed, the heat distribution is more uniform, and local hot spots are avoided; the gate 143 is arranged along the first direction, which facilitates metal interconnect wiring and improves layout efficiency.

[0054] In practical applications, such as Figure 3 , Figure 4 , Figure 6 as well as Figure 7 As shown, shallow trench isolation structures are respectively set on both sides of the third connection region 144, which is the first N-type heavily doped region. The shallow trench isolation structures are shallow trenches filled with SiO2, used to achieve local active region 131 isolation. The depth of the shallow trench isolation structures is typically between 0.2 and 0.5 μm.

[0055] This application also provides a method for fabricating a semiconductor device 100, used to fabricate the aforementioned semiconductor device 100, such as... Figure 9 As shown, it may include: S100: Provides substrate 110. Substrate 110 may be a silicon-on-insulator substrate.

[0056] S200: A deep trench isolation structure 120 is formed on the substrate 110. The deep trench isolation structure 120 encloses and forms a device region. The device region includes an active region 131 and terminal regions 132 disposed on opposite sides of the active region 131 along a second direction.

[0057] Specifically, the formation process of the deep trench isolation structure 120 is as follows: photolithography defines the DTI pattern, specifically, the DTI pattern surrounds the target device area; then, high aspect ratio dry etching (such as RIE) is used to etch trenches with a depth of 2–5 μm; then, the inner wall is thermally oxidized to form a pad oxide layer; then, SiO2 is deposited by CVD to fill the trench; finally, CMP is used to planarize the surface to complete the fabrication of the deep trench isolation structure 120.

[0058] S300: A multi-finger gate transistor is formed on the active region 131, and a stress buffer structure is formed in the terminal region 132. The multiple gates 143 of the multi-finger gate transistor are arranged along a first direction, which is perpendicular to the second direction.

[0059] As one possible implementation, forming a multi-finger gate transistor on the active region 131 and forming a stress buffer structure in the termination region 132 may include: S210: Alternating P-well regions 141 and N-drift regions 142 are formed on substrate 110. The P-well regions 141 and N-drift regions 142 are located within the active region 131 and extend to the terminal region 132.

[0060] In this embodiment, the P-well region 141 can be formed by defining the implantation window using photolithography and then performing ion implantation. Specifically, the P-well region 141 can be formed by high-energy boron (B) or BF2 ion implantation.

[0061] In this embodiment, the N-drift region 142 can be formed by low-dose phosphorus / arsenic ion implantation.

[0062] In this embodiment, the P-well region 141 and the N-drift region 142 are arranged alternately along the first direction to form multiple cells.

[0063] In this embodiment, the P-well region 141 and the N-drift region 142 also cover the active region 131 and the terminal regions 132 on both sides to ensure structural consistency.

[0064] S220: A gate material is formed at the interface between two adjacent P-well regions 141 and N-drift regions 142.

[0065] S230: Ion implantation is performed on the P-well region 141, the N-drift region 142 and the gate material to form a first connection region 146 and a second connection region 147 on the upper surface of the P-well region 141, a third connection region on the upper surface of the N-drift region 142, and a gate located at the interface between the P-well region 141 and the N-drift region 142.

[0066] In this terminal region 132, the first connection region 146 and the second connection region 147 are both first P-type heavily doped regions, the third connection region 144 is a first N-type heavily doped region, and the gate of the terminal region 132 is a pseudo-gate structure, which includes a first gate region 151 and a second gate region 152. The second gate region 152 is close to the first P-type heavily doped region and is a second P-type heavily doped region. The first P-type heavily doped region 161 and the second P-type heavily doped region are connected to form a stress buffer structure in the terminal region 132.

[0067] In this embodiment, within the P-well region 141 of the active region 131, a second connection region 147 (a third heavily doped N-type region) is formed as the source by high-dose As / P ion implantation; a first connection region 146 (a first heavily doped P-type region 161) is formed as the body region connection by high-dose B ion implantation; and a third connection region 144 (a first heavily doped N-type region) is formed as the drain on the N-drift region 142 by high-dose As ion implantation.

[0068] In this embodiment, within the terminal region, the first connection region 146 and the second connection region 147 are first P-type heavily doped regions 161, and the third connection region 144 is a first N-type heavily doped region. The gate 143 includes a second gate adjacent to the first P-type heavily doped region 161, and the second gate is a second P-type heavily doped region. The first P-type heavily doped region 161 and the second P-type heavily doped region are connected. It should be noted that the connection here refers to a connection in the hierarchical direction.

[0069] It should be noted that ion implantation is performed simultaneously in the active region 131 and the terminal region 132. All P-type heavily doped regions in the active region 131 and the terminal region 132 are formed through a single ion implantation. In this way, the stress buffer structure can be fabricated without adding any steps.

[0070] As one possible approach, ion implantation of the P-well region 141, the N-drift region 142, and the gate material may include performing P-type ion implantation and N-type ion implantation on the P-well region 141, the N-drift region 142, and the gate material, respectively.

[0071] Specifically, the P-type ion implantation region may include the P-well region 141 in the active region 131 away from the gate, the P-well region 141 in the terminal region 132, and the gate material on the P-well region 141 in the terminal region 132; the N-type ion implantation region may include the N-type drift region, the P-well region 141 in the active region 131 close to the gate, and the gate material in the active region 131.

[0072] In this embodiment, P-type ion implantation and N-type ion implantation can be performed sequentially, and there is no restriction on the specific order of implantation.

[0073] In practical applications, the fabrication method of semiconductor device 100 may also include: S410: Form a passivation layer covering the substrate 110 and the gate surface, and etch the passivation layer to form a connection hole.

[0074] The passivation layer can be a Si3N4 / SiO2 stack, which serves to protect the chip surface, suppress sodium ion contamination, and provide mechanical support, among other functions.

[0075] S420: A metal material is formed on the upper surface of the passivation layer. The metal material also fills the connection holes. The metal material leads out the first connection region 146, the second connection region 147, the third connection region 144 and the gate 143 in the active region 131 as the drain, the body connection part, the source and the gate 143 respectively, forming a multi-finger gate transistor.

[0076] It should be noted that the specific structure and beneficial effects of the semiconductor device 100 prepared by the method for preparing the semiconductor device 100 have been described in detail in the foregoing embodiments, and will not be repeated here.

[0077] The above are merely optional embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0078] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A semiconductor device, characterized by, include: Substrate; A deep trench isolation structure is disposed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and terminal regions disposed on opposite sides of the active region along a second direction, a multi-finger gate transistor is disposed in the active region, and the multiple gates of the multi-finger gate transistor are arranged along a first direction, a stress buffer structure is formed in the terminal region, the stress buffer structure is used to buffer the stress between the deep trench isolation structure and the multi-finger gate transistor, the first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, wherein The active region is provided with P-well region and N-drift region alternately arranged in sequence along the first direction, and the P-well region and the N-drift region extend into the terminal region along the second direction; The plurality of gates are respectively disposed on the interface between the P-well region and the N-drift region and are in contact with the P-well region and the N-drift region; a first connection region and a second connection region are formed in the P-well region and a third connection region is formed in the N-drift region; Wherein, the first connection region and the second connection region within the terminal region are both first P-type heavily doped regions, the third connection region within the terminal region is a first N-type heavily doped region, and the gate within the terminal region is a pseudo-gate structure.

3. The semiconductor device of claim 2, wherein, The gate in the terminal region includes a first gate region and a second gate region, the second gate region being close to the first heavily doped P-type region, and the second gate region being a second heavily doped P-type region; The first P-type heavily doped region and the second P-type heavily doped region are connected to form a stress buffer structure in the terminal region.

4. The semiconductor device according to claim 3, wherein The first gate region is either a second N-type heavily doped region or an undoped region.

5. The semiconductor device of claim 2, wherein Within the active region, there are two second connection regions, which are respectively located on both sides of the first connection region.

6. The semiconductor device of claim 2, wherein Within the active region, the first connection region is a first P-type heavily doped region serving as a body region connection portion, the second connection region is a third N-type heavily doped region serving as a source, the third connection region is a first N-type heavily doped region serving as a drain, and the gate is a second N-type heavily doped region.

7. A method of manufacturing a semiconductor device, characterized by include: Provide substrate; A deep trench isolation structure is formed on the substrate, the deep trench isolation structure enclosing a device region, the device region including an active region and terminal regions disposed on opposite sides of the active region along a second direction; A multi-finger gate transistor is formed on the active region, and a stress buffer structure is formed in the terminal region. The multiple gates of the multi-finger gate transistor are arranged along a first direction, which is perpendicular to the second direction.

8. The method of producing a semiconductor device according to Claim 7, wherein The formation of a multi-finger gate transistor on the active region and the formation of a stress buffer structure in the terminal region include: Alternating P-well regions and N-drift regions are formed on the substrate, the P-well regions and the N-drift regions being located within the active region and extending to the terminal region; A gate material is formed at the interface between two adjacent P-well regions and the N-drift region; Ion implantation is performed on the P-well region, the N-drift region, and the gate material to form a first connection region and a second connection region on the upper surface of the P-well region, a third connection region on the upper surface of the N-drift region, and a gate located at the interface between the P-well region and the N-drift region. Wherein, the first connection region and the second connection region within the terminal region are both first P-type heavily doped regions, and the third connection region within the terminal region is a first N-type heavily doped region; the gate of the terminal region is a pseudo-gate structure, the pseudo-gate structure includes a first gate region and a second gate region, the second gate region is close to the first P-type heavily doped region, and the second gate region is a second P-type heavily doped region, the first P-type heavily doped region and the second P-type heavily doped region are connected to form a stress buffer structure within the terminal region.

9. The method of producing a semiconductor device according to claim 8, wherein The ion implantation of the P-well region, the N-drift region, and the gate material includes: P-type ion implantation and N-type ion implantation are performed on the P-well region, the N-drift region, and the gate material, respectively. The P-type ion implantation region includes a P-well region in the active region away from the gate, a P-well region in the terminal region, and the gate material on the P-well region in the terminal region; the N-type ion implantation region includes an N-type drift region, a P-well region in the active region close to the gate, and the gate material in the active region.

10. The method of producing a semiconductor device according to Claim 8, wherein The preparation method further includes: A passivation layer is formed covering the substrate and the gate surface, and the passivation layer is etched to form a connection hole; A metal material is formed on the surface of the passivation layer, and the metal material also fills the connection hole. The metal material leads out the first connection region, the second connection region, the third connection region and the gate in the active region to serve as the drain, the body connection part, the source and the gate respectively, forming a multi-finger gate transistor.

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