Device structures and methods of forming the same

Abstract

An exemplary device structure includes a semiconductor layer extending along a first direction between a first source / drain and a second source / drain. The semiconductor layer may be disposed above a semiconductor substrate. The device structure also includes a gate disposed between the first source / drain and the second source / drain. The gate is disposed above and engages the channel layer, and extends along a second direction different from the first direction. The gate also extends through the channel layer along a third direction different from the first and second directions. In some embodiments, the gate may engage four sidewalls of the semiconductor layer. In some embodiments, the semiconductor layer is a ring-shaped semiconductor layer, and the semiconductor layer may extend around a portion of the gate. In some embodiments, the semiconductor layer is a segmented channel layer. Embodiments of this application also relate to device structures and methods of forming the same.

Description

Technical Field

[0001] The embodiments of this application relate to device structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. Such miniaturization has also increased the complexity of handling and manufacturing ICs, and similar developments in IC materials and manufacturing are required to achieve these advancements. Summary of the Invention

[0003] Some embodiments of this application provide a device structure including: an active region comprising a semiconductor ring, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, and the semiconductor ring extends longitudinally along the first direction between the first source / drain and the second source / drain; and a gate disposed above and connected to the semiconductor ring, wherein the gate extends through the semiconductor ring, the gate is disposed between the first source / drain and the second source / drain along the first direction, the gate extends longitudinally along a second direction different from the first direction, and the gate extends along the second direction from above the semiconductor ring to above an isolation structure.

[0004] Other embodiments of this application provide a method for forming a device structure, comprising: forming an active region including a channel layer, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, the channel layer is disposed above a semiconductor substrate, and the channel layer extends longitudinally along the first direction between the first source / drain and the second source / drain; and forming a gate extending longitudinally along a second direction different from the first direction, wherein the gate is disposed between the first source / drain and the second source / drain along the first direction, the gate is disposed above the channel layer and engages the channel layer, the gate extends along the second direction above the channel layer and the isolation structure, and the gate extends through the channel layer along a third direction, wherein the third direction is different from the first direction and the second direction.

[0005] Some embodiments of this application provide a method for forming a device structure, comprising: receiving a device structure including a multilayer stack extending longitudinally along a first direction between a first source / drain and a second source / drain, and a dummy gate disposed above the multilayer stack and between the first source / drain and the second source / drain, wherein the dummy gate extends longitudinally along a second direction different from the first direction, and the multilayer stack includes a semiconductor layer and a sacrificial layer; forming a channel cut in the dummy gate and the multilayer stack, wherein the channel cut extends through the dummy gate and the multilayer stack along a third direction, wherein the channel cut segments the semiconductor layer of the multilayer stack, and the third direction is different from the first direction and the second direction; and forming a gate stack in the channel cut, wherein forming the gate stack includes replacing the remaining portion of the dummy gate and the remaining portion of the sacrificial layer of the multilayer stack with the gate stack, wherein the gate stack extends longitudinally along the second direction above the semiconductor layer and the isolation structure of the multilayer stack, and wherein the gate stack includes a gate dielectric and a gate electrode. Attached Figure Description

[0006] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 1E These are partial or all of the various views of a device having segmented channels according to various aspects of embodiments of the present disclosure.

[0008] Figure 2 , Figure 3A , Figure 3B and Figure 4 Description of various aspects of embodiments according to this disclosure Figure 1A Schematic cross-sectional views of some or all of the different configurations of the device 100.

[0009] Figures 5A to 5Q and Figures 6A to 6Q Devices (such as) according to various aspects of embodiments of this disclosure Figures 1A to 1E A schematic cross-sectional view of part or all of the device at various stages of the manufacturing process.

[0010] Figures 7A to 7M and Figures 8A to 8M Devices (such as) according to various aspects of embodiments of this disclosure Figures 1A to 1E A schematic cross-sectional view of part or all of the device at various stages of another manufacturing process.

[0011] Figures 9A to 9F Devices (such as) according to various aspects of embodiments of this disclosure Figures 1A to 1E The device) in the manufacturing process (such as Figures 5A to 5Q and Figures 6A to 6Q and / or Figures 7A to 7M and Figures 8A to 8M A schematic cross-sectional view of part or all of the channel cutting stage of the manufacturing process.

[0012] Figures 10A to 10D Devices (such as) according to various aspects of embodiments of this disclosure Figures 1A to 1E The device) in the manufacturing process (such as Figures 5A to 5Q and Figures 6A to 6Q and / or Figures 7A to 7M and Figures 8A to 8M A schematic cross-sectional view of part or all of the device isolation stage of the manufacturing process.

[0013] Figure 11 Device layouts according to various aspects of embodiments of this disclosure (which may include) Figures 1A to 1E A schematic top view of part or all of the device.

[0014] Figures 12 to 17 It is according to various aspects of embodiments of this disclosure that the channel cutting stage (such as with) can be used in the manufacturing of the device. Figures 5A to 5Q and Figures 6A to 6Q and / or Figures 7A to 7M and Figures 8A to 8M A schematic top view of part or all of the channel cut layout implemented (related to the manufacturing process).

[0015] Figure 18A , Figure 18B , Figure 19A and Figure 19B According to various aspects of embodiments of this disclosure, transistors (such as transistors with segmented channels) may be included. Figures 1A to 1E A schematic cross-sectional view of part or all of a device (a transistor) and a device with a non-segmented channel transistor. Detailed Implementation

[0016] This disclosure generally relates to multi-gate devices (e.g., FinFETs, gate-all-around (GAA) transistors (e.g., nanowire transistors or nanosheet transistors), fork-plate transistors, etc.) and methods of manufacturing them.

[0017] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the embodiments of this disclosure. Spatially relative terms are intended to cover different orientations of the device including the components. Furthermore, when numerical values ​​or ranges of values ​​are described using terms such as “about,” “approximately,” etc., as will be understood by those skilled in the art, the term is intended to cover values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having numerically related characteristics, the numerical value or range of numerical values ​​encompasses a reasonable range including the described numerical value, such as within + / - 20% of the described numerical value. For example, a material layer having a thickness of “about 5 nm” can include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 15%, as is known to those skilled in the art. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Multi-gate devices include gate structures that extend partially or completely around a channel region to provide access to the channel region on at least two sides. One such multi-gate device is a gate all-around (GAA) device, which includes a channel layer (region) stacked vertically or horizontally and suspended above a substrate in a manner that allows the gate stack to wrap around and engage the channel layer. The channel layer extends between a source region and a drain region (e.g., an epitaxial source / drain), and a voltage can be applied to the gate stack, the source region, and / or the drain region to control current flow between the source and drain regions. GAA devices can significantly increase the contact area between the gate stack and the channel region, which can reduce subthreshold swing (SS), reduce short-channel effect (SCE), increase drive current, and / or improve channel control compared to other multi-gate devices such as FinFETs.

[0019] This disclosure provides embodiments of multi-gate devices and methods for manufacturing multi-gate devices, which can reduce short-channel effects, enable gate length reduction, enable channels with a smaller width-to-height ratio, enable larger source / drain volumes, improve multi-gate device performance, and enable other improvements or combinations thereof. Such improvements can be provided by segmenting larger channel structures (e.g., nanosheets) into smaller channel structures (e.g., nanowires), which can be connected and / or spliced ​​together. Segmenting larger channel structures into smaller channel structures can provide more sides and / or shorter sides for the junction through the gate, which can improve gate control and reduce short-channel effects. Because forming larger channels and subsequently segmenting them into smaller channel structures is easier than initially forming smaller channel structures, the proposed segmentation is seamlessly integrated into the multi-gate device manufacturing process without significantly increasing manufacturing complexity, time, cost, or a combination thereof. In some embodiments, such segmentation is introduced before or during a gate replacement process. In some embodiments, segmentation provides a smaller channel structure with a width / height ratio that maximizes gate control and thus improves short-channel effect control. In some embodiments, the improved gate control (and therefore improved short-channel effect control) provided by the disclosed segmentation can compensate for any degradation in short-channel effect control that may occur as the gate length scales for advanced nodes (e.g., gate length less than about 20 nm). Therefore, the disclosed multi-gate devices and fabrication techniques described herein can improve device performance as described herein. Different embodiments may have different advantages, and no particular advantage is desired in any embodiment.

[0020] Figures 1A to 1E These are partial or all of the various views of the device 100 according to various aspects of embodiments of the present disclosure. Figure 1A These are schematic perspective views of part or all of the device 100 according to various aspects of embodiments of the present disclosure. Figure 1B Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic top view of part or all of the line BB (e.g., through the top channel of device 100). Figure 1C Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic cross-sectional view of part or all of line CC. Figure 1D Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic cross-sectional view of part or all of line DD. Figure 1E Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic cross-sectional view of part or all of line EE. Figure 2 , Figure 3A , Figure 3B and Figure 4 These are schematic cross-sectional views depicting some or all of the different configurations of the device 100 according to various aspects of embodiments of the present disclosure. Figure 2 Device 100 according to various aspects of embodiments of this disclosure Figure 1A A partial or complete cross-sectional view of line EE. Figure 3A Device 100 according to various aspects of embodiments of this disclosure Figure 1A A partial or complete cross-sectional view of line EE. Figure 3B Device 100 according to various aspects of embodiments of this disclosure Figure 1A A partial or complete cross-sectional view of line DD. Figure 4 Device 100 according to various aspects of embodiments of this disclosure Figure 1A A partial or complete cross-sectional view of line DD. For ease of description and understanding, this paper also discusses... Figures 1A to 1E , Figure 2 , Figure 3A , Figure 3B and Figure 4 For clarity, it has been simplified. Figures 1A to 1E , Figure 2 , Figure 3A , Figure 3B and Figure 4 To better understand the inventive concept of the embodiments of this disclosure. Additional components may be added to device 100, and in other embodiments of device 100, some of the components described below may be replaced, modified, or eliminated.

[0021] Device 100 may include at least one transistor T, such as a gate-all-around (GAA) transistor (i.e., a transistor having a gate that at least partially surrounds a suspended channel (e.g., nanowire, nanosheet, nanorod, etc.) extending between the source and drain). Device 100 may be included in a microprocessor, memory, other integrated circuit (IC) devices, or combinations thereof. In some embodiments, device 100 is part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, and device 100 may include a variety of passive and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0022] Device 100 may include a substrate 105, a protrusion 105', an isolation structure 110 (also referred to as a substrate isolation structure), a semiconductor layer 120, and a gate structure 130. The gate structure 130 may include a gate stack 132 (e.g., a gate dielectric 134 and a gate electrode 136) and a gate spacer 138. Device 100 may also include an internal spacer 140 and a source / drain structure 150. Each source / drain structure 150 may be multilayered, including, for example, a semiconductor layer 152, an insulating layer 154, a semiconductor layer 156, and a semiconductor layer 158. An active region 160 of device 100 extends longitudinally along the x-direction (i.e., length along the x-direction, width along the y-direction, and height along the z-direction), and the active region 160 may be oriented substantially parallel to other active regions. The active region 160 includes at least one channel region (C), a source region, and a drain region. The source region and drain region may be collectively referred to as the source / drain region (S / D). In some embodiments, a source / drain structure 150 may be formed in the source / drain region of the active region 160 and / or provide the source / drain region of the active region 160, and a semiconductor layer 120 extending between the source / drain regions may be formed in the channel region of the active region 160 and / or provide the channel region of the active region 160.

[0023] In some embodiments, as depicted, transistor T includes a channel (e.g., semiconductor layer 120), a source / drain (e.g., source / drain structure 150), and a gate (e.g., gate stack 132). Gate stack 132 is disposed between source / drain structures 150 (e.g., along the x-direction), and internal spacers 140 may be disposed between gate stack 132 and source / drain structures 150. Gate stack 132 engages the channel (e.g., semiconductor layer 120), and the channel extends between the source / drain (e.g., source / drain structure 150) (e.g., along the x-direction). In the depicted embodiment, transistor T is a GAA transistor, and gate stack 132 surrounds the channel (e.g., semiconductor layer 120). In some embodiments, transistor T is a p-type transistor. In some embodiments, transistor T is an n-type transistor.

[0024] The substrate 105, protrusion 105', and semiconductor layer 120 include: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some embodiments, the substrate 105 is a silicon substrate, and the protrusion 105' may be formed of the same semiconductor material (e.g., silicon) as the substrate 105 or a different semiconductor material (e.g., silicon-germanium). In some embodiments, the protrusion 105' is a patterned, protruding portion, and / or extension of the substrate 105, and the protrusion 105' may be referred to as a substrate extension, a substrate fin portion, a fin portion, an etched substrate portion, etc. The semiconductor layer 120 may be formed of the same semiconductor material as the substrate 105 or a different semiconductor material. In the depicted embodiment, the semiconductor layer 120 is a silicon layer or a silicon-germanium layer.

[0025] Substrate 105 (and protrusion 105') may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. n-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped regions include both p-type and n-type dopants. The doped regions may provide p-well structures, n-well structures, double-well structures, protrusion structures, other suitable structures, or combinations thereof. In some embodiments, substrate 105 and / or protrusion 105' may include n-wells and / or p-wells. For example, substrate 105 and / or protrusion 105' may include p-wells in an n-type transistor region and n-wells in a p-type transistor region. In some embodiments, semiconductor layer 120 includes n-type and / or p-type dopants.

[0026] An isolation structure 110 may be formed over the substrate 105 and is formed adjacent to and / or around the protrusion 105'. In some embodiments, the active region 160 is separated from other active regions and / or device regions by the isolation structure 110. The isolation structure 110 can electrically isolate the active region 160 (such as the protrusion 105' and / or its source / drain structure 150) from other active regions. The isolation structure 110 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The isolation structure 110 may have a multilayer structure. For example, the isolation structure 110 may include a bulk dielectric (e.g., an oxide layer) located over a dielectric pad (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, the isolation structure 110 may include a bulk dielectric located above a doped pad, such as a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad. The dimensions and / or characteristics of the isolation structure 110 may be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof.

[0027] Semiconductor layers 120 are vertically stacked (e.g., along the z-direction) and suspended over substrate 105 and / or protrusion 105', and semiconductor layers 120 or portions thereof can provide a channel for transistor T. In the depicted embodiment, three semiconductor layers 120—upper semiconductor layer 120U, middle semiconductor layer 120M, and lower semiconductor layer 120L—are vertically stacked over protrusion 105' and extend longitudinally between source / drain structures 150. For example, semiconductor layers 120 extend along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. Device 100 and / or transistor T can be configured to have different numbers of semiconductor layers 120. For example, a semiconductor layer stack (also referred to as a channel stack) may include two to six semiconductor layers 120.

[0028] Gate structure 130 is disposed over the channel region (C) of active region 160 (e.g., a channel stack formed by semiconductor layer 120) and between corresponding source / drain regions (S / D) of active region 160 (e.g., source / drain structure 150). Gate structure 130 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of active region 160. For example, gate structure 130 extends in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. Gate structure 130 may extend substantially parallel to other gate structures. As noted above, gate structure 300 includes gate stack 132 (e.g., gate dielectric 134 and gate electrode 136) and gate spacer 138. Figure 1C In the middle (e.g., the XZ plane), a gate structure 130 is disposed between the source / drain structure 150, a gate stack 132 is disposed on the top and bottom of the semiconductor layer 120 and bonds the top and bottom of the semiconductor layer 120, and a gate spacer 138 is disposed on the topmost semiconductor layer 120 (e.g., semiconductor layer 120U). Figure 1D In the middle (e.g., the YZ plane), a gate stack 132 is disposed above the protrusion 105', the isolation structure 110, and the semiconductor layer 120, and the gate stack 132 at least covers the semiconductor layer 120. The gate stack 132 may be disposed on the top, bottom, and sidewalls of the semiconductor layer 120 and engage the top, bottom, and sidewalls of the semiconductor layer 120 (e.g., the gate stack 132 surrounds the semiconductor layer 120). Thus, the gate stack 132 is disposed between semiconductor layers 120U and 120M, between semiconductor layers 120M and 120L, and between semiconductor layer 120L and the protrusion 105'. In some embodiments, the gate stack 132 may cover the protrusion 105'. For example, the gate stack 132 is disposed on the top and sidewalls of the protrusion 105'.

[0029] Stacked channels (e.g., semiconductor layer 120) can increase device density and improve device performance. For example, configuring transistor T with stacked semiconductor layer 120 reduces the area consumed by transistor T, allowing more transistors to be packed into a given area, while also increasing the effective channel width, thereby increasing transistor drive current. However, as device part sizes shrink to accommodate the higher device densities of scaling IC technology nodes, gate control degradation has been observed, particularly with decreasing gate length and increasing channel width to height ratio, leading to worsening control of short-channel effects in scaling devices.

[0030] This disclosure proposes to segment and / or cut larger channel structures (e.g., nanosheets) into smaller channel structures (e.g., nanowires and / or nanorods) that can be spliced ​​together, thereby improving the performance of transistor T and / or device 100. In some embodiments, semiconductor layer 120 is a segmented channel, and semiconductor layer 120 may have an annular profile rather than a sheet profile. For example, semiconductor layer 120U includes semiconductor segment 120U-1 extending longitudinally along the active region longitudinal direction (e.g., x-direction), semiconductor segment 120U-2 extending longitudinally along the active region longitudinal direction (e.g., x-direction), and semiconductor segment 120U-3 extending longitudinally from semiconductor segment 120U-1 to semiconductor segment 120U-2 along the gate longitudinal direction (e.g., y-direction); semiconductor layer 120M includes semiconductor segment 120M-1 extending longitudinally along the active region longitudinal direction (e.g., x-direction), and semiconductor segment 120M-3 extending longitudinally along the active region longitudinal direction (e.g., x-direction). The semiconductor segment 120M-2 and the semiconductor segment 120M-3 extending longitudinally from semiconductor segment 120M-1 to semiconductor segment 120M-2 along the gate longitudinal direction (e.g., the y direction); and the semiconductor layer 120L includes semiconductor segment 120L-1 extending longitudinally along the active region longitudinal direction (e.g., the x direction), semiconductor segment 120L-2 extending longitudinally along the active region longitudinal direction (e.g., the x direction), and semiconductor segment 120L-3 extending longitudinally from semiconductor segment 120L-1 to semiconductor segment 120L-2 along the gate longitudinal direction (e.g., the y direction).

[0031] Semiconductor layers 120U and 120M are separated by a spacer s1 (e.g., along the z-direction), semiconductor layers 120M and 120L are separated by a spacer s1, and semiconductor layer 120L and protrusion 105' may be separated by a spacer s1. Semiconductor segments 120U-1 and 120U-2 are separated by a spacer s2 (e.g., along the y-direction); semiconductor segments 120M-1 and 120M-2 are separated by a spacer s2; and semiconductor segments 120L-1 and 120L-2 are separated by a spacer s2. Semiconductor segment 120U-3 is separated by a spacer s3 (e.g., along the x-direction), and semiconductor segment 120U-3 connects and / or splices semiconductor segments 120U-1 and 120U-2 together. Semiconductor segment 120M-3 is separated by spacer s3, and semiconductor segment 120M-3 connects and / or splices semiconductor segments 120M-1 and 120M-2 together. Semiconductor segment 120L-3 is separated by spacer s3, and semiconductor segment 120L-3 connects and / or splices semiconductor segments 120L-1 and 120L-2 together. In some embodiments, as depicted, because semiconductor layer 120U has substantially straight inner sidewalls (e.g., formed by the inner sidewalls of semiconductor segment 120U-1, semiconductor segment 120U-2, and semiconductor segment 120U-3), semiconductor layer 120M has substantially straight inner sidewalls (e.g., formed by the inner sidewalls of semiconductor segment 120M-1, semiconductor segment 120M-2, and semiconductor segment 120M-3), and semiconductor layer 120L has substantially straight inner sidewalls (e.g., formed by the inner sidewalls of semiconductor segment 120L-1, semiconductor segment 120L-2, and semiconductor segment 120L-3), the spacings s2 and s3 are substantially the same from top to bottom of the channel structure of transistor T (e.g., its semiconductor layer 120).

[0032] In some embodiments, as depicted, because semiconductor layer 120U has substantially straight inner sidewalls and substantially straight outer sidewalls (e.g., formed by the outer sidewalls of semiconductor segment 120U-1, semiconductor segment 120U-2, and semiconductor segment 120U-3), semiconductor layer 120M has substantially straight inner sidewalls and substantially straight outer sidewalls (e.g., formed by the outer sidewalls of semiconductor segment 120M-1, semiconductor segment 120M-2, and semiconductor segment 120M-3), and semiconductor layer 120L has substantially straight inner sidewalls and substantially straight outer sidewalls (e.g., formed by the outer sidewalls of semiconductor segment 120L-1, semiconductor segment 120L-2, and semiconductor segment 120L-3), the width of the channel segment of the channel structure of transistor T is substantially the same from the top to the bottom of the channel structure. For example, semiconductor segments 120U-1, 120M-1, and 120L-1 may have a width w1 (along the y-direction) and a length l1 (e.g., along the x-direction); semiconductor segments 120U-2, 120M-2, and 120L-2 may have a width w2 (along the y-direction) and a length l2 (e.g., along the x-direction); and semiconductor segments 120U-3, 120M-3, and 120L-3 may have a width w3 (e.g., along the x-direction) and a length l3 (e.g., along the y-direction). In some embodiments, the width w1 is equal to the width w2, and the length l1 is equal to the length l2. In some embodiments, the width w1 is different from the width w2 and / or the length l1 is different from the length l2. The sum of the width w1, width w2, and length l3 (which may correspond to the interval s2) may be equal to the total width of the active region 160 (e.g., along the x-direction).

[0033] Because the semiconductor layer 120 is segmented with an annular profile, the gate stack 132 can extend through the semiconductor layer 120, and the gate stack 132 can engage more than one outer wall (or multiple sidewalls) of the semiconductor layer 120. For example, the gate stack 132 can be disposed above and engage the outer and inner sidewalls of the semiconductor layer 120. In some embodiments, the gate stack 132 is disposed on the top, bottom, and four sidewalls of the semiconductor layer 120 (two of the four sidewalls can jointly provide an inner sidewall, and two of the four sidewalls can jointly provide an outer sidewall). As an example, the gate stack 132 can engage the upper, lower, left, and right sides of semiconductor segments 120U-1 and 120U-2; the upper, lower, left, and right sides of semiconductor segments 120M-1 and 120M-2; and the upper, lower, left, and right sides of semiconductor segments 120L-1 and 120L-2. The increased gate bonding (e.g., by configuring a channel structure with more sides and shorter sides) enables greater electrostatic gate control of the semiconductor layer 120 and thus improved SCE control.

[0034] In addition, since the widths w1 and w2 are less than the total width of the active region 160, the width / height ratio of the semiconductor layer 120 (e.g., its channel segment) is less than the width / height ratio of the unsegmented semiconductor layer 120 (e.g., having a width equal to the total width of the active region 160), which can further improve the gate control of the channel structure. For example, the semiconductor layer 120 has a height h (e.g., along the z direction), the ratio of the width w1 to the height h (i.e., w1 / h) is less than the ratio of the total width of the active region 160 to the height h, and the ratio of the width w2 to the height h (i.e., w2 / h) is less than the ratio of the total width of the active region 160 to the height h. In some embodiments, the ratio of the total width of the active region 160 to the height h is greater than or equal to about 2. In some embodiments, w1 / h is less than about 2 and greater than about 0.5 (i.e., 0.5 < w1 / h < 2). For example, w1 / h can be about 1. In some embodiments, w2 / h is less than about 2 and greater than about 0.5 (i.e., 0.5 < w2 / h < 2). For example, w2 / h can be about 1. It has been observed that gate length scaling (e.g., to less than 20 nm (e.g., about 12 nm)) and the corresponding reduction of source-drain separation reduce the gate control of the middle of the channel, thus deteriorating the SCE control. Channels with an overly large (e.g., greater than or equal to 2) or overly small (e.g., less than 0.5) width / height ratio may thus provide poorer gate control because such channel width / height ratios may result in two of the four sides (e.g., the upper side, the lower side, the right side, and the left side) of the channel (e.g., the channel segment) being too far from the middle of the channel, which may be difficult to gate-control at scaled dimensions. Since the device performance may be dominated by these two sides (i.e., those closer to the middle of the channel), transistors configured with channels having a width / height ratio less than 0.5 or greater than or equal to 2 may exhibit greater SCE. In contrast, channels with a width / height ratio greater than or equal to 0.5 and less than 2 maximize gate control by enabling sufficient "gate control" of the upper side, the lower side, the right side, and the left side of the channel, thereby minimizing SCE.

[0035] Semiconductor segments (e.g., semiconductor segments 120U-1, 120U-2, 120M-1, 120M-2, 120L-1, 120L-2, or combinations thereof) extending between source / drain structures 150 in semiconductor layer 120 can provide channels for transistor T. The semiconductor segments can have cylindrical profiles (and thus provide transistor T with nanowires), quadrilateral profiles (and thus provide transistor T with nanorods), or any other suitable shape. In some embodiments, as depicted, the semiconductor segments can be nanowires, and transistor T can be referred to as a nanowire transistor. In some embodiments, semiconductor layer 120 and / or its semiconductor segments have nanoscale dimensions and can be referred to as a “nanostructure.” In some embodiments, semiconductor layer 120 and / or its semiconductor segments have subnanometer dimensions and / or other suitable dimensions. In some embodiments, as depicted, semiconductor layer 120 can be a rectangular ring. In some embodiments, the semiconductor layer 120 may be a circular ring, a rhomboid ring, a trapezoidal ring, a polygonal ring, an elliptical ring, a diamond-shaped ring, a hexagonal ring, an octagonal ring, other suitable ring shapes, or combinations thereof.

[0036] In some embodiments, such as Figure 2 As depicted, semiconductor layer 120 may have tapered inner sidewalls and / or tapered outer sidewalls, such that spacing s2, spacing s3, width w1, width w2, width w3, or combinations thereof may be tapered (i.e., increasing or decreasing along the gate height direction (e.g., the z-direction)). In such embodiments, gate stack 132 may enclose channel connection segments (e.g., semiconductor segments 120U-3, 120M-3, 120L-3, or combinations thereof), as depicted. In some embodiments, such as Figure 3A and Figure 3B As depicted, the gate stack 132 may extend into and / or penetrate the protrusion 105' and / or substrate 105. Such a configuration can facilitate the fabrication of the device 100, for example, by expanding the etching process window associated with the channel notch stage during the fabrication of the device 100 (e.g., this may involve forming a channel notch (i.e., segmented semiconductor layer 120) that can subsequently be filled by the gate stack 132). In some embodiments, the gate stack 132 extends a distance d into the protrusion 105' and / or substrate 105. In some embodiments, the distance d is less than about 20 nm. In some embodiments, such as Figure 4As depicted, transistor T may include more than two channel segments. For example, semiconductor layer 120U may also include semiconductor segment 120U-4 (which may be connected and / or spliced ​​to semiconductor segment 120U-1 and / or semiconductor segment 120U-2 via semiconductor segment 120U-3); semiconductor layer 120M may also include semiconductor segment 120M-4 (which may be connected and / or spliced ​​to semiconductor segment 120M-1 and / or semiconductor segment 120M-2 via semiconductor segment 120M-3); and semiconductor layer 120L may also include semiconductor segment 120L-4 (which may be connected and / or spliced ​​to semiconductor segment 120L-1 and / or semiconductor segment 120L-2 via semiconductor segment 120L-3). Various channel segmentation configurations are considered in embodiments of this disclosure.

[0037] The gate dielectric 134 includes at least one dielectric gate layer. In some embodiments, the gate dielectric 134 includes an interface layer comprising a dielectric material such as SiO2 or SiGeO. x HfSiO, SiON, other dielectric materials, or combinations thereof. In some embodiments, the gate dielectric 134 includes a high-k dielectric layer. The high-k dielectric layer includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k≈3.9), such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. x ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. For example, the gate dielectric 134 may include a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer. In some embodiments, the interface layer and / or the high-k dielectric layer have a multilayer structure.

[0038] A gate electrode 136 is disposed above a gate dielectric 134. The gate electrode 136 includes at least one conductive gate layer. The conductive gate layer includes a conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some embodiments, the gate electrode 136 includes a work function layer. The work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function). The work function layer includes a work function metal and / or alloys thereof, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the gate electrode 136 includes a bulk layer located above the gate dielectric and / or the work function layer. The bulk layer includes a suitable conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the gate electrode 136 includes a barrier layer located above the work function layer and / or the gate dielectric. The barrier layer includes a material that prevents or eliminates the diffusion and / or reaction of components between adjacent layers and / or promotes adhesion between adjacent layers, such as between the work function layer and the bulk layer. In some embodiments, the barrier layer includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, or combinations thereof.

[0039] Gate spacer 138 is formed adjacent to gate stack 130 and along the sidewall of gate stack 130. Gate spacer 138 includes a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). In some embodiments, gate spacer 138 has a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacer 138 includes more than one group of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such embodiments, the respective groups of spacers have different compositions.

[0040] Internal spacers 140 may be disposed below gate structure 130 (e.g., below its gate spacer 138) and along the sidewalls of gate stack 132. Internal spacers 140 are disposed between gate stack 132 and source / drain structure 150, between adjacent semiconductor layers 120, and between the bottommost semiconductor layer 120 (e.g., semiconductor layer 120L) and protrusion 105'. Internal spacers 140 comprise a dielectric material comprising silicon, oxygen, carbon, nitrogen, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, etc. In some embodiments, internal spacers 140 comprise a low-k dielectric material. In some embodiments, dopants (e.g., p-type and / or n-type) are introduced into the dielectric material, and internal spacers 140 comprise doped dielectric material. In some embodiments, the formation of internal spacers 140 (including corresponding manufacturing steps associated therewith) is optional. In other words, the formation of the internal spacer 140 can be omitted, so that the internal spacer 140 may not exist in the transistor depicted in the device 100.

[0041] The source / drain structure 150 comprises a semiconductor material that may be doped with n-type and / or p-type dopants. In some embodiments, the source / drain structure 150 is formed by an epitaxial process, such that the source / drain structure 150 comprises an epitaxially grown / deposited semiconductor material and may be referred to as an epitaxial source / drain. In some embodiments, the source / drain structure 150 comprises silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments, the source / drain structure 150 comprises silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof. In some embodiments, a heavily doped source / drain (HDD) region, a lightly doped source / drain (LDD) region, other doped regions, or combinations thereof are formed in the source / drain structure 150. In some embodiments, the doped regions (such as LDD regions) may be disposed in and / or extend into the channel region (such as semiconductor layer 120). As used herein, source / drain region, source / drain, source / drain structure, epitaxial source / drain, epitaxial source / drain component, etc., may refer to the source of device 100 and / or the drain of its transistors, or the source and / or drain of multiple devices (including device 100) and / or multiple transistors.

[0042] The source / drain structure 150 may include a respective semiconductor layer 152, a respective insulating layer 154, a respective semiconductor layer 156, and a respective semiconductor layer 158. The semiconductor layer 152 is disposed on the protrusion 105' and / or the substrate 105. In the depicted embodiment, the semiconductor layer 152 comprises a doped semiconductor material (i.e., substantially free of n-type and / or p-type dopants). For example, when the semiconductor layer 152 is formed, for example, by an epitaxial growth process, no intentional doping is implemented. Therefore, the semiconductor layer 152 can provide a high-resistance path at the bottom of the source / drain structure 150, thereby preventing leakage current from flowing between the source / drain structures 150 through the protrusion 105' and / or the substrate 105. In some embodiments, the undoped semiconductor layer is formed of silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. For example, the semiconductor layer 152 may be an undoped silicon layer or an undoped silicon-germanium layer.

[0043] An insulating layer 154 is disposed on the semiconductor layer 152, and the insulating layer 154 may be disposed between the semiconductor layer 158 and the semiconductor layer 152. The insulating layer 154 includes an electrically insulating material, such as a dielectric material, that can also prevent unwanted leakage current from flowing through the protrusion 105' and / or the substrate 105 between the source / drain structure 150 (e.g., its semiconductor layer 158). In some embodiments, the insulating layer 154 includes a silicon-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, silicon carbon oxynitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof) or combinations thereof. In some embodiments, the insulating layer 154 includes a metal-containing dielectric material, such as a metal oxide material (e.g., aluminum oxide and / or hafnium oxide) and / or a metal nitride material. In some embodiments, the insulating layer 154 includes a doped semiconductor material, the doped semiconductor material comprising a dopant of the opposite type to that of the semiconductor layer 158. For example, where the source / drain structure 150 may be a p-type transistor having a p-type doped semiconductor layer, the insulating layer 154 may include an n-type doped semiconductor material, such as phosphorus-doped silicon. In another example, where the source / drain structure 150 may be an n-type transistor having an n-type doped semiconductor layer, the insulating layer 154 may include a p-type doped semiconductor material, such as boron-doped silicon. In some embodiments, the insulating layer 154, alone or in combination with the semiconductor layer 152 (e.g., an undoped semiconductor layer), may be referred to as bottom source / drain isolation.

[0044] Semiconductor layers 156 and 158 are disposed above insulating layer 154 and coupled to semiconductor layer 120. Semiconductor layer 156 may be disposed between semiconductor layers 158 and 120. In the depicted embodiments, semiconductor layers 156 and 158 comprise semiconductor materials doped with n-type and / or p-type dopants (e.g., silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof). Semiconductor layers 156 and 158 may have different compositions and / or different sizes / configurations, and different compositions may be achieved using different semiconductor materials, different dopants, different atomic percentages of components, different dopant concentrations, or combinations thereof. For example, semiconductor layer 158 may be a heavily doped semiconductor layer, and semiconductor layer 156 may be a lightly doped semiconductor layer, wherein the dopant concentration of the heavily doped semiconductor layer is greater than that of the lightly doped semiconductor layer. In some embodiments, semiconductor layers 156 and 158 may comprise silicon doped with different concentrations of carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof. In another example, semiconductor layer 156 and semiconductor layer 158 may comprise silicon germanium doped with varying concentrations of boron, gallium, other p-type dopants, or combinations thereof. In some embodiments, semiconductor layer 156 and semiconductor layer 158 include materials and / or dopants that provide desired tensile and / or compressive stresses in the channel region.

[0045] Device 100 may further include a dielectric layer 170, which may include a contact etch stop layer (CESL) 172 and an interlayer dielectric (ILD) layer 174. CESL 172 is disposed over a gate structure 130 (e.g., its gate spacer 138), a source / drain structure 150, an isolation structure 110, and a substrate 105 (e.g., its protrusion 105'). The composition of CESL 172 differs from that of ILD layer 174 to enable etch selectivity between them. In some embodiments, CESL 172 includes a silicon-containing dielectric material. For example, CESL 172 includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof) or combinations thereof. In some embodiments, CESL 172 includes a metal-containing dielectric material. For example, CESL 172 comprises a metal and oxygen, nitrogen, carbon, or combinations thereof, such as metal oxides (e.g., aluminum oxide) and / or metal nitrides (e.g., aluminum nitride). The metal may be aluminum, hafnium, titanium, copper, manganese, vanadium, other suitable metals, or combinations thereof. In some embodiments, CESL 172 has a multilayer structure.

[0046] ILD layer 174 may comprise a silicon- and oxygen-containing dielectric material. For example, ILD layer 174 is a silicon oxide layer. In some embodiments, the silicon- and oxygen-containing dielectric material is a low-k dielectric material, which generally refers to a dielectric material having a dielectric constant less than that of silicon dioxide (k≈3.9). For example, ILD layer 174 may be a porous silicon oxide layer, which may have a dielectric constant less than about 2.5 (k≈2.5). In another example, ILD layer 174 may be a carbon-doped silicon oxide layer (e.g., a SiOC layer), which may have a dielectric constant less than about 2.5 (k≈2.5). In some embodiments, ILD layer 174 is a doped silicon oxide layer, such as a carbon-doped silicon oxide layer, a phosphorus-doped silicon oxide layer (e.g., PSG), a boron-doped silicon oxide layer (e.g., BSG), a boron and phosphorus-doped silicon oxide layer (e.g., BPSG), a fluorine-doped silicon oxide layer (e.g., FSG), other suitable doped silicon oxide layers, or combinations thereof. In some embodiments, ILD layer 174 is an oxide layer formed of tetraethyl orthosilicate (TEOS). In some embodiments, ILD layer 174 is a dielectric layer based on benzocyclobutene (BCB). In some embodiments, ILD layer 174 has a multilayer structure.

[0047] Device 100 may further include source / drain contacts 180. Source / drain contacts 180 are disposed on and coupled to source / drain structure 150 (e.g., its semiconductor layer 158), and extend through dielectric layer 170. In the depicted embodiment, source / drain contacts 180 extend into source / drain structure 150. Source / drain contacts 180 comprise conductive materials such as tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, source / drain contacts 180 are unobstructed / padded metal plugs, such as tungsten plugs, cobalt plugs, or ruthenium plugs. For example, each of the source / drain contacts 180 may include a bulk metal layer, such as a tungsten plug, adjacent to surrounding dielectric material (such as ILD layer 174 and / or CESL 172). In some embodiments, the source / drain contact 180 includes a bulk metal layer and a metal pad, wherein the metal pad is located between the bulk metal layer and the surrounding dielectric material (e.g., ILD layer 174 and / or CESL 172). In some embodiments, the metal pad is located between the bulk metal layer and the source / drain structure 150 (e.g., its semiconductor layer 185) and / or silicide layer 185. In some embodiments, the metal pad includes tantalum, tantalum nitride, aluminum tantalum nitride, silicon tantalum nitride, tantalum carbide, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof. In some embodiments, the source / drain contact 180 includes an insulating layer (e.g., a contact spacer), such as a dielectric layer and / or an air gap, located between the sidewalls of its conductive portion (e.g., its metal plug and / or metal pad) and the surrounding dielectric material (e.g., dielectric layer 170).

[0048] A silicide layer 185 may be disposed between the source / drain contact 180 and the source / drain structure 150 (e.g., its semiconductor layer 158). The silicide layer 185 may include metallic and semiconductor components. The metallic component may be nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The semiconductor component may be the component of the source / drain structure 150, such as silicon, germanium, other semiconductors, or combinations thereof. In some embodiments, the silicide layer 185 comprises titanium and silicon, and the silicide layer may be referred to as a titanium silicide layer. In some embodiments, the conductivity of the silicide layer 185 is greater than the conductivity of the semiconductor layer 158 and less than the conductivity of the source / drain contact 180.

[0049] This disclosure proposes segmenting and / or cutting the channel of device 100 (e.g., semiconductor layer 120) before and / or during the formation of the gate of device 100 (e.g., gate stack 132). Figures 5A to 5Q The device 100 according to various aspects of embodiments of this disclosure is manufactured along various stages of a manufacturing process (which may implement channel segmentation before forming its gate (e.g., gate stack 132)). Figure 1A A schematic cross-sectional view of part or all of line EE. Figures 6A to 6Q respectively with Figures 5A to 5Q Corresponding to each manufacturing stage, and Figures 6A to 6Q Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic cross-sectional view of part or all of line DD. Figures 9A to 9F Devices (such as device 100) according to various aspects of embodiments of this disclosure are manufactured in processes (such as...) Figures 5A to 5Q and Figures 6A to 6Q A schematic cross-sectional view of part or all of the channel cutting stage of the manufacturing process. Figures 10A to 10D Devices (such as device 100) according to various aspects of embodiments of this disclosure are manufactured in processes (such as...) Figures 5A to 5Q and Figures 6A to 6Q A schematic top view of part or all of the device isolation stage of the manufacturing process. For ease of description and understanding, this document also discusses... Figures 5A to 5Q , Figures 6A to 6Q , Figures 9A to 9F and Figures 10A to 10D For clarity, it has been simplified. Figures 5A to 5Q , Figures 6A to 6Q , Figures 9A to 9F and Figures 10A to 10D To better understand the inventive concept of embodiments of this disclosure. Additional components may be added to device 100 and / or its manufacturing process, and in other embodiments of device 100 and / or its manufacturing process, some of the components described below may be replaced, modified, or eliminated.

[0050] refer to Figure 5A and Figure 6A Device 100 may be in an intermediate stage of processing. For example, device 100 includes a substrate 105, an isolation structure 110, a multilayer stack 210 (including, for example, protrusions 105', a sacrificial layer 215, and a semiconductor layer 220), a gate structure 130, an internal spacer 140, a source / drain structure 150, and a dielectric layer 170 (e.g., CESL 172 and ILD layer 174). In an intermediate stage of manufacturing, gate structure 130 may include a dummy gate stack 232 and a gate spacer 138. Dummy gate stack 232 may include a dummy gate dielectric 234, a dummy gate block 236, and a hard mask.

[0051] Along the longitudinal direction of the active region ( Figure 5A A multilayer stack 210 is disposed between source / drain structures 150, an internal spacer 140 is disposed between sacrificial layer 215 and source / drain structures 150, and sacrificial layer 220 extends from the first source / drain structure 150 to the second source / drain structure 150. Sacrificial layer 215 and semiconductor layer 220 are vertically stacked from the top of substrate 105 in an alternating and / or staggered configuration (e.g., along the z-direction). The composition of sacrificial layer 215 differs from that of semiconductor layer 220 to achieve etch selectivity (i.e., providing different etch rates to a given etchant). For example, sacrificial layer 215 and semiconductor layer 220 comprise different materials, atomic percentages of components, weight percentages of components, other properties, or combinations thereof to achieve etch selectivity. In some embodiments, sacrificial layer 215 comprises silicon germanium, and semiconductor layer 220 comprises silicon. In some embodiments, sacrificial layer 215 and semiconductor layer 220 comprise the same material but with different atomic percentages of components, such as silicon germanium with different percentages of germanium atoms and / or silicon atoms. In some embodiments, such as the depicted embodiment, the sacrificial layer 215 is a dielectric layer (e.g., an oxide layer), and the semiconductor layer 220 is a silicon layer or a silicon-germanium layer. The sacrificial layer 215 and the semiconductor layer 220 may include any combination of materials that provide desired etch selectivity, desired oxidation rate differences, desired performance characteristics, or combinations thereof (e.g., materials that maximize current), including any of the materials disclosed herein.

[0052] In the depicted embodiment, the multilayer stack 210 includes three sacrificial layers 215 (e.g., a lower sacrificial layer 215L, a middle sacrificial layer 215M, and a top sacrificial layer 215U) and three semiconductor layers 220 (e.g., a lower semiconductor layer 220L, a middle semiconductor layer 220M, and a top semiconductor layer 220U). Therefore, the multilayer stack 210 includes three sacrificial / semiconductor layer pairs above the substrate 105, each of the sacrificial / semiconductor layer pairs having a corresponding sacrificial layer 215 and a corresponding semiconductor layer 220. After processing the multilayer stack 210, this configuration can provide a transistor T with three channels. In some embodiments, the multilayer stack 210 includes more or fewer semiconductor layers 220, depending on, for example, the desired number of channels for the transistor T. For example, the multilayer stack 210 may include two to six sacrificial / semiconductor layer pairs, each of which may include a corresponding sacrificial layer 215 and a corresponding semiconductor layer 220.

[0053] The sacrificial layer 215 has a thickness t1, and the semiconductor layer 220 has a thickness t2, which may be greater than, less than, or the same as the thickness t1. In some embodiments, the sacrificial layer 215 and the semiconductor layer 220 have the same width along the gate longitudinal direction and / or the active region lateral direction, such as width W (see example...). Figure 6A Furthermore, the length of the sacrificial layer 215 along the longitudinal direction of the active region can be less than the length of the semiconductor layer 220 (see example). Figure 5A Thickness t1, thickness t2, width W, and length can be selected based on manufacturing and / or device performance considerations. In some embodiments, thickness t2 is configured to provide the desired thickness and / or desired height of the channel of transistor T (i.e., thickness t2 corresponds to the height H of the channel of transistor T), and thickness t1 is configured to provide the desired spacing / distance between adjacent channels of transistor T (e.g., between semiconductor layers 220).

[0054] Along the longitudinal direction of the active region ( Figure 5A The dummy gate stack 232 is disposed on top of the multilayer stack 210 and between the source / drain structure 150. Along the gate longitudinal direction ( Figure 6A The dummy gate stack 232 extends along the y-direction, having a length along the y-direction, a width along the x-direction, and a height along the z-direction. The dummy gate stack 232 may enclose the multilayer stack 210 (e.g., disposed above its top and sidewalls), and the dummy gate stack 232 may be disposed above the top of the isolation structure 110. The dummy gate dielectric 234 comprises a dielectric material, such as silicon oxide and / or other suitable dielectric materials. Where the sacrificial layer 215 is formed of a dielectric material, as in the depicted embodiment, the dummy gate dielectric 234 may be formed of the same or different dielectric materials. For example, the dummy gate dielectric 234 and the sacrificial layer 215 may be silicon oxide layers having the same composition or different compositions. The dummy gate block 236 comprises a suitable occupant / sacrificial material, such as polysilicon. In some embodiments, the dummy gate stack 232 may also include a hard mask that can be configured to protect the dummy gate dielectric 234 and / or the dummy gate block 236 during processing. For example, a hard mask may include materials resistant to etching processes, such as etching associated with forming source / drain recesses and / or etching associated with forming source / drain contact openings, to protect the dummy gate dielectric 234 and / or dummy gate block 236 from the etching process. In some embodiments, the hard mask has a multilayer structure.

[0055] refer to Figures 5B to 5J and Figures 6B to 6JPrior to the gate replacement process (e.g., before removing and replacing the dummy gate stack 232 with gate stack 132) and / or prior to the channel release process (e.g., selectively removing sacrificial layer 215 to suspend semiconductor layer 220 over substrate 105), semiconductor layer 220 is segmented and / or cut through semiconductor layer 220. Reference Figure 5B , Figure 6B , Figure 5C and Figure 6C Segments of semiconductor layer 220 may include a patterned hard mask 242 formed over device 100 (e.g., on dielectric layer 170 and gate structure 130, both of which form the top of device 100 during this fabrication stage). The patterned hard mask 242 includes openings, such as opening 243, disposed on and overlapping multilayer stack 210. In the depicted embodiment, opening 243 exposes a portion of dummy gate stack 232 covering multilayer stack 210. The width of opening 243 is greater than the width of dummy gate stack 232 (and / or gate stack 132). For example, dummy gate stack 232 has a critical dimension CD1, opening 243 has a critical dimension CD2, and the critical dimension CD2 is greater than the critical dimension CD1. In some embodiments, the critical dimension CD2 is approximately 2 nm to approximately 10 nm greater than the critical dimension CD1. The critical dimension CD1 is related to the “gate length” (L) of transistor T along the longitudinal direction of the active region (e.g., along the x-direction). g The critical dimension CD1 corresponds to the distance (or length) that current can travel between the source / drain structures 150, and the critical dimension CD2 corresponds to the width of the channel cut along the longitudinal direction of the active region (e.g., along the x-direction). In some embodiments, the critical dimension CD1 is less than about 12 nm (e.g., CD1 ≤ 12 nm). In some embodiments, as depicted, the opening 243 has tapered sidewalls such that the critical dimension CD2 decreases (or increases) from the top to the bottom of the opening 243. In some embodiments, the critical dimension CD2 is greater than the critical dimension CD1 (e.g., about 2 nm to about 10 nm) at least at the top of the opening 243.

[0056] Patterned hard mask 242 can be achieved by depositing mask layer 242' over device 100. Figure 5B and Figure 6B ) and patterned mask layer 242' ( Figure 5C and Figure 6CThe mask layer 242' is formed by including one or more openings (such as opening 243). Patterning may include etching the mask layer 242' using a patterned resist layer as an etch mask. The patterned resist layer may be formed by a photolithography process, which may include resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, resist development, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. The mask layer 242' and thus the patterned hard mask 242 include materials that are negligible (or minimally etched / removed) during selective etching / removal of the sacrificial layer 215, semiconductor layer 220, and dummy gate stack 232 exposed by opening 243. In some embodiments, the mask layer 242' is a silicon nitride layer, and the patterned hard mask 242 is a silicon nitride mask. In some embodiments, the mask layer 242' and / or the patterned hard mask 242 include silicon and nitrogen, carbon, oxygen, or combinations thereof. In some embodiments, the mask layer 242' and / or the patterned hard mask 242 comprises metal and nitrogen, carbon, oxygen, or combinations thereof. In some embodiments, the mask layer 242' and / or the patterned hard mask 242 has a multilayer structure.

[0057] refer to Figures 5D to 5J and Figures 6D to 6JThe segmentation of semiconductor layer 220 may include forming at least one channel cutout 245 in the multilayer stack 210 extending through at least one of the semiconductor layers 220. In some embodiments, as depicted, the channel cutout 245 partially extends through the multilayer stack 210. For example, the channel cutout 245 extends through dummy gate stack 232 (e.g., dummy gate block 236 and dummy gate dielectric 234), semiconductor layer 220U, sacrificial layer 215U, semiconductor layer 220M, sacrificial layer 215M, and semiconductor layer 220L. Thus, the channel cutout 245 extends through all semiconductor layers 220, but stops at and exposes the sacrificial layer 215L (i.e., the bottommost sacrificial layer 215). In some embodiments, as depicted, the channel cutout 245 has tapered sidewalls such that the width of the channel cutout 245 decreases from its top to its bottom. In such embodiments, as further described herein, the spacing SA (e.g., along the x-direction) and spacing SB (e.g., along the y-direction) between segments of the multilayer stack 210 can decrease from its top to its bottom. For example, along the gate lateral direction, the spacing SA1 between segments of semiconductor layer 220U is greater than the spacing SA2 between segments of semiconductor layer 220M, and the spacing SA2 between segments of semiconductor layer 220M is greater than the spacing SA3 between segments of semiconductor layer 220L. Furthermore, along the gate longitudinal direction, the spacing SB1 between segments of semiconductor layer 220U is greater than the spacing SB2 between segments of semiconductor layer 220M, and the spacing SB2 between segments of semiconductor layer 220M is greater than the spacing SB3 between segments of semiconductor layer 220L. The spacing between segments of the sacrificial layer 215 can similarly decrease from the top to the bottom of the multilayer stack 210. In some embodiments, the width of the channel notch 245 can increase from its top to its bottom, rather than decrease, thereby allowing the spacing SA and / or spacing SB to increase from the top to the bottom of the multilayer stack 210. In some embodiments, the channel cutout 245 has substantially straight sidewalls (e.g., extending in the z-direction), and the width of the channel cutout 245 is substantially uniform from its top to its bottom, such that the spacing SA and / or the spacing SB are substantially the same from the top to the bottom of the multilayer stack 210.

[0058] The etching process can use a patterned hard mask 242 to form the channel notch 245, and the patterned hard mask 242 can protect the dielectric layer 170 (e.g., its ILD layer 174 and / or CESL 172) and the gate spacer 138 during the etching process. The etching process may include and / or may be dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a multi-step etching. For example, the etching process may alternate etchants and / or adjust other etching parameters (e.g., etching time, etching temperature, etching pressure, etchant flow rate, etc.) to remove the dummy gate block 236 individually and alternately. Figure 5D and Figure 6D ), pseudo-gate dielectric 234 ( Figure 5E and Figure 6E ), Semiconductor layer 220U ( Figure 5F and Figure 6F ), Sacrificial layer 215U ( Figure 5G and Figure 6G ), Semiconductor layer 220M ( Figure 5H and Figure 6H ), Sacrificial layer 215M ( Figure 5I and Figure 6I ) and semiconductor layer 220L ( Figure 5J and Figure 6J In some embodiments, the etching process includes: selectively removing the dummy gate block 236 relative to the dummy gate dielectric 234. Figure 5D and Figure 6D (e.g., the first etching step); selectively remove the dummy gate dielectric 234 relative to the dummy gate block 236 and the semiconductor layer 220U. Figure 5E and Figure 6E (For example, the second etching step); selectively remove semiconductor layer 220U relative to dummy gate block 236, dummy gate dielectric 234 and sacrificial layer 215U. Figure 5F and Figure 6F (e.g., the third etching step); selective removal of the sacrificial layer 215U relative to the dummy gate block 236, semiconductor layer 220U, and semiconductor layer 220M. Figure 5G and Figure 6G (For example, the fourth etching step); selectively remove semiconductor layer 220M relative to dummy gate block 236, dummy gate dielectric 234, sacrificial layer 215U, and sacrificial layer 215M. Figure 5H and Figure 6H (For example, the fifth etching step); selectively remove the sacrificial layer 215M relative to the dummy gate block 236, semiconductor layer 220U, semiconductor layer 220M and semiconductor layer 220L. Figure 5I and Figure 6I (e.g., the sixth etching step); and selective removal of semiconductor layer 220L relative to dummy gate block 236, dummy gate dielectric 234, sacrificial layer 215U, sacrificial layer 215M and sacrificial layer 215L. Figure 5J and Figure 6J(e.g., the seventh etching step). In some embodiments, the dummy gate block 236 is formed of polysilicon (Poly), the dummy gate dielectric 234 and the sacrificial layer 215 are formed of oxide (Ox) (having the same composition or different compositions), the semiconductor layer 220 is formed of silicon (Si), and the etching process can be Poly / Ox / Si / Ox / Si / Ox / Si etching. The etching process can use different etchants to remove polysilicon, oxide, and silicon separately. For example, the etching process can implement a first etchant to selectively remove polysilicon without (or negligibly) removing oxide and silicon, implement a second etchant to selectively remove oxide without (or negligibly) removing polysilicon and silicon, and implement a third etchant to selectively remove silicon without (or negligibly) removing polysilicon and oxide. In some embodiments, multiple etching steps of the etching process are performed in the same process chamber. For example, when the etching process is Poly / Ox / Si / Ox / Si / Ox / Si etching, device 100 can be exposed to the first etchant, the second etchant, and the third etchant in the same process chamber. In some embodiments, a cleanup process may be performed after each etching step to remove the given etchant and any byproducts from the corresponding etching step before performing the next etching step in the same process chamber. In some embodiments, the etching process is anisotropic dry etching.

[0059] In the depicted embodiments, the etching process forms the channel notch 245 without (or negligibly) etching / removing the patterned hard mask 242. In some embodiments, the etching process may slowly remove the patterned hard mask 242 during etching / removing one or more of the dummy gate block 236, dummy gate dielectric 234, semiconductor layer 220, sacrificial layer 215, or combinations thereof. In such embodiments, the etching process may reduce the thickness of the patterned hard mask 242. In other words, the thickness of the patterned hard mask 242 after the etching process may be less than the initial thickness of the patterned hard mask 242.

[0060] Following the channel notch 245, the semiconductor layer 220 has an annular profile instead of a sheet-like profile. For example, see reference... Figure 5F and Figure 6FThe semiconductor layer 220U has an opening 245U (also referred to as a via) formed by a channel cutout 245, and the channel cutout 245 provides a semiconductor layer 220U having a semiconductor segment 220U-1 extending longitudinally along the active region longitudinal direction (e.g., the x-direction), a semiconductor segment 220U-2 extending longitudinally along the active region longitudinal direction (e.g., the x-direction), and a semiconductor segment 220U-3 extending longitudinally from semiconductor segment 220U-1 to semiconductor segment 220U-2 along the gate longitudinal direction (e.g., the y-direction). Semiconductor segments 220U-3 are separated by a spacer SA1 (e.g., along the x-direction), and semiconductor segments 220U-3 connect and / or splice semiconductor segments 220U-1 and 220U-2 together. Semiconductor segments 220U-1 and 220U-2 are separated by a spacer SB1 (e.g., along the y-direction). In some embodiments, because the channel cutout 245 may have tapered sidewalls, the spacing SA1 and / or spacing SB1 may decrease (or increase) from the top to the bottom of the semiconductor layer 220U. Semiconductor segments 220U-1 and 220U-2 extend between the source / drain structures 150, and semiconductor segments 220U-1 and 220U-2 may provide the channel for the transistor T as described herein.

[0061] The semiconductor segments 220U-1 and 220U-2 have widths that are less than the width of the semiconductor layer 220U before the channel cut 245. For example, the semiconductor segment 220U-1 has a width WU1 (e.g., along the y direction), the semiconductor segment 220U-2 has a width WU2 (e.g., along the y direction), and the semiconductor segment 220U-3 has a width WU3 (e.g., along the y direction). The widths WU1, WU2, and WU3 are less than the width W, and the sum of the widths WU1, WU2, and WU3 is equal to the width W (i.e., the width of the semiconductor layer 220U having a sheet-like profile). Because the widths WU1 and WU2 are less than the width W, the width / height ratios of the semiconductor segments 220U-1 and 220U-2 are less than the width / height ratio of the semiconductor layer 220U before the channel cut 245. For example, the ratio of the width WU1 to the height H (i.e., WU1 / H) is less than the ratio of the width W to the height H (i.e., W / H), and the ratio of the width WU2 to the height H (i.e., WU2 / H) is less than W / H. In some embodiments, W / H is greater than or equal to 2 (i.e., W / H > 2), WU1 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WU1 / H < 2), and WU2 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WU2 / H < 2). In some embodiments, as depicted, the widths WU1 and WU2 are approximately the same. In some embodiments, the width WU1 is less than or greater than the width WU2. In some embodiments, because the channel cut 245 can have tapered sidewalls, the width WU1 and / or the width WU2 can increase (or decrease) from the top to the bottom of the semiconductor layer 220U along the height H.

[0062] Due to their reduced widths and / or reduced width / height ratios, the semiconductor segments 220U-1 and 220U-2 can have a cylindrical profile or a rectangular profile, and the semiconductor segments 220U-1 and 220U-2 can be nanowires or nanorods of the transistor T, respectively. Thus, the channel cut 245 modifies the nanosheet (e.g., the semiconductor layer 220U having a sheet-like profile) into nanowires and / or nanorods (e.g., the semiconductor segments 220U-1 and 220U-2) that are spliced together (e.g., via the semiconductor segment 220U-3). As further described below, such a configuration improves gate control and / or reduces SCE. Embodiments of the present disclosure contemplate that the semiconductor segments 220U-1 and 220U-2 have any other suitable shaped profiles. Additionally, in some embodiments, the semiconductor layers 220 (and their respective segments) have nanoscale dimensions and can be referred to as "nanostructures". In some embodiments, the semiconductor layers 220 (and their respective segments) have sub-nanoscale dimensions and / or super-nanoscale dimensions. <o

[0063] The semiconductor layer 220M may also have an annular profile. For example, referring to Figure 5H and Figure 6H , an opening 245M formed by the channel notch 245 is provided in the semiconductor layer 220M, and the channel notch 245 provides a semiconductor layer 220M having semiconductor segments 220M-1, semiconductor segments 220M-2, and a semiconductor segment 220M-3 extending from the semiconductor segment 220M-1 to the semiconductor segment 220M-2. The semiconductor segment 220M-3 is separated by a spacer SA2, and the semiconductor segment 220M-3 connects and / or splices the semiconductor segment 220M-1 and the semiconductor segment 220M-2 together. In some embodiments, since the channel notch 245 may have a tapered sidewall, the spacer SA2 and / or the spacer SB2 may decrease (or increase) from the top to the bottom of the semiconductor layer 220M. The semiconductor segment 220M-1 and the semiconductor segment 220M-2 are separated by a spacer SB2. The semiconductor segments 220M-1 and the semiconductor segments 220M-2 extend between the source / drain structures 150, and the semiconductor segments 220M-1 and the semiconductor segments 220M-2 may provide the channel of the transistor T.

[0064] The semiconductor segments 220M-1 and the semiconductor segments 220M-2 have a width smaller than the width of the semiconductor layer 220M before the channel notch 245. For example, the semiconductor segment 220M-1 has a width WM1 (e.g., along the y direction), the semiconductor segment 220M-2 has a width WM2 (e.g., along the y direction), and the semiconductor segment 220M-3 has a width WM3 (e.g., along the y direction). The width WM1, the width WM2, and the width WM3 are smaller than the width W, and the sum of the width WM1, the width WM2, and the width WM3 is equal to the width W (i.e., the width of the semiconductor layer 220M having a sheet-like profile). Since the width WM1 and the width WM2 are smaller than the width W, the width / height ratio of the semiconductor segments 220M-1 and the semiconductor segments 220M-2 is smaller than the width / height ratio of the semiconductor layer 220M before the channel notch 245. For example, the ratio of the width WM1 to the height H (i.e., WM1 / H) is smaller than W / H, and the ratio of the width WM2 to the height H (i.e., WM2 / H) is smaller than W / H. In some embodiments, W / H is greater than or equal to 2, WM1 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WM1 / H < 2), and WM2 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WM2 / H < 2). In some embodiments, the width WM1 and the width WM2 are approximately the same. In some embodiments, the width WM1 is smaller than or larger than the width WM2. In some embodiments, since the channel notch 245 may have a tapered sidewall, the width WM1 and / or the width WM2 may increase (or decrease) from the top to the bottom of the semiconductor layer 220M.

[0065] The semiconductor layer 220L may also have an annular profile. For example, referring to Figure 5J and Figure 6J , an opening 245L formed by the channel cut 245 is provided in the semiconductor layer 220L, and the channel cut 245 provides a semiconductor layer 220L having semiconductor segments 220L-1, semiconductor segments 220L-2, and a semiconductor segment 220L-3 extending from the semiconductor segment 220L-1 to the semiconductor segment 220L-2. The semiconductor segment 220L-3 is separated by a spacer SA3, and the semiconductor segment 220L-3 connects and / or splices the semiconductor segment 220L-1 and the semiconductor segment 220L-2 together. The semiconductor segment 220L-1 and the semiconductor segment 220L-2 are separated by a spacer SB3. In some embodiments, since the channel cut 245 may have tapered sidewalls, the spacer SA3 and / or the spacer SB3 may decrease (or increase) from the top to the bottom of the semiconductor layer 220L. The semiconductor segments 220L-1 and the semiconductor segments 220L-2 extend between the source / drain structures 150, and the semiconductor segments 220L-1 and the semiconductor segments 220L-2 may provide the channel of the transistor T.

[0066] The semiconductor segments 220L-1 and the semiconductor segments 220L-2 have a width smaller than the width of the semiconductor layer 220L before the channel cut 245. For example, the semiconductor segment 220L-1 has a width WL1 (e.g., along the y direction), the semiconductor segment 220L-2 has a width WL2 (e.g., along the y direction), and the semiconductor segment 220L-3 has a width WL3 (e.g., along the y direction). The width WL1, the width WL2, and the width WL3 are smaller than the width W, and the sum of the width WL1, the width WL2, and the width WL3 is equal to the width W (i.e., the width of the semiconductor layer 220L having a sheet-like profile). Since the width WL1 and the width WL2 are smaller than the width W, the width / height ratio of the semiconductor segments 220L-1 and the semiconductor segments 220L-2 is smaller than the width / height ratio of the semiconductor layer 220L before the channel cut 245. For example, the ratio of the width WL1 to the height H (i.e., WL1 / H) is smaller than W / H, and the ratio of the width WL2 to the height H (i.e., WL2 / H) is smaller than W / H. In some embodiments, W / H is greater than or equal to 2, WL1 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WL1 / H < 2), and WL2 / H is less than about 2 and greater than about 0.5 (i.e., 0.5 < WL2 / H < 2). In some embodiments, the width WL1 and the width WL2 are approximately the same. In some embodiments, the width WL1 is smaller than or larger than the width WL2. In some embodiments, since the channel cut 245 may have tapered sidewalls, the width WL1 and / or the width WL2 may increase (or decrease) from the top to the bottom of the semiconductor layer 220L.

[0067] Due to their reduced width and / or reduced width / height ratio, semiconductor segments 220M-1, 220M-2, 220L-1, and 220L-2 can have cylindrical or rectangular profiles, and can be nanowires or nanorods of transistor T, respectively. Therefore, the channel notch 245 modifies nanosheets (e.g., semiconductor layers 220M and 220L with sheet-like profiles) into nanowires and / or nanorods (e.g., semiconductor segments 220M-1, 220M-2, 220L-1, and 220L-2) spliced ​​together (e.g., via semiconductor segments 220M-3 or 220L-3). As further described below, such a configuration improves gate control and / or reduces SCE. This disclosure considers semiconductor segments having any other suitable shape profile.

[0068] refer to Figures 9A to 9E This disclosure describes embodiments that consider adjusting and / or configuring etching processes to provide channel cutouts through the multilayer stack 210 with various configurations and / or profiles. In some embodiments, such as Figure 9A As depicted, a channel cutout 245A with substantially straight sidewalls (e.g., extending along the z-direction) rather than tapered sidewalls can be formed in the dummy gate stack 232 and the multilayer stack 210. In such an embodiment, the width of the channel cutout 245A is substantially uniform from its top to its bottom, such that the spacing SA and the spacing SB are substantially the same from the top to the bottom of the multilayer stack 210. For example, the spacing SB1 may be approximately the spacing SB2, and the spacing SB2 may be approximately the spacing SB3 (i.e., SB1≈SB2≈SB3). Furthermore, in such an embodiment, the widths WU1, WU2, WM1, WM2, WL1, WL2, or combinations thereof may be substantially the same along their height H.

[0069] In some embodiments, such as Figures 9B to 9D As depicted, the channel cut can extend to the bottommost sacrificial layer 215. For example, in Figure 9B In this configuration, the channel cut 245B can partially extend into the sacrificial layer 215L, thereby retaining a portion of the sacrificial layer 215L between the bottom of the channel cut 245B and the protrusion 105'. In another example, in Figure 9C and Figure 9D In this configuration, the channel cutouts 245C and 245D can extend completely through the sacrificial layer 215L, thereby exposing the protrusion 105'. In some embodiments, such as Figure 9E and Figure 9F As depicted, the channel cuts can extend into the protrusion 105' and / or the substrate 105. For example, channel cuts 245E and 245F can extend completely through the sacrificial layer 215L and extend to a distance d in the protrusion 105' and / or the substrate 105, thereby exposing the protrusion 105'. In some embodiments, the distance d is less than about 20 nm (e.g., 0 nm ≤ d ≤ 20 nm).

[0070] In some embodiments, the channel cutout may be configured to have a substantially flat bottom, such as channel cutout 245A (e.g., having a bottom formed by sacrificial layer 215L), channel cutout 245B (e.g., having a bottom formed by sacrificial layer 215L), and channel cutout 245C (e.g., having a bottom formed by protrusion 105'). In some embodiments, the channel cutout may be configured to have a rounded bottom, which may or may not have a defined tip, such as channel cutout 245D (e.g., having a bottom formed by sacrificial layer 215L and protrusion 105'). In some embodiments, the channel cutout may be configured to have a trapezoidal bottom (e.g., channel cutout 245E (e.g., having a bottom formed by protrusion 105')), a pentagonal bottom (e.g., channel cutout 245F (e.g., having a bottom formed by protrusion 105')), or other suitable bottom shapes. It should be noted that, although Figures 9A to 9F The embodiments depict a channel cut with straight sidewalls, but embodiments of this disclosure contemplate... Figures 9A to 9F One embodiment of the channel cut has a tapered sidewall, such as channel cut 245.

[0071] refer to Figure 5K , Figure 6K , Figure 5L and Figure 6L Fabrication of device 100 may include forming a sacrificial plug 250 in a channel notch 245. The sacrificial plug 250 is disposed in a dummy gate stack 232 and a multilayer stack 210, and extends through a semiconductor layer 220. Forming the sacrificial plug 250 may include depositing a sacrificial material 250' filling the channel notch 245 over device 100. Figure 5K and Figure 6K ); and to perform a planarization process (e.g., chemical mechanical polishing (CMP)) to remove the sacrificial material 250' formed over the dielectric layer 170 and / or the gate spacer 138. Figure 5L and Figure 6LThis includes unfilled portions of the channel cutout 245, such as sacrificial material 250'. The contour of the sacrificial plug 250 corresponds to the contour of the channel cutout 245 (e.g., the sacrificial plug 250 may have tapered sidewalls). In some embodiments, as depicted, the patterned hard mask 242 may be retained after the channel cutout 245 is formed, the sacrificial material 250' may be formed over the patterned hard mask 242, the sacrificial material 250' may fill the opening 243 in the patterned hard mask 242, and a planarization process may remove the sacrificial material 250' disposed over the patterned hard mask 242 (i.e., the patterned hard mask 242 may be used as a planarization stop layer, such as a CMP stop). In such embodiments, the sacrificial plug 250 is also disposed within the patterned hard mask 242. The composition of the sacrificial material 250' (and therefore the sacrificial plug 250) differs from the composition of the patterned hard mask 242 and the dummy gate block 236 to achieve etch selectivity. For example, the sacrificial material 250' and sacrificial plug 250 may be formed of a dielectric material capable of etching / removing the patterned hard mask 242 (e.g., a silicon nitride mask) and / or the dummy gate block 236 (e.g., polysilicon) without (or negligibly) etching / removing the sacrificial material 250' / sacrificial plug 250, or vice versa. The dielectric material may also enable the removal of the sacrificial plug 250 without (or negligibly) removing the semiconductor layer 220. In some embodiments, the sacrificial material 250' is an oxide material, and the sacrificial plug 250 is an oxide plug (e.g., a silicon oxide plug or a metal oxide plug). In some embodiments, the sacrificial plug 250 is formed of the same material as the sacrificial layer 215 and / or the dummy gate dielectric 234. In some embodiments, the sacrificial plug 250 is formed of a different material than the sacrificial layer 215 and / or the dummy gate dielectric 234. In some embodiments, the sacrificial material 250' and / or the sacrificial plug 250 have a multilayer structure.

[0072] In some embodiments, reference Figure 5M , Figure 6M and Figures 10A to 10D It can be done after the channel incision (e.g., Figures 5B to 5L and Figures 6B to 6L And before replacing the dummy gate stack 232 with the gate stack 132 (e.g., Figures 50 to 5Q and Figures 60 to 6Q This involves implementing a continuous polysilicon patterning process on the diffusion edge (CPODE). Such an embodiment can be referred to as a CPODE-first process. (See reference...) Figure 10AThe gate structure 130 may be one of a plurality of gate structures 130 disposed above and across the active region 160, the gate structure 130 being an active gate structure, and the device 100 may further include a dummy gate structure 230 disposed above and across the active region 160. In the depicted embodiments, the dummy gate structure 230 is disposed along and / or at the edge of the active region 160, and the gate structure 130 is disposed between the dummy gate structures 230. "Active gate structure," "active gate stack," and "active gate" generally refer to electrically functional gate structures (and / or gate stacks), while "dummy gate structure" generally refers to electrically non-functional gate structures (and / or gate stacks). The dummy gate structure may mimic the physical characteristics of an active gate structure, such as the physical dimensions and / or layers of the active gate structure, but is electrically inoperable (i.e., applying a voltage to the dummy gate structure does not allow current to flow through the channel and / or between the source / drain). Figure 10A The manufacturing stages described in the text (and its relationship with) Figure 5L and Figure 6L (corresponding to the manufacturing stage), both the active gate structure 130 and the pseudo gate structure 230 include a pseudo gate stack 232.

[0073] As part of the CPODE process, the dummy gate stack 232 of the dummy gate structure 230 is replaced with an isolation structure (e.g., a dielectric material). In some embodiments, reference is made to... Figure 10B , Figure 5M and Figure 6M Before removing the dummy gate stack 232 from the dummy gate structure 230, the portion of the sacrificial plug 250 disposed in the patterned hard mask 242 can be replaced with a hard mask plug 252. In some embodiments, the hard mask plug 252 is formed by: removing the sacrificial plug 250 from the patterned hard mask 242 (e.g., by etching back the sacrificial plug 250 (e.g., oxide material)), thereby reopening the opening 243 in the patterned hard mask 242; and depositing a hard mask material to fill the opening 243 of the patterned hard mask 242. The hard mask material (and therefore the hard mask plug 252) can be formed of the same material as the patterned hard mask 242 (having the same composition or a different composition) or a different material. For example, the hard mask plug 252 can be a nitride plug, such as a silicon nitride plug. In some embodiments, planarization and / or etch-back processes may be applied to the hard mask material to reduce its thickness, such that the thickness of the hard mask plug 252 is substantially the same as the thickness of the patterned hard mask 242.

[0074] refer to Figure 10CThe CPODE process may include forming a trench 253 that extends through a portion of the dummy gate structure 230 and into the substrate 105. The trench 253 may be formed by removing the dummy gate stack 232 from the gate structure 230 (e.g., dummy gate block 236 and its dummy gate dielectric), the underlying multilayer stack 210, and the protrusion 105' and / or the underlying portion of the substrate 105. (See reference...) Figure 10D The CPODE process may include filling trench 253 with an isolation structure 254, such as a dielectric structure. In some embodiments, the isolation structure 254 may be formed from a single dielectric layer. In some embodiments, the isolation structure 254 may be formed from multiple dielectric layers. The isolation structure 254 may be formed by depositing one or more dielectric materials filling the trench 253 over the device 100 (e.g., over a patterned hard mask 242) and performing a planarization process. In some embodiments, the planarization process removes one or more dielectric materials over the patterned hard mask 242, which may serve as a planarization stop layer. In some embodiments, prior to forming the trench 253, a patterning process may be performed to form a patterned layer over the patterned hard mask 242, and the patterned layer has openings overlapping the dummy gate structure 230. An etching process may be used to form openings in the patterned hard mask 242 that expose the dummy gate structure 230 (e.g., its dummy gate stack 232), and then the trench 253 is formed. In some embodiments, the hard mask plug 252 is formed from a portion of a patterned layer. In some embodiments, a patterning process may be performed prior to forming the trench 253 to form an opening in the patterned hard mask 242 that exposes the dummy gate structure 230 (e.g., its dummy gate stack 232), and the patterned hard mask 242 may be used as an etching mask when forming the trench 253.

[0075] refer to Figure 5N and Figure 6N The patterned hard mask 242 can be removed by a planarization process (e.g., CMP) and / or other suitable processes. In some embodiments, the dielectric layer 170 (e.g., its ILD layer 174 and / or CESL 172) and / or the gate spacer 138 can be used as a planarization stop layer. In some embodiments, the CPODE process is performed after the formation of the gate stack 132 (referred to as a post-CPODE process). In such embodiments, when manufacturing device 100, the process can be omitted. Figure 5M and Figure 6M Related processing.

[0076] refer to Figure 5O and Figure 6OThe dummy gate block 236 is removed from the gate structure 130 to form a gate opening 255. The gate opening 255 exposes a channel region including a semiconductor layer 220, a sacrificial layer 215, and a sacrificial plug 250. In some embodiments, such as Figure 6O As depicted, the dummy gate dielectric 234 remains over the semiconductor layer 220, the sacrificial layer 215, and the isolation structure 110. In some embodiments, the etching process selectively removes the dummy gate block 236 (e.g., a polysilicon gate), while negligible (or no) removal of the dielectric layer 170 (e.g., ILD layer 174 and CESL 172), gate spacer 138, internal spacer 140, sacrificial layer 215, semiconductor layer 220, dummy gate dielectric 234, sacrificial plug 250, or combinations thereof. The etching process is dry etching, wet etching, other suitable etching, or combinations thereof. In some embodiments, such as Figure 5O As depicted, etchants and / or other removal methods may be unable to reach and / or substantially remove the dummy gate block 236 between the sacrificial plug 250 and the gate spacer 138, thereby potentially leaving a dummy gate block residue 236' between the sacrificial plug 250 and the gate spacer 138. In some embodiments, the etching process may use a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 138.

[0077] refer to Figure 5P and Figure 6P A channel release process can be implemented to form a channel structure (e.g., semiconductor layer 120). The channel release process may include selectively removing the sacrificial plug 250, the dummy gate dielectric 234, and the sacrificial layer 215 exposed by the gate opening 255 to form a gap 258. For example, a corresponding gap 258 may be located between semiconductor layers 220U and 220M, a corresponding gap 258 may be located between semiconductor layers 220M and 220L, and a corresponding gap 258 may be located between the bottom semiconductor layer 220L and the protrusion 105' and / or the substrate 105, thereby suspending semiconductor layer 220 in the channel region. Removing the sacrificial plug 250 may also provide a semiconductor layer 220U with an opening 245U, a semiconductor layer 220M with an opening 245M, and a semiconductor layer 220L with an opening 245L. Thus, the channel release process reopens vias in semiconductor layer 220.

[0078] In the depicted embodiment, after the channel release process, three semiconductor rings (e.g., semiconductor layer 220) are stacked vertically along the z-direction and suspended above the protrusion 105'. The suspended semiconductor layer 220 with the ring structure provides a channel for transistor T through which current can flow between the source / drain structure 150. Thus, semiconductor layer 220 may be referred to as semiconductor layer 120, channel layer 120, channel, channel structure, or a combination thereof. In some embodiments, the channel release process includes an etching process that selectively etches the sacrificial plug 250, the dummy gate dielectric 234, and the sacrificial layer 215 without (or negligibly) etching the semiconductor layer 220 (120), the protrusion 105', the isolation structure 110, the gate spacer 138, the internal spacer 140, the dielectric layer 170 (e.g., its ILD layer 174 and / or CESL 172), or a combination thereof. An etchant can be selected for the etching process that etches the oxide (i.e., sacrificial plug 250, dummy gate dielectric 234, and sacrificial layer 215) at a higher rate than silicon (i.e., semiconductor layer 220 and protrusion 105') and other dielectric materials (i.e., gate spacer 138 and internal spacer 140) (i.e., the etchant has high etch selectivity relative to the oxide). In some embodiments, a single etchant can remove the sacrificial plug 250, dummy gate dielectric 234, and sacrificial layer 215. In some embodiments, the etching process can be a multi-step process that implements different etchants to individually remove the sacrificial plug 250, dummy gate dielectric 234, and sacrificial layer 215. The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process can remove dummy gate block residue 236'. In some embodiments, prior to the etching process, an oxidation process can convert the dummy gate block residue 236' (e.g., polysilicon) into oxide residue, thereby allowing the etching process to also remove the oxide residue while removing the sacrificial plug 250, dummy gate dielectric 234, sacrificial layer 215, or combinations thereof. In some embodiments, prior to the etching process, an oxidation process can convert the sacrificial layer 215 into a semiconductor oxide component (e.g., silicon germanium oxide), and then the etching process removes the semiconductor oxide component. In some embodiments, a separate etching process and / or other suitable removal process are performed before or after the etching process that removes the sacrificial plug 250, dummy gate dielectric 234, sacrificial layer 215, or combinations thereof to remove the dummy gate block residue 236'. In some embodiments, during and / or after the removal of the sacrificial plug 250, dummy gate dielectric 234, sacrificial layer 215, or combinations thereof, an etching process can be performed to modify the contour of the semiconductor layer 220 to provide a channel structure (e.g., semiconductor layer 120) with a target size and / or target shape.For example, etching processes can provide profiles with cylindrical profiles (e.g., nanowires), rectangular profiles (e.g., nanorods), or other shapes (see example). Figure 6P Semiconductor segment 220U-1, semiconductor segment 220U-2, semiconductor segment 220M-1, semiconductor segment 220M-2, semiconductor segment 220L-1, semiconductor segment 220L-2 or combinations thereof.

[0079] refer to Figure 5Q , Figure 6Q and Figures 1A to 1C A gate stack 132 (e.g., gate dielectric 134 and gate electrode 136) is formed over a channel structure (e.g., semiconductor layer 120). The gate stack 132 fills the gate opening 255 and the gap 258. The gate stack 132 is disposed between gate spacers 138, between internal spacers 140, between semiconductor layers 120 (220), and between the bottom semiconductor layer 120 (220) and the protrusion 105'. The gate stack 132 may surround and / or wrap around the semiconductor layer 120 (e.g., in the YZ plane). Figure 6Q Because semiconductor layer 120 (220) is configured as a semiconductor ring, gate stack 132 also fills the openings in semiconductor layer 120 (220) and extends through semiconductor layer 120 (220). For example, gate stack 132 fills openings 245U, 245M, and 245L, such that gate stack 132 extends through semiconductor layers 120U (220U), 120M (220M), and 120L (220L). In a cross-sectional view of the unsegmented portion through semiconductor layer 120 (see, for example) Figure 1C Semiconductor layer 120 (220) (e.g., semiconductor segments 120U-1 (220U-1), 120U-2 (220U-2), 120M-1 (220M-1), 120M-2 (220M-2), 120L-1 (220L-1), and 120L-2 (220L-2)) extends continuously in the longitudinal direction of the active region between source / drain structures 150. A cross-sectional view of the segmented portion passing through semiconductor layer 120 (220) is shown in the figure. Figure 5Q Gate stack 132 extends through semiconductor layer 120 (220) and is disposed between corresponding semiconductor segments of semiconductor layer 120 (220) along the longitudinal direction of active region (e.g., between semiconductor segments 120U-3 (220U-3), between semiconductor segments 120M-3 (220M-3) and between semiconductor segments 120L-3 (220L-3)).

[0080] Using this configuration, the gate stack 132 bonds more than two sides of the semiconductor layer 120 having a ring-shaped profile. For example, as Figure 6Q As depicted in the text, Figure 6Q The diagram includes a partial top view of semiconductor layer 120U (220U) along its line 1-1'. Gate stack 132 is disposed on and bonded to the four sidewalls of semiconductor layer 120U—each sidewall of semiconductor segment 120U-1 (220U-1) and each sidewall of semiconductor segment 120U-2 (220U-2), instead of two sidewalls. Gate stack 132 is also disposed on the two tops and two bottoms of semiconductor layer 120U and bonded to the two tops and two bottoms of semiconductor layer 120U—the top and bottom of semiconductor segment 120U-1 (220U-1) and the top and bottom of semiconductor segment 120U-2 (220U-2), instead of one top and one bottom. Gate stack 132 is similarly disposed on and bonded to semiconductor layers 220M and 220L. This configuration improves gate control and reduces short-channel effects, as described herein.

[0081] Figures 7A to 7M The device 100 according to various aspects of embodiments of this disclosure is manufactured at various stages of another manufacturing process. Figure 1A A schematic cross-sectional view of part or all of line EE. Figures 8A to 8M respectively with Figures 7A to 7M Corresponding to each manufacturing stage, and Figures 8A to 8M Device 100 according to various aspects of embodiments of this disclosure Figure 1A A schematic cross-sectional view of part or all of line DD. Figures 7A to 7M and Figures 8A to 8M The manufacturing process is similar in many ways to Figures 5A to 5Q and Figures 6A to 6Q The manufacturing process. Therefore, for clarity and simplicity, Figures 5A to 5Q , Figures 6A to 6Q , Figures 7A to 7M and Figures 8A to 8M Similar components are denoted by the same reference numerals. For ease of description and understanding, this article also discusses... Figures 7A to 7M and Figures 8A to 8M For clarity, it has been simplified. Figures 7A to 7M and Figures 8A to 8M To better understand the inventive concept of embodiments of this disclosure. Additional components may be added to device 100 and / or its manufacturing process, and in other embodiments of device 100 and / or its manufacturing process, some of the components described below may be replaced, modified, or eliminated.

[0082] refer to Figure 7A and Figure 8ADevice 100 can be in an intermediate stage of processing, as described above. Figure 5A and Figure 6A As described. In some embodiments, a mask 305 may be disposed and / or formed over the dielectric layer 170. The mask 305 includes a material capable of enabling etch selectivity during subsequent processing, such as during a gate replacement process, a channel nicking process, a channel release process, or a combination thereof. The mask 305 may cover and protect the dielectric layer 170. In some embodiments, the mask 305 is a silicon nitride layer, a metal nitride layer, a metal oxide layer, or a combination thereof. The silicon nitride layer and / or the metal nitride layer may also include carbon and / or oxygen. The metal oxide layer may also include nitrogen and / or carbon. In some embodiments, the mask 305 has a multilayer structure. The mask 305 may be formed by: etching back the dielectric layer 170 and / or recessing the dielectric layer 170; depositing a mask material over the device 100; and performing a planarization process to remove the mask material from over the gate structure 130. Thus, the mask 305 and the gate structure 130 may form the top of the device 100. In some embodiments, the gate spacer 138 and / or the dummy gate stack 232 can be used as a planarization stop layer. Embodiments of this disclosure also contemplate the use of mask 305 in reference... Figures 5A to 5Q and Figures 6A to 6Q The embodiment formed over dielectric layer 170 during the described manufacturing process.

[0083] refer to Figures 7A to 7M and Figures 8A to 8M The described manufacturing process segments and / or cuts semiconductor layer 220 during, but not before, the gate replacement process. (Reference) Figure 7B and Figure 8B The dummy gate block 236 is removed from the gate structure 130 to form a gate opening 255. The gate opening 255 exposes a channel region including the semiconductor layer 220 and the sacrificial layer 215. It should be noted that in the depicted embodiment, the sacrificial plug 250 has not yet been formed, and therefore the gate opening 255 does not expose the sacrificial plug 250. In some embodiments, as depicted, the dummy gate dielectric 234 remains over the semiconductor layer 220, the sacrificial layer 215, and the isolation structure 110. In some embodiments, the etching process selectively removes the dummy gate block 236 (e.g., a polysilicon gate) while ignoring (or not removing) the mask 305, gate spacer 138, internal spacer 140, sacrificial layer 215, semiconductor layer 220, dummy gate dielectric 234, or combinations thereof. The etching process is dry etching, wet etching, other suitable etching, or combinations thereof. In some embodiments, the etching process may use a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 138.

[0084] refer to Figure 7C and Figure 8C An antireflective coating (ARC) 310 is formed in the gate opening 255. In other words, the antireflective coating 310 replaces the dummy gate block 236. The antireflective coating 310 may be formed of an antireflective material that resists etching processes performed on underlying layers, such as semiconductor layer 220 and / or sacrificial layer 215. Therefore, the composition of the antireflective coating 310 differs from that of semiconductor layer 220 and sacrificial layer 215. The composition of the antireflective coating 310 may also differ from that of the dummy gate dielectric 234. In some embodiments, the antireflective coating 310 is a bottom antireflective coating (BARC). In some embodiments, the antireflective coating 310 comprises an organic material. For example, the antireflective coating 310 may be a carbon-rich polymer layer that may include carbon and hydrogen and / or oxygen. In some embodiments, the carbon-rich polymer layer is C i H j O k Layer. In another example, the antireflective coating 310 may be a silicon-rich polymer layer, which may include silicon and carbon, hydrogen, oxygen, or combinations thereof. In some embodiments, the silicon-rich polymer layer is SiC. x H y O z Layer. In some embodiments, the antireflective coating 310 is silicon-free. In some embodiments, the antireflective coating 310 is formed by a spin coating process, which may optionally be followed by a baking process. In some embodiments, a planarization process may be performed after depositing and / or spin coating an antireflective coating material filling the gate opening 255 over the device 100. The planarization process may remove the antireflective coating material disposed over the mask 305 and / or the gate spacer 138.

[0085] refer to Figures 7D to 7J and Figures 8D to 8J The segmentation of semiconductor layer 220 may include forming at least one channel cutout 345 in the multilayer stack 210 extending through at least one of the semiconductor layers 220. In some embodiments, as depicted, the channel cutout 345 partially extends through the multilayer stack 210. For example, the channel cutout 345 extends through the antireflective coating 310, the dummy gate dielectric 234, semiconductor layer 220U, sacrificial layer 215U, semiconductor layer 220M, sacrificial layer 215M, and semiconductor layer 220L. Thus, the channel cutout 345 extends through all semiconductor layers 220, but stops at the sacrificial layer 215L and exposes the sacrificial layer 215L. The channel cutout 345 is configured similarly to the referenced above. Figures 5D to 5J and Figures 6D to 6JThe described channel cutout 245, and the channel cutout 345 segment the semiconductor layer 220 in a manner similar to that of the channel cutout 245, as described above. The channel cutout 345 provides a semiconductor layer 220U with an opening 345U, a semiconductor layer 220M with an opening 345M, and a semiconductor layer 220L with an opening 345L, which may be similar to the openings 245U, 245M, and 245L described above, respectively.

[0086] An etching process can be performed to form the channel cut 345. The etching process may include and / or dry etching, wet etching, other suitable etching processes, or combinations thereof. In some embodiments, the etching process is a multi-step etching. For example, the etching process may alternate etchants and / or adjust other etching parameters (e.g., etching time, etching temperature, etching pressure, etchant flow rate, etc.) to remove the anti-reflective coating 310 individually and alternately. Figure 7D and Figure 8D ), pseudo-gate dielectric 234 ( Figure 7E and Figure 8E ), Semiconductor layer 220U ( Figure 7F and Figure 8F ), Sacrificial layer 215U ( Figure 7G and Figure 8G ), Semiconductor layer 220M ( Figure 7H and Figure 8H ), Sacrificial layer 215M ( Figure 7I and Figure 8I ) and semiconductor layer 220L ( Figure 7J and Figure 8J In some embodiments, the etching process includes: selectively removing the antireflective coating 310 relative to the dummy gate dielectric 234. Figure 7D and Figure 8D (e.g., the first etching step); selective removal of the dummy gate dielectric 234 relative to the anti-reflective coating 310 and the semiconductor layer 220U. Figure 7E and Figure 8E (e.g., the second etching step); selective removal of semiconductor layer 220U relative to antireflective coating 310, dummy gate dielectric 234, and sacrificial layer 215U. Figure 7F and Figure 8F (e.g., the third etching step); selective removal of sacrificial layer 215U relative to antireflective coating 310, semiconductor layer 220U, and semiconductor layer 220M. Figure 7G and Figure 8G (e.g., the fourth etching step); selective removal of semiconductor layer 220M relative to antireflective coating 310, dummy gate dielectric 234, sacrificial layer 215U, and sacrificial layer 215M. Figure 7H and Figure 8H(For example, the fifth etching step); selective removal of the sacrificial layer 215M relative to the anti-reflective coating 310, semiconductor layer 220U, semiconductor layer 220M and semiconductor layer 220L. Figure 7I and Figure 8I (e.g., the sixth etching step); and selective removal of semiconductor layer 220L relative to antireflective coating 310, dummy gate dielectric 234, sacrificial layer 215U, sacrificial layer 215M and sacrificial layer 215L. Figure 7J and Figure 8J (e.g., the seventh etching step). In some embodiments, the dummy gate dielectric 234 and the sacrificial layer 215 are formed of oxide (Ox) (having the same composition or different compositions), the semiconductor layer 220 is formed of silicon (Si), and the etching process can be ARC / Ox / Si / Ox / Si / Ox / Si etching. The etching process can use different etchants to remove ARC, oxide, and silicon individually. For example, the etching process can implement a first etchant to selectively remove ARC without (or negligibly) removing oxide and silicon, a second etchant to selectively remove oxide without (or negligibly) removing ARC and silicon, and a third etchant to selectively remove silicon without (or negligibly) removing ARC and oxide. In some embodiments, multiple etching steps of the etching process are performed in the same process chamber. For example, when the etching process is ARC / Ox / Si / Ox / Si / Ox / Si etching, device 100 can be exposed to the first etchant, the second etchant, and the third etchant in the same process chamber. In some embodiments, after each etching step, a cleanup process may be performed to remove the given etchant and any byproducts of the corresponding etching step before performing the next etching step in the same process chamber.

[0087] In some embodiments, the etching process may selectively remove the antireflective coating 310, the dummy gate dielectric 234, the semiconductor layer 220, the sacrificial layer 215, or combinations thereof, relative to mask 305. In other words, the channel notch 345 may be formed without (or negligibly) removing mask 305. In some embodiments, such as Figure 7D and Figure 8DAs depicted, a patterned layer 312 may be formed over device 100 prior to etching antireflective coating 310, and the etching process may use the patterned layer 312 as an etching mask. For example, the patterned layer 312 may have an opening 313 that overlaps with and / or exposes a portion of antireflective coating 310 located above the multilayer stack 210, and the etching process may remove the exposed portion of antireflective coating 310 (i.e., the portion not covered by patterned layer 312). The opening 313 may be similar to the opening 243 described above. For example, the opening 313 may have a critical dimension D2. In some embodiments, the patterned layer 312 is a patterned resist layer that can be removed by an etching process and / or a resist stripping process. In some embodiments, as depicted, the patterned layer 312 is removed before the channel notch 345 extends into the dummy gate dielectric 234. In some embodiments, the patterned layer 312 is removed during the etching process, such that the patterned layer 312 (or a portion thereof) may remain over the antireflective coating 310 during the etching of the dummy gate dielectric 234, semiconductor layer 220U, sacrificial layer 215U, semiconductor layer 220M, sacrificial layer 215M, semiconductor layer 220L, or combinations thereof.

[0088] refer to Figure 7K and Figure 8K The anti-reflective coating 310 is removed from the gate structure 130 to form a gate opening 355. The gate opening 355 exposes a channel region including a semiconductor layer 220 and a sacrificial layer 215. In some embodiments, as depicted, a dummy gate dielectric 234 remains over the semiconductor layer 220, the sacrificial layer 215, and the isolation structure 110. In some embodiments, the etching process selectively removes the anti-reflective coating 310 while ignoring (or not removing) the mask 305, gate spacer 138, internal spacer 140, sacrificial layer 215, semiconductor layer 220, dummy gate dielectric 234, or combinations thereof. The etching process is dry etching, wet etching, other suitable etching, or combinations thereof. In the depicted embodiment, because the channel notch 345 is formed after the removal of the dummy gate block 236, the channel notch 345 exists in the multilayer stack 210 during and after the removal of the anti-reflective coating 310. In other words, in Figures 7A to 7M and Figures 8A to 8M The manufacturing process may omit the steps associated with forming sacrificial plugs (such as sacrificial plug 250) in the channel cutout 345. In some embodiments, the etching process may use a patterned mask layer as an etching mask, wherein the patterned mask layer covers the dielectric layer 170 and / or the gate spacer 138.

[0089] refer to Figure 7L and Figure 8L A channel release process can be implemented to form a channel structure (e.g., semiconductor layer 120), such as a reference. Figure 5P and Figure 6P As described above, the channel release process may include selectively removing the dummy gate dielectric 234 and the sacrificial layer 215 exposed by the gate opening 355 to form a gap 258. In the depicted embodiment, because the openings within the semiconductor layer 220 (e.g., openings 345U, 345M, and 345L) exist prior to the channel release process, the channel release process can connect the openings within the semiconductor layer 220 to the gap 258 without reopening the openings, as described above. Reference Figure 7M , Figure 8M and Figures 1A to 1C A gate stack 132 (e.g., gate dielectric 134 and gate electrode 136) is formed over a channel structure (e.g., semiconductor layer 120), as shown in the reference above. Figure 5Q and Figure 6Q As described. The gate stack 132 may fill the gate opening 355, the gap 258, and the openings (e.g., openings 345U, 345M, and 345L) within the semiconductor layer 220. Reference Figures 7A to 7M and Figures 8A to 8M The described manufacturing process can be further implemented as a pre-CPODE process or a post-CPODE process. In a pre-CPODE process embodiment, the CPODE process can be performed before replacing the dummy gate block 236 with anti-reflective coating 310. In a post-CPODE process embodiment, the CPODE process can be performed after replacing the dummy gate stack 232 with gate stack 132.

[0090] Figure 11This is a schematic top view of part or all of a device layout that may be implemented when manufacturing device 100 according to various aspects of embodiments of the present disclosure. In the device layout, device 100 may include CMOS transistors, and transistor T may form portions of CMOS transistors, such as n-type or p-type transistors. In such embodiments, device 100 may include two active regions 160, a gate structure 130 may span the two active regions 160, and a dummy gate structure 230 may span the two active regions 160. In some embodiments, the upper active region 160 may be configured for an n-type transistor (e.g., a p-well may be formed in substrate 105, and the source / drain structure 150 may be an n-type source / drain), and the lower active region may be configured for a p-type transistor (e.g., an n-well may be formed in substrate 105, and the source / drain structure 150 may be a p-type source / drain), or vice versa. The channel notch layout can be superimposed on device layouts, and the channel notch layout can include a channel notch 390, which can define the location and / or size of channel notches (such as channel notches 245 and / or channel notches 345) when the channel of device 100 is segmented. For example, the channel notch layout can be used to form channel notch openings in a patterned layer, such as opening 243 in a patterned hard mask 242 and / or opening 313 in a patterned layer 312. In some embodiments, the channels of n-type transistors and p-type transistors can be segmented at the same time. In some embodiments, the channels of n-type transistors and p-type transistors can be segmented at different times. The etching process performed during channel segmentation can be configured to minimize the loss of gate spacer 138 and / or internal spacer 140. For clarity, simplification has been provided. Figure 11 To better understand the inventive concept of embodiments of this disclosure. It is possible to... Figure 11 Adding additional components to the device layout, and Figure 11 In other embodiments of the device layout, some of the components described below may be replaced, modified, or eliminated.

[0091] Figures 12 to 14 This is a schematic top view of part or all of a channel cutout layout that may be implemented when manufacturing device 100 according to various aspects of embodiments of the present disclosure (e.g., when forming channel cutouts 245 and / or channel cutouts 345). For example, the channel cutout layout may be used to form channel cutout openings in a patterned layer, such as opening 243 in a patterned hard mask 242 and / or opening 313 in a patterned layer 312, and the channel cutout openings may define the location and / or size of the channel cutouts (such as channel cutouts 245 and / or channel cutouts 345). Figures 12 to 14The channel notch layout can be configured to provide devices of different sizes with channel segments of the same width. For example, a channel notch layout can be implemented to segment nanosheets of different sizes into nanowires / nanorings of the same width. In some embodiments, the active region 160 is within a channel notch layout 400 Å ( Figure 12 It has a width Y1 (e.g., along the y direction) in the channel cutout layout 400B ( Figure 13 It has a width Y2 (e.g., along the y direction) and a channel cutout layout of 400C ( Figure 14 The active region 160 has a width Y3 (e.g., along the y-direction). Widths Y1, Y2, and Y3 are different. For example, width Y1 is smaller than width Y2, and width Y2 is smaller than width Y3. In channel cutout layouts 400A-400C, gate line 405 may be disposed above the channel region of active region 160, and gate line 405 may extend substantially parallel to each other along the lateral direction of active region (e.g., y-direction). The length of gate line 405 (e.g., along the y-direction) is greater than the width of active region 160 (e.g., width Y1, width Y2, and / or width Y3), gate line 405 corresponds to the gate stacks of gate structure 130 and pseudo-gate structure 230 (e.g., pseudo-gate stack 232 and / or gate stack 132), and gate line 405 may define a critical dimension CD1 (e.g., along the x-direction).

[0092] Channel cutout layouts 400A-400C may define a channel cutout 410 that overlaps with the channel region of the active region 160 and the gate line 405 disposed above it. The channel cutout 410 has a critical dimension D2 (e.g., along the x-direction) and a width B along the lateral direction of the active region (e.g., the y-direction). In channel cutout layouts 400A-400C, the number of channel cutouts 410 for a given channel region depends on the width of the active region 160, and the number of channel cutouts 410 is selected to provide channel segments with the same width (such as width A) along the lateral direction of the active region. For example, a channel cutout layout 400A can provide one channel cutout 410 to segment a channel region with width Y1 into two channel segments with width A; a channel cutout layout 400B can provide two channel cutouts 410 to segment a channel region with width Y2 into three channel segments with width A; and a channel cutout layout 400C can provide three channel cutouts 410 to segment a channel region with width Y3 into four channel segments with width A. In such an embodiment, a channel cutout layout 400A can be generated, drawn, and / or placed above the device layout according to the cutout formula Y1=2A+B; a channel cutout layout 400B can be generated, drawn, and / or placed above the device layout according to the cutout formula Y2=3A+2B; and a channel cutout layout 400C can be generated, drawn, and / or placed above the device layout according to the cutout formula Y3=4A+3B. The channel segments provided by the channel cut layout 400A-400C can be separated by width B, and width B can correspond to the interval SB.

[0093] In some embodiments, channel notch layout 400A may provide one channel notch to segment a nanosheet having width Y1 into two nanowires / nanorons having width A and separated by width B (e.g., a spacing SB approximately width B). In some embodiments, channel notch layout 400B may provide two channel notches to segment a nanosheet having width Y2 into three nanowires / nanorons having width A and separated by width B. In some embodiments, channel notch layout 400C may provide three channel notches to segment a nanosheet having width Y3 into four nanowires / nanorons having width A and separated by width B. In some embodiments, channel notch layouts 400A-400C may be implemented together to simultaneously segment the channels of multiple devices with different active region widths, thereby providing multiple devices with the same channel width simultaneously. In some embodiments, channel notch layouts 400A-400C may be implemented to separately segment the channels of multiple devices with different active region widths, thereby providing multiple devices with the same channel width. For clarity, it has been simplified. Figures 12 to 14To better understand the inventive concept of embodiments of this disclosure. It is possible to... Figures 12 to 14 Add additional components to the channel cut-out layout, and Figures 12 to 14 In other embodiments of the channel cut-out layout, some of the components described below may be replaced, modified, or eliminated.

[0094] Figures 15 to 17 This is a schematic top view of some or all of other channel cutout layouts that may be implemented when manufacturing device 100 according to various aspects of embodiments of the present disclosure (e.g., when forming channel cutouts 245 and / or channel cutouts 345). For example, the channel cutout layout may be used to form channel cutout openings in a patterned layer, such as opening 243 in a patterned hard mask 242 and / or opening 313 in a patterned layer 312, and the channel cutout openings may define the location and / or size of the channel cutouts (such as channel cutouts 245 and / or channel cutouts 345). Figures 15 to 17 The channel notch layouts (e.g., channel notch layouts 500A, 500B, and 500C) can be configured to provide devices of different sizes with channel segments of variable width. For example, channel notch layouts can be implemented to segment nanosheets of different-sized devices into nanowires / nanorings with the same and / or different widths. Channel notch layouts 500A-500C are similar in many respects to channel notch layouts 400A-400C. Therefore, for clarity and simplicity, Figures 12 to 14 and Figures 15 to 17 Similar parts in the diagram are denoted by the same reference numerals. For clarity, simplification has been implemented. Figures 15 to 17 To better understand the inventive concept of embodiments of this disclosure. It is possible to... Figures 15 to 17 Add additional components to the channel cut-out layout, and Figures 15 to 17 In other embodiments of the channel cut-out layout, some of the components described below may be replaced, modified, or eliminated.

[0095] exist Figures 15 to 17 In the active region 160, a 500A array is deployed at the trench cut. Figure 15 It has a width Y1 and a channel cut layout of 500B ( ) Figure 16 It has a width Y2 in the channel cutout layout 500C ( Figure 17The active region 160 has a width Y3. In the channel cutout layouts 500A-500C, the gate line 405 can be disposed above the channel region of the active region 160, and the channel cutout layouts 500A-500C can define a channel cutout 410 having a width B, the channel cutout 410 overlapping the channel region of the active region 160 and the gate line 405 disposed thereon. In the channel cutout layouts 500A-500C, the number of channel cutouts 410 for a given channel region can depend on the width of the active region 160 and / or the desired performance characteristics of its corresponding transistor, and the number of channel cutouts 410 is selected to provide channel segments with variable widths (such as width A and / or width C) along the lateral direction of the active region. For example, trench cut layout 500A can provide one trench cut 410 to segment a trench region with width Y1 into two trench segments with width A, trench cut layout 500B can provide one trench cut 410 to segment a trench region with width Y2 into two trench segments with width C, where width C is different from (for example, greater than) width A, and trench cut layout 500C can provide two trench cuts 410 to segment a trench region with width Y3 into three trench segments, wherein one of the trench segments has width A, and two of the trench segments have width C. In such an embodiment, a channel cutout layout 500A can be generated, drawn, and / or placed above the device layout according to the cutout formula Y1=2A+B, a channel cutout layout 500B can be generated, drawn, and / or placed above the device layout according to the cutout formula Y2=2C+B, and a channel cutout layout 500C can be generated, drawn, and / or placed above the device layout according to the cutout formula Y3=2C+2B+A. The channel segments provided by the channel cutout layouts 500A-500C can be separated by a width B, which can correspond to a spacing SB. In some embodiments, fewer channel cutouts 410 can provide better performance (e.g., by providing wider channel segments).

[0096] In some embodiments, channel notch layout 500A may provide a channel notch to segment a nanosheet having width Y1 into two nanowires / nanorings having width A and separated by width B. In some embodiments, channel notch layout 500B may provide a channel notch to segment a nanosheet having width Y2 into two nanowires / nanorings having width C and separated by width B. In some embodiments, channel notch layout 500C may provide two channel notches to segment a nanosheet having width Y3 into three nanowires / nanorings separated by width B, wherein one of the nanowires / nanorings has width WA, and two of the nanowires / nanorings have width C. In some embodiments, channel notch layouts 500A-500C may be implemented together to simultaneously segment the channels of multiple devices with different active region widths, thereby providing multiple devices with various channel widths, which may be the same and / or different. In some embodiments, channel cutout layouts 500A-500C may be implemented to individually segment the channels of multiple devices with different active region widths, thereby providing multiple devices with various channel widths. In some embodiments, channel cutouts 410 may have different widths (e.g., width B in channel layout 500A may be different from width B in channel layout 500B, and width B in channel layout 500B may be different from width B in channel layout 500C, to provide channel segments with different widths).

[0097] Figure 18A , Figure 18B , Figure 19A and Figure 19B This is a schematic cross-sectional view of a device 500 that may include transistors with segmented channels (such as transistor 502A) and transistors with unsegmented channels (such as transistor 502B) according to various embodiments of the present disclosure. Transistor 502A may be configured as described herein, such as similar to transistor T. Transistor 502B may be configured as described herein, except that channel segmentation is not implemented when transistor 502B is manufactured, such that transistor 502B includes an unsegmented semiconductor layer 120. In some embodiments, transistor 502A is a nanowire transistor, and transistor 502B is a nanosheet transistor. Figure 18A and Figure 18B In this process, transistors 502A and 502B can be fabricated on the same wafer, and the height of transistor 502A can be substantially the same as the height of transistor 502B. Figure 19A and Figure 19BIn this design, transistors 502A and 502B can be fabricated on the same wafer with the same critical polysilicon pitch (CPP), where CPP typically refers to the distance between adjacent gates (e.g., gate structure 130). The height of transistor 502A can differ from the height of transistor 502B. In some embodiments, because transistor 502A (i.e., having a segmented channel as described herein) can achieve a shorter gate length with better short-channel effect control, transistor 502A can have a larger volumetric source / drain structure 150, which can reduce source / drain resistance and / or increase channel stress. A shorter gate length and / or a higher channel height of transistor 502A can facilitate a larger volumetric source / drain structure 150. In some embodiments, the channel width / height ratio of transistor 502A is less than about 2, and the channel width / height ratio of transistor 502B is greater than or equal to about 2. For clarity, simplified diagrams have been provided. Figure 18A , Figure 18B , Figure 19A and Figure 19B To better understand the inventive concept of embodiments of this disclosure. It is possible to... Figure 18A , Figure 18B , Figure 19A and Figure 19B Add additional components to device 500, and in Figure 18A , Figure 18B , Figure 19A and Figure 19B In other embodiments of device 500, some of the components described below may be replaced, modified, or eliminated.

[0098] This disclosure provides numerous different embodiments. In some embodiments, the device structure includes a semiconductor ring and a gate. The gate is disposed above and engages the semiconductor ring. The semiconductor ring extends longitudinally along a first direction between a first source / drain and a second source / drain, and the gate is disposed along the first direction between the first source / drain and the second source / drain. The gate extends longitudinally along a second direction different from the first direction and extends through the semiconductor ring. In some embodiments, the semiconductor ring is disposed above a semiconductor substrate, and the gate extends into the semiconductor substrate. In some embodiments, the semiconductor ring is a rectangular ring surrounding a portion through which the gate extends. In some embodiments, the portion of the gate extending through the semiconductor ring has a width that gradually decreases from the top to the bottom of the semiconductor ring along the second direction. In some embodiments, the portion of the gate extending through the semiconductor ring has a uniform width from the top to the bottom of the semiconductor ring along the second direction. In some embodiments, the gate is disposed above and engages the top, bottom, inner sidewall, and outer sidewall of the semiconductor ring.

[0099] In some embodiments, the semiconductor ring includes a first semiconductor segment and a second semiconductor segment extending from a first source / drain to a second source / drain along a first direction, with a gate filling the gap between the first and second semiconductor segments. In some embodiments, the semiconductor ring includes at least one third semiconductor segment extending from the first semiconductor segment to the second semiconductor segment along a second direction. In some embodiments, the semiconductor ring includes a width-to-height ratio of less than about 2 for the first and second semiconductor segments. In some embodiments, the first semiconductor segment is a first nanowire, and the second semiconductor segment is a second nanowire. In some embodiments, at least one third semiconductor segment connects the first nanowire to the second nanowire.

[0100] In some embodiments, the device includes a channel layer and a gate. The channel layer extends along a first direction between a first source / drain and a second source / drain, and the gate is disposed between the first source / drain and the second source / drain. The gate is disposed over the channel layer and engages the channel layer. The gate extends along a second direction different from the first direction. The gate also extends through the channel layer along a third direction different from the first and second directions. In some embodiments, the channel layer may be disposed over a semiconductor substrate, and a portion of the gate extending through the channel layer extends into the semiconductor substrate. In some embodiments, the channel layer has a length along the first direction, a segment of the channel layer has a corresponding width along the second direction and a corresponding height along the third direction, and the ratio of the corresponding width to the corresponding height is greater than about 0.5 and less than about 2. In some embodiments, the gate includes a first portion and a second portion extending through the channel layer along the third direction. In some embodiments, the channel layer includes a first segment disposed between the gate and the first source / drain and a second segment disposed between the gate and the second source / drain.

[0101] In some embodiments, the method includes a receiving device structure comprising a multilayer stack extending longitudinally along a first direction between a first source / drain and a second source / drain, and a dummy gate disposed above the multilayer stack and between the first source / drain and the second source / drain. The dummy gate extends longitudinally along a second direction different from the first direction, and the multilayer stack includes a semiconductor layer and a sacrificial layer. The method further includes forming a channel cut in the dummy gate and the multilayer stack. The channel cut extends through the dummy gate and the multilayer stack along a third direction. The channel cut segments the semiconductor layer of the multilayer stack, and the third direction is different from the first and second directions. The method further includes forming a gate stack in the channel cut. Forming the gate stack includes replacing the remainder of the dummy gate and the remainder of the sacrificial layer of the multilayer stack with the gate stack. In some embodiments, forming the channel cut includes removing a central portion of the multilayer stack to form an opening therein.

[0102] In some embodiments, the method further includes forming a sacrificial plug in a channel slit prior to forming a gate stack, and forming the gate stack includes replacing the sacrificial plug with the gate stack. In some embodiments, forming the sacrificial plug includes depositing an oxide material and performing a planarization process. In some embodiments, the dummy gate includes a dummy gate block and a dummy gate dielectric. In some embodiments, the method further includes replacing the dummy gate block with an anti-reflective coating prior to forming a channel slit in the dummy gate and the multilayer stack. In such embodiments, forming the gate stack may include replacing the remaining portion of the anti-reflective coating and the remaining portion of the dummy gate dielectric with the gate stack. In some embodiments, the channel slit is a first channel slit, and the method further includes forming a second channel slit in the dummy gate and the multilayer stack. The second channel slit extends through the dummy gate and the multilayer stack in a third direction, and the second channel slit also segments the semiconductor layer. The gate stack may be formed in the second channel slit.

[0103] In some embodiments, the method includes forming a fin structure, the fin structure including a first semiconductor layer and a second semiconductor layer alternately stacked over a substrate. The method further includes: forming a dummy gate structure over the fin structure; forming a source / drain trench in the fin structure (e.g., on opposite sides of the dummy gate structure); replacing the first semiconductor layer with a dielectric interposer (e.g., a sacrificial layer); and forming source / drain components in the source / drain trench. The method further includes: forming a dielectric layer over the dummy gate structure and the source / drain components; and forming a first opening in the dielectric layer to expose a first portion of the dummy gate structure. The method further includes performing an etching process to etch the dummy gate structure, the first semiconductor layer, and the dielectric interposer through the first opening to form a first trench extending through the dummy gate structure, the first semiconductor layer, and the dielectric interposer. The method further includes: depositing an oxide material to fill the first trench. The method further includes removing the oxide material, the remaining portion of the dummy gate structure, and the remaining portion of the dielectric interposer to form a gate trench; and depositing a conductive material in the gate trench to form a metal gate structure enclosing a second semiconductor layer.

[0104] In some embodiments, the substrate is etched during the etching process, such that the trench extends into the substrate. In some embodiments, the etching process is performed until the bottommost one of the dielectric interposers is exposed, such that the bottom surface of the trench is separated from the substrate by the bottommost one of the dielectric interposers. In some embodiments, the method further includes forming a second opening in the dielectric layer to expose a second portion of the dummy gate structure, wherein the etching process etches the dummy gate structure, the first semiconductor layer, and the dielectric interposer through the first and second openings to form a first trench and a second trench extending through the dummy gate structure, the first semiconductor layer, and the dielectric interposer, respectively. In some embodiments, the fin structure extends in a first direction, and the dummy gate structure extends in a second direction different from the first direction (e.g., perpendicular to the first direction). In the second direction, a first width between the first trench and a first side of the fin structure may be the same as a second width between the second trench and a second side of the fin structure. In some embodiments, a third width between the first trench and the second trench is the same as the first width. In some embodiments, the third width between the first trench and the second trench is greater than or less than the first width.

[0105] Some embodiments of this application provide a device structure including: an active region comprising a semiconductor ring, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, and the semiconductor ring extends longitudinally along the first direction between the first source / drain and the second source / drain; and a gate disposed above and connected to the semiconductor ring, wherein the gate extends through the semiconductor ring, the gate is disposed between the first source / drain and the second source / drain along the first direction, the gate extends longitudinally along a second direction different from the first direction, and the gate extends along the second direction from above the semiconductor ring to above an isolation structure.

[0106] In some embodiments, the semiconductor ring is disposed above a semiconductor substrate, and the gate extends into the semiconductor substrate. In some embodiments, the semiconductor ring is a quadrilateral ring surrounding a portion through which the gate extends. In some embodiments, the portion of the gate extending through the semiconductor ring has a width that gradually decreases from the top to the bottom of the semiconductor ring along the second direction. In some embodiments, the portion of the gate extending through the semiconductor ring has a uniform width from the top to the bottom of the semiconductor ring along the second direction. In some embodiments, the gate is disposed above the top, bottom, inner sidewall, and outer sidewall of the semiconductor ring and engages the top, bottom, inner sidewall, and outer sidewall of the semiconductor ring. In some embodiments, the semiconductor ring includes: a first semiconductor segment and a second semiconductor segment extending from the first source / drain to the second source / drain along the first direction, wherein the gate fills the gap between the first semiconductor segment and the second semiconductor segment; and at least one third semiconductor segment extending from the first semiconductor segment to the second semiconductor segment along the second direction. In some embodiments, the width-to-height ratio of the first semiconductor segment and the second semiconductor segment is less than about 2. In some embodiments, the first semiconductor segment is a first nanowire, the second semiconductor segment is a second nanowire, and the at least one third semiconductor segment connects the first nanowire to the second nanowire.

[0107] Other embodiments of this application provide a method for forming a device structure, comprising: forming an active region including a channel layer, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, the channel layer is disposed above a semiconductor substrate, and the channel layer extends longitudinally along the first direction between the first source / drain and the second source / drain; and forming a gate extending longitudinally along a second direction different from the first direction, wherein the gate is disposed between the first source / drain and the second source / drain along the first direction, the gate is disposed above the channel layer and engages the channel layer, the gate extends along the second direction above the channel layer and the isolation structure, and the gate extends through the channel layer along a third direction, wherein the third direction is different from the first direction and the second direction.

[0108] In some embodiments, the formation of the channel layer and the formation of the gate are configured to provide a gate having a portion extending through the channel layer and into the semiconductor substrate. In some embodiments, the formation of the channel layer is configured to provide a channel layer having a segment having a corresponding width along the second direction and a corresponding height along the third direction, wherein the ratio of the corresponding width to the corresponding height is greater than about 0.5 and less than about 2. In some embodiments, the formation of the channel layer and the formation of the gate are configured to provide a gate having a first portion and a second portion extending through the channel layer along the third direction. In some embodiments, the formation of the channel layer includes forming a first segment of the channel layer between the gate and the first source / drain and forming a second segment of the channel layer between the gate and the second source / drain.

[0109] Some embodiments of this application provide a method for forming a device structure, comprising: receiving a device structure including a multilayer stack extending longitudinally along a first direction between a first source / drain and a second source / drain, and a dummy gate disposed above the multilayer stack and between the first source / drain and the second source / drain, wherein the dummy gate extends longitudinally along a second direction different from the first direction, and the multilayer stack includes a semiconductor layer and a sacrificial layer; forming a channel cut in the dummy gate and the multilayer stack, wherein the channel cut extends through the dummy gate and the multilayer stack along a third direction, wherein the channel cut segments the semiconductor layer of the multilayer stack, and the third direction is different from the first direction and the second direction; and forming a gate stack in the channel cut, wherein forming the gate stack includes replacing the remaining portion of the dummy gate and the remaining portion of the sacrificial layer of the multilayer stack with the gate stack, wherein the gate stack extends longitudinally along the second direction above the semiconductor layer and the isolation structure of the multilayer stack, and wherein the gate stack includes a gate dielectric and a gate electrode.

[0110] In some embodiments, the method further includes: forming a sacrificial plug in the channel notch before forming the gate stack; and forming the gate stack includes replacing the sacrificial plug with the gate stack. In some embodiments, forming the sacrificial plug includes: depositing an oxide material; and performing a planarization process. In some embodiments, the dummy gate includes a dummy gate block and a dummy gate dielectric, and the method further includes: replacing the dummy gate block with an anti-reflective coating before forming the channel notch in the dummy gate and the multilayer stack; and forming the gate stack includes replacing the remaining portion of the anti-reflective coating and the remaining portion of the dummy gate dielectric with the gate stack. In some embodiments, forming the channel notch includes removing a central portion of the multilayer stack to form an opening therein. In some embodiments, the channel notch is a first channel notch; and the method further includes: forming a second channel notch in the dummy gate and the multilayer stack, wherein the second channel notch extends through the dummy gate and the multilayer stack along the third direction, wherein the second channel notch also segments the semiconductor layer; and forming the gate stack in the second channel notch.

[0111] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A device structure, comprising: An active region, comprising a semiconductor ring, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, and the semiconductor ring extends longitudinally along the first direction between the first source / drain and the second source / drain; and A gate is disposed above and engaged with the semiconductor ring, wherein the gate extends through the semiconductor ring, the gate is disposed between the first source / drain and the second source / drain along a first direction, the gate extends longitudinally along a second direction different from the first direction, and the gate extends along the second direction from above the semiconductor ring to above the isolation structure.

2. The device structure according to claim 1, wherein, The semiconductor ring is disposed above the semiconductor substrate, and the gate extends into the semiconductor substrate.

3. The device structure according to claim 1, wherein, The semiconductor ring is a quadrilateral ring that extends through a portion of the gate.

4. The device structure according to claim 1, wherein, The portion of the gate extending through the semiconductor ring has a width that gradually decreases from the top to the bottom of the semiconductor ring along the second direction.

5. The device structure according to claim 1, wherein, The portion of the gate extending through the semiconductor ring has a uniform width from the top to the bottom of the semiconductor ring along the second direction.

6. The device structure according to claim 1, wherein, The gate is disposed above the top, bottom, inner sidewall and outer sidewall of the semiconductor ring and engages the top, bottom, inner sidewall and outer sidewall of the semiconductor ring.

7. The device structure according to claim 1, wherein, The semiconductor ring includes: A first semiconductor segment and a second semiconductor segment extend along the first direction from the first source / drain to the second source / drain, wherein the gate fills the gap between the first semiconductor segment and the second semiconductor segment; and At least one third semiconductor segment extends from the first semiconductor segment to the second semiconductor segment along the second direction.

8. The device structure according to claim 7, wherein, The width-to-height ratio of the first semiconductor segment and the second semiconductor segment is less than about 2.

9. A method for forming a device structure, comprising: An active region is formed, comprising a channel layer, a first source / drain, and a second source / drain, wherein the active region extends longitudinally along a first direction, the channel layer is disposed above a semiconductor substrate, and the channel layer extends longitudinally along the first direction between the first source / drain and the second source / drain; and A gate is formed extending longitudinally along a second direction different from the first direction, wherein the gate is disposed between the first source / drain and the second source / drain along the first direction, the gate is disposed above the channel layer and bonded to the channel layer, the gate extends along the second direction above the channel layer and the isolation structure, and the gate extends through the channel layer along a third direction, wherein the third direction is different from the first direction and the second direction.

10. A method for forming a device structure, comprising: A receiving device structure includes a multilayer stack extending longitudinally along a first direction between a first source / drain and a second source / drain, and a dummy gate disposed above the multilayer stack and between the first source / drain and the second source / drain, wherein the dummy gate extends longitudinally along a second direction different from the first direction, and the multilayer stack includes a semiconductor layer and a sacrificial layer. A channel cut is formed in the dummy gate and the multilayer stack, wherein the channel cut extends through the dummy gate and the multilayer stack in a third direction, wherein the channel cut segments the semiconductor layers of the multilayer stack, and the third direction is different from the first direction and the second direction; and A gate stack is formed in the channel cut, wherein the formation of the gate stack includes replacing the remaining portion of the dummy gate and the remaining portion of the sacrificial layer of the multilayer stack with the gate stack, wherein the gate stack extends longitudinally in the second direction above the semiconductor layer and isolation structure of the multilayer stack, wherein the gate stack includes a gate dielectric and a gate electrode.

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