Semiconductor device and method of manufacturing semiconductor device

Abstract

This application relates to a semiconductor device and a method of manufacturing a semiconductor device. A semiconductor device is provided. The semiconductor device includes: a substrate including a cell region and a peripheral circuit region; a gate structure including a conductive layer and located in the cell region; an electrode stack including an electrode layer and located in the peripheral circuit region; a slit structure extending through the gate structure; a first electrode structure extending through the electrode stack and electrically connected to the electrode layer; a second electrode structure extending through the electrode stack and located at a height corresponding to the slit structure; and an insulating spacer surrounding the second electrode structure.

Description

Technical Field

[0001] This disclosure relates to an electronic device and a method of manufacturing an electronic device, and more specifically, to a semiconductor device and a method of manufacturing a semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices with memory cells stacked on the substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device may include: a substrate including a cell region and a peripheral circuit region; a gate structure including a conductive layer and located in the cell region; an electrode stack including an electrode layer and located in the peripheral circuit region; a slit structure extending through the gate structure; a first electrode structure extending through the electrode stack and electrically connected to the electrode layer; a second electrode structure extending through the electrode stack and located at a height corresponding to the slit structure; and an insulating spacer surrounding the second electrode structure.

[0004] According to one embodiment of the present disclosure, a semiconductor device may include: an electrode stack including an electrode layer; a first electrode structure extending through the electrode stack and electrically connected to the electrode layer; a second electrode structure extending through the electrode stack and including a material different from that of the first electrode structure; and an insulating spacer surrounding the second electrode structure.

[0005] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include the following steps: alternately stacking a first material layer and a second material layer on a substrate to form a laminate, the substrate including a cell region and a peripheral circuit region; forming an electrode via penetrating the laminate in the peripheral circuit region; forming an electrode sacrificial layer in the electrode via; forming a first slit penetrating the laminate in the cell region; forming a second slit penetrating the laminate in the peripheral circuit region; forming an insulating spacer in the second slit; forming a second electrode structure within the insulating spacer; forming first contact holes that expose the second material layers while opening the electrode vias by removing the electrode sacrificial layer; and forming a first electrode structure in the electrode vias. Attached Figure Description

[0006] Figures 1A to 1C This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0007] Figures 2A to 2C This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3A and Figure 3B This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B and Figure 7C This is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0011] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The drawings are schematic diagrams of various embodiments and intermediate structures. Thus, deviations in the illustrated configurations and shapes are expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present disclosure as defined in the appended claims.

[0012] Embodiments of this disclosure are described herein with reference to cross-sectional and / or plan views of the embodiments. However, the embodiments of this disclosure should not be construed as limiting the concept of the invention. While several embodiments of this disclosure will be shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and scope of this disclosure.

[0013] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the principles and scope of this disclosure, the first element described below may also be referred to as the second or third element.

[0014] To be further understood, when a component is referred to as "connected to" or "attached to" another component, that component can be directly on, directly connected to, or attached to the other component, or there can be one or more intermediate components. Furthermore, connection / attachment is not limited to physical connections but can also include non-physical connections, such as wireless connections.

[0015] Additionally, it will be understood that when an element is referred to as being “between” two elements, that element can be the only element between the two elements, or there can be one or more intermediate elements.

[0016] When the first element is referred to as being "above" the second element, it refers not only to the case where the first element is directly formed on the second element, but also to the case where a third element exists between the first and second elements. When the first element is referred to as being "on" the second element, it refers to the case where the first element is formed directly or indirectly on the second element or substrate.

[0017] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a lower or upper layer, or its extent may be less than that of the lower or upper layer. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers within a substrate, or may have one or more layers on, above, and / or below a substrate.

[0018] It should be understood that the accompanying drawings are simplified schematic diagrams of the described apparatus and may exclude well-known details in order to avoid obscuring the features of the implementation.

[0019] It should also be noted that, without departing from the scope of this disclosure, a feature present in one embodiment may be used in conjunction with one or more features in another embodiment.

[0020] It should also be noted that in the various figures, the same reference numerals denote the same elements.

[0021] As used herein, unless otherwise expressly indicated, the singular form is intended to include the plural form as well.

[0022] One embodiment of this disclosure provides a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0023] According to this technology, a semiconductor device with a stable structure and improved reliability can be provided.

[0024] In the following description, embodiments based on the technical spirit of this disclosure are described with reference to the accompanying drawings.

[0025] Figures 1A to 1C This is a view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 1A It is a floor plan (100-A). Figure 1B yes Figure 1A The A-A' section view (100-B), and Figure 1C yes Figure 1A B-B' section view (100-C).

[0026] Reference Figures 1A to 1C The semiconductor device 100 may include a substrate 105, a gate structure 110G1, an electrode stack 110G2, a residual stack 110S, a channel structure 120, a first contact via 130, a slit structure 140, a slit spacer 150, a second contact via 160, a first electrode structure 170, a second electrode structure 180, and an insulating spacer 190. The semiconductor device 100 may also include peripheral circuitry PC, a source structure SS, a first support SP1, a second support SP2, an interconnect structure IC, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a component isolation layer ISO.

[0027] The substrate 105 may include a cell region CR and a peripheral circuit region PCR. The cell region CR may be spaced apart from the peripheral circuit region PCR in a first direction I. However, the cell region CR is not limited to this and may be spaced apart from the peripheral circuit region PCR in a second direction II intersecting the first direction I. The cell region CR may be the region where a memory cell is located. The peripheral circuit region PCR may be the region where a peripheral circuit (PC), such as a transistor 1, is located.

[0028] The peripheral circuit PC can be located on the substrate 105. For example, the peripheral circuit PC can be located in the peripheral circuit region PCR. However, the peripheral circuit PC is not limited to this, and the peripheral circuit PC can be located in both the cell region CR and the peripheral circuit region PCR. The peripheral circuit PC may include transistor 1, capacitors, and similar electrical components. Transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. Here, the gate insulating layer 1C may be located between the gate electrode 1D and the substrate 105. A device isolation layer ISO may be located in the substrate 105, the active region may be defined by the device isolation layer ISO, and transistor 1 may be located in the active region.

[0029] The interconnect structure IC can be connected to the peripheral circuit PC. For example, at least one of the vias ICA (note that although a single example of a via ICA is shown for clarity, there can be several) can be connected to transistor 1. At least one of the vias ICA can interconnect with lines ICB (note that although a single example of an interconnect line ICB is shown for clarity, there can be several). Lines ICB can interconnect with vias ICA. The interconnect structure IC can include a conductive material such as tungsten. The first interlayer insulating layer IL1 can include an insulating material such as oxide.

[0030] Gate structure 110G1 may be located in cell region CR. Gate structure 110G1 may include alternating layers of first insulating layer 110A and conductive layer 110C1. Conductive layer 110C1 may be a gate line such as a source select line, word line, and drain select line. Source select transistors, memory cells, or drain select transistors may be located in the region where channel structure 120 and conductive layer 110C1 intersect. For example, at least one source select transistor, a plurality of memory cells, and at least one drain select transistor stacked along channel structure 120 may constitute a memory string. Conductive layer 110C1 may include a conductive material such as tungsten, molybdenum, or polysilicon.

[0031] Electrode stack 110G2 may be located in the peripheral circuit region PCR. Electrode stack 110G2 may include alternating layers of a first insulating layer 110A and an electrode layer 110C2. Here, electrode layer 110C2 may be located at a height corresponding to that of conductive layer 110C1. Electrode layer 110C2 may include a conductive material such as tungsten, molybdenum, or polycrystalline silicon.

[0032] The residual stack 110S may be located in the peripheral circuit region PCR. However, the residual stack 110S is not limited thereto, and the residual stack 110S1 may extend from the peripheral circuit region PCR to the unit region CR. The residual stack 110S may include an alternately stacked first insulating layer 110A and a second insulating layer 110B. Here, the second insulating layer 110B may be located at a height corresponding to the conductive layer 110C1 and the electrode layer 110C2. The first insulating layer 110A may include an insulating material such as an oxide. The second insulating layer 110B may include a sacrificial material such as a nitride.

[0033] The source structure SS can be located on the peripheral circuit PC. For example, the source structure SS can be located between the peripheral circuit PC and the gate structure 110G1, and between the peripheral circuit PC and the electrode stack 110G2. In other words, the source structure SS can extend from the peripheral circuit region PCR to the unit region CR. The source structure SS can be monolayer or multilayer. The source structure SS can include polysilicon and materials that perform similar functions.

[0034] The channel structure 120 can extend through the gate structure 110G1 into the source structure SS. Each of the channel structures 120 may include a channel layer 120A and a memory layer 120B surrounding the channel layer 120A. Each of the channel structures 120 may include an insulating core 120C in the channel layer 120A. Here, the channel layer 120A may be connected to the source structure SS.

[0035] Each of the first contact vias 130 can be connected to a conductive layer 110C1 of the gate structure 110G1. For example, the first contact vias 130 can be connected to the conductive layer 110C1 of the gate structure 110G1. The first contact vias 130 can extend through the second interlayer insulating layer IL2 and can be connected to the upper surface of the conductive layer 110C1. Here, the second interlayer insulating layer IL2 can be located on the gate structure 110G1. The first contact vias 130 can have different heights. The first contact vias 130 can include a conductive material such as tungsten, and the second interlayer insulating layer IL2 can include an insulating material such as oxide.

[0036] For reference, although the figure shows an example of gate structure 110G1 including a stepped structure, gate structure 110G1 may not include a stepped structure. In this case, the first contact via 130 may extend through gate structure 110G1 and may be connected to conductive layer 110C1.

[0037] The slit structure 140 may extend through the gate structure 110G1. For example, the slit structure 140 may extend through the gate structure 110G1 into the source structure SS. Here, the slit structure 140 may be a source contact structure. The slit structure 140 may have a line shape extending along a first direction I. The slit structure 140 may include at least one of a semiconductor material or a conductive material. For example, the slit structure 140 may include polysilicon.

[0038] The slit spacer 150 may surround the sidewall of the slit structure 140. The slit spacer 150 may prevent electrical connection between the slit structure 140 and the conductive layer 110C1. The slit spacer 150 may include an insulating material such as an oxide.

[0039] The second contact via 160 may be located in the cell region CR and the peripheral circuit region PCR. The second contact via 160 may be connected to at least one of the slit structure 140, the channel structure 120, or the first contact via 130. The second contact via 160 may include a conductive material such as tungsten.

[0040] The first support SP1 may be located in the peripheral circuit region PCR. The first support SP1 may extend through the electrode stack 110G2. The first support SP1 may be arranged along a first direction I and a second direction II. The first support SP1 may have a plug shape. During the fabrication of the semiconductor device, the first support SP1 may prevent or reduce bending of the electrode stack 110G2. The first support SP1 may include an insulating material such as an oxide.

[0041] The second support SP2 can be located in the peripheral circuit region PCR. The second support SP2 can be located between the electrode stack 110G2 and the residual stack 110S. The second support SP2 can extend in the second direction II. In other words, the second support SP2 can have a linear shape. During the fabrication of the semiconductor device, the second support SP2 can prevent the electrode stack 110G2 from forming in excess areas. In other words, the second support SP2 can ensure the area where the residual stack 110S is retained. Therefore, damage to the contact plugs extending through the residual stack 110S and electrically connected to the peripheral circuit PC can be prevented.

[0042] The first electrode structure 170 may be located in the peripheral circuit region PCR. The first electrode structure 170 may extend through the electrode stack 110G2. The first electrode structure 170 may be connected to the electrode layer 110C2 of the electrode stack 110G2. For example, the first electrode structure 170 may be electrically connected to the electrode layer 110C2. The first electrode structure 170 may be electrically connected to the peripheral circuit PC via an interconnect structure IC. The first electrode structure 170 may have a plug shape. The first electrode structure 170 may include a conductive material such as tungsten.

[0043] The second electrode structure 180 may be located in the peripheral circuit region PCR. The second electrode structure 180 may extend through the electrode stack 110G2. For example, the second electrode structure 180 may extend through the electrode stack 110G2 into the source structure SS. Here, the insulating spacer 190 may surround the sidewall of the second electrode structure 180. Furthermore, the second contact via 160 may be connected to at least one of the first electrode structure 170 or the second electrode structure 180.

[0044] The second electrode structure 180 may have a linear shape extending along the first direction I. The second electrode structure 180 may be located at a height corresponding to the slit structure 140. The second electrode structure 180 may include a material different from that of the first electrode structure 170. For example, the second electrode structure 180 may include polycrystalline silicon. The insulating spacer 190 may include an insulating material such as an oxide.

[0045] According to embodiments of this disclosure, in order to store a larger amount of data in a semiconductor device of limited size, the cell region CR can be increased and the peripheral circuit region PCR can be decreased. In this case, the area occupied by the capacitor in the peripheral circuit region PCR can be reduced. However, even if the peripheral circuit region PCR is limited, the first electrode structure 170, electrode layer 110C2, second electrode structure 180, and insulating spacer 190 of the peripheral circuit region PCR can also be used as capacitor CS. For example, the first electrode structure 170 and the electrode layer 110C2 connected to the first electrode structure 170 can be used as the first electrode of capacitor CS, the second electrode structure 180 can be used as the second electrode of capacitor CS, and the insulating spacer 190 can be used as the insulating layer of capacitor CS. Therefore, the capacitor CS, which is separate from the capacitor included in the peripheral circuit PC, can be configured in the limited area of ​​the peripheral circuit region PCR.

[0046] A first bias voltage can be applied to the first electrode structure 170. In this case, the first bias voltage can be applied to the electrode layer 110C2 connected to the first electrode structure 170. A second bias voltage, different from the first bias voltage, can be applied to the second electrode structure 180. In this way, the capacitor CS can be operated.

[0047] Furthermore, the capacitor CS may include multiple first electrode structures 170. In this case, when a first bias voltage is applied, the resistance can be reduced by applying the first bias voltage to each of the first electrode structures 170 individually. In other words, the resistance of the capacitor can be reduced by connecting the first electrode structures 170 in parallel.

[0048] According to the above structure, the capacitor CS can be located on or within the peripheral circuit PC. In other words, in addition to the capacitor included in the peripheral circuit PC, the first electrode structure 170, the electrode layer 110C2, the second electrode structure 180, and the insulating spacer 190 can also be used as the capacitor CS.

[0049] Figures 2A to 2C This is a view showing a semiconductor device 200 according to an embodiment of the present disclosure. Figure 2A It is a floor plan (200-A). Figure 2B yes Figure 2A The C-C' section view (200-B), and Figure 2C yes Figure 2A The D-D' section view (200-C). In the following text, aspects that overlap with the above content are omitted.

[0050] Reference Figures 2A to 2C The semiconductor device 200 may include a substrate 205, peripheral circuit PC, source structure SS, junction structure BS, gate structure 210G1, electrode stack 210G2, residual stack 210S, channel structure 220, first contact via 230, slit structure 240, slit spacer 250, second contact via 260, first electrode structure 270, second electrode structure 280, insulating spacer 290, first support SP1, second support SP2, element isolation layer ISO, first interconnect structure IC1, second interconnect structure IC2, third interconnect structure IC3, first interlayer insulating layer IL1, second interlayer insulating layer IL2, third interlayer insulating layer IL3, and fourth interlayer insulating layer IL4.

[0051] The peripheral circuit PC can be located on the substrate 205. Here, the substrate 205 may include a cell region CR and a peripheral circuit region PCR. The peripheral circuit PC may include a transistor 1. The transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. A device isolation layer ISO may be located in the substrate 205, the active region may be defined by the device isolation layer ISO, and the transistor 1 may be located in the active region.

[0052] The first interconnect structure IC1 may be located on the peripheral circuit PC. The first interconnect structure IC1 may be located in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 may be located on the substrate 205. The first interconnect structure IC1 may include a first via ICA and a first line ICB. The first interconnect structure IC1 may include a conductive material such as tungsten. The first interlayer insulating layer IL1 may include an insulating material such as an oxide or nitride.

[0053] The bonding structure BS can be located on the peripheral circuit PC. For example, the bonding structure BS can be located on the first interconnect structure IC1. The bonding structure BS can include a first bonding pad BP1 and a second bonding pad BP2. The first bonding pad BP1 can be located in a first interlayer insulating layer IL1. The second bonding pad BP2 can be located on the first bonding pad BP1 and can be located in a second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 can be located on the first interlayer insulating layer IL1. The bonding structure BS can include a conductive material such as copper. The second interlayer insulating layer IL2 can include an insulating material such as an oxide or nitride.

[0054] The second interconnect structure IC2 may be located on the bonding structure BS. The second interconnect structure IC2 may be located within the second interlayer insulating layer IL2. The second interconnect structure IC2 may include a second via ICC and a second line ICD. Although not shown in the figure, the second interconnect structure IC2 may be connected to the bonding structure BS. The second interconnect structure IC2 may include a conductive material such as tungsten.

[0055] Gate structure 210G1 may be located in cell region CR. Gate structure 210G1 may include alternating layers of first insulating layer 210A and conductive layer 210C1. Channel structure 220 may extend through gate structure 210G into source structure SS. Here, source structure SS may be located on gate structure 210G. Each of channel structures 220 may include channel layer 220A, memory layer 220B surrounding channel layer 220A, and insulating core 220C in channel layer 220A. Channel layer 220A may be connected to source structure SS.

[0056] The first contact via 230 can extend through the third interlayer insulating layer IL3 and can be connected to the conductive layer 210C1 of the gate structure 210G1. Here, the third interlayer insulating layer IL3 can be located on the second interlayer insulating layer IL2.

[0057] The slit structure 240 may extend through the gate structure 210G1. The slit structure 240 may extend through the gate structure 210G1 into the fourth interlayer insulating layer IL4. Here, the fourth interlayer insulating layer IL4 may be located on the gate structure 210G1. The slit spacer 250 may surround the sidewall of the slit structure 240. The slit structure 240 may include at least one of an insulating material, a semiconductor material, or a conductive material.

[0058] Electrode stack 210G2 may be located in the peripheral circuit region of the PCR. Electrode stack 210G2 may include alternating layers of a first insulating layer 210A and an electrode layer 210C2. A first electrode structure 270 may extend through electrode stack 210G2. For example, the first electrode structure 270 may extend through electrode stack 210G2. A second electrode structure 280 may extend through electrode stack 210G2 into the source structure SS. Here, an insulating spacer 290 may surround the sidewall of the second electrode structure 280.

[0059] The residual laminate 210S may be located in the peripheral circuit region PCR. However, the residual laminate 210S is not limited thereto, and the residual laminate 210S may extend from the peripheral circuit region PCR to the unit region CR. The residual laminate 210S may include an alternately laminated first insulating layer 210A and a second insulating layer 210B.

[0060] The first support SP1 may extend through the electrode stack 210G2. The first support SP1 may have a plug shape. The second support SP2 may be located between the residual stack 210S and the electrode stack 210G2. The second support SP2 may have a line shape extending along the second direction II.

[0061] The second contact via 260 can be connected to at least one of the channel structure 220, the first contact via 230, the slit structure 240, the first electrode structure 270, and the second electrode structure 280. Here, the second contact via 260 can be located on the second interconnect structure IC2 and can be located in the third interlayer insulating layer IL3. At least one of the second contact vias 260 can be electrically connected to the bonding structure BS through the second interconnect structure IC2.

[0062] The third interconnect structure IC3 can be located on the gate structure 210G1, the electrode stack 210G2, and the residual stack 210S. The third interconnect structure IC3 can be connected to the source structure SS or the first electrode structure 270. Here, the third interconnect structure IC3 can be located in the fourth interlayer insulating layer IL4. The fourth interlayer insulating layer IL4 can be located on the source structure SS and can extend to a height corresponding to the source structure SS. For example, the fourth interlayer insulating layer IL4 can be located at a position corresponding to the first electrode structure 270 at a height corresponding to the source structure SS.

[0063] According to the above structure, the semiconductor device may include a bonding structure BS. The bonding structure BS may be located on the peripheral circuit PC, and the source structure SS may be located on the bonding structure BS. The bonding structure BS may be electrically connected to the peripheral circuit PC.

[0064] Figure 3A and Figure 3B Cross-sectional views (300-A and 300-B) of a semiconductor device 300 according to embodiments of the present disclosure are shown in different directions. In the following text, aspects overlapping with the above description are omitted.

[0065] Reference Figure 3A and Figure 3B The semiconductor device 300 may include a gate structure GS, an interlayer insulating layer IL, contact vias CT1 and CT2, and contact spacers CSP1 and CSP2.

[0066] Specific reference Figure 3A The gate structure GS may include alternating layers of insulating layers IS and conductive layers CL. The gate structure GS may include a stepped structure STR. The upper surface of at least one of the conductive layers CL of the gate structure GS may be in contact with an interlayer insulating layer IL. The interlayer insulating layer IL may include an insulating material such as an oxide.

[0067] Contact vias CT1 can extend through the interlayer insulating layer IL and the gate structure GS. Each of the contact vias CT1 can be connected to a conductive layer CL of the conductive layer GS. For example, each of the contact vias CT1 can include a body portion 310 and a protrusion 320 projecting from the body portion 310, and can be connected to a conductive layer CL through the protrusion 320. Here, the protrusion 320 of the contact via CT1 can be connected to the upper surface of the conductive layer CL. The contact vias CT1 can have substantially the same height. The contact vias CT1 can include a conductive material such as tungsten.

[0068] The contact spacer CSP1 can be located at a height corresponding to the conductive layer CL. The contact spacer CSP1 prevents the conductive layer CL from being electrically connected to the body portion 310 of the contact via CT1. Here, the contact spacer CSP1 can include an insulating material such as an oxide.

[0069] Refer again Figure 3B The gate structure GS may not include the stepped structure STR. Contact vias CT2 may extend through the gate structure GS. Each of the contact vias CT2 may be connected to a conductive layer CL of the gate structure GS. Each of the contact spacers CSP2 may surround a sidewall of the contact via CT2. The contact spacers CSP2 prevent residual conductive layers CL other than those connected to the contact via CT2 from being electrically connected to the contact via CT2. The contact vias CT2 may have different heights. The contact vias CT2 may include a conductive material such as tungsten, and the contact spacers CSP2 may include an insulating material such as oxide.

[0070] For reference, the gate structure GS can correspond to Figure 1B The gate structure 110G1 and Figure 2B The gate structure is 210G1. Furthermore, contact vias CT1 and CT2 can correspond to... Figure 1B First contact via 130 and Figure 2B The first contact via 230.

[0071] in other words, Figure 1B The gate structure 110G1 and Figure 2B The gate structure 210G1 may include a stepped structure STR. In this case, contact vias 130 and 230 may extend through interlayer insulating layers IL2 and IL3 and gate structures 110G1 and 210G1. Furthermore, each of contact vias 130 and 230 may include a body portion 310 and a protrusion 320 protruding from the body portion 310, and may be connected to one of the conductive layers 110C1 and 210C1 of gate structures 110G1 and 210G1 via the protrusion 320. Here, the contact spacer CSP1 may be located at a height corresponding to the conductive layers 110C1 and 210C1.

[0072] also, Figure 1B The gate structure 110G1 and Figure 2BThe gate structure 210G1 may not include the stepped structure STR. In this case, contact vias 130 and 230 may extend through the gate structures 110G1 and 210G1 and may be connected to one of the conductive layers 110C1 and 210C1 of the gate structures 110G1 and 210G1. Here, the contact spacer CSP2 may surround the sidewalls of the contact vias 130 and 230.

[0073] According to the above structure, the gate structure GS may include a stepped structure STR. Here, contact vias CT1 and CT2 may extend through the gate structure GS. Each of the contact vias CT1 may be connected to the conductive layer CL via a protrusion 320, and the contact spacer CPS1 may be located at a height corresponding to the conductive layer CL.

[0074] Furthermore, the gate structure GS may not include the stepped structure STR. Here, each of the contact vias CT2 may extend through the gate structure GS and may be connected to the conductive layer CL. The contact spacers CSP2 may surround the sidewalls of the contact vias CT2.

[0075] Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B , Figure 5C , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B and Figure 7C This is a view illustrating a method of manufacturing a semiconductor device 400 according to an embodiment of the present disclosure.

[0076] Figure 4A , Figure 5A , Figure 6A and Figure 7A These are floor plans, Figure 4B , Figure 5B , Figure 6B and Figure 7B They are respectively the corresponding Figure 4A , Figure 5A , Figure 6A and Figure 7A The E-E' section view, and Figure 4C , Figure 5C , Figure 6C and Figure 7C They are respectively the corresponding Figure 4A , Figure 5A , Figure 6A and Figure 7A The F-F' cross-sectional view. In the following text, aspects overlapping with the above are omitted.

[0077] Reference Figures 4A to 4C (Steps 400-1-A to 400-1-C of the method for manufacturing semiconductor device 400) allow for the formation of peripheral circuitry PC on a substrate 405 comprising a cell region CR and a peripheral circuitry region PCR. The peripheral circuitry PC may include transistor 1, capacitors, etc. Transistor 1 may include junctions 1A and 1B, a gate electrode 1D, and a gate insulating layer 1C. Here, the gate insulating layer 1C may be located between the gate electrode 1D and the substrate 405. A device isolation layer ISO may be located in the substrate 405, an active region may be defined by the device isolation layer ISO, and transistor 1 may be located in the active region.

[0078] Subsequently, an interconnect structure IC can be formed on the peripheral circuit PC. The interconnect structure IC can be formed in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be formed on the substrate 405. The interconnect structure IC may include vias ICA and lines ICB.

[0079] The interconnect structure IC can be connected to the peripheral circuit PC. For example, at least one of the vias ICA can be connected to transistor 1. At least one of the vias ICA can interconnect with the lines ICB. The lines ICB can interconnect with the vias ICA. The interconnect structure IC1 can include a conductive material such as tungsten. The first interlayer insulating layer IL1 can include an insulating material such as oxide.

[0080] Subsequently, a stack 410S can be formed on the substrate 405. For example, the stack 410S can be formed by alternately stacking a first material layer 410A and a second material layer 410B. Here, the stack 410S formed in the cell region CR can have a stepped structure in which the upper surface of the second material layer 410B is exposed. In this case, a second interlayer insulating layer IL2 can be formed on the stepped structure. However, the stack 410S is not limited to this, and the stack 410S may not include the stepped structure. The first material layer 410A may include an insulating material such as an oxide, and the second material layer 410B may include a sacrificial material such as a nitride.

[0081] Before forming the laminate 410S, a source structure SS can be formed on the substrate 405. Here, the source structure SS can extend from the cell region CR to the peripheral circuit region PCR. The source structure SS can be partially removed in the peripheral circuit region PCR. For example, considering the region where the first electrode structure is to be formed, a portion of the source structure SS can be removed. In this case, an interlayer insulating layer IL1 can be formed in the region where the source structure SS is removed. The source structure SS can include polysilicon and / or materials that perform similar functions in the semiconductor device 400.

[0082] In the cell region CR, a channel structure 420 extending through the laminate 410S can be formed. For example, a channel structure 420 extending through the laminate 410S into the source structure SS can be formed. Here, the channel structure 420 can be arranged along a first direction I and a second direction II intersecting the first direction I. Each of the channel structures 420 may include a channel layer 420A, a memory layer 420B surrounding the channel layer 420A, and an insulating core 420C in the channel layer 420A.

[0083] In the peripheral circuit region PCR, a first support SP1 and a second support SP2 extending through the laminate 410S can be formed. First, a first support hole SPH1 and a second support hole SPH2 extending through the laminate 410S can be formed. Here, the first support hole SPH1 can have a plug shape, and the second support hole SPH2 can have a line shape extending along a second direction II. Subsequently, an insulating material such as an oxide can be formed in the first support hole SPH1 and the second support hole SPH2. Therefore, the first support SP1 can be formed in the first support hole SPH1, and the second support SP2 can be formed in the second support hole SPH2.

[0084] In peripheral circuit region PCR, an electrode sacrificial layer 470S extending through the laminate 410S can be formed. First, an electrode aperture CDH extending through (e.g., penetrating) the laminate 410S can be formed. A first support aperture SPH1 and a second support aperture SPH2 can be formed by forming the electrode aperture CDH. Subsequently, an insulating material such as an oxide can be formed in the electrode aperture CDH. The electrode sacrificial layer 470S can be formed in the electrode aperture CDH. The electrode sacrificial layer 470S can be formed when the first support SP1 and the second support SP2 are formed.

[0085] Reference Figures 5A to 5C (Steps 400-2-A to 400-2-C of the method for manufacturing semiconductor device 400) may include forming a first slit SL1 extending through the stacked member 410S in the cell region CR. A second slit SL2 extending through the stacked member 410S in the peripheral circuit region PCR may also be formed. The second slit SL2 may be formed while the first slit SL1 is being formed. Here, the first slit SL1 and the second slit SL2 may have a line shape extending along a first direction I.

[0086] Subsequently, a first opening OP1 can be formed by removing the second material layer 410B of the stack 410S via the first slit SL1. A third material layer 410C can then be formed in the first opening OP1. Here, the third material layer 410C of the cell region CR can serve as a conductive layer. Therefore, a gate structure 410G1 in which the first material layer 410A and the third material layer 410C are alternately stacked can be formed. Subsequently, a source opening can be formed by removing a portion of the source structure SS via the first slit SL1. After exposing the channel layer 420A by partially etching the memory layer 420B of the channel structure 420 via the source opening, the source structure SS and the channel layer 420A can be connected by forming a semiconductor material in the source opening.

[0087] The second opening OP2 can be formed by removing the second material layer 410B of the laminate 410S via the second slit SL2. The second opening OP2 can be formed while the first opening OP1 is being formed. Subsequently, a third material layer 410C can be formed in the second opening OP2. Here, the third material layer 410C of the peripheral circuit region PCR can be used as an electrode layer. In other words, the third material layer 410C can be used as an electrode for the capacitor CS. Therefore, an electrode laminate 410G2 in which the first material layer 410A and the third material layer 410C are alternately laminated can be formed.

[0088] When the second material layer 410B includes a conductive material, the step of replacing the second material layer 410B with a third material layer 410C can be omitted. In this case, the stacked unit 410S of the cell region CR can be used as the gate structure 410G1, and the stacked unit 410S of the peripheral circuit region PCR can be used as the electrode stacked unit 410G2.

[0089] The portion of the laminate 410S that is not formed as the electrode laminate 410G2 can be defined as a residual laminate. The linear second support SP2 prevents the electrode laminate 410G2 from extending into an excessive area. In other words, the second support SP2 ensures that the residual laminate is retained in the designated area. In this case, even if a contact plug extending through the residual laminate to electrically connect to the peripheral circuit PC is formed, electrical connection of the contact plug to the electrode laminate 410G2 is prevented.

[0090] Subsequently, a slit insulating layer can be formed in the first slit SL1. The source structure SS can then be exposed by etching the lower surface of the slit insulating layer. In this process, the slit insulating layer can be separated to form a slit spacer 450. Here, the slit spacer 450 may include an insulating material such as an oxide. Subsequently, a slit structure 440 can be formed in the first slit SL1. Here, the slit structure 440 may include polysilicon and / or a material that performs a similar function.

[0091] An insulating layer can be formed in the second slit SL2. Subsequently, the source structure SS can be exposed by etching the lower surface of the insulating layer. In this process, the insulating layer can be separated to form an insulating spacer 490. An insulating layer can be formed when the slit insulating layer is formed. Furthermore, the insulating spacer 490 can be formed when the slit spacer 450 is formed. Subsequently, a second electrode structure 480 can be formed in the second slit SL2. The second electrode structure 480 can be formed when the slit structure 440 is formed. Here, the second electrode structure 480 can be used as an electrode of the capacitor CS.

[0092] Reference Figures 6A to 6C (Steps 400-3-A to 400-3-C of the method for manufacturing semiconductor device 400) may involve forming first contact holes CTH1 that expose a third material layer 410C of the gate structure 410G1 in the cell region CR. In other words, before forming the third material layer 410C, first contact holes CTH1 may be formed that expose locations where a second material layer 410B is formed. For example, the first contact holes CTH1 may be formed by etching a second interlayer insulating layer IL2. Subsequently, first contact vias 430 may be formed in the first contact holes CTH1. For example, the first contact vias 430 may be formed by forming a conductive material such as tungsten in the first contact holes CTH1.

[0093] The electrode via CDH can be opened by removing the electrode sacrificial layer 470S in the peripheral circuit region PCR. The electrode via CDH can be formed when the first contact via CTH1 is formed. For example, the electrode sacrificial layer 470S can be removed when the interlayer insulating layer IL2 is etched. Subsequently, a first electrode structure 475 can be formed in the electrode via CDH. The first electrode structure 475 can be formed when the first contact via 430 is formed. The first electrode structure 475 may include a conductive material such as tungsten. Here, the first electrode structure 475 can be used as an electrode of a capacitor CS.

[0094] According to one embodiment of this disclosure, the first electrode structure 475, electrode layer, second electrode structure 480, and insulating spacer 490 of the peripheral circuit region PCR can be used as a capacitor CS. For example, the first electrode structure 475 and the electrode layer 310C2 connected to the first electrode structure 475 can be used as the first electrode of the capacitor CS, the second electrode structure 480 can be used as the second electrode of the capacitor CS, and the insulating spacer 490 can be used as the insulating layer of the capacitor CS. Therefore, a capacitor CS separate from the capacitor included in the peripheral circuit PC can be configured in the limited area of ​​the peripheral circuit region PCR.

[0095] Reference Figures 7A to 7C(Steps 400-4-A to 400-4-C of the method for manufacturing semiconductor device 400) include forming a second contact via 460 in the third interlayer insulating layer IL3. For example, the second contact via 460 may be formed in the cell region CR and the peripheral circuit region PCR. Here, the third interlayer insulating layer IL3 may be formed on the gate structure 410G1, the electrode stack 410G2, and the residual stack. First, a second contact hole CTH2 may be formed, exposing at least one of the channel structure 420, the first contact via 430, the slit structure 440, the first electrode structure 475, and the second electrode structure 480. Subsequently, the second contact via 460 may be formed in the second contact hole CTH2. Here, the second contact via 460 may comprise a conductive material such as tungsten.

[0096] According to the manufacturing method described above, the capacitor CS formed in the peripheral circuit region PCR can be formed by utilizing the process of forming a structure in the cell region CR. In other words, when forming the structure of the cell region CR, the structure for forming the capacitor CS can be formed simultaneously. Therefore, by unifying the processes of the cell region CR and the peripheral circuit region PCR, the manufacturing cost of the semiconductor device can be reduced.

[0097] For example, when forming the first support hole SPH1 and the second support hole SPH2, an electrode hole CDH can be formed. When forming the first support SP1 and the second support SP2, an electrode sacrificial layer 470S can be formed. When forming the first slit SL1, a second slit SL2 can be formed. When forming the conductive layer, an electrode layer can be formed. When forming the slit structure 440, a second electrode structure 480 can be formed.

[0098] In addition to the capacitors included in the peripheral circuit PC, the first electrode structure 475, the electrode layer, the second electrode structure 480, and the insulating spacer 490 can also be used as capacitors CS.

[0099] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following text, content overlapping with the above description is omitted.

[0100] Reference Figure 8A and Figure 8B This allows the formation of peripheral circuit wafers (PWFs). For example, a peripheral circuit wafer (PWF) including a peripheral circuit PC and a first bonding pad BP1 can be formed.

[0101] First, peripheral circuit PC can be formed on peripheral circuit substrate 700A. Here, peripheral circuit substrate 700A may include cell region CR and peripheral circuit region PCR. Figure 8A The cell region CR of the peripheral circuit board 700A is shown, and Figure 8B The peripheral circuit region PCR of the peripheral circuit board 700A is shown.

[0102] Subsequently, a first interconnect structure IC1 can be formed on the peripheral circuit PC. The first interconnect structure IC1 can be formed in a first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be formed on the peripheral circuit substrate 700A. The first interconnect structure IC1 may include a first via ICA and a first line ICB. The first interconnect structure IC1 can be connected to the peripheral circuit PC. For example, at least one of the first vias ICA can be connected to the peripheral circuit PC.

[0103] Subsequently, a first bonding pad BP1 can be formed on the first interconnect structure IC1. The first bonding pad BP1 can be formed in the first interlayer insulating layer IL1. The first bonding pad BP1 can be connected to the first interconnect structure IC1. For example, at least one of the first bonding pads BP1 can be connected to the first via ICA. The first bonding pad BP1 can include a conductive material such as copper.

[0104] Reference Figure 9A and Figure 9B This allows for the formation of unit wafers (CWFs). For example, a unit wafer CWF can be formed that includes a second bonding pad BP2, a first electrode structure 770, an electrode layer, a second electrode structure 780, and an insulating spacer 790.

[0105] For reference only. Figure 9A and Figure 9B The state in which the unit wafer CWF is rotated can be shown. Therefore, in the description of this disclosure, terms such as above and below used to describe the positional relationship between structures are for ease of description and can be used to describe the state in which the unit wafer CWF is not rotated.

[0106] The unit substrate 700B may include a unit area and a peripheral circuit area. Figure 9A The cell region of the cell substrate 700B is shown, and Figure 9B The peripheral circuit area of ​​the unit substrate 700B is shown.

[0107] A stacked component 710S, a gate structure 710G1, an electrode stacked component 710G2, a channel structure 720, a first contact via 730, a slit structure 740, a slit spacer 750, a second contact via 760, a first electrode structure 770, a second electrode structure 780, an insulating spacer 790, a first support SP1, and a second support SP2 can be formed on the unit substrate 700B.

[0108] The channel structure 720 extends through the gate structure 710G1 into the cell substrate 700B. The slit structure 740 and the slit spacer 750 extend through the gate structure 710G1 into the cell substrate 700B. The first electrode structure 770 extends through the electrode stack 710G2 into the cell substrate 700B. The second electrode structure 780 and the insulating spacer 790 extend through the electrode stack 710G2 into the cell substrate 700B. Here, the first electrode structure 770, the electrode layer, the second electrode structure 780, and the insulating spacer 790 of the cell wafer CWF can serve as a capacitor CS.

[0109] Furthermore, the method of forming the laminate 710S, gate structure 710G1, electrode laminate 710G2, channel structure 720, first contact via 730, slit structure 740, slit spacer 750, second contact via 760, first electrode structure 770, second electrode structure 780, insulating spacer 790, first support SP1, and second support SP2 on the unit substrate 700B can be compared with the method of forming the laminate 710S, gate structure 710G1, electrode laminate 710G2, channel structure 720, first contact via 730, slit structure 740, slit spacer 750, second contact via 760, first electrode structure 770, second electrode structure 780, insulating spacer 790, first support SP1, and second support SP2 on the unit substrate 700B. Figures 4A to 7C The methods for forming the stacked component 410S, gate structure 410G1, electrode stacked component 410G2, channel structure 420, first contact via 430, slit structure 440, slit spacer 450, second contact via 460, first electrode structure 475, second electrode structure 480, insulating spacer 490, first support SP1 and second support SP2 are the same or similar.

[0110] Subsequently, a second interconnect structure IC2 can be formed on the second contact via 760. The second interconnect structure IC2 may include a second via ICC and a second line ICD. The second interconnect structure IC2 can be formed in a third interlayer insulating layer IL3. The third interlayer insulating layer IL3 can be formed on the second interlayer insulating layer IL2. The second interconnect structure IC2 can be connected to the second contact via 760. For example, at least one of the second vias ICC can be connected to the second contact via 760.

[0111] Subsequently, a second bonding pad BP2 can be formed on the second interconnect structure IC2. The second bonding pad BP2 can be connected to the second interconnect structure IC2. For example, at least one of the second bonding pads BP2 can be connected to the second via ICC. The second bonding pad BP2 can include a conductive material such as copper.

[0112] Reference Figure 10A and Figure 10B The peripheral circuit wafer (PWF) and the unit wafer (CWF) can be bonded. For example, the first bonding pad BP1 and the second bonding pad BP2 can be bonded. Therefore, the peripheral circuit wafer (PWF) and the unit wafer (CWF) can be electrically connected.

[0113] Subsequently, the unit substrate 700B can be removed. In this case, the channel structure 720, slit structure 740, slit spacer 750, first electrode structure 770, second electrode structure 780, and insulating spacer 790 can be exposed.

[0114] Subsequently, the channel layer 720A can be exposed by partially removing the memory layer 720B of the channel structure 720. Then, a source structure SS can be formed on the channel structure 720. Here, the channel layer 720A can be connected to the source structure SS. Furthermore, the source structure SS can be formed on the second electrode structure 780. Here, the first electrode structure 770 can be exposed.

[0115] Subsequently, a fourth interlayer insulating layer IL4 can be formed on the source structure SS. Then, a third interconnect structure IC3 can be formed. The third interconnect structure IC3 may include a third via ICE and a third line ICF. The third interconnect structure IC3 can be connected to at least one of the source structure SS or the first electrode structure 770. For example, at least one of the third via ICE can be connected to at least one of the source structure SS or the first electrode structure 770.

[0116] According to the above manufacturing method, a peripheral circuit wafer (PWF) including a first bonding pad BP1 and a unit wafer (CWF) including a second bonding pad BP2 can be formed. Subsequently, the peripheral circuit wafer (PWF) and the unit wafer (CWF) can be electrically connected by bonding the first bonding pad BP1 and the second bonding pad BP2.

[0117] Furthermore, a capacitor can be formed on the peripheral circuit PC of the peripheral circuit wafer PWF, and the first electrode structure 770, the electrode layer, the second electrode structure 780, and the insulating spacer 790 can be used as the capacitor CS on the unit wafer CWF. Therefore, the capacitor CS can be formed in a region other than the limited area of ​​the peripheral circuit PC.

[0118] Although embodiments according to the technical spirit of this disclosure have been described with reference to the accompanying drawings, this is merely for illustrating embodiments according to the concepts of this disclosure, and this disclosure is not limited to the described embodiments. Within the scope of the technical spirit of this disclosure as described in the claims, those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and alterations to the embodiments, and such substitutions, modifications, and alterations also fall within the scope of this disclosure.

[0119] Cross-references to related applications

[0120] This application claims priority to Korean Patent Application No. 10-2025-0012428, filed on January 31, 2025, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A substrate, comprising a cell region and a peripheral circuit region; A gate structure, the gate structure including a conductive layer and located in the cell region; An electrode stack comprising an electrode layer and located in the peripheral circuit region; A slit structure that extends through the gate structure; A first electrode structure extends through the electrode layer stack and is electrically connected to the electrode layer; A second electrode structure extends through the electrode stack and is located at a height corresponding to the slit structure; as well as An insulating spacer surrounds the second electrode structure.

2. The semiconductor device according to claim 1, wherein The first electrode structure, the electrode layer, the second electrode structure, and the insulating spacer are used as a capacitor.

3. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: Peripheral circuitry located on the substrate; A source structure located on the peripheral circuit; A channel structure that extends through the gate structure into the source structure; as well as The first contact via is connected to the conductive layer.

4. The semiconductor device according to claim 3, wherein The second electrode structure extends through the electrode stack into the source structure.

5. The semiconductor device according to claim 4, wherein, The source structure is located between the peripheral circuit and the gate structure, and between the peripheral circuit and the electrode stack.

6. The semiconductor device according to claim 4, wherein, The source structure is located on the gate structure and the electrode stack.

7. The semiconductor device of claim 6, further comprising a bonding structure located between the peripheral circuit and the gate structure and between the peripheral circuit and the electrode stack.

8. The semiconductor device of claim 3, further comprising a second contact via connected to the slit structure and the second electrode structure respectively.

9. The semiconductor device according to claim 1, in, Each of the slit structure and the second electrode structure has a line shape extending along a first direction, and The first electrode structure has a plug shape.

10. The semiconductor device of claim 1, further comprising a residual stack located in the peripheral circuit region and at a height corresponding to the electrode stack.

11. The semiconductor device of claim 10, further comprising: A first support member extends through the electrode stack and is arranged along a first direction and a second direction intersecting the first direction; as well as A second support member extends along the second direction and is located between the electrode stack and the residual stack.

12. The semiconductor device according to claim 1, wherein, The first electrode structure and the second electrode structure are made of different materials.

13. The semiconductor device according to claim 12, in, The first electrode structure comprises tungsten, and The second electrode structure comprises polycrystalline silicon.

14. A semiconductor device, the semiconductor device comprising: An electrode stack comprising an electrode layer; A first electrode structure extends through the electrode layer stack and is electrically connected to the electrode layer; A second electrode structure extends through the electrode stack and comprises a material different from that of the first electrode structure; as well as An insulating spacer surrounds the second electrode structure.

15. The semiconductor device according to claim 14, wherein, The first electrode structure, the electrode layer, the second electrode structure, and the insulating spacer are used as a capacitor.

16. The semiconductor device of claim 14, further comprising: A substrate, comprising a cell region and a peripheral circuit region; A gate structure located in the cell region and at a height corresponding to the electrode stack; A slit structure that extends through the gate structure; as well as A channel structure that extends through the gate structure.

17. The semiconductor device according to claim 16, wherein, The second electrode structure is located at a height corresponding to the slit structure.

18. The semiconductor device of claim 16, further comprising: Peripheral circuitry located on the substrate; as well as A source structure located on the peripheral circuit.

19. The semiconductor device according to claim 18, wherein, The second electrode structure extends through the electrode stack into the source structure.

20. The semiconductor device of claim 19, wherein, The source structure is located between the peripheral circuit and the gate structure, and between the peripheral circuit and the electrode stack.

21. The semiconductor device according to claim 19, wherein, The source structure is located on the gate structure and the electrode stack.

22. The semiconductor device of claim 21, further comprising a bonding structure located between the peripheral circuit and the gate structure and between the peripheral circuit and the electrode stack.

23. The semiconductor device according to claim 16, in, Each of the slit structure and the second electrode structure has a line shape extending along a first direction, and The first electrode structure has a plug shape.

24. The semiconductor device of claim 14, further comprising a unit stack located at a height corresponding to the electrode stack.

25. The semiconductor device of claim 24, further comprising: A first support member extends through the electrode stack and is arranged along a first direction and a second direction intersecting the first direction; as well as A second support member extends along the second direction and is located between the electrode stack and the unit stack.

26. The semiconductor device according to claim 14, in, The first electrode structure comprises tungsten, and The second electrode structure comprises polycrystalline silicon.

27. A method for manufacturing a semiconductor device, the method comprising the following steps: A first material layer and a second material layer are alternately stacked on a substrate to form a laminate, the substrate including a unit region and a peripheral circuit region; Electrode holes penetrating the laminate are formed in the peripheral circuit region; An electrode sacrificial layer is formed in the electrode hole; A first slit penetrating the laminate is formed in the unit region; A second slit penetrating the laminate is formed in the peripheral circuit region; An insulating spacer is formed in the second slit; A second electrode structure is formed within the insulating spacer; First contact holes are formed to expose the second material layer, while the electrode holes are opened by removing the electrode sacrificial layer; as well as A first electrode structure is formed in the electrode hole.

28. The method of claim 27, further comprising the following steps: The second material layer is removed through the second slit to form the second opening; as well as An electrode layer is formed in the second opening to form an electrode layer stack.

29. The method of claim 28, further comprising the following steps: The second material layer is removed through the first slit to form the first opening; as well as A conductive layer is formed in the first opening to form a gate structure.

30. The method according to claim 29, wherein, The second opening is formed when the first opening is formed.

31. The method according to claim 29, wherein, The electrode layer is formed during the formation of the conductive layer.

32. The method according to claim 28, wherein, The first electrode structure, the electrode layer, the second electrode structure, and the insulating spacer are used as a capacitor.

33. The method according to claim 28, further comprising the following steps: Peripheral circuitry is formed on the substrate; and Before forming the stacked components, a source structure is formed on the peripheral circuit.

34. The method according to claim 33, wherein, The second electrode structure is formed to extend through the electrode stack into the source structure.

35. The method according to claim 29, further comprising the following steps: Forming a peripheral circuit wafer including peripheral circuitry and a first bonding pad; Forming a unit wafer comprising a second bonding pad, the substrate, the first electrode structure, the electrode layer, the second electrode structure, and the insulating spacer; as well as Join the first bonding pad and the second bonding pad.

36. The method of claim 35, further comprising the following steps: Remove the substrate; and A source structure is formed on the gate structure.

37. The method of claim 27, further comprising the following steps: A support extending through the laminate is formed in the peripheral circuit region; A slit spacer is formed in the first slit; A slit structure is formed within the slit spacer; as well as A first contact via is formed in the first contact hole.

38. The method according to claim 37, wherein, The electrode sacrificial layer is formed during the formation of the support.

39. The method according to claim 37, wherein, The second slit is formed when the first slit is formed.

40. The method of claim 37, wherein, The insulating spacer is formed during the formation of the slit spacer.

41. The method according to claim 37, wherein, The second electrode structure is formed during the formation of the slit structure.

42. The method according to claim 37, wherein, The first electrode structure is formed when the first contact via is formed.

43. The method of claim 37, further comprising the following steps: Forming a channel structure that extends through the laminated member; A second contact hole is formed, which exposes the slit structure and the second electrode structure, respectively; as well as A second contact via is formed in the second contact hole.

44. The method of claim 27, wherein, The first slit and the second slit are formed to extend along a first direction.

45. The method according to claim 27, wherein, The first electrode structure and the second electrode structure are made of different materials.

46. ​​The method according to claim 45, in, The first electrode structure comprises tungsten, and The second electrode structure comprises polycrystalline silicon.

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