Solar cell and photovoltaic module

Abstract

This application relates to the field of solar cells, and provides a solar cell and a photovoltaic module. The solar cell includes: a substrate; a first tunneling dielectric layer located on a portion of the substrate surface; a first polycrystalline silicon layer located on the surface of the first tunneling dielectric layer, at least a portion of the first polycrystalline silicon layer being doped with aluminum; the aluminum doping concentration in the portion of the first polycrystalline silicon layer closer to the substrate is lower than the aluminum doping concentration in the portion of the first polycrystalline silicon layer farther from the substrate; and a first passivation layer located on the surface of the first polycrystalline silicon layer. The solar cell and photovoltaic module provided in this application can at least improve the photoelectric conversion efficiency of the cell.

Description

[0001] This application is a divisional application of the patent application filed on August 30, 2024, application number: 202411215347.8, entitled "Solar Cell and Photovoltaic Module". Technical Field

[0002] This application relates to the field of solar cells, and particularly to a solar cell and a photovoltaic module. Background Technology

[0003] Currently, with the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts sunlight into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient utilization of electrical energy.

[0004] Current solar cells mainly include IBC cells (Interdigitated Back Contact), TOPCON (Tunnel Oxide Passivated Contact) cells, PERC cells (Passivated emitter and real cell), and heterojunction cells. Different film layer configurations and functional limitations are used to reduce optical losses and decrease photogenerated carrier recombination on and within the silicon substrate, thereby improving the photoelectric conversion efficiency of solar cells.

[0005] However, the photoelectric conversion efficiency of current solar cells is still unsatisfactory. Summary of the Invention

[0006] This application provides a solar cell and a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the solar cell.

[0007] According to some embodiments of this application, one aspect of this application provides a solar cell, comprising: a substrate; a first tunneling dielectric layer located on a portion of the substrate surface; a first polycrystalline silicon layer located on the surface of the first tunneling dielectric layer, wherein at least a portion of the first polycrystalline silicon layer is doped with aluminum; the doping concentration of aluminum in the portion of the first polycrystalline silicon layer near the substrate is less than the doping concentration of aluminum in the portion of the first polycrystalline silicon layer away from the substrate; and a first passivation layer located on the surface of the first polycrystalline silicon layer.

[0008] In some embodiments, the aluminum doping concentration is 1 × 10⁻⁶. 18 cm -3 ~1×1021 cm -3 .

[0009] In some embodiments, the thickness of the first polycrystalline silicon layer is 20 nm to 500 nm.

[0010] In some embodiments, the invention further includes an alumina layer located on the surface of the first polysilicon layer and between the first polysilicon layer and the first passivation layer.

[0011] In some embodiments, the doping concentration of aluminum in the first polysilicon layer decreases along a third direction, where the third direction is the thickness direction of the first polysilicon layer and the direction pointing towards the substrate.

[0012] In some embodiments, the substrate has a metal region and a non-metal region, and further includes: a semiconductor layer located in the metal region, the semiconductor layer being doped with a P-type dopant; a first tunneling dielectric layer located in the non-metal region, the first polysilicon layer including: a first polysilicon portion located on a portion of the surface of the first tunneling dielectric layer, the first polysilicon portion being doped with the aluminum element; and a second polysilicon portion adjacent to the first polysilicon portion and located on the remaining portion of the surface of the first tunneling dielectric layer, the second polysilicon portion being doped with the P-type dopant, the concentration of the P-type dopant in the second polysilicon portion being less than or equal to the concentration of the P-type dopant in the semiconductor doped layer.

[0013] In some embodiments, the second polysilicon portion and the first polysilicon portion are arranged alternately along a first direction, the two ends of the first polysilicon portion along a second direction are respectively in contact with two adjacent semiconductor doped layers, and the two ends of a portion of the second polysilicon portion are respectively in contact with two adjacent semiconductor doped layers.

[0014] In some embodiments, the second polysilicon portion is located between the semiconductor doped layer and the first polysilicon portion.

[0015] In some embodiments, the area of ​​the first polysilicon portion in the first polysilicon layer is greater than or equal to 60%.

[0016] According to some embodiments of this application, another aspect of this application provides a photovoltaic module, including: a battery string, the battery string being composed of a plurality of solar cells as described in any of the above embodiments; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film facing away from the battery string.

[0017] The technical solution provided in this application has at least the following advantages: In the solar cell provided in this application embodiment, aluminum is doped into the first polycrystalline silicon layer. Aluminum has low solid solubility in polycrystalline silicon, making it relatively easy to obtain a first polycrystalline silicon layer with a low aluminum doping concentration. This avoids recombination losses caused by high doping concentrations in the non-metallic region. Furthermore, the aluminum-containing first polycrystalline silicon layer has good gettering properties (high minority carrier lifetime), allowing for better passivation of the substrate and thus improving the photoelectric conversion efficiency of the cell. Attached Figure Description

[0018] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A cross-sectional view of a solar cell provided in an embodiment of this application; Figure 2 A top view of the first surface of a solar cell provided in an embodiment of this application; Figure 3 Another top view of the first surface of a solar cell provided in an embodiment of this application; Figure 4 Another top view of the first side of a solar cell provided in an embodiment of this application; Figure 5 Another cross-sectional view of a solar cell provided in an embodiment of this application; Figures 6 to 12 A cross-sectional view of the solar cell corresponding to each step in the method for preparing a solar cell according to another embodiment of this application; Figure 13 A cross-sectional view of a stacked battery provided in yet another embodiment of this application; Figure 14 This is a schematic diagram of a photovoltaic module provided in another embodiment of the present application; Figure 15 for Figure 14 A cross-sectional view along section M1-M2. Detailed Implementation

[0020] As can be seen from the background technology, the photoelectric conversion efficiency of current solar cells is not good.

[0021] This application provides a solar cell and a photovoltaic module, wherein a first polycrystalline silicon layer doped with aluminum is formed in the non-metallic region of the solar cell to reduce the recombination rate and improve the photoelectric conversion efficiency.

[0022] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0025] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0026] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0027] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0028] In the accompanying drawings corresponding to the embodiments of the wood application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component may be "directly" located on the surface of the other component, or there may be a third component between the two components. Conversely, when describing a component on the surface of another component, or when another component is formed or disposed on the surface of a component, it indicates that there is no third component between the two components. Furthermore, when describing a component as being "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0029] In the description of the embodiments of this application, when a component "includes" another component, other components are not excluded unless otherwise stated, and other components may be further included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component may be present therein. Moreover, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located therein.

[0030] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "part" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] Figure 1 This is a cross-sectional view of a solar cell provided in an embodiment of this application.

[0033] According to some embodiments of this application, one aspect of this application provides a solar cell. (Reference) Figure 1 The solar cell includes a substrate 100, the surface of which has alternating metal regions 11 and non-metal regions 12. The solar cell includes a semiconductor doped layer 112 located on the surface of the substrate 100 corresponding to the metal regions 11, and the semiconductor doped layer 112 contains a p-type dopant element. The solar cell includes a first tunneling dielectric layer 121 located on the surface of the substrate 100 corresponding to the non-metal regions 12. The solar cell includes a first polycrystalline silicon layer 122 located on the surface of the first tunneling dielectric layer 121, and at least a portion of the first polycrystalline silicon layer 122 is doped with aluminum. The solar cell includes a first passivation layer 105 located on the surfaces of the semiconductor doped layer 112 and the first polycrystalline silicon layer 122. The solar cell includes a first electrode 106 located on the surface of the first passivation layer 105 corresponding to the metal regions 11, and the first electrode 106 is electrically connected to the semiconductor doped layer 112.

[0034] In the solar cell provided in this application embodiment, the solar cell has a metal region 11 and a non-metal region 12. The substrate 100 surface corresponding to the metal region 11 has a semiconductor doped layer 112. The P-type dopant in the semiconductor doped layer 112 can provide a large number of P-type ions, thus functioning as a PN junction to effectively generate and separate photogenerated carriers. The electrode is electrically connected to the semiconductor doped layer 112, resulting in low contact resistance and reduced electrical losses. The substrate 100 surface corresponding to the non-metal region 12 has a first tunneling dielectric layer 121 and a first polycrystalline silicon layer 122. The combined double passivation effect of the first tunneling dielectric layer 121 and the first polycrystalline silicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the photoelectric conversion efficiency. Furthermore, aluminum is doped into the first polycrystalline silicon layer 122. Aluminum has low solid solubility in polycrystalline silicon, making it relatively easy to obtain a first polycrystalline silicon layer 122 with a low doping concentration. The non-metal region 12 can avoid recombination losses caused by high doping concentrations. Moreover, the first polycrystalline silicon layer 122 containing aluminum has a better gettering degree (high minority carrier lifetime), which can better passivate the substrate 100, thereby improving the photoelectric conversion efficiency of the battery.

[0035] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0036] In some embodiments, the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen phosphate, perovskite, cadmium telluride, copper indium selenide, etc. The substrate 100 may also be a sapphire substrate 100, a silicon-on-insulator substrate 100, or a germanium-on-insulator substrate 100.

[0037] In some embodiments, the substrate 100 may be an N-type semiconductor substrate. The N-type semiconductor substrate 100 is doped with an N-type dopant element, which may be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0038] In some embodiments, the substrate 100 has a first side and a second side disposed opposite to each other. The solar cell is a single-sided cell, where the first side can serve as a light-receiving surface for receiving incident light, and the second side serves as a backlight surface. The backlight surface can also receive incident light, but its efficiency in receiving incident light is somewhat lower than that of the light-receiving surface.

[0039] In some embodiments, the metal region 11 refers to the region where the orthographic projection of the first electrode 106 onto the substrate 100 is located, and the non-metal region 12 refers to the region outside the orthographic projection of the first electrode 106 onto the substrate 100. To ensure that the film layer contacted by the first electrode 106 has a high doping concentration, or that the region contacted by the first electrode 106 is a high-concentration semiconductor doped layer 112, the area of ​​the metal region 11 is generally set to be greater than or equal to the area of ​​the orthographic projection of the first electrode 106 onto the substrate 100.

[0040] The conductivity type of the dopant elements in the semiconductor doped layer is different from that of the dopant elements in the substrate 100. If the substrate 100 is an N-type substrate, then the semiconductor doped layer is doped with P-type dopant elements.

[0041] In some embodiments, the semiconductor doped layer 112 is doped with boron. Boron has a high solid solubility in semiconductor materials, resulting in a high doping concentration in the semiconductor doped layer 112. As a locally heavily doped region, the semiconductor doped layer 112 can reduce the contact resistance between the first electrode 106 and the semiconductor doped layer 112, thus forming a good ohmic contact.

[0042] Boron has a relatively large segregation coefficient in silicon, resulting in uniform resistivity throughout the semiconductor doped layer 112 and consistent resistance values ​​across different regions. This allows for superior contact performance between the first electrode 106 and the semiconductor doped layer 112, reducing electrical losses. Furthermore, the high segregation coefficient of boron in silicon prevents the semiconductor doped layer 112 from having a low concentration, which would otherwise lead to a weak electric field in the formed PN junction, low carrier migration rates, and ultimately, reduced photoelectric conversion efficiency.

[0043] In some embodiments, the semiconductor doped layer 112 may be doped with other p-type doping elements, such as any one of group III elements such as aluminum (Al), gallium (Ga), or indium (In).

[0044] In some embodiments, the semiconductor doped layer 112 and the substrate 100 are the same initial substrate. After a diffusion process, part of the initial substrate is used as the semiconductor doped layer 112 and part of the initial substrate is used as the substrate 100. That is, there is no clear boundary between the substrate 100 and the semiconductor doped layer 112. Instead, the region formed by the PN junction is used as the distinction. That is, the substrate 100 is the N region and the semiconductor doped layer 112 is the P region.

[0045] In some embodiments, the semiconductor doped layer 112 is a film layer formed on the substrate 100 by a deposition process or an in-situ generation process, and then a diffusion layer is formed by in-situ doping or diffusion doping.

[0046] The first tunneling dielectric layer 121 and the first polysilicon layer 122 form a passivation contact structure. Due to the special band structure of the passivation contact structure, the first polysilicon layer 122 is electrically connected to the substrate, causing the energy band of the substrate to bend downward and reducing the electron transport barrier. Therefore, the ultrathin first tunneling dielectric layer can allow majority carriers (the substrate is an N-type substrate, and the first polysilicon layer 122 is a P-region, where the majority carriers are holes) to tunnel through while blocking minority carriers (where the minority carriers are electrons) from passing through, thereby separating electrons and holes, reducing recombination, and lowering the recombination rate.

[0047] Specifically, the ultrathin first tunneling dielectric layer 121 causes an asymmetric shift in the energy bands of the substrate 100 surface, making the potential barrier for majority carriers (also known as majority carriers) lower than that for minority carriers (also known as minority carriers). Therefore, majority carriers can more easily tunnel through the first tunneling dielectric layer 121, while minority carriers have difficulty passing through, thus achieving selective carrier transport. Secondly, the first tunneling dielectric layer 121 acts as a chemical passivation agent. Due to the presence of interface state defects at the interface between the substrate 100 and the first tunneling dielectric layer 121, the interface state density on the substrate surface is relatively high. This increased interface state density promotes the recombination of photogenerated carriers, increasing the fill factor, short-circuit current, and open-circuit voltage of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. In other words, the first tunneling dielectric layer 121 reduces the defect state density of the substrate 100 by saturating the dangling bonds of the substrate 100, reducing the number of recombination centers and thus lowering the carrier recombination rate.

[0048] In some embodiments, the thickness of the first tunneling dielectric layer 121 is 0.5 nm to 10 nm. The thickness range of the first tunneling dielectric layer 121 is 0.5 nm to 1.3 nm, 1.3 nm to 4.6 nm, 4.6 nm to 6.1 nm, or 6.1 nm to 10 nm. When the thickness of the first tunneling dielectric layer 121 is within any of the above ranges, the thickness of the first tunneling dielectric layer 121 is relatively thin, allowing majority carriers to easily tunnel through the first tunneling dielectric layer 121, while minority carriers have difficulty passing through, thus achieving selective carrier transport.

[0049] In some embodiments, the material of the first tunneling dielectric layer 121 includes at least one of silicon oxide, amorphous silicon, microcrystalline silicon, nanocrystalline silicon, or silicon carbide.

[0050] The first polycrystalline silicon layer 122 serves as a field passivation layer. Specifically, an electrostatic field pointing inwards from the substrate 100 is formed on the surface of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and decreasing the carrier recombination rate at the interface of the substrate 100. This increases the open-circuit voltage, short-circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0051] The first polysilicon layer 122 not only serves as a passivation layer to passivate the substrate surface, but also functions as part of the emitter. The semiconductor doped layer 112 acts as a heavily doped region (deep junction region) in the emitter, while the first polysilicon layer 122 acts as a lightly doped region (shallow junction region) in the emitter. Together, the semiconductor doped layer 112 and the first polysilicon layer 122 form a selective emitter (SE). This structure reduces the contact resistance between the silver-aluminum paste and the metal electrode contact area, while simultaneously reducing the recombination current density in the non-metal electrode contact area, thereby increasing the open-circuit voltage and fill factor of the battery and ultimately improving the photoelectric conversion efficiency.

[0052] The aluminum doping within the first polycrystalline silicon layer 122 avoids the light decay problem caused by boron-oxygen complexes formed by the combination of boron and oxygen, thereby improving the lifespan of the solar cell. Aluminum doping within the polycrystalline silicon layer, due to its low solid solubility in polycrystalline silicon, makes it easier to obtain a polycrystalline silicon layer with a low doping concentration. The non-metallic region avoids recombination losses caused by high doping concentrations. Furthermore, the aluminum-containing polycrystalline silicon layer has better gettering properties (high minority carrier lifetime), allowing for better passivation of the substrate and thus improving the photoelectric conversion efficiency of the cell.

[0053] In some embodiments, the aluminum doping concentration is 1×10⁻⁶. 18 cm -3 ~1×10 21 cm -3 This doping concentration range allows the first polysilicon layer 122 corresponding to the non-metallic region to form a PN junction with the substrate 100, thereby generating photogenerated carriers and improving the photoelectric conversion efficiency of the battery; it also results in a lower doping concentration of the first polysilicon layer 122, thus having lower parasitic absorption and carrier recombination loss, thereby reducing optical losses.

[0054] In some embodiments, the aluminum doping concentration can be 1 × 10⁻⁶. 18 cm -3 3×10 18 cm -3 6×10 18 cm -3 8×10 18 cm -3 2×10 19 cm -3 5×10 19 cm -3 9×10 19 cm -3 3×10 20 cm -3 6×10 20 cm-3 Or 1×10 21 cm -3 .

[0055] In some embodiments, the thickness of the first polysilicon layer 122 is 20 nm to 500 nm. The thickness range of the first polysilicon layer 122 can reduce the parasitic absorption of the first polysilicon layer 122, thereby reducing optical loss and improving photoelectric conversion efficiency.

[0056] The thickness of the first polysilicon layer 122 can be 20nm, 110nm, 180nm, 210nm, 250nm, 280nm, 320nm, 380nm, 430nm or 500nm.

[0057] Figure 2 A top view of the first surface of a solar cell provided in an embodiment of this application; Figure 3 Another top view of the first surface of a solar cell provided in an embodiment of this application; Figure 4 This is yet another top view of the first side of a solar cell provided in an embodiment of this application.

[0058] refer to Figure 2 The first polysilicon layer 122 is located in the non-metallic region 12, and the semiconductor doped layer 112 is located in the metallic region 11. The two are independent of each other to avoid the region contacted by the first electrode 106 being a lightly doped region.

[0059] It should be noted that, although Figure 2 The boundary between the first polysilicon layer 122 and the semiconductor doped layer 112 is clear, and the first polysilicon layer 122 is located only in the non-metallic region, while the semiconductor doped layer 112 is located only in the metallic region. However, in actual operation, the doping elements in the first polysilicon layer 122 may partially diffuse into the semiconductor doped layer 112, and the doping elements in the semiconductor doped layer 112 may partially diffuse into the first polysilicon layer 122. That is, the boundary between the two may not be so clear, which is also the scope of protection of the embodiments of this application. Similarly, the first polysilicon layer 122 may extend into the metallic region, and the semiconductor doped layer 112 may extend into the non-metallic region, which are also within the scope of protection of the embodiments of this application.

[0060] refer to Figure 3 or Figure 4The first polysilicon layer 122 includes: a first polysilicon portion 151, located on a portion of the surface of the first tunneling dielectric layer, and doped with aluminum; and a second polysilicon portion 152, adjacent to the first polysilicon portion 151 and located on the remaining surface of the first tunneling dielectric layer, and doped with p-type dopant, the concentration of which is less than or equal to the concentration of which is less than or equal to that of the semiconductor doped layer 112. The first polysilicon portion 151 enhances passivation, and the second polysilicon portion 152 enhances carrier transport capability. Thus, the first polysilicon layer 122 corresponding to the non-metallic region can generate photogenerated carriers, which are transported through the second polysilicon portion 152 and collected by the first electrode, thereby improving the photoelectric conversion efficiency of the battery.

[0061] In some embodiments, reference Figure 3 The second polysilicon portion 152 is located between the semiconductor doped layer 112 and the first polysilicon portion 151. The arrangement of the first polysilicon portion 151 and the second polysilicon portion 152, with the second polysilicon portion 152 serving as an intermediate layer with two different doping concentrations, ensures that there are no large transitional plateaus in carrier migration.

[0062] In some embodiments, reference Figure 4 The second polysilicon portion 152 and the first polysilicon portion 151 are arranged alternately along the first direction Y. The two ends of the first polysilicon portion 151 along the second direction X are respectively in contact with two adjacent semiconductor doped layers 112, and the two ends of a portion of the second polysilicon portion 152 are also in contact with two adjacent semiconductor doped layers 112. The arrangement of the first polysilicon portion 151 and the second polysilicon portion 152, with the second polysilicon portion 152 in contact with the semiconductor doped layers 112, serves as a lateral transport channel.

[0063] refer to Figure 3 or Figure 4 The first polycrystalline silicon portion 151 accounts for more than or equal to 60% of the area of ​​the first polycrystalline silicon layer 122. This reduces the content of doping elements that require high-temperature activity, thereby reducing the high-temperature activation time required for the solar cell and thus reducing the thermal damage to the cell. The large area of ​​the first polycrystalline silicon portion 151 in the first polycrystalline silicon layer 122, i.e., the large proportion of the low-doped region corresponding to the non-metallic region, can reduce the recombination rate of the non-metallic region, thereby improving the passivation effect and increasing the photoelectric conversion efficiency of the cell.

[0064] Continue to refer to Figure 1 The first passivation layer 105 covers the surface of the first polysilicon layer 122 and the surface of the semiconductor doped layer 112.

[0065] In some embodiments, the first passivation layer 105 may be a single-layer structure or a stacked structure, and the material of the first passivation layer 105 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0066] Figure 5 Another cross-sectional view of a solar cell provided in an embodiment of this application.

[0067] refer to Figure 5 In other embodiments, the solar cell further includes an aluminum oxide layer 123, which is located on the surface of the first polycrystalline silicon layer 122 and between the first polycrystalline silicon layer 122 and the first passivation layer 105. The aluminum oxide layer 123 can serve as a passivation layer, which can passivate the first polycrystalline silicon layer 122, thereby reducing the recombination rate of the first polycrystalline silicon layer 122; the aluminum oxide layer can also serve as a fixed negative charge layer to enhance the electric field effect of the first polycrystalline silicon layer 122 and promote the migration of charge carriers to the P-region.

[0068] In some embodiments, the aluminum doping concentration of the first polycrystalline silicon layer 122 decreases along a third direction, which is the thickness direction of the first polycrystalline silicon layer 122 and the direction pointing towards the substrate. The polycrystalline silicon layer is formed using an AIC (aluminum-induced crystallization) process. The closer to the substrate, the lower the aluminum concentration, resulting in better passivation of the formed first polycrystalline silicon layer 122. Furthermore, this process activates aluminum at a lower temperature, which can shorten the thermal processing time of the solar cell.

[0069] The aluminum doping concentration of the first polysilicon layer 122 decreases along a third direction, which is the thickness direction of the first polysilicon layer 122 and the direction pointing towards the substrate. That is, the aluminum doping concentration of the first polysilicon layer 122 near the substrate 100 is less than the aluminum doping concentration of the first polysilicon layer 122 far from the substrate 100.

[0070] Continue to refer to Figure 1 The first electrode 106 serves as an electrode for collecting charge carriers. The first electrode 106 can be formed by sintering a burn-through paste. The method for forming the first electrode 106 includes: printing a metal paste onto a portion of the antireflective layer surface using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, the metal paste is subjected to a sintering process. The metal paste contains highly corrosive components such as glass powder, so that during sintering, the corrosive components will corrode the first passivation layer 105, thereby allowing the metal paste to penetrate into the first passivation layer 105 and make electrical contact with the semiconductor doped layer 112.

[0071] In some embodiments, the first electrode 106 may be formed by sintering LECO (Laser-enhanced contact optimization) paste, and part of the LECO paste may be etched into the first passivation layer 105 and penetrate into it to contact the semiconductor doped layer 112 or form an electrical connection with the semiconductor doped layer 112 through a crystal.

[0072] It should be noted that the substrate includes a first surface and a second surface, and the aforementioned film layers are located on either the first or second surface of the substrate. In this embodiment, the first surface is considered the front side, the second surface the back side, the aforementioned film layers are located on the first surface, and the first electrode is the front electrode, as an example. Even if this embodiment does not explicitly state that the first surface is the back side and the second surface the front side, but the aforementioned film layers are located on the first surface and the first electrode is the back electrode, this is still within the scope of this embodiment.

[0073] In the solar cell provided in this application embodiment, the relationship between the thickness of the semiconductor doped layer 112 and the thickness of the first polycrystalline silicon layer 122 located in the non-metallic region, as well as which layer's top surface is higher than the other's top surface, can be set according to actual needs. Figure 1 and Figure 2 The relationships shown are merely examples and do not constitute a limiting relationship.

[0074] In some embodiments, the first surface of the substrate has a textured structure 111, which includes a plurality of raised structures 101. The inclined surfaces of the raised structures 101 can increase the internal reflection of incident light, thereby improving the utilization rate of incident light and improving the photoelectric conversion efficiency.

[0075] Continue to refer to Figure 1 The solar cell further includes: a second tunneling dielectric layer 131 located on the second surface of the substrate 100; a doped semiconductor layer 132 located on the surface of the second tunneling dielectric layer 131; a second passivation layer 115 located on the surface of the doped semiconductor layer 132; and a second electrode 116 located on the surface of the second passivation layer 115, which is electrically connected to the doped semiconductor layer 132.

[0076] It should be noted that the contents of the second tunneling medium layer 131 can be referred to the contents of the first tunneling medium layer 121 mentioned above, and will not be described in detail here.

[0077] The doped semiconductor layer 132 provides a field passivation effect. Specifically, an electrostatic field pointing towards the interior of the substrate 100 is formed on the surface of the substrate 100, causing minority carriers to escape from the interface, thereby reducing the minority carrier concentration and decreasing the carrier recombination rate at the interface of the substrate 100. This increases the open-circuit voltage, short-circuit current, and fill factor of the solar cell, thereby improving the photoelectric conversion efficiency of the solar cell.

[0078] In some embodiments, the substrate 100 is doped with an N-type dopant element, and the dopant element in the doped semiconductor layer 132 has the same conductivity type as the dopant element in the substrate 100, that is, the doped semiconductor layer 132 is doped with an N-type dopant element.

[0079] The doping element concentration in the doped semiconductor layer 132 is greater than that in the substrate 100. A high-low junction is formed between the doped semiconductor layer 132 and the substrate 100. Under the electric field formed by the high-low junction, a sufficiently high potential barrier can be formed on the surface of the substrate 100, so that majority carriers in the substrate 100 can pass through the second tunneling dielectric layer 131 to the doped semiconductor layer 132, which is beneficial to improving the carrier mobility.

[0080] In some embodiments, the doped semiconductor layer 132 includes at least one of a doped amorphous silicon layer, a doped polycrystalline silicon layer, a doped microcrystalline silicon layer, or a doped silicon carbide layer.

[0081] In some embodiments, the second passivation layer 115 may be a single-layer structure or a stacked structure, and the material of the second passivation layer 115 may be one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0082] In some embodiments, the second electrode 116 may be formed by sintering a burn-through paste. A method for forming the second electrode 116 includes: printing a metal paste onto a portion of the back passivation layer surface using a screen printing process. The metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. Then, the metal paste is subjected to a sintering process, wherein the metal paste contains highly corrosive components such as glass powder, so that during sintering, the corrosive components will corrode the second passivation layer 115, thereby allowing the metal paste to penetrate into the second passivation layer 115 and make electrical contact with the doped semiconductor layer 132.

[0083] In some embodiments, the second electrode 116 may be formed by sintering LECO paste, and part of the LECO paste may be used to etch the second passivation layer 115 to contact the doped semiconductor layer 132 or to form an electrical connection with the doped semiconductor layer 132 through a crystal.

[0084] In the solar cell provided in this application embodiment, the solar cell has a metal region 11 and a non-metal region 12. A semiconductor doped layer 112 is provided on the surface of the substrate 100 corresponding to the metal region 11. The P-type dopant element in the semiconductor doped layer 112 can provide a large number of P-type ions, thus functioning as a PN junction to effectively generate and separate photogenerated carriers. The electrode is electrically connected to the semiconductor doped layer 112, resulting in low contact resistance and reduced electrical losses. A first tunneling dielectric layer 121 and a first polycrystalline silicon layer 122 are provided on the surface of the substrate 100 corresponding to the non-metal region 12. The combined double passivation effect of the first tunneling dielectric layer 121 and the first polycrystalline silicon layer 122 can effectively reduce the carrier recombination rate of the substrate 100, thereby improving the photoelectric conversion efficiency. Furthermore, aluminum is doped in the first polycrystalline silicon layer 122. Since aluminum has low solid solubility in polycrystalline silicon, it is relatively easy to obtain a first polycrystalline silicon layer 122 with a low aluminum doping concentration. The non-metal region 12 can avoid recombination losses caused by high doping concentrations. Moreover, the first polycrystalline silicon layer 122 containing aluminum has a better gettering degree (high minority carrier lifetime), which can better passivate the substrate 100, thereby improving the photoelectric conversion efficiency of the battery.

[0085] According to some embodiments of this application, another aspect of this application also provides a method for preparing a solar cell, which is used to prepare the solar cell provided in the above embodiments. The same or corresponding technical features as those in the above embodiments will not be described in detail here.

[0086] Figures 6 to 12 Cross-sectional views of the solar cells corresponding to each step in the method for fabricating a solar cell provided in another embodiment of this application.

[0087] refer to Figure 6 Provides the initial base 107.

[0088] refer to Figure 7 One side of the initial substrate 107 is texturing to give one side of the initial substrate 107 a texturing structure 111. The texturing structure 111 includes a plurality of first protrusions 101. The surface of the initial substrate has alternating metallic and non-metallic regions, and both the metallic and non-metallic regions have the texturing structure 111.

[0089] In some embodiments, the texturing process includes chemical etching, for example, cleaning the initial substrate 107 with a mixed solution of potassium hydroxide and hydrogen peroxide. Specifically, the desired texturing structure can be formed by controlling the concentration ratio of potassium hydroxide and hydrogen peroxide solutions. In some embodiments, the texturing structure can also be formed using methods such as laser etching, mechanical etching, or plasma etching. In laser etching, the desired texturing structure is obtained by controlling the laser process parameters.

[0090] refer to Figure 8 and Figure 9 The preparation method includes forming a semiconductor doped layer 112, which is located on the substrate surface corresponding to the metal region, and has a P-type dopant element in the semiconductor doped layer 112.

[0091] refer to Figure 8 A diffusion layer 102 is formed by high-temperature diffusion or ion implantation. A portion of the initial substrate 100 is diffused to form the diffusion layer 102.

[0092] refer to Figure 9 A diffusion layer is formed on the surface of the diffusion layer corresponding to the metal region, and the diffusion layer corresponding to the non-metal region is removed. The remaining diffusion layer serves as the semiconductor doping layer 112.

[0093] Before removing the diffusion layer corresponding to the non-metallic region, a mask layer 104 is formed on the diffusion layer corresponding to the metallic region.

[0094] refer to Figure 10 The preparation method includes: forming a first tunneling medium layer 121, wherein the first tunneling medium layer 121 is located on the surface of the substrate 100 corresponding to the non-metallic region 12.

[0095] The first tunneling medium layer 121 is formed by oxidation, heat treatment or deposition processes.

[0096] It should be noted that if the first tunneling dielectric layer is formed using oxidation or heat treatment processes, there will be no first tunneling dielectric layer on the mask layer. If the first tunneling dielectric layer is formed using deposition processes, then the first tunneling dielectric layer will be present on the mask layer, but it will not be on the surface of the mask. Figure 10 As shown in the image.

[0097] refer to Figures 10 to 12 The preparation method includes: forming a first polycrystalline silicon layer 122, the first polycrystalline silicon layer 122 being located on the surface of a first tunneling dielectric layer, and at least a portion of the first polycrystalline silicon layer 122 being doped with aluminum.

[0098] Forming the first polysilicon layer 122 can include two methods, which will be described in detail below with reference to the relevant figures.

[0099] The first method: using a diffusion process.

[0100] refer to Figure 10 A semiconductor film 113 is formed, which is an intrinsic polycrystalline silicon film. (Reference) Figure 12 An ion implantation process is performed on the semiconductor film 113 to transform the intrinsic polycrystalline silicon film into a first polycrystalline silicon layer 122 doped with aluminum.

[0101] Since aluminum does not require a high-temperature activation process, i.e., no subsequent high-temperature activation step is needed, the number of high-temperature treatments for solar cells is reduced, thus reducing thermal damage to solar cells.

[0102] In other embodiments, reference is made to Figure 10 A semiconductor film 113 is formed, which is an intrinsic polycrystalline silicon film. (Reference) Figure 11 This forms a doped source layer 114, which contains aluminum. (Reference) Figure 12 Laser doping is performed on the semiconductor film 113 to diffuse aluminum elements in the doping source layer 114 into the intrinsic polycrystalline silicon film, thereby transforming the intrinsic polycrystalline silicon film into a first polycrystalline silicon layer 122 doped with aluminum elements.

[0103] The second method uses the AIC process.

[0104] refer to Figure 10 A semiconductor film 113 is formed, which is an intrinsic amorphous silicon (a-Si) film. (Reference) Figure 11 This forms a doped source layer 114, which is an aluminum layer; Reference Figure 12 A low-temperature induced process is applied to the semiconductor film, allowing Al atoms to diffuse into the a-Si layer through the Al / a-Si interface, transforming the Si-Si covalent bond into a Si-Al metallic bond. This silicide formation near the interface further accelerates the interdiffusion between Al and Si atoms, leading to the formation of a Si-Al mixed phase. Since the solid solubility of Si in Al is negligible at low temperatures, supersaturated Si in Al precipitates and nucleates at the Al / a-Si interface, gradually growing into polycrystalline silicon. While supersaturated Si precipitates from the Si-Al mixed phase as nuclei, the remaining Al atoms tend to migrate towards the sample surface and eventually precipitate entirely on the top layer. This transforms the intrinsic polycrystalline silicon film into a first polycrystalline silicon layer 122 doped with aluminum.

[0105] The polycrystalline silicon layer prepared by the AIC process is thin and has a low annealing temperature. The resulting polycrystalline silicon layer has a high degree of crystallization and good crystal orientation. In other words, the prepared first polycrystalline silicon layer 122 has fewer physical defects.

[0106] It should be noted that, using the AIC process, aluminum atoms need to exchange with silicon elements in the semiconductor film at the interface between the semiconductor film and the aluminum layer. Based on the diffusion and exchange thresholds, the doping concentration of aluminum elements is highest at the interface adjacent to the semiconductor film and the aluminum layer, and the doping concentration of aluminum elements is lower on the side closer to the substrate.

[0107] In some embodiments, the aluminum layer on the surface may be removed after the first polycrystalline silicon layer 122 is formed; alternatively, the aluminum layer on the surface may be oxidized to form an aluminum oxide layer.

[0108] refer to Figure 1 The fabrication method includes: forming a first passivation layer 105, wherein the first passivation layer 105 is located on the surface of the semiconductor doped layer 112 and the surface of the first polysilicon layer 122. The fabrication method includes: forming a first electrode 106, wherein the first electrode 106 is located on the surface of the first passivation layer 105 corresponding to the metal region 11, and the first electrode 106 is electrically connected to the semiconductor doped layer 112.

[0109] Continue to refer to Figure 1 The fabrication method includes: forming a second tunneling dielectric layer 131, the second tunneling dielectric layer 131 being located on the second surface of the substrate 100; forming a doped semiconductor layer 132, the doped semiconductor layer 132 being located on the surface of the second tunneling dielectric layer 131; forming a second passivation layer 115, the second passivation layer 115 being located on the surface of the doped semiconductor layer 132; forming a second electrode 116, the second electrode 116 being located on the surface of the second passivation layer 115, and the second electrode 116 being electrically connected to the doped semiconductor layer 132.

[0110] The solar cell fabrication method provided in this application forms the first polycrystalline silicon layer 122 through diffusion and AIC processes, avoiding the high-temperature activation step, thereby reducing the fabrication cost.

[0111] According to some embodiments of this application, another aspect of this application also provides a stacked battery.

[0112] Figure 13 A cross-sectional view of a stacked battery provided in another embodiment of this application.

[0113] refer to Figure 13 The tandem solar cell includes: a bottom cell 150, which is a solar cell as described in any of the above embodiments or a solar cell prepared by any of the above embodiments; and a top cell 180, which is located on the side of the substrate 100 of the bottom cell 150 away from the first electrode 106.

[0114] In some embodiments, the stacked battery has a first grid line 186 of a first polarity and a second grid line of a second polarity. The first grid line 186 is in electrical contact with the top battery 180, and the second grid line is in electrical contact with the bottom battery 150. The second grid line is the first electrode 106 of the bottom battery.

[0115] In some embodiments, an interface layer 181 is provided between the top cell and the bottom cell, and the interface layer 181 also covers the passivation contact structure on the back side, i.e., covers the doped semiconductor layer 132.

[0116] It is worth noting that the stacked battery in this application embodiment only illustrates two layers of solar cells. Those skilled in the art can set up three layers of solar cells or more than three layers of multi-layer stacked solar cells according to actual needs.

[0117] In some embodiments, the top cell 180 can be a perovskite solar cell, which includes: a first transport layer 182, a perovskite substrate 183, a second transport layer 184, a transparent conductive layer 185, and an antireflection layer (not shown). The first transport layer is directly opposite the bottom cell.

[0118] In some embodiments, the first transport layer may be either an electron transport layer or a hole transport layer, and the second transport layer may be either an electron transport layer or a hole transport layer.

[0119] Accordingly, according to some embodiments of this application, another aspect of this application provides a photovoltaic module, including the solar cell provided in the above embodiments, with the same or corresponding technical features as the above embodiments, which will not be described in detail here.

[0120] Figure 14 This is a schematic diagram of a photovoltaic module provided in another embodiment of the present application; Figure 15 for Figure 14 A cross-sectional view along section M1-M2.

[0121] refer to Figure 14 and Figure 15 The photovoltaic module includes: a battery string, which is composed of a plurality of solar cells 20 as described in any of the above embodiments; an encapsulating film 21 for covering the surface of the battery string; and a cover plate 22 for covering the surface of the encapsulating film 21 facing away from the battery string.

[0122] Specifically, in some embodiments, multiple solar cells can be electrically connected to each other via a connecting member 218, which is welded to the main grid on the solar cell. The main grid includes a main electrode electrically connected to a first electrode 106 and a main electrode electrically connected to a second electrode 116.

[0123] In some embodiments, there is no spacing between the solar cells, meaning that the solar cells overlap each other.

[0124] In some embodiments, the connecting member 218 is welded to a sub-gate 208 on the battery cell, the sub-gate 208 including a first electrode 106 and a second electrode 116.

[0125] In some embodiments, the encapsulating film 21 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first encapsulating layer or the second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0126] It is worth noting that the first encapsulation layer and the second encapsulation layer still have a dividing line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 21.

[0127] In some embodiments, the cover plate 22 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 22 facing the encapsulating film 21 can be an uneven surface, thereby increasing the utilization rate of incident light. The cover plate 22 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer and the second cover plate being opposite to the second encapsulation layer; or the first cover plate being opposite to one side of the solar cell and the second cover plate being opposite to the other side of the solar cell.

[0128] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A solar cell, characterized in that, include: Base; A first tunneling medium layer is located on a portion of the substrate surface; A first polysilicon layer is located on the surface of the first tunneling dielectric layer, and at least a portion of the first polysilicon layer is doped with aluminum; the doping concentration of aluminum in the portion of the first polysilicon layer closer to the substrate is less than the doping concentration of aluminum in the portion of the first polysilicon layer farther from the substrate. A first passivation layer is located on the surface of the first polysilicon layer.

2. The solar cell according to claim 1, characterized in that, The aluminum doping concentration is 1×10⁻⁶. 18 cm -3 ~1×10 21 cm -3 .

3. The solar cell according to claim 1, characterized in that, The thickness of the first polycrystalline silicon layer is 20nm~500nm.

4. The solar cell according to claim 1, characterized in that, Also includes: An alumina layer is located on the surface of the first polycrystalline silicon layer and between the first polycrystalline silicon layer and the first passivation layer.

5. The solar cell according to claim 1, characterized in that, The doping concentration of aluminum in the first polycrystalline silicon layer decreases along a third direction, which is the thickness direction of the first polycrystalline silicon layer and the direction pointing towards the substrate.

6. The solar cell according to claim 1, characterized in that, The substrate has a metallic region and a non-metallic region, and further includes: a semiconductor layer located in the metallic region, the semiconductor layer being doped with a p-type dopant element; a first tunneling dielectric layer located in the non-metallic region, the first polysilicon layer comprising: The first polysilicon portion is located on a portion of the surface of the first tunneling dielectric layer, and the first polysilicon portion is doped with the aluminum element. The second polysilicon portion is adjacent to the first polysilicon portion and located on the remaining surface of the first tunneling dielectric layer. The second polysilicon portion is doped with the P-type dopant element, and the concentration of the P-type dopant element in the second polysilicon portion is less than or equal to the concentration of the P-type dopant element in the semiconductor doped layer.

7. The solar cell according to claim 6, characterized in that, The second polysilicon portion and the first polysilicon portion are arranged alternately along the first direction. The two ends of the first polysilicon portion along the second direction are respectively in contact with two adjacent semiconductor doped layers, and the two ends of a portion of the second polysilicon portion are respectively in contact with two adjacent semiconductor doped layers.

8. The solar cell according to claim 6, characterized in that, The second polysilicon portion is located between the semiconductor doped layer and the first polysilicon portion.

9. The solar cell according to claim 6, characterized in that, The area of ​​the first polycrystalline silicon portion in the first polycrystalline silicon layer is greater than or equal to 60%.

10. A photovoltaic module, characterized in that, include: A battery string, wherein the battery string is composed of a plurality of solar cells as described in any one of claims 1 to 9; An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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