A method of forming a semiconductor structure

Abstract

This invention relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a semiconductor structure. The method includes: forming an adhesion layer on a substrate; forming a mask layer on the adhesion layer; and obtaining a high aspect ratio mask structure through photolithography and anisotropic etching processes; and depositing a protective layer on the mask structure and its sidewall surfaces. The protective layer covers and supports the mask structure, enhancing the interfacial bonding strength between the mask structure and the substrate, and improving the mechanical stability of the mask sidewalls, thereby suppressing sidewall tilting or material peeling during subsequent etching, cleaning, or high-energy ion implantation processes. The protective layer can be formed using conventional thin-film deposition processes such as chemical vapor deposition and atomic layer deposition, exhibiting good sidewall coverage and process compatibility. The method of this invention has a simple process flow and can be implemented on existing semiconductor manufacturing platforms. Without significantly increasing manufacturing costs, it effectively improves the reliability of high aspect ratio mask structures and device manufacturing yield, and is suitable for the manufacture of image sensors and other integrated circuit devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the continuous development of semiconductor manufacturing technology, integrated circuit devices such as image sensors are evolving towards higher resolution, smaller pixel size, and higher integration. In related manufacturing processes, to achieve device isolation, confined doping regions, and controlled electrical performance, high aspect ratio structures with larger vertical dimensions and smaller horizontal dimensions are gradually being introduced. To facilitate key process steps such as deep etching and high-energy ion implantation, mask structures are typically formed on the substrate surface to effectively shield and protect selected areas.

[0003] However, with the continuous improvement of the aspect ratio of mask structures, the mechanical stability problems they face during manufacturing are becoming increasingly prominent. Especially during processes such as anisotropic etching, cleaning, and high-energy ion implantation, mask structures are susceptible to factors such as ion bombardment, stress concentration, and thermal effects, which can lead to failure phenomena such as sidewall morphology degradation, local peeling, or overall tilting. When the mask peels off, its ability to block ions or etching media will decrease significantly, potentially leading to accidental doping or etching of non-target areas; when the mask tilts, it will cause mask pattern shift or occlusion failure, preventing the areas that should be processed from being accurately processed, thus seriously affecting the consistency and electrical performance of the device.

[0004] To address the aforementioned issues, existing technologies typically introduce an adhesion layer between the mask and the substrate to enhance interfacial bonding strength, thereby reducing the risk of mask peeling during subsequent processes. Additionally, some technologies attempt to improve mask stability by optimizing mask material types, adjusting etching parameters, or introducing multilayer mask structures. However, in practical applications, these solutions often primarily target peeling issues, offering limited effectiveness in suppressing sidewall tilting in high aspect ratio structures. Furthermore, complex material systems or additional process steps may lead to narrowing process windows, increased manufacturing costs, and insufficient compatibility with existing production lines. Therefore, improving the overall stability of high aspect ratio mask structures in subsequent high-energy processes, especially suppressing mask sidewall tilting and failure, without significantly increasing process complexity and cost, remains a pressing technical challenge in the image sensor and related semiconductor manufacturing fields. Summary of the Invention

[0005] To address the problems existing in the prior art, the present invention proposes a method for forming a semiconductor structure, the method comprising the following steps: forming an adhesion layer on a substrate; forming a first mask layer on the adhesion layer; A photolithography layer is formed and patterned on the first mask layer to obtain the desired pattern; the first mask layer is etched to form a high aspect ratio pattern structure and a mask feature with sidewalls; a protective layer is deposited on the first mask layer and its sidewalls to enhance the bonding between the first mask layer and the substrate and the mechanical support of the sidewalls, thereby preventing the mask sidewalls from tipping over or the mask material from peeling off in subsequent processes.

[0006] Furthermore, the substrate is a silicon-based substrate or a silicon-compatible semiconductor substrate.

[0007] Furthermore, the adhesive layer is formed of a silicon compound, and the adhesive layer material is composed of at least one thin film selected from the group consisting of: nitrogen silicide, silicon dioxide, silicon oxynitride, silicon carbide, aluminum oxide, titanium oxide, aluminum nitride, or combinations thereof.

[0008] Furthermore, the first mask layer is composed of organic or inorganic materials, including spin-coated organic carbon, silicon nitride, silicon nitride carbide, silicon nitride oxide, or other materials used to form a high aspect ratio barrier / mask.

[0009] Furthermore, the etching step gives the pattern features formed by the first mask layer a high aspect ratio structure, wherein the aspect ratio of the high aspect ratio structure is not less than 4.

[0010] Furthermore, after etching the first mask layer to form a high aspect ratio pattern structure and before depositing the protective layer, the method includes a step of performing a low-energy isotropic plasma treatment on the surface of the mask layer to repair damage caused by etching or reduce surface roughness. Furthermore, the protective layer is composed of one or more of oxides, nitrides, and oxynitrides; the protective layer is formed by one or more deposition methods, including chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof.

[0011] Furthermore, the protective layer has a certain thickness to ensure the coverage and mechanical support of the mask sidewalls, the thickness ranges from 2-100nm, and it has good coverage and sidewall consistency.

[0012] Furthermore, after the protective layer is deposited, the method further includes heat-treating or annealing the protective layer or the overall mask structure to improve the bonding strength and interface stability between the protective layer and the first mask layer and the adhesion layer.

[0013] Furthermore, the method is applicable to subsequent high-ion implantation or other process steps that apply impact or mechanical load to the mask sidewalls, and the protective layer prevents mask sidewall tilting or peeling during such subsequent processes by improving sidewall stiffness and interfacial adhesion.

[0014] Furthermore, after etching the first mask layer to form a high aspect ratio pattern structure and before depositing the protective layer, the process includes a step of performing a low-energy isotropic plasma light treatment on the surface of the mask layer to repair the damage caused by etching or reduce the surface roughness of the high aspect ratio mask layer surface.

[0015] Compared with the prior art, the present invention has the following technical effects: First, by further covering the surface of the mask layer with its already formed high aspect ratio structure with a protective layer, the mask structure gains additional mechanical support and constraint in the longitudinal and sidewall directions, effectively improving the overall stability of the mask structure. This structural design can reduce the risk of mask sidewalls tipping over or degrading due to stress concentration, ion bombardment, or thermal effects during subsequent high-energy ion implantation, etching, and cleaning processes, thereby ensuring effective shielding of the target area and the integrity of the pattern.

[0016] Secondly, this invention enhances the interfacial bonding strength between the mask structure and the substrate through the synergistic effect of the protective layer, mask layer, and adhesion layer. This not only helps to suppress localized delamination of the mask material during processing but also improves the sidewall consistency and repeatability of high aspect ratio structures to a certain extent. This effectively reduces doping or processing deviations in non-target areas caused by mask failure, improving the consistency of device electrical performance and manufacturing yield.

[0017] Furthermore, the fabrication method employed in this invention has a simple process flow and can be implemented on existing semiconductor manufacturing platforms. The protective layer can be formed using conventional thin-film deposition methods, without the need for complex additional processes or special equipment, exhibiting good process compatibility and mass production feasibility. Compared to solutions that involve changing mask materials or significantly adjusting etching conditions, this invention improves mask stability while having a smaller impact on overall manufacturing costs and process windows, making it suitable for widespread application in large-scale production.

[0018] Furthermore, by covering the high aspect ratio mask structure with a protective layer, this invention helps maintain the stable morphology of the mask sidewalls, providing a more reliable process basis for subsequent deep etching or fine doping processes. This improves the overall performance and long-term reliability of the device without significantly increasing costs, and has high engineering application value. Attached Figure Description

[0019] Figure 1-3 This is a flowchart of the existing mask structure process.

[0020] Figure 4-6 This is a schematic cross-sectional view of a grating structure for an optical sensor in the prior art. Detailed Implementation

[0021] It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the purpose of illustrating the embodiments of the present invention, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationship, or adjustments to the size should still fall within the scope of the technical content disclosed in the present invention, provided that they do not affect the effects and objectives that the present invention can produce.

[0022] like Figure 1-3 As shown, in existing technologies, to meet the process requirements of deep etching or high-energy ion implantation in the manufacturing of semiconductor devices such as image sensors, high aspect ratio mask structures are typically used to selectively shield specific areas. A typical process flow is as follows.

[0023] First, a substrate 100 is provided, which is typically a silicon substrate, but may also be a semiconductor substrate compatible with silicon processes. An adhesion layer 110 is formed on the surface of the substrate 100 to enhance the adhesion between the subsequent mask layer and the substrate. The adhesion layer is generally made of silicon nitride or silicon dioxide and is formed by methods such as chemical vapor deposition. Subsequently, a hard mask layer 120 is formed on the adhesion layer. The hard mask layer is typically formed using spin-coated organic carbon material to meet the process requirements of high selectivity etching and ion blocking.

[0024] Next, photoresist 130 is spin-coated onto the surface of the hard mask layer 120. The designed pattern is transferred to the photoresist layer through exposure and development processes, thereby forming the corresponding pattern opening area in the photoresist layer. After photolithography and development are completed, the photoresist 130 is used as an etching mask to etch the underlying hard mask layer 120.

[0025] Subsequently, an anisotropic etching process is used to etch the hard mask layer 120, forming a high aspect ratio structure with a large vertical dimension and a small horizontal dimension. The aspect ratio of the formed structure is typically greater than or equal to 4. After etching, the photoresist 130 is completely lost during the etching process, and finally the hard mask layer 120 is formed on the adhesion layer 110.

[0026] However, as Figure 3 As shown, the final hard mask layer structure 120 has a high aspect ratio and is relatively long and thin perpendicular to the substrate. Therefore, it is susceptible to ion bombardment, stress, or thermal effects during subsequent processes, leading to problems such as sidewall tilting or localized peeling. Once these defects occur, the mask structure's shielding capability for subsequent ion implantation or etching processes will decrease, and it may even cause processing failure in the target area, affecting the device's electrical performance and manufacturing yield. Therefore, existing technologies still need further improvement to address the insufficient stability of high aspect ratio hard mask structures. Example 1

[0027] This embodiment uses a silicon substrate as an example to illustrate a method for fabricating a tilt-resistant high aspect ratio mask according to the present invention. First, as... Figure 4 As shown, a substrate 200 is provided, preferably a single-crystal silicon substrate or a semiconductor substrate compatible with silicon processes. After conventional surface treatment of the substrate 200, an adhesion layer 210 is formed on the substrate surface. The adhesion layer 210 can be selected from materials such as silicon dioxide, silicon nitride, silicon oxynitride, or aluminum oxide, and its thickness is preferably 5 nanometers to 500 nanometers. It can be formed by one or more processes selected from plasma-enhanced chemical vapor deposition, atomic layer deposition, or thermochemical vapor deposition to improve the interfacial bonding strength between the mask layer and the substrate and improve the wettability of the substrate surface.

[0028] like Figure 5 As shown, a hard mask layer 220 is then formed on the adhesion layer 210. This hard mask layer can be formed using a spin-coated organic carbon solution (e.g., a spin-coated organic carbon layer), or in some other embodiments, other organic / inorganic hard mask materials may be used. The thickness of the hard mask layer 220 is matched to the target depth and etching selectivity, typically ranging from hundreds of nanometers to several micrometers. After the hard mask layer deposition is complete, a dielectric layer 230 is formed on the hard mask layer 220. This dielectric layer can be low-temperature silicon oxide or silicon nitride, with a thickness of 5 nanometers to 500 nanometers. A photoresist 240 is spin-coated onto the dielectric layer 230, and then exposed and developed to form a design pattern on the photoresist 240.

[0029] Using the photoresist 240 as an etching mask, anisotropic etching is employed to etch the dielectric layer 230 and the hard mask layer 220 to obtain a high aspect ratio mask structure. The anisotropic etching can employ reactive ion etching, inductively coupled plasma etching, etc., controlling the etching selectivity and sidewall contours to ensure that the aspect ratio of the formed structure is preferably not less than 4. During the etching process, the photoresist 240 is completely lost. After etching, the surface of the high aspect ratio mask structure is lightly treated with low-energy isotropic plasma to repair surface damage caused by etching and reduce surface roughness, resulting in a high aspect ratio hard mask structure formed on the adhesion layer 210.

[0030] like Figure 6As shown, to prevent sidewall tilting or localized peeling of the aforementioned high aspect ratio structure during subsequent processes, this embodiment deposits a protective layer 250 on the hard dielectric layer 230, the mask layer 220, and their sidewall surfaces after etching. The protective layer 250 can be made of silicon dioxide, aluminum oxide, aluminum nitride, or other oxide / nitride materials, and the deposition methods include, but are not limited to, atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The thickness of the protective layer 250 is preferably 2 to 100 nanometers to balance sidewall coverage and the processability of subsequent processes. To obtain good interfacial adhesion and reduce stress concentration, low-temperature heat treatment or annealing can be performed after the protective layer deposition to improve the bonding strength between the protective layer and the hard mask layer and adhesion layer.

[0031] Through the above embodiments, without significantly increasing process complexity or introducing expensive alternative materials, the mechanical stability and interface reliability of high aspect ratio mask structures in subsequent processes such as ion implantation, etching and cleaning can be significantly improved, thereby reducing pattern distortion and mask failure caused by mask tilting or peeling, and improving device yield and electrical consistency. Example 2

[0032] The present invention also provides a semiconductor device structure formed according to the method described in Embodiment 1, such as... Figure 6 As shown, the semiconductor intermediate structure includes: a substrate 200, an adhesion layer 210, a mask layer 220, and a protective layer 250 covering the top surface of the mask layer and at least partially covering its sidewalls. The substrate 200 is monocrystalline silicon or a semiconductor substrate compatible with silicon processes; the adhesion layer 210 is made of silicon dioxide or silicon nitride, preferably with a thickness of 5 nm to 500 nm, and is formed by plasma-enhanced chemical vapor deposition or atomic layer deposition to improve interfacial bonding. The mask layer 220 is a hard mask layer made of spin-coated organic carbon, typically with a thickness of several hundred nanometers to several micrometers, and at least one high aspect ratio structure with a vertical height significantly greater than its horizontal width is formed on the mask layer 220, preferably with an aspect ratio of not less than 4. The protective layer covers the top surface of the mask layer and at least partially covers its sidewalls. The protective layer material is selected from silicon dioxide, alumina, or aluminum nitride. The protective layer 250 is formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition, and its thickness is preferably 2 to 100 nm to balance sidewall coverage and subsequent processability. The protective layer 250 forms a contact interface with the mask layer 220 and the adhesive layer 210. The interface is subjected to low-temperature annealing or surface activation treatment to enhance the bonding strength.

[0033] This device structure, by increasing sidewall mechanical support and interface bonding, helps to suppress mask sidewall tilting and material peeling during subsequent high-energy ion implantation, deep etching, or cleaning processes, thereby improving the reliability of pattern protection and device process yield. This embodiment can also employ a multi-layer protective layer configuration or perform surface activation of the mask sidewalls before deposition to further enhance coverage and bonding performance.

[0034] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0035] It should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes the following steps: An adhesion layer is formed on the substrate; A first mask layer is formed on the adhesion layer; A photolithography layer is formed and patterned on the first mask layer to obtain the desired pattern; The first mask layer is etched to form a high aspect ratio pattern structure and a mask feature with sidewalls; A protective layer is deposited on the first mask layer and its sidewalls to enhance the bonding between the first mask layer and the substrate and the mechanical support of the sidewalls, thereby preventing the mask sidewalls from tilting or the mask material from peeling off in subsequent processes. The first mask layer and the protective layer together serve as a mask for high-energy ion implantation.

2. The method according to claim 1, characterized in that, The substrate is a silicon-based substrate or a silicon-compatible semiconductor substrate.

3. The method according to claim 1 or 2, characterized in that, The adhesive layer is formed of a silicon compound, and the adhesive layer material is composed of at least one thin film selected from the group consisting of: nitrogen silicide, silicon dioxide, silicon oxynitride, silicon carbide, aluminum oxide, titanium oxide, aluminum nitride, or combinations thereof.

4. The method according to claim 1, characterized in that, The first mask layer is composed of organic or inorganic materials, including spin-coated organic carbon, silicon nitride, silicon nitride carbide, silicon nitride oxide, or other materials used to form a high aspect ratio barrier / mask.

5. The method according to claim 1, characterized in that, The etching step gives the pattern features formed by the first mask layer a high aspect ratio pattern structure, wherein the aspect ratio of the high aspect ratio structure is not less than 4.

6. The method according to claim 1, characterized in that, After etching the first mask layer to form a high aspect ratio pattern structure and before depositing the protective layer, the process includes a step of performing low-energy isotropic plasma treatment on the surface of the mask layer to repair damage caused by etching or reduce surface roughness.

7. The method according to claim 1, characterized in that, The protective layer is composed of one or more of oxides, nitrides, and nitrogen oxides; The protective layer is formed by one or more deposition methods, including chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof.

8. The method according to claim 7, characterized in that, The protective layer has a certain thickness to ensure the coverage and mechanical support of the mask sidewalls. The thickness ranges from 2 to 100 nm and has good coverage and sidewall consistency.

9. The method according to claim 1, characterized in that, After the protective layer is deposited, the method further includes heat-treating or annealing the protective layer or the overall mask structure to improve the bonding strength and interface stability between the protective layer and the first mask layer and the adhesion layer.

10. The semiconductor structure formed by the method according to any one of claims 1-9, characterized in that, include: Substrate; Adhesion layer disposed on the substrate; A mask layer disposed on the adhesion layer, the mask layer comprising at least one high aspect ratio structure whose longitudinal height is significantly greater than its lateral width; and A protective layer covering the top surface of the mask layer and at least partially covering the sidewalls of the mask layer. The protective layer forms contact with the mask layer and / or the adhesion layer to enhance the mechanical support and interfacial bonding of the mask layer to the substrate, thereby suppressing the tilting of the mask layer sidewalls or the peeling of the mask material in subsequent processes such as high-energy ion implantation, etching or cleaning.

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