An image sensor and a method of manufacturing the same

Abstract

This application provides an image sensor and a method for fabricating the same, comprising: providing a substrate including a first surface and a second surface, wherein an interlayer dielectric layer is formed on the second surface; forming a patterned first mask layer on the first surface, using the first mask layer as a mask to etch the substrate to form trenches, wherein a connection hole is also formed at the bottom of the trenches; forming a conductive layer; forming a patterned second mask layer on the conductive layer, using the second mask layer as a mask to etch and remove the sidewalls of the trenches and the conductive layer on the first surface to form a pad structure, wherein the patterned first mask layer and the patterned second mask layer are formed using the same mask, and the pattern of the mask is designed based on the shape of the trenches or the shape of the pad structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an image sensor and a method for fabricating the same. Background Technology

[0002] Back-side illuminated CMOS image sensors (BSI CIS) are high-performance image sensors widely used in smartphones, digital cameras, and security monitoring in recent years. In the manufacturing process of BSI image sensors, a key step is wafer thinning after the front-end and mid-end processes, followed by a series of back-end processes on the back side. Among these, etching deep and wide trenches on the back side of the pixel area and forming metal lines or pads within these trenches is crucial for achieving back-side electrical connections and signal output. The metal lines within the trenches are typically used to connect the pixel array to peripheral circuitry or as pads for solder ball connections.

[0003] In related technologies, the method for generating pad structures within trenches in back-illuminated image sensors typically includes the following steps: First, a substrate is exposed and developed using a first photomask, and a first trench with a large depth-to-width ratio is formed on the back side of the substrate using a dry etching process; then, a second photomask is used for further exposure and development, and etching continues at the bottom of the first trench to form a connecting via; next, a metal layer is deposited in the trench and the connecting via; finally, a third photomask is used to expose, develop, and dry etch the aluminum layer, thereby forming the desired pad structure within the trench. However, forming the pad structure in related technologies requires multiple exposure, development, and dry etching operations using three photomasks, significantly increasing production costs. During mass production, frequent switching of photomasks is necessary, leading to reduced effective operating time and throughput of the photolithography equipment, thus affecting overall production efficiency.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating an image sensor, comprising: providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other; forming an interlayer dielectric layer on the second surface of the substrate, wherein interconnect structures are formed in the interlayer dielectric layer; forming a patterned first mask layer on the first surface of the substrate; using the patterned first mask layer as a mask, etching the substrate to form a trench penetrating the substrate and exposing a portion of the surface of the interlayer dielectric layer; wherein at least one connection hole is formed at the bottom of the trench, and each connection hole... The interconnect structure is partially exposed and communicates with the trench; a conductive layer is formed covering the bottom and sidewalls of the trench and the first surface; a patterned second mask layer is formed on the conductive layer; using the patterned second mask layer as a mask, the conductive layer on the sidewalls of the trench and the first surface is etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure, wherein the patterned first mask layer and the patterned second mask layer are formed using the same mask, and the pattern of the mask is designed based on the shape of the trench or the shape of the pad structure.

[0007] For example, when the pattern of the mask is designed based on the shape of the trench, a first adjustment process is performed on the patterned second mask layer, including: performing a first graying process on the patterned second mask layer, causing the circumferential edge of the patterned second mask layer to be inwardly recessed by a first preset distance in the direction pointing to its pattern center, thereby adjusting the pattern size of the patterned second mask layer to the pattern size of the predetermined formed pad structure.

[0008] For example, when the pattern of the mask is based on the shape design of the pad structure, a second adjustment process is performed on the patterned first mask layer, including: performing a second graying process on the patterned first mask layer, so that the circumferential edge of the patterned first mask layer is expanded outward by a second preset distance in a direction away from its pattern center, thereby adjusting the pattern size of the patterned first mask layer to the pattern size of the predetermined formed groove.

[0009] For example, the first preset distance is equal to the second preset distance.

[0010] For example, the gases used in the first ashing process and the second ashing process include at least one of oxygen, nitrogen, hydrogen or carbon monoxide.

[0011] For example, one of the first mask layer and the second mask layer is a positive photoresist layer, and the other is a negative photoresist layer.

[0012] For example, a dielectric layer is also formed on the first surface of the substrate, and the trench penetrates the dielectric layer and the substrate and exposes a portion of the surface of the interlayer dielectric layer.

[0013] For example, the pad structure is located at the bottom and sidewall of the connection hole and at the bottom of the trench, wherein the pad structure is connected to the interconnect structure through the connection hole, and the pad structure also has a gap with the sidewall of the trench.

[0014] For example, the material of the conductive layer includes at least one of aluminum, titanium, tungsten, tantalum, tantalum nitride, or titanium nitride.

[0015] This application also provides an image sensor, which is obtained using the aforementioned fabrication method.

[0016] The image sensor and its fabrication method provided in this application form a patterned first mask layer and a patterned second mask layer using the same mask. The pattern of the mask is designed based on the shape of the trench or the shape of the pad structure. This allows the same mask to simultaneously meet the dual process requirements of etching trenches and defining pad structures, reducing the number of masks. This not only significantly reduces process costs but also saves the time required to change masks during production, greatly improving the effective operating time and throughput of the equipment and increasing production efficiency. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0018] In the attached image: Figures 1A to 1F A schematic diagram showing the image sensor obtained by sequentially implementing the image sensor fabrication method of the related technology of this application is illustrated. Figure 2 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown; Figures 3A to 3G This illustration shows a schematic diagram of the image sensor obtained by sequentially implementing a method for fabricating an image sensor according to a specific embodiment of this application; Figures 4A to 4G A schematic diagram illustrating the image sensor obtained by sequentially implementing a method for fabricating an image sensor according to another specific embodiment of this application is shown. Figure 5 A schematic diagram of a trench and pad structure according to a specific embodiment of this application is shown. Detailed Implementation

[0019] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In related technologies, such as Figures 1A to 1F As shown, the method for generating the pad structure within the trench in a back-illuminated image sensor typically includes the following steps: First, the substrate 20 includes a first surface and a second surface. A first dielectric layer 11 is formed on the first surface, and a second dielectric layer 12 is formed on the second surface. An interconnect structure 202 is formed in the second dielectric layer 12. A patterned first photoresist layer 13 is formed on the first dielectric layer 11, wherein the patterned first photoresist layer 13 is formed using a first mask. The first dielectric layer 11 and the substrate 20 are etched using the patterned first photoresist layer 13 as a mask to form the trench 23. Then, a patterned second photoresist layer is formed by etching using a second mask. The process involves etching a second dielectric layer 12 using a patterned second photoresist layer as a mask to form a connection hole 24 at the bottom of a trench 23. Next, a conductive layer 25 is formed within the trench 23 and the connection hole 24, as well as on the surface of the first dielectric layer 11. Then, a patterned third photoresist layer 14 is formed on the conductive layer 25 within the trench 23, using a third photomask. Finally, using the patterned third photoresist layer 14 as a mask, the conductive layer 25 on the sidewalls of the trench 23 and the conductive layer 25 on the first dielectric layer 11 are etched away, leaving only the conductive layer 25 at the bottom of the trench 23 and within the connection hole 24 to form a pad structure 27. However, in related technologies, forming the pad structure within the trench requires multiple exposures, developments, and dry etching operations using three photomasks, significantly increasing production costs. Frequent switching of photomasks during mass production reduces the effective operating time and throughput of the photolithography equipment, thus affecting overall production efficiency.

[0025] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating an image sensor, such as... Figure 2 As shown, it mainly includes the following steps: Step S1, providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other, an interlayer dielectric layer is formed on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; Step S2: A patterned first mask layer is formed on the first surface of the substrate. Using the patterned first mask layer as a mask, the substrate is etched to form a trench that penetrates the substrate and exposes a portion of the surface of the interlayer dielectric layer. At least one connection hole is also formed at the bottom of the trench. Each connection hole communicates with the trench and exposes a portion of the interconnect structure. Step S3: Form a conductive layer covering the bottom and sidewalls of the trench and the first surface; Step S4: A patterned second mask layer is formed on the conductive layer. Using the patterned second mask layer as a mask, the conductive layer on the sidewalls of the trench and the first surface is etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure. The patterned first mask layer and the patterned second mask layer are formed using the same mask, and the pattern of the mask is designed based on the shape of the trench or the shape of the pad structure.

[0026] The image sensor and its fabrication method according to the embodiments of this application form a patterned first mask layer and a patterned second mask layer using the same mask. The pattern of the mask is designed based on the shape of the trench or the shape of the pad structure. This allows the same mask to simultaneously meet the dual process requirements of etching trenches and defining pad structures, reducing the number of masks. This not only significantly reduces process costs but also saves the time required to change masks during production, greatly improving the effective operating time and throughput of the equipment and increasing production efficiency.

[0027] Example 1 Below, for reference Figure 2 , Figures 3A to 3G as well as Figures 4A to 4G The method for fabricating the image sensor of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown. Figures 3A to 3G This illustration shows a schematic diagram of the image sensor obtained by sequentially implementing a method for fabricating an image sensor according to a specific embodiment of this application; Figures 4A to 4G A schematic diagram of the image sensor obtained by sequentially implementing a method for fabricating an image sensor according to another specific embodiment of this application is shown.

[0028] For example, the method for fabricating the image sensor of this application includes the following steps: First, step S1 is performed, providing a substrate, the substrate including a first surface and a second surface disposed opposite to each other, an interlayer dielectric layer being formed on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer.

[0029] In one example, such as Figure 3A and Figure 4A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz or glass substrate, or it may be a single layer or multiple layers of dielectric layers. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0030] For example, the substrate 20 includes a first surface and a second surface disposed opposite to each other, that is, the substrate 20 has a first surface and a second surface disposed opposite to each other along its thickness direction, wherein the first surface can serve as a subsequent photosensitive surface and the second surface can serve as a subsequent circuit surface.

[0031] In one example, such as Figure 3A and Figure 4A As shown, an interlayer dielectric layer 201 is formed on the second surface of the substrate 20, and an interconnect structure 202 is formed in the interlayer dielectric layer 201. Specifically, the interlayer dielectric layer 201 can be formed on the second surface of the substrate 20 using processes including but not limited to chemical vapor deposition (CVD). The interlayer dielectric layer 201 can be a single-layer structure or a multilayer composite structure, without specific limitation. For example, the interlayer dielectric layer 201 can be a multilayer composite structure composed of at least two of oxides, nitrides, and low-dielectric-constant materials. Exemplarily, after forming the interlayer dielectric layer 201, photolithography and etching processes are performed to define vias in the interlayer dielectric layer 201. Subsequently, metal material is filled into the vias using physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroplating processes to form the interconnect structure 202. The interconnect structure 202 realizes the electrical connection between the pixel unit and the driving circuit, ensuring efficient signal transmission. The formation process of the interconnect structure can also employ other conventional processes in the art, and the specific process will not be described in detail here.

[0032] Next, step S2 is performed to form a patterned first mask layer on the first surface of the substrate. Using the patterned first mask layer as a mask, the substrate is etched to form a trench that penetrates the substrate and exposes a portion of the surface of the interlayer dielectric layer. At least one connection hole is also formed at the bottom of the trench, and each connection hole communicates with the trench and exposes a portion of the interconnect structure.

[0033] In one example, such as Figure 3A and Figure 4A As shown, before forming the patterned first mask layer 22, a dielectric layer 21 is formed on the first surface of the substrate 20. Exemplarily, the dielectric layer 21 can be a composite structure composed of multiple dielectric materials, wherein the material of the dielectric layer 21 includes silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or a high dielectric constant material, etc. The methods for forming the dielectric layer 21 include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The dielectric layer mainly serves to provide electrical isolation, surface passivation to reduce dark current, block impurity diffusion, and act as an optical anti-reflection layer, thereby ensuring the photoelectric performance and reliability of the image sensor.

[0034] In one example, a patterned first mask layer 22 is formed on the dielectric layer 21. The material of the first mask layer 22 can be at least one of photoresist, spin-coated carbon, or silicon nitride; for example, photoresist is used as the material of the first mask layer 22. The first mask layer is formed on the surface of the dielectric layer 21 by spin coating or chemical vapor deposition (CVD), and then photolithography exposure and development processes are performed using a mask to obtain the patterned first mask layer 22, which provides a mask for subsequent etching processes of the substrate and dielectric layer, ensuring that the pattern size and positional accuracy of the trench meet the design requirements.

[0035] In one example, such as Figure 3B and Figure 4C As shown, using a patterned first mask layer 22 as a mask, the substrate 20 and dielectric layer 21 are etched to form a trench 23 that penetrates the substrate 20 and dielectric layer 21 and exposes a portion of the surface of the interlayer dielectric layer 201. The specific steps for forming the trench 23 include: first, forming a patterned first mask layer 22 on the dielectric layer 21, which defines the shape and location of the trench 23; then, using the patterned first mask layer 22 as a mask, etching the substrate 20, dielectric layer 21, and interlayer dielectric layer 201 to form the trench 23. The formed trench 23 extends from the surface of the dielectric layer 21, penetrates the dielectric layer 21 and substrate 20, and exposes a portion of the surface of the interlayer dielectric layer 201. Afterwards, the patterned first mask layer 22 is removed. The etching of the substrate, dielectric layer, and interlayer dielectric layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0036] In one example, such as Figure 3C and Figure 4D As shown, at least one connection hole 24 is also formed at the bottom of the trench 23. Each connection hole 24 communicates with the trench 23 and exposes a portion of the interconnect structure 202. Specifically, a patterned third mask layer is formed on the dielectric layer 21. The third mask layer covers the surface of the dielectric layer 21 and fills the trench 23. The patterned third mask layer defines the shape and position of the connection hole. Using the patterned third mask layer as a mask, the interlayer dielectric layer at the bottom of the trench 23 is etched to form at least one connection hole 24. The formed connection hole 24 is located at the bottom of the trench 23 and communicates with the trench 23, exposing a portion of the interconnect structure 202. Finally, the patterned third mask layer is removed. The etching of the interlayer dielectric layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching. Exemplarily, the number of connection holes 24 can be one, two, three, or more, and there is no specific limitation thereto.

[0037] It is worth mentioning that, instead of forming the dielectric layer 21, a patterned first mask layer 22 can be directly formed on the substrate 20. Then, the substrate 20 can be etched with the patterned first mask layer 22 to form a trench 23 that penetrates the substrate 20 and exposes part of the surface of the interlayer dielectric layer 201. This approach simplifies the process flow, reduces the time and cost required for dielectric layer deposition, and is suitable for application scenarios with low process complexity requirements or low dielectric layer functional requirements.

[0038] Continue, perform step S3 to form a conductive layer covering the bottom and sidewalls of the trench and the first surface.

[0039] In one example, such as Figure 3D and Figure 4EAs shown, a conductive layer 25 is formed covering the bottom and sidewalls of the trench 23 and the first surface. When a dielectric layer 21 is formed on the substrate 20, the conductive layer 25 covers the surface of the dielectric layer 21 and the bottom and sidewalls of the trench 23. The conductive layer 25 also fills each connection hole 24. Exemplarily, the material of the conductive layer 25 includes, but is not limited to, aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). It can be formed using processes including, but not limited to, physical vapor deposition (PVD) or chemical vapor deposition (CVD). During the conductive layer deposition process, process parameters are controlled to ensure that the conductive layer 25 has good step coverage on the sidewalls and bottom of the trench 23, avoiding voids or breaks, thereby forming a continuous and uniform conductive film. This conductive layer 25 not only covers the bottom and sidewalls of the trench 23 and fills the connection holes 24, but also covers the surface of the dielectric layer 21, providing a material basis for the subsequent formation of the pad structure through self-aligned etching. The thickness of the conductive layer is set according to process requirements to balance conductivity and the controllability of the etching process. It is worth mentioning that when the dielectric layer 21 is not formed on the substrate 20, the conductive layer 25 covers the first surface of the substrate 20, as well as the bottom and sidewalls of the trench 23.

[0040] Then, step S4 is performed to form a patterned second mask layer on the conductive layer. Using the patterned second mask layer as a mask, the conductive layer on the sidewalls of the trench and the first surface is etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure. The patterned first mask layer and the patterned second mask layer are formed using the same mask, and the pattern of the mask is designed based on the shape of the trench or the shape of the pad structure.

[0041] In one example, such as Figures 3E to 3G and Figures 4F to 4G As shown, a patterned second mask layer 26 is formed on the conductive layer 25. Using the patterned second mask layer 26 as a mask, the conductive layer 25 on the sidewalls of the trench 23 and the first surface is etched away, leaving only the conductive layer 25 at the bottom of the trench 23 to form the pad structure 27. Exemplarily, the material of the second mask layer 26 can be at least one of photoresist, spin-coated carbon, or silicon nitride; for example, photoresist is used as the material of the second mask layer 26. The etching of the conductive layer 25 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, or plasma etching. It should be noted that when a dielectric layer 21 is formed on the substrate 20, the conductive layer 25 covers the surface of the dielectric layer. In this case, using the patterned second mask layer 26 as a mask, the conductive layer 25 on the sidewalls of the trench 23 and the conductive layer 25 on the dielectric layer 21 is etched away, leaving only the conductive layer 25 at the bottom of the trench 23 to form the pad structure 27.

[0042] For example, one of the first mask layer 22 and the second mask layer 26 is a positive photoresist layer, and the other is a negative photoresist layer. For instance, the first mask layer 22 is a positive photoresist layer and the second mask layer 26 is a negative photoresist layer, or the first mask layer 22 is a negative photoresist layer and the second mask layer 26 is a positive photoresist layer. Utilizing the opposite mechanism of "dissolution in the exposure area" of positive photoresist and "curing and retention in the exposure area" of negative photoresist, combined with the aforementioned adjustment process, flexible control of the pattern size can be achieved while using the same mask.

[0043] In one example, the formed pad structure 27 is located at the bottom and sidewalls of the connection hole 24 and at the bottom of the trench 23, wherein the pad structure 27 is connected to the interconnect structure 202 through the connection hole 24, and the pad structure 27 also has a gap with the sidewalls of the trench 23. Figure 5 As shown, the formed pad structure 27 is located in the center region of the bottom of the trench 23, and the radial distance from the edge of the pad structure 27 to the edge of the trench 23 is the edge width w, where w is greater than or equal to zero.

[0044] For example, a patterned second mask layer 26 is formed on the conductive layer 25, wherein the patterned first mask layer 22 and the patterned second mask layer 26 are formed using the same mask, the pattern of which is designed based on the shape of the trench 23 or the shape of the pad structure 27.

[0045] When the pattern of the mask is based on the shape design of the trench, a first adjustment process is performed on the patterned second mask layer to adjust the pattern size of the patterned second mask layer to the pattern size of the predetermined formed pad structure; when the pattern of the mask is based on the shape design of the pad structure, a second adjustment process is performed on the patterned first mask layer to adjust the pattern size of the patterned first mask layer to the pattern size of the predetermined formed trench.

[0046] In one example, such as Figures 3A to 3GAs shown, when the mask pattern is designed based on the shape of the trench 23, a first adjustment process is performed on the patterned second mask layer 26, including: performing a first graying process on the patterned second mask layer 26, causing the circumferential edge of the patterned second mask layer 26 to be recessed inward by a first preset distance along the direction pointing to its pattern center, thereby adjusting the pattern size of the patterned second mask layer 26 to the pattern size of the predetermined formed pad structure 27. Specifically, when the mask image is designed according to the shape of the trench 23, since the linewidth of the trench 23 is greater than the linewidth of the pad structure, the initial pattern of the patterned second mask layer 26 is larger than the target image size of the pad structure. In order to match the pattern size of the patterned second mask layer 26 with the target pattern size of the pad structure, the patterned second mask layer 26 needs to be subjected to a first graying process to adjust the pattern size of the patterned second mask layer 26 to be consistent with the target pattern size of the pad structure. Specifically, the patterned second mask layer 26 is placed in a plasma environment for ashing. By controlling the ashing time, gas flow rate, and plasma power, the circumferential edge of the patterned second mask layer 26 is uniformly recessed inward by a first preset distance along the direction pointing to its pattern center. This first preset distance is determined based on the size difference between the trench 23 and the pad structure, thereby adjusting the pattern size of the patterned second mask layer 26 to match the target pattern size of the pad structure, ensuring the formation of a precise pad structure through subsequent etching. It should be noted that, as Figure 4F As shown, when the pattern of the mask is based on the shape design of the pad structure, there is no need to perform an adjustment process on the patterned second mask layer 26. The original pattern is retained as the etching mask, and the pad structure is directly etched.

[0047] Exemplarily, the gas used in the first ashing process includes at least one of oxygen, nitrogen, hydrogen, or carbon monoxide. Exemplarily, the first preset distance is greater than 0. Figure 5 As shown, the formed pad structure 27 is located in the center region of the bottom of the trench 23. The radial distance from the edge of the pad structure 27 to the edge of the trench 23 is the edge width w, which is also the first preset distance, where w is greater than zero.

[0048] In another example, such as Figures 4A to 4GAs shown, when the mask pattern is designed based on the shape of the pad structure 27, before forming the trench 23, a second adjustment process is performed on the patterned first mask layer 22, causing the circumferential edge of the patterned first mask layer 22 to expand outward by a second preset distance in a direction away from its pattern center, thereby adjusting the pattern size of the patterned first mask layer 22 to match the pattern size of the trench 23. That is, since the image of the mask is designed according to the shape of the pad structure 27, an adjustment process needs to be performed on the patterned first mask layer 22 before etching the trench to adjust its pattern size. Since the linewidth of the trench 23 is greater than the linewidth of the pad structure 27, the initial pattern of the patterned first mask layer 22 is smaller than the target image size of the trench. To match the pattern size of the patterned first mask layer 22 with the target pattern size of the trench, a second graying process needs to be performed on the patterned first mask layer 22 to adjust its pattern size to be consistent with the target pattern size of the trench 23. Specifically, the patterned first mask layer 22 is placed in a plasma environment for ashing treatment. By controlling the ashing time, gas flow rate and plasma power, the circumferential edge of the patterned first mask layer 22 is expanded outward by a second preset distance along the direction away from its pattern center. This second preset distance is determined according to the size difference between the trench and the pad structure, thereby adjusting the pattern size of the patterned first mask layer 22 to match the target pattern size of the trench. Subsequently, a conductive layer covering the bottom and sidewalls of the trench is formed, and a patterned second mask layer is formed on the conductive layer. The conductive layer is etched using the second mask layer as a mask to form the pad structure. The second mask layer does not require adjustment process and is directly etched using the same pattern size as the mask to form the pad structure.

[0049] It should be noted that, as Figure 3A As shown, when the pattern of the mask is based on the shape design of the trench, there is no need to perform an adjustment process on the patterned first mask layer 22. The original pattern is retained as the etching mask, and the trench is directly etched.

[0050] For example, the gas used in the second ashing process includes at least one of oxygen, nitrogen, hydrogen, or carbon monoxide. For example, the first preset distance is equal to the second preset distance, and the second preset distance is greater than 0. Therefore, by using the same mask to form a patterned first mask layer 22 and a patterned second mask layer 26, and the pattern of the mask is designed based on the shape of the trench 23 or the shape of the pad structure 27, the same mask can simultaneously meet the dual process requirements of etching the trench 23 and defining the pad structure 27, reducing the number of photolithography masks used. This not only significantly reduces process costs but also saves the time required to change masks during production, greatly improving the effective operating time and throughput of the equipment, and increasing production efficiency.

[0051] It should be noted that the ashing process can be performed on a separate machine or on the same machine as the dry etching step, depending on the production line configuration and process integration requirements. During the ashing process, by controlling the process parameters, it is ensured that the thickness of the patterned second mask layer after ashing is sufficient to block the subsequent dry etching process, so that the conductive layer pattern below the patterned second mask layer remains intact and is not over-etched.

[0052] In one example, after forming the pad structure 27, the process further includes removing the patterned second mask layer 26 on the pad structure 27. Exemplarily, processes such as ashing or wet cleaning can be used to remove the patterned second mask layer 26 and residual byproducts on the pad structure 27, ensuring a clean surface for the pad structure 27, providing a good interface for subsequent processes, and improving device reliability.

[0053] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0054] Thus, the process steps of the image sensor fabrication method according to the embodiments of this application are completed. It is understood that the image sensor fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0055] In summary, the image sensor fabrication method of this application uses the same mask to form a patterned first mask layer and a patterned second mask layer. The pattern of the mask is designed based on the shape of the trench or the shape of the pad structure. This allows the same mask to simultaneously meet the dual process requirements of etching trenches and defining pad structures, reducing the number of masks required. This not only significantly reduces process costs but also saves the time required to change masks during production, greatly improving the effective operating time and throughput of the equipment and increasing production efficiency.

[0056] This application also provides an image sensor, which can be prepared by the method described in Embodiment 1 above.

[0057] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating an image sensor, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other, an interlayer dielectric layer being formed on the second surface of the substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; A patterned first mask layer is formed on a first surface of the substrate. Using the patterned first mask layer as a mask, the substrate is etched to form a trench that penetrates the substrate and exposes a portion of the surface of the interlayer dielectric layer. At least one connection hole is also formed at the bottom of the trench. Each connection hole communicates with the trench and exposes a portion of the interconnect structure. A conductive layer is formed covering the bottom and sidewalls of the trench and the first surface; A patterned second mask layer is formed on the conductive layer. Using the patterned second mask layer as a mask, the sidewalls of the trench and the conductive layer on the first surface are etched away, leaving only the conductive layer at the bottom of the trench to form a pad structure. The patterned first mask layer and the patterned second mask layer are formed using the same mask, and the pattern of the mask is designed based on the shape of the trench or the shape of the pad structure.

2. The preparation method according to claim 1, characterized in that, When the pattern of the mask is designed based on the shape of the trench, a first adjustment process is performed on the patterned second mask layer, including: The patterned second mask layer is subjected to a first graying process, which causes the circumferential edge of the patterned second mask layer to be recessed inward by a first preset distance along the direction pointing to the center of its pattern, thereby adjusting the pattern size of the patterned second mask layer to the pattern size of the predetermined pad structure.

3. The preparation method according to claim 2, characterized in that, When the pattern of the mask is based on the shape design of the pad structure, a second adjustment process is performed on the patterned first mask layer, including: The patterned first mask layer is subjected to a second graying process, which causes the circumferential edge of the patterned first mask layer to expand outward by a second preset distance in a direction away from its pattern center, thereby adjusting the pattern size of the patterned first mask layer to the pattern size of the predetermined groove.

4. The preparation method according to claim 3, characterized in that, The first preset distance is equal to the second preset distance.

5. The preparation method according to claim 4, characterized in that, The gases used in the first ashing process and the second ashing process include at least one of oxygen, nitrogen, hydrogen, or carbon monoxide.

6. The preparation method according to claim 1, characterized in that, One of the first mask layer and the second mask layer is a positive photoresist layer, and the other is a negative photoresist layer.

7. The preparation method according to claim 1, characterized in that, A dielectric layer is also formed on the first surface of the substrate, and the trench penetrates the dielectric layer and the substrate and exposes a portion of the surface of the interlayer dielectric layer.

8. The preparation method according to claim 1, characterized in that, The pad structure is located at the bottom and sidewall of the connection hole and at the bottom of the trench. The pad structure is connected to the interconnect structure through the connection hole, and there is a gap between the pad structure and the sidewall of the trench.

9. The preparation method according to claim 1, characterized in that, The material of the conductive layer includes at least one of aluminum, titanium, tungsten, tantalum, tantalum nitride, or titanium nitride.

10. An image sensor, characterized in that, The image sensor is prepared using any one of the preparation methods described in claims 1 to 9.

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