A method for etching the surface of cadmium telluride crystals and a method for fabricating cadmium telluride semiconductor devices.

Abstract

This invention belongs to the field of semiconductor material surface treatment technology, specifically relating to a method for etching the surface of cadmium telluride crystals and a method for fabricating cadmium telluride semiconductor devices. The etching method provided by this invention uses an aqueous etching solution containing specific iodates, potassium iodide, and specific organic acids to etch the surface of cadmium telluride or cadmium zinc telluride crystals. Compared to the traditional bromomethanol process, this invention effectively inhibits the formation of a tellurium-rich layer on the crystal surface, removes damage layers introduced by machining, and eliminates microscopic scratches, significantly improving the flatness and cleanliness of the wafer surface. Semiconductor devices fabricated using this method, while ensuring good ohmic contact, can significantly reduce surface leakage current and enhance carrier transport efficiency, thereby improving the electrical stability, noise characteristics, and detection performance of the device. Furthermore, the process of this invention is stable and controllable, and the reagents used are highly safe and environmentally friendly, meeting the industrial requirements of clean production.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor material surface treatment technology, specifically relating to a method for etching the surface of cadmium telluride crystals and a method for preparing cadmium telluride semiconductor devices. Background Technology

[0002] Cadmium zinc telluride (CdTe) / CZT, as typical II-VI compound semiconductor materials, have become the core basic materials for various optoelectronic devices such as room temperature nuclear radiation detectors, infrared detectors, and photovoltaic devices due to their excellent room temperature photoelectric conversion characteristics, nuclear radiation detection characteristics, and good crystal film formation properties. They have shown irreplaceable application value in nuclear industry, aerospace, optoelectronic detection, new energy and other fields, and are currently a research and application hotspot in the field of semiconductor materials.

[0003] In the fabrication of CdTe / CZT-based semiconductor devices, the surface quality of the material directly affects electrode contact performance, carrier transport efficiency, and electrical stability. Currently, the industry commonly employs a process route of "mechanical grinding-mechanical polishing-chemical etching" to treat the wafer surface. Among these processes, chemical etching, as the core step in removing mechanically damaged layers, eliminating microscopic scratches, and optimizing surface smoothness, has a decisive impact on the subsequent device performance.

[0004] In the chemical etching process of CdTe / CZT materials, bromomethanol solution is currently the most commonly used etching solution both domestically and internationally. Due to its certain etching efficiency, it can quickly remove the mechanically damaged layer on the material surface, fitting the basic pace of industrial processing. It has become the mainstream technical solution for chemical etching treatment of CdTe / CZT materials at present and is widely used in the fabrication of various CdTe / CZT-based devices. However, with the continuous improvement of the performance requirements of high-end optoelectronic and nuclear radiation detection equipment, the technical defects exposed by the bromomethanol etching process are becoming increasingly apparent.

[0005] First, the consistency and stability of surface quality are difficult to control. In actual processing, it has been found that bromomethanol solution easily causes the chemical composition of the wafer surface to deviate from the stoichiometry, often accompanied by non-uniform residues of tellurium (Te)-rich layers or oxides. These surface residues significantly increase the surface leakage current of the device, leading to increased noise, decreased energy resolution, and severely affecting the stability and accuracy of the detector. Second, the controllability of process parameters is poor. The corrosive effect of bromomethanol solution is extremely sensitive to environmental factors such as concentration and temperature, making precise control of corrosion extremely difficult. This easily leads to over-corrosion or the generation of new microscopic damage, disrupting surface flatness and affecting the contact quality between the metal electrode and the crystal. Finally, there is significant pressure on production safety and environmental protection. Bromomethanol solution is highly volatile and toxic, and its volatilized harmful gases pose a threat to the health of operators. Furthermore, the waste liquid generated by this process is difficult and costly to treat, which is inconsistent with the current trend of clean production and green chemistry in the semiconductor manufacturing industry.

[0006] In summary, although the CdTe / CZT surface etching process based on bromomethanol solution has shortcomings in terms of surface quality control, process controllability, and safety and environmental protection, it remains the mainstream choice for CdTe / CZT material surface treatment at present due to the lack of mature alternatives that can currently achieve good etching efficiency, high etching precision, and easy and stable control of surface quality. Therefore, developing a novel surface etching treatment scheme that can achieve high-quality, low-damage surface etching while also ensuring process robustness and environmental friendliness is a highly technically challenging research topic with profound industrial application value. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a method for surface etching of cadmium telluride crystals and a method for fabricating cadmium telluride semiconductor devices. This invention aims to achieve low-damage surface etching treatment of cadmium telluride crystal materials, improve their surface quality, enhance the stability and electrical performance of devices fabricated based on this material, and simultaneously achieve better process controllability and environmental friendliness compared to existing technologies.

[0008] The first aspect of this invention provides a method for etching the surface of cadmium telluride crystals, wherein the cadmium telluride crystals are cadmium telluride crystals or cadmium zinc telluride crystals. The etching method uses an aqueous etching solution to treat the surface of the cadmium telluride crystals. The etching solution contains the following components at mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 5-25 wt% potassium iodide; Component C: 8-65 wt% lactic acid or citric acid; The corrosion treatment time is 3-20 minutes.

[0009] As a further optimization of the above corrosion method, the corrosion solution contains the following components at the following mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 5-10 wt% potassium iodide; Component C: 55-65 wt% lactic acid.

[0010] As a further optimization of the above corrosion method, the corrosion solution contains the following components at the following mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 20-25 wt% potassium iodide; Component C: 8-12 wt% citric acid.

[0011] As a further optimization of the above corrosion method, the corrosion solution contains the following components at the following mass percentage concentrations: Component A: 0.4-0.6 wt% potassium iodate; Component B: 7-9 wt% potassium iodide; Component C: 57-63 wt% lactic acid; The corrosion treatment time is 6-10 minutes.

[0012] As a further optimization of the above corrosion method, a step of surface pretreatment and polishing of the cadmium telluride crystal is included before corrosion treatment. The surface pretreatment steps include: ultrasonically cleaning the crystals sequentially in acetone, isopropanol and deionized water and then drying them; The polishing process includes: first, rough polishing with alumina polishing slurry, and then fine polishing with silica polishing slurry.

[0013] A second aspect of the present invention provides a method for fabricating a cadmium telluride semiconductor device, comprising the following steps: Surface pretreatment: The surface of the cadmium telluride crystals is washed to obtain clean and dry crystals; Polishing: The clean and dry surface of cadmium telluride crystals is polished to obtain crystals with a smooth surface.

[0014] Chemical corrosion: The surface of the cadmium telluride crystal is subjected to surface corrosion treatment, and the surface corrosion treatment adopts any of the above-mentioned surface corrosion methods for cadmium telluride crystals; Chemical passivation: Chemical passivation treatment is performed on the surface of cadmium telluride crystals after chemical etching; Electrode preparation: Metal electrodes, serving as anodes and / or cathodes, are prepared on the surface of cadmium telluride crystals.

[0015] As a further optimization of the above preparation method, the surface pretreatment step includes: ultrasonically cleaning the cadmium telluride crystals in acetone, isopropanol and deionized water for 10-20 minutes respectively, and then drying them with high-purity nitrogen to obtain clean and dry crystals.

[0016] As a further optimization of the above preparation method, the polishing step includes: first, rough polishing with alumina polishing slurry for 25-35 minutes, and then fine polishing with silicon oxide polishing slurry for 50-70 minutes.

[0017] As a further optimization of the above preparation method, the chemical passivation treatment uses an aqueous solution containing ammonium fluoride and hydrogen peroxide as the passivation solution, with the total mass of ammonium fluoride and hydrogen peroxide accounting for 8-12 wt% of the total mass of the passivation solution; the chemical passivation treatment time is 8-12 min; after passivation, the cadmium telluride crystal is placed in deionized water for ultrasonic cleaning to remove the residual passivating agent on the surface.

[0018] As a further optimization of the above preparation method, the electrode preparation steps include: preparing a Pt metal electrode by sputtering and depositing a film-like structure on the crystal surface using an ion sputtering process.

[0019] Beneficial effects Compared with existing technologies, the cadmium telluride crystal etching solution provided by this invention is adapted to the surface physicochemical properties of CdTe / CZT crystals. Combined with corresponding surface etching processes, it effectively reduces surface damage to CdTe / CZT crystals, inhibits the formation and deposition of Te-rich layers on the crystal surface, significantly improves the smoothness and cleanliness of the crystal surface, effectively avoids excessive corrosion or new damage defects caused by uncontrolled etching rates, optimizes the interfacial contact between the cadmium telluride crystal and the metal electrode, forming a good ohmic contact, effectively reducing the leakage current of semiconductor devices fabricated based on this crystal, improving the carrier transport efficiency within the crystal, and thus significantly improving the core performance of cadmium telluride semiconductor devices, such as electrical stability and noise characteristics. Furthermore, the etching solution used in this invention is safer for operator health and has lower environmental pollution, combining excellent performance with environmental friendliness. Attached Figure Description

[0020] Figure 1 The image shows the IV characteristic curves of the CdTe device prepared in Example 1.

[0021] Figure 2 The image shows the IV characteristic curves of the CdTe device prepared in Example 2.

[0022] Figure 3 The image shows the IV characteristic curves of the CdTe device prepared in Example 3.

[0023] Figure 4 The image shows the IV characteristic curves of the CdTe device prepared in Example 4.

[0024] Figure 5 The image shows the surface morphology of the CdTe wafer prepared in Example 2.

[0025] Figure 6 The surface morphology of the CdTe wafer prepared for Comparative Example 1 is shown.

[0026] Figure 7 Comparison of corrosion rates for different corrosion systems Detailed Implementation

[0027] The present invention is further illustrated below with specific embodiments. These embodiments are exemplary and intended to illustrate the problem and explain the present invention, and are not intended to be limiting.

[0028] Example 1 (1) Crystal surface pretreatment: The CdTe wafer was ultrasonically cleaned in acetone, isopropanol and deionized water for 15 minutes in sequence, and then dried with high-purity nitrogen to obtain a clean and dry wafer.

[0029] (2) Polishing of CdTe wafer: The CdTe wafer processed in step (1) is polished. Alumina polishing liquid is used for rough polishing for 30 minutes, followed by silicon oxide polishing liquid for fine polishing for 1 hour to obtain the polished CdTe wafer.

[0030] (3) Chemical etching: The wafer is placed in an etching device and then immersed in a prepared 0.5%KIO3-8%KI-60% lactic acid etching solution for 4 minutes. The etched CdTe wafer is then ultrasonically cleaned with deionized water to remove residual etchant and impurities from the wafer surface.

[0031] (4) Chemical passivation: After chemical etching, the CdTe surface is passivated for 10 min with a 10% NH4F / H2O2 solution. After the treatment, the wafer is placed in deionized water for ultrasonic cleaning to remove the passivating agent and other impurities remaining on the surface.

[0032] (5) Electrode preparation: A circular cutout mask is placed on the surface of the CdTe wafer after chemical passivation treatment in step (4). The wafer is then placed in an ion sputtering instrument. After vacuuming, a layer of metal Pt electrode is sputtered on the anode and cathode surfaces of the wafer.

[0033] The 0.5%KIO3-8%KI-60% lactic acid etching solution used in this embodiment is an aqueous etching solution with deionized water as the solvent. The mass percentage concentration of each component is based on the total mass of the etching solution. Specifically, the mass concentration of potassium iodate (KIO3) is 0.5 wt%, potassium iodide (KI) is 8 wt%, lactic acid is 60 wt%, and the remainder is deionized water. All components are mixed and stirred until completely dissolved to obtain the etching solution. The NH4F / H2O2 solution used in this embodiment is an aqueous passivation solution with deionized water as the solvent. The overall mass percentage concentration is 10 wt% based on the total mass of the passivation solution, meaning the total mass of ammonium fluoride (NH4F) and hydrogen peroxide (H2O2) accounts for 10 wt% of the total mass of the passivation solution. The mass ratio of ammonium fluoride to hydrogen peroxide is 1:1, and the remainder is deionized water. All components are mixed and stirred until homogeneous to obtain the passivation solution. The etching solutions and passivation solutions used in other embodiments of this invention also employ the same mass percentage concentration measurement method described above.

[0034] Example 2 (1) Crystal surface pretreatment: The CdTe wafer was ultrasonically cleaned in acetone, isopropanol and deionized water for 15 minutes in sequence, and then dried with high-purity nitrogen to obtain a clean and dry wafer.

[0035] (2) Polishing of CdTe wafer: The CdTe wafer processed in step (1) is polished. Alumina polishing liquid is used for rough polishing for 30 minutes, followed by silicon oxide polishing liquid for fine polishing for 1 hour to obtain the polished CdTe wafer.

[0036] (3) Chemical etching: The wafer is placed in an etching apparatus and then immersed in a prepared 0.5% KIO3-8% KI-60% lactic acid etching solution for 8 minutes. The etched CdTe wafer is then ultrasonically cleaned with deionized water to remove residual etchant and impurities from the wafer surface. (4) Chemical passivation: After chemical etching, the CdTe surface is passivated for 10 min with a 10% NH4F / H2O2 solution. After the treatment, the wafer is placed in deionized water for ultrasonic cleaning to remove the passivating agent and other impurities remaining on the surface.

[0037] (5) Electrode preparation: A circular cutout mask is placed on the surface of the CdTe wafer after chemical passivation treatment in step (4). The wafer is then placed in an ion sputtering instrument. After vacuuming, a layer of metal Pt electrode is sputtered on the anode and cathode surfaces of the wafer.

[0038] Example 3 (1) Crystal surface pretreatment: The CdTe wafer was ultrasonically cleaned in acetone, isopropanol and deionized water for 15 minutes in sequence, and then dried with high-purity nitrogen to obtain a clean and dry wafer.

[0039] (2) Polishing of CdTe wafer: The CdTe wafer processed in step (1) is polished. Alumina polishing liquid is used for rough polishing for 30 minutes, followed by silicon oxide polishing liquid for fine polishing for 1 hour to obtain the polished CdTe wafer.

[0040] (3) Chemical etching: The wafer is placed in an etching device and then immersed in a prepared 0.5%KIO3-8%KI-60% lactic acid etching solution for 16 minutes. The etched CdTe wafer is then ultrasonically cleaned with deionized water to remove residual etchant and impurities from the wafer surface.

[0041] (4) Chemical passivation: After chemical etching, the CdTe surface is passivated for 10 min with a 10% NH4F / H2O2 solution. After the treatment, the wafer is placed in deionized water for ultrasonic cleaning to remove the passivating agent and other impurities remaining on the surface.

[0042] (5) Electrode preparation: A circular cutout mask is placed on the surface of the CdTe wafer after chemical passivation treatment in step (4). The wafer is then placed in an ion sputtering instrument. After vacuuming, a layer of metal Pt electrode is sputtered on the anode and cathode surfaces of the wafer.

[0043] Example 4 (1) Crystal surface pretreatment: The CdTe wafer was ultrasonically cleaned in acetone, isopropanol and deionized water for 15 minutes in sequence, and then dried with high-purity nitrogen to obtain a clean and dry wafer.

[0044] (2) Polishing of CdTe wafer: The CdTe wafer processed in step (1) is polished. Alumina polishing liquid is used for rough polishing for 30 minutes, followed by silicon oxide polishing liquid for fine polishing for 1 hour to obtain the polished CdTe wafer.

[0045] (3) Chemical etching: The wafer is placed in an etching device and then immersed in a prepared 0.5% KIO3-22% KI-10% citric acid etching solution for 4 minutes. The etched CdTe wafer is then ultrasonically cleaned with deionized water to remove residual etchant and impurities from the wafer surface.

[0046] (4) Chemical passivation: After chemical etching, the CdTe surface is passivated for 10 min with a 10% NH4F / H2O2 solution. After the treatment, the wafer is placed in deionized water for ultrasonic cleaning to remove the passivating agent and other impurities remaining on the surface.

[0047] (5) Electrode preparation: A circular cutout mask is placed on the surface of the CdTe wafer after chemical passivation treatment in step (4). The wafer is then placed in an ion sputtering instrument. After vacuuming, a layer of metal Pt electrode is sputtered on the anode and cathode surfaces of the wafer.

[0048] Comparative Example 1 (1) Crystal surface pretreatment: The CdTe wafer was ultrasonically cleaned in acetone, isopropanol and deionized water for 15 minutes in sequence, and then dried with high-purity nitrogen to obtain a clean and dry wafer.

[0049] (2) Polishing of CdTe wafer: The CdTe wafer processed in step (1) is polished. Alumina polishing liquid is used for rough polishing for 30 minutes, followed by silicon oxide polishing liquid for fine polishing for 1 hour to obtain the polished CdTe wafer.

[0050] (3) Chemical etching: The wafer is placed in a special etching device and then immersed in a 2% bromomethanol (Br-MeOH) etching solution for 2 minutes. The etched CdTe wafer is then ultrasonically cleaned with methanol and deionized water to remove residual etchant and impurities from the wafer surface.

[0051] (4) Chemical passivation: After chemical etching, the CdTe surface is passivated for 10 min with a 10% NH4F / H2O2 solution. After the treatment, the wafer is placed in deionized water for ultrasonic cleaning to remove the passivating agent and other impurities remaining on the surface.

[0052] (5) Electrode preparation: A circular cutout mask is placed on the surface of the CdTe wafer after chemical passivation treatment in step (4). The wafer is then placed in an ion sputtering instrument. After vacuuming, a layer of metal Pt electrode is sputtered on the anode and cathode surfaces of the wafer.

[0053] Device performance testing and result analysis The fabricated device was characterized by current-voltage (IV) characteristics over a wide bias voltage range of -800V to 800V. Figure 1 , Figure 2 , Figure 3 , Figure 4The IV characteristic curves of the devices corresponding to Examples 1, 2, 3, and 4 are shown in sequence. The test results of Comparative Example 1, which uses a 2% bromomethanol etching process, are also included in each figure as a control.

[0054] As can be seen from the figures, after treatment with the etching solution system prepared according to this invention in Examples 1-4, the IV curves of the corresponding devices all strictly pass through the origin and are symmetrical about the center of the origin, indicating that charge carriers can achieve free bidirectional flow without potential barriers. This confirms that this process can achieve excellent ohmic contact between CdTe crystals and Pt electrodes. Therefore, the etching process of this invention can effectively suppress the formation of a Te-rich layer on the CdTe surface, avoid interfacial band distortion and contact barriers caused by the Te-rich layer, and ultimately achieve ideal ohmic contact effect.

[0055] Meanwhile, within the full bias voltage range, the leakage current density of devices in Examples 1-4 is significantly lower than that in Comparative Example 1. Especially under the rated operating conditions of a high bias voltage of 800V, the devices in the Example group not only have lower leakage current values, but also exhibit a much gentler increase in leakage current with increasing voltage compared to Comparative Example 1. These results indicate that the etching process of the present invention can achieve uniform and controllable micro-oxidation etching, which can remove the surface damage layer introduced by mechanical polishing and effectively suppress the generation of surface defect states and leakage channels, thereby reducing device leakage current at its source and significantly improving the electrical stability and noise characteristics of the device.

[0056] Comparison of the IV test results of each embodiment shows that the comprehensive control of the etching solution formulation and etching time can further optimize device performance. Specifically, Examples 1-3 used the same 0.5%KIO3-8%KI-60% lactic acid etching system, with only differences in etching time (4 min, 8 min, and 16 min respectively). As the etching time increased, the device leakage current showed a trend of first decreasing and then increasing. Among them, Example 2, with an etching time of 8 min, simultaneously achieved sufficient removal of surface damage and optimal control of surface morphology, resulting in a leakage current density as low as 22.2 nA / mm² at an 800V bias. 2 This is the lowest value among all experimental groups, while maintaining the optimal IV curve shape. Example 4 uses a 0.5%KIO3-22%KI-10%citric acid etching system, which also achieves good ohmic contact, but the control effect on surface defects is weaker than that of Example 2, and the leakage current is also slightly higher than that of Example 2.

[0057] The samples prepared by the chemical etching step in Example 2 and Comparative Example 1 were further characterized by electron microscopy. The surface morphologies of the samples in Example 2 and Comparative Example 1 are as follows: Figure 5 , Figure 6As shown, after treatment with the 0.5%KIO3-8%KI-60% lactic acid etching solution of Example 2, the wafer surface is extremely smooth and flat, eliminating scratches and damage defects left by mechanical polishing, and without the appearance of damage defects such as polishing scratches caused by excessive etching, significantly improving the wafer surface quality. In contrast, the sample surface of Comparative Example 1 shows dense and randomly distributed scratches. From the perspective of device performance mechanism, the scratches and damage layer remaining on the wafer surface can act as recombination centers or leakage channels for charge carriers, directly leading to a large leakage current in the device, which increases rapidly with increasing voltage. However, Example 2 of this invention achieves efficient and smooth removal of the surface damage layer through uniform and controllable micro-oxidation etching, which can significantly reduce surface defects, thereby greatly reducing device leakage current and improving device electrical stability.

[0058] Figure 7 The single-sided corrosion rates of different corrosion systems were recorded. The corrosion rate of Comparative Example 1 was 2.7 μm / min, while the corrosion rates of Examples 1 and 4 were even lower, at 0.3 μm / min and 0.8 μm / min, respectively. These results further confirm that the corrosion system of the present invention has a milder and more stable reaction process, good corrosion process stability, and excellent controllability of corrosion precision and results. It can effectively remove the surface damage layer while avoiding excessive erosion of the CdTe substrate, ultimately obtaining a high-quality surface with high smoothness.

[0059] The above embodiments are exemplary and are intended to illustrate the technical concept and features of the present invention, so that those skilled in the art can understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for etching the surface of cadmium telluride crystals, characterized in that, The cadmium telluride crystal is either cadmium telluride crystal or cadmium zinc telluride crystal. The corrosion method uses an aqueous corrosion solution to treat the surface of the cadmium telluride crystal. The corrosion solution contains the following components at mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 5-25 wt% potassium iodide; Component C: 8-65 wt% lactic acid or citric acid; The corrosion treatment time is 3-20 minutes.

2. The method for etching the surface of cadmium telluride crystals according to claim 1, characterized in that, The corrosive solution contains the following components at mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 5-10 wt% potassium iodide; Component C: 55-65 wt% lactic acid.

3. The method for etching the surface of cadmium telluride crystals according to claim 1, characterized in that, The corrosive solution contains the following components at mass percentage concentrations: Component A: 0.3-0.7 wt% potassium iodate; Component B: 20-25 wt% potassium iodide; Component C: 8-12 wt% citric acid.

4. The method for etching the surface of cadmium telluride crystals according to claim 1, characterized in that, The corrosive solution contains the following components at mass percentage concentrations: Component A: 0.4-0.6 wt% potassium iodate; Component B: 7-9 wt% potassium iodide; Component C: 57-63 wt% lactic acid; The corrosion treatment time is 6-10 minutes.

5. The method for etching the surface of cadmium telluride crystals according to any one of claims 1-4, characterized in that, Prior to the etching process, the process also includes surface pretreatment and polishing of the cadmium telluride crystals. The surface pretreatment steps include: ultrasonically cleaning the crystals sequentially in acetone, isopropanol and deionized water and then drying them; The polishing process includes: first, rough polishing with alumina polishing slurry, and then fine polishing with silica polishing slurry.

6. A method for fabricating a cadmium telluride semiconductor device, characterized in that, Includes the following steps: Surface pretreatment: The surface of the cadmium telluride crystals is washed to obtain clean and dry crystals; Polishing: Polishing the surface of clean and dry cadmium telluride crystals to obtain crystals with a smooth surface; Chemical corrosion: The surface of the cadmium telluride crystal is subjected to surface corrosion treatment, wherein the surface corrosion treatment is performed using the surface corrosion method for cadmium telluride crystals as described in any one of claims 1 to 5; Chemical passivation: Chemical passivation treatment is performed on the surface of cadmium telluride crystals after chemical etching; Electrode preparation: Metal electrodes, serving as anodes and / or cathodes, are prepared on the surface of cadmium telluride crystals.

7. The method for fabricating a cadmium telluride semiconductor device according to claim 6, characterized in that, The surface pretreatment step includes: ultrasonically cleaning the cadmium telluride crystals in acetone, isopropanol and deionized water for 10-20 minutes respectively, and then drying them with high-purity nitrogen to obtain clean and dry crystals.

8. The method for fabricating a cadmium telluride semiconductor device according to claim 6, characterized in that, The polishing steps include: first, using alumina polishing slurry for rough polishing, with a rough polishing time of 25-35 minutes, and then using silicon oxide polishing slurry for fine polishing, with a fine polishing time of 50-70 minutes.

9. The method for fabricating a cadmium telluride semiconductor device according to claim 6, characterized in that, The chemical passivation treatment uses an aqueous solution containing ammonium fluoride and hydrogen peroxide as the passivation solution, and the total mass of the ammonium fluoride and hydrogen peroxide accounts for 8-12 wt% of the total mass of the passivation solution. The chemical passivation treatment time is 8-12 min. After the passivation is completed, the cadmium telluride crystal is placed in deionized water for ultrasonic cleaning to remove the residual passivating agent on the surface.

10. The method for fabricating a cadmium telluride semiconductor device according to claim 6, characterized in that, The electrode preparation steps include: preparing a film-like Pt metal electrode by sputtering deposition on the crystal surface using an ion sputtering process.

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