Method for manufacturing solar cell and solar cell

Abstract

The application discloses a preparation method of a solar cell and the solar cell, adopts a wet etching patterning process to replace a laser patterning, and can directly form a steep and abrupt PN junction between a first doped layer and a second doped layer. The width of a doped transition region of the PN junction is far less than the width of a depletion region, and the doped distribution is similar to a step function, so that the built-in electric field strength is higher and the recombination current is lower. On this basis, the application constructs a triple synergistic electric isolation mechanism without a physical isolation groove: the PN junction self-built electric field provides the first line of defense for lateral isolation; the carrier selection characteristic of the doped layer on both sides forms a reflection potential barrier to minority carriers, constituting the second line of defense; and the tunneling layer only allows selective tunneling of target carriers, prevents non-selective carrier injection, and cuts off the vertical leakage channel of the PN junction to the silicon substrate, so that the self-isolation type solar cell with high efficiency and high yield is realized.

Description

Technical Field

[0001] This invention belongs to the field of solar cell fabrication technology, specifically relating to a method for fabricating a solar cell and the solar cell itself. Background Technology

[0002] Tunnel oxide passivated contact back contact (TBC) cells completely eliminate the light loss caused by the front grid lines of traditional cells by integrating the PN junction and metal electrodes on the back of the cell. It is one of the important core technologies in the field of high-efficiency crystalline silicon solar cells.

[0003] However, existing TBC batteries face two major bottlenecks in their industrialization process: the inherent defects of the physical isolation structure and the inherent technical limitations of laser patterning technology.

[0004] To prevent carrier recombination and bypass leakage between the P-type and N-type regions on the back of the battery, the industry commonly uses processes such as laser grooving, insulating layer deposition, and patterned etching to form a physical isolation trench structure. This technology requires multiple additional specialized processes, resulting in high equipment investment. The isolation trench structure introduces numerous interface defects and stress concentration points, reducing passivation effectiveness and long-term battery reliability. During mass production, impurities easily remain within the isolation trench structure, and the insulating layer is prone to detachment, making it difficult to achieve a battery yield exceeding 90% for a long time, severely restricting the economic viability of large-scale mass production.

[0005] Laser patterning technology has failed to overcome the inherent physical limitations of laser processing, mainly in the following aspects: First, the heat-affected zone (HAZ) leads to PN junction degradation. Even with picosecond or femtosecond lasers, a 100nm to 200nm HAZ is unavoidable. This thermal effect causes the formation of a gradually changing PN junction at the PN boundary, weakening the built-in electric field by more than 30%, directly destroying the self-isolation effect of the PN junction. Second, insufficient etching precision easily damages critical film layers. The poor precision of laser ablation depth control makes it easy to etch through ultra-thin tunneling layers, forming fatal leakage channels. Third, limited mass production capacity. Laser equipment is expensive per unit, and the capacity of a single unit is limited, making it difficult to support the demand for GW-level large-scale mass production.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a method for preparing a solar cell and a solar cell that can solve the problems in the prior art.

[0008] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0009] A method for preparing a solar cell, comprising:

[0010] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacently distributed first regions and second regions;

[0011] A tunneling layer and a first doped layer are formed sequentially on the second surface;

[0012] The first doped layer in the second region is removed by a wet etching process, while the first doped layer in the first region is retained.

[0013] A second doped layer is formed on the tunneling layer in the second region. The doping type of the second doped layer is opposite to that of the first doped layer. The second doped layer and the first doped layer are attached to each other at the side interface.

[0014] In one or more embodiments of the present invention, the ratio of the surface doping concentration of the second doped layer to the surface doping concentration of the first doped layer is greater than or equal to 10.

[0015] In one or more embodiments of the present invention, a tunneling layer and a first doped layer are formed sequentially on the second surface, including:

[0016] A tunneling layer is formed on the second surface;

[0017] A first intrinsic layer is formed on the tunneling layer;

[0018] The first intrinsic layer is converted into a first doped layer, and a first doped glass layer is formed on the surface of the first doped layer;

[0019] The surface doping concentration of the first doped layer is 3×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq.

[0020] In one or more embodiments of the present invention, a wet etching process is used to remove the first doped layer in the second region, including:

[0021] A first mask layer is formed on the first doped glass layer in the first region using a screen printing process;

[0022] The first doped layer on the second region is removed using a first etching solution;

[0023] Remove the first mask layer;

[0024] Specifically, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is controlled to be greater than 100:1, the thickness change of the tunneling layer after etching is less than or equal to 0.2 nm, and the roughness of the side interface of the first doped layer is less than or equal to 0.8 nm.

[0025] In one or more embodiments of the present invention, the first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid and acetic acid;

[0026] By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is made greater than 100:1.

[0027] In the mixed etching solution, the ratio of hydrofluoric acid, nitric acid and acetic acid is 1:(4-5):(10-12).

[0028] In one or more embodiments of the present invention, the first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid, acetic acid, benzotriazole and polyethylene glycol;

[0029] By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is made greater than 200:1. After etching, the thickness change of the tunneling layer is less than or equal to 0.1 nm, and the etching amount at the side interface of the first doped layer is less than or equal to 0.5 μm.

[0030] In one or more embodiments of the present invention, a second doped layer is formed on the tunneling layer of the second region, including:

[0031] A second intrinsic layer is formed on the tunneling layer in the second region and the first doped glass layer in the first region;

[0032] The second intrinsic layer is transformed into a second doped layer, and a second doped glass layer is formed on the surface of the second doped layer;

[0033] A second mask layer is formed on the second doped glass layer in the second region;

[0034] Remove the second doped glass layer and the second doped layer from the first region;

[0035] Remove the second mask layer, the first doped glass layer on the first region, and the second doped glass layer on the second region;

[0036] The surface doping concentration of the second doped layer is 3×10⁻⁶. 20 cm -3 -6×10 20cm -3 The sheet resistance is 30Ω / sq-80Ω / sq. The second doped layer and the first doped layer form a PN junction. The width of the doped transition region of the PN junction is smaller than the width of the depletion region.

[0037] In one or more embodiments of the present invention, the second doped layer and the first doped layer form a PN junction;

[0038] The width of the doped transition region of the PN junction is less than or equal to 5 nm; and / or, the roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm; and / or, the surface of the second doped layer of the PN junction is flush with the surface of the first doped layer; and / or, the thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm.

[0039] In one or more embodiments of the present invention, the preparation method further includes:

[0040] A light-trapping structure is fabricated on the first surface of the silicon substrate using a texturing process; and / or,

[0041] A first passivation layer and / or a first antireflection layer are formed on a first surface of a silicon substrate; and / or,

[0042] A second passivation layer and / or a second antireflection layer are prepared on a second surface of a silicon substrate; and / or,

[0043] Electrodes are fabricated on the second surface of a silicon substrate, which are in contact with the first doped layer and the second doped layer, respectively.

[0044] A method for preparing a solar cell, comprising:

[0045] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacently distributed first regions and second regions;

[0046] A tunneling layer and a first doped layer are formed sequentially on the second surface;

[0047] The first doped layer and tunneling layer of the second region are removed by wet etching process, while the first doped layer and tunneling layer of the first region are retained;

[0048] A tunneling layer and a second doped layer are formed sequentially on the second region. The second doped layer has the opposite doping type to the first doped layer, and the second doped layer and the first doped layer are attached to each other at the side interface.

[0049] In one or more embodiments of the present invention, the ratio of the surface doping concentration of the second doped layer to the surface doping concentration of the first doped layer is greater than or equal to 10.

[0050] In one or more embodiments of the present invention, a tunneling layer and a first doped layer are formed sequentially on the second surface, including:

[0051] A tunneling layer is formed on the second surface;

[0052] A first intrinsic layer is formed on the tunneling layer;

[0053] The first intrinsic layer is converted into a first doped layer, and a first doped glass layer is formed on the surface of the first doped layer;

[0054] The surface doping concentration of the first doped layer is 3×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq.

[0055] In one or more embodiments of the present invention, a wet etching process is used to remove the first doped layer and tunneling layer in the second region, including:

[0056] A first mask layer is formed on the first doped glass layer in the first region using a screen printing process;

[0057] The first doped layer and tunneling layer on the second region are removed using a first etching solution;

[0058] Remove the first mask layer.

[0059] In one or more embodiments of the present invention, the first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid, and acetic acid; or,

[0060] The first etching solution is a mixed etching solution composed of hydrofluoric acid, nitric acid, acetic acid, benzotriazole and polyethylene glycol.

[0061] In one or more embodiments of the present invention, a tunneling layer and a second doped layer are formed sequentially on the second region, including:

[0062] A tunneling layer is formed on the second region and the first doped glass layer in the first region;

[0063] A second intrinsic layer is formed on the tunneling layer;

[0064] The second intrinsic layer is transformed into a second doped layer, and a second doped glass layer is formed on the surface of the second doped layer;

[0065] A second mask layer is formed on the second doped glass layer in the second region;

[0066] Remove the second doped glass layer, the second doped layer, and the tunneling layer on the first doped glass layer in the first region;

[0067] Remove the second mask layer, the first doped glass layer on the first region, and the second doped glass layer on the second region;

[0068] The surface doping concentration of the second doped layer is 3×10⁻⁶. 20 cm -3 -6×10 20 cm -3 The sheet resistance is 30Ω / sq-80Ω / sq. The second doped layer and the first doped layer form a PN junction. The width of the doped transition region of the PN junction is smaller than the width of the depletion region.

[0069] In one or more embodiments of the present invention, the second doped layer and the first doped layer form a PN junction;

[0070] The width of the doped transition region of the PN junction is less than or equal to 5 nm; and / or, the roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm; and / or, the surface of the second doped layer of the PN junction is flush with the surface of the first doped layer; and / or, the thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm.

[0071] In one or more embodiments of the present invention, the preparation method further includes:

[0072] A light-trapping structure is fabricated on the first surface of the silicon substrate using a texturing process; and / or,

[0073] A first passivation layer and / or a first antireflection layer are formed on a first surface of a silicon substrate; and / or,

[0074] A second passivation layer and / or a second antireflection layer are prepared on a second surface of a silicon substrate; and / or,

[0075] Electrodes are fabricated on the second surface of a silicon substrate, which are in contact with the first doped layer and the second doped layer, respectively.

[0076] A solar cell structure, characterized in that it is prepared by the above-described method for preparing solar cells.

[0077] Compared with existing technologies, the solar cell fabrication method and solar cell of the present invention, through a wet etching patterning process, can form a steeply abrupt PN junction between the first and second doped layers—the doping concentration abruptly changes from one doping type to another at the PN junction interface. The width of the doped transition region is much smaller than the width of the entire depletion region (space charge region), and the doping distribution curve approximates a step function, thus exhibiting higher built-in electric field strength and lower recombination current. In this invention, the built-in electric field of the PN junction provides the first line of defense for lateral isolation. The carrier selectivity characteristics of the first and second doped layers form a reflective barrier for minority carriers, constituting the second line of defense. The tunneling layer only allows collected target carriers to selectively tunnel, preventing the injection of non-selective carriers, thereby cutting off the vertical channel for leakage from the PN junction to the silicon substrate, constituting the third line of defense. This achieves complete electrical isolation without the need for physical isolation trenches.

[0078] The solar cell fabrication method and solar cell of this invention eliminate the need for laser patterning, completely avoiding the impact of the heat-affected zone of picosecond / femtosecond lasers on the quality of the PN junction. Due to the absence of laser thermal interference, the PN junction boundary can maintain a steep metallurgical junction structure; that is, the PN junction has a steep metallurgical junction interface where the doping concentration abruptly changes from P-type to N-type, thus fully preserving the built-in electric field (with a reduction of less than 5%) and ensuring the self-isolation capability of the PN junction. Simultaneously, the absence of laser ablation means that the thin tunneling layer will not be broken down or damaged due to etching precision issues, eliminating the formation of leakage channels at the source and significantly reducing reverse leakage current.

[0079] The solar cell fabrication method and solar cell of the present invention achieve equivalent electrical isolation between the first and second doped layers without the need for physical isolation trenches through the synergistic effect of carrier selectivity of different types of heavily doped layers, tunneling layer barrier, and built-in electric field of PN junction, ensuring directional transport of carriers. Experimental and theoretical studies show that this structure can enable the theoretical conversion efficiency of the trenchless cell to reach over 25%, while also possessing high open-circuit voltage, high fill factor, and high short-circuit current density.

[0080] The solar cell fabrication method and solar cell of this invention eliminate the need for physical isolation processes such as laser grooving, insulating layer deposition, and patterned etching, completely avoiding interface defects and stress concentration points introduced by the isolation trench, and significantly improving the interface passivation quality and long-term cell reliability. Simultaneously, it fundamentally eliminates yield-loss factors such as residual impurities in the isolation trench and insulating layer detachment, enabling mass production yields to exceed 90%, thus breaking through the yield bottleneck that has long constrained the industrialization of solar cells.

[0081] The solar cell preparation method and solar cell of the present invention are highly compatible with mainstream solar cell process platforms, and can achieve technological upgrades without large-scale modifications to production lines. This feature significantly lowers the technology introduction threshold and is conducive to industrialization and application in the short term. Attached Figure Description

[0082] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0083] Figure 1 This is a process flow diagram of the method for preparing a solar cell in Embodiment 1 of the present invention;

[0084] Figures 2a to 2k This is a schematic diagram of the process steps for fabricating a solar cell in Embodiment 1 of the present invention;

[0085] Figure 3 This is a process flow diagram of the method for preparing a solar cell in Embodiment 2 of the present invention;

[0086] Figures 4a to 4k This is a schematic diagram of the process steps for preparing a solar cell in Embodiment 2 of the present invention. Detailed Implementation

[0087] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0088] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0089] In this invention, unless otherwise expressly specified and limited, the disclosed "range" is defined in the form of a lower limit and / or an upper limit. A given range is defined by selecting a lower limit and / or an upper limit, which defines the boundary of the particular range. Ranges defined in this way may include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form an unspecified range, and any lower limit can be combined with other lower limits to form an unspecified range. Similarly, any upper limit can be combined with any other upper limit to form an unspecified range. Furthermore, each individually disclosed point or single value can itself serve as a lower limit or upper limit and can be combined with any other point or single value or with other lower limits or upper limits to form an unspecified range.

[0090] In this invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0091] In this invention, unless otherwise expressly specified and limited, all embodiments and optional embodiments, or all technical features and optional technical features, can be combined with each other to form new technical solutions, and such technical solutions should be considered to be included in the disclosure of this application.

[0092] As mentioned in the background technology, the current battery industrialization faces two major bottlenecks: First, the physical isolation trench process requires additional steps, resulting in a yield rate of less than 90% and a decline in reliability. Second, the laser patterning solution has a heat-affected zone, which weakens the built-in electric field by more than 30% and is prone to penetrating the tunneling layer. In addition, the equipment is expensive and has limited production capacity.

[0093] Based on this, the present invention provides a method for fabricating a solar cell and a solar cell in which a wet etching patterning process is used instead of laser patterning, which can directly form a steeply abrupt PN junction between the first and second doped layers. The width of the doped transition region of this PN junction is much smaller than the width of the depletion region, and the doping distribution approximates a step function, thus resulting in a higher built-in electric field strength and a lower recombination current. Based on this, the present invention constructs a triple synergistic electrical isolation mechanism without the need for physical isolation trenches: the self-built electric field of the PN junction provides the first line of defense for lateral isolation; the carrier selection characteristics of the two doped layers form a reflective barrier for minority carriers, constituting the second line of defense; the tunneling layer only allows selective tunneling of target carriers, preventing the injection of non-selective carriers and cutting off the vertical leakage channel from the PN junction to the silicon substrate. Since the laser process is completely abandoned, the damage to the PN junction by the heat-affected zone is completely avoided, the weakening of the built-in electric field is less than 5%, and the extremely thin tunneling layer will not be broken down due to ablation precision issues, thus eliminating the leakage channel at the source and truly realizing a high-efficiency, high-yield self-isolated solar cell.

[0094] The present invention will be further illustrated by the following specific embodiments.

[0095] Example 1:

[0096] In this embodiment, the solar cell is illustrated using a TBC cell (Tunnel Oxide Passivated Contact BackContact Battery) as an example. (See reference...) Figure 1 As shown, the preparation method of the TBC battery in this embodiment specifically includes the following steps:

[0097] S1, a silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacent first regions and second regions.

[0098] S2, a tunneling layer and a first doped layer are formed sequentially on the second surface.

[0099] S3, the first doped layer of the second region is removed by wet etching process, while the first doped layer of the first region is retained.

[0100] S4, a second doped layer is formed on the tunneling layer in the second region. The doping type of the second doped layer is opposite to that of the first doped layer. The second doped layer and the first doped layer are attached to each other at the side interface. The ratio of the surface doping concentration of the second doped layer to the surface doping concentration of the first doped layer is greater than or equal to 10.

[0101] S5, a light-trapping structure is prepared on the first surface of the silicon substrate by a texturing process.

[0102] S6, a first passivation layer and / or a first antireflection layer are prepared on a first surface of a silicon substrate.

[0103] S7, a second passivation layer and / or a second antireflection layer are prepared on the second surface of the silicon substrate.

[0104] S8, electrodes are formed on the second surface of the silicon substrate that are in contact with the first doped layer and the second doped layer, respectively.

[0105] In step S2, a tunneling layer and a first doped layer can be sequentially stacked on the second surface by first forming a tunneling layer on the second surface, then forming a first intrinsic layer on the tunneling layer, then converting the first intrinsic layer into a first doped layer, and finally forming a first doped glass layer on the surface of the first doped layer. The surface doping concentration of the first doped layer is 3 × 10⁻⁶. 19 cm -3 -6×10 19 cm -3 For example, it can be 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq, for example, it can be 120Ω / sq, 150Ω / sq, 180Ω / sq, 210Ω / sq, 250Ω / sq, etc., or it can be a range of any of the above values.

[0106] In step S3, the first doped layer in the second region is removed by a wet etching process, specifically including: forming a first mask layer on the first doped glass layer in the first region by screen printing; removing the first doped layer in the second region by a first etching solution; and removing the first mask layer.

[0107] The first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid, and acetic acid. By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etchant for the first doped layer and the tunneling layer is made greater than 100:1. For example, it can be 101:1, 110:1, 150:1, 190:1, 250:1, 500:1, 1000:1, 2000:1, or any range of the above values. After etching, the thickness change of the tunneling layer is less than or equal to 0.2 nm. For example, it can be 0.2 nm, 0.15 nm, 0.1 nm, 0.05 nm, 0.02 nm, 0.01 nm, or any range of the above values. The roughness of the side interface of the first doped layer is less than or equal to 0.8 nm. For example, it can be 0.8 nm, 0.6 nm, 0.4 nm, 0.2 nm, 0.05 nm, 0.01 nm, or any range of the above values. Preferably, the ratio of hydrofluoric acid, nitric acid, and acetic acid in the mixed etching solution is 1:(4-5):(10-12), for example, 1:4:10, 1:5:10, 1:4:12, 1:5:12, etc., or any range of the above values.

[0108] The first etching solution can also be a mixed etching solution containing hydrofluoric acid, nitric acid, acetic acid, benzotriazole, and polyethylene glycol. By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etching solution for the first doped layer to the tunneling layer is made greater than 200:1, for example, it can be 201:1, 210:1, 250:1, 300:1, 1000:1, 2000:1, or any range of the above values. After etching, the thickness change of the tunneling layer is less than or equal to 0.1 nm, for example, it can be 0.1 nm, 0.05 nm, 0.01 nm, 0.005 nm, 0.002 nm, 0.001 nm, or any range of the above values. The etching depth of the side interface of the first doped layer is less than or equal to 0.5 μm, for example, it can be 0.5 μm, 0.4 μm, 0.2 μm, 0.05 μm, 0.01 μm, etc., or it can be any range of the above values.

[0109] In step S4, a second intrinsic layer can be formed first on the tunneling layer of the second region and the first doped glass layer of the first region; then the second intrinsic layer is converted into a second doped layer, and a second doped glass layer is formed on the surface of the second doped layer; then a second mask layer is formed on the second doped glass layer of the second region, and the second doped glass layer and the second doped layer on the first region are removed; finally, the second mask layer, the first doped glass layer on the first region, and the second doped glass layer on the second region are removed; thus, a second doped layer is formed on the tunneling layer of the second region. The surface doping concentration of the second doped layer is 3 × 10⁻⁶. 20cm -3 -6×10 20 cm -3 , which may for example be 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , etc., or may be a range composed of any of the above values; the sheet resistance is 30 Ω / sq to 80 Ω / sq, which may for example be 30 Ω / sq, 50 Ω / sq, 70 Ω / sq, 80 Ω / sq, etc., or may be a range composed of any of the above values. The second doped layer and the first doped layer form an abrupt PN junction, and the width of the doping transition region of the PN junction is smaller than the width of the depletion region.

[0110] Preferably, the width of the doping transition region of the PN junction is less than or equal to 5 nm, which may for example be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.1 nm, 0.01 nm, etc., or may be a range composed of any of the above values. The roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm, which may for example be 1 nm, 0.5 nm, 0.1 nm, 0.05 nm, 0.02 nm, 0.01 nm, etc., or may be a range composed of any of the above values. The surface of the second doped layer of the PN junction is flush with the surface of the first doped layer. The thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm, which may for example be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.2 nm, 0.05 nm, etc., or may be a range composed of any of the above values.

[0111] The preparation method of the present embodiment will be described in detail below in conjunction with Figures 2a-2k , so as to facilitate understanding of the technical solution of the present embodiment.

[0112] as shown in the Figure 2a , a silicon substrate 10 is provided.

[0113] The silicon substrate 10 in this embodiment includes a first surface S1 (i.e., front surface or light-receiving surface) and a second surface S2 (i.e., back surface or light-back surface) disposed opposite to each other, and the second surface includes a first region S21 and a second region S22 that are alternately and adjacently distributed; that is, one second region S22 is disposed between two adjacent first regions S21, and one first region S21 is disposed between two adjacent second regions S22; there is no interval between the first region S21 and the second region S22.

[0114] Exemplarily, the silicon substrate 10 in this embodiment is an N-type monocrystalline silicon wafer. First, the silicon substrate 10 is subjected to alkaline polishing and acid washing to remove damage and impurities on the surface of the silicon substrate 10, so as to obtain a clean and flat surface. For example, rough polishing is performed in a KOH alkaline solution at 80°C to remove the slicing damage layer, followed by sequential cleaning with standard SC-1 (NH4OH:H2O2:H2O) and SC-2 (HCl:H2O2:H2O) cleaning solutions to remove metal ions and particulate contaminants, and finally rinsing with deionized water and drying to obtain a silicon wafer with a clean and flat surface.

[0115] See Figure 2b as shown, the tunneling layer 21 and the first intrinsic layer 22' are deposited over the entire surface on the second surface S2 of the silicon substrate 10; then see Figure 2c as shown, the first intrinsic layer 22' is doped to convert the first intrinsic layer 22' into the first doped layer 22, and the first doped glass layer 23 is formed on the surface of the first doped layer 22.

[0116] Exemplarily, the cleaned silicon substrate 10 is loaded into a low-pressure chemical vapor deposition (LPCVD) furnace tube, the tunneling layer 21 is first prepared using a low-pressure chemical vapor deposition process, and then the first intrinsic layer 22' is deposited in-situ. Boron doping is performed using a tubular high-temperature diffusion furnace, and high-temperature boron doping is carried out at 920°C-940°C to form a surface doping concentration of 3×10 19 cm -3 -6×10 19 cm -3 ; a uniform first doped layer 22 with a sheet resistance of 120Ω / sq-250Ω / sq, and the first doped glass layer 23 is generated in-situ during the doping process.

[0117] The tunneling layer 21 in this embodiment is a tunneling oxide layer, which may be any one or a combination of a silicon oxide layer and a silicon oxynitride layer, with a thickness of 1.2nm-1.8nm, for example, may be 1.2nm, 1.5nm, 1.7nm, 1.8nm, etc., or may be a range composed of any of the above values. The first intrinsic layer 22' is an intrinsic polysilicon layer, with a thickness of 5nm-10nm, for example, may be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc., or may be a range composed of any of the above values. The first doped layer 22 is a P-type doped polysilicon layer. The first doped glass layer 23 is borosilicate glass (BSG) naturally formed on the surface of the first doped layer 22 under a high-temperature process.

[0118] See Figure 2d as shown, a first mask layer 61 is formed on the first doped glass layer 23 in the first region S21 by a screen printing process.

[0119] Exemplarily, acid-resistant mask paste is printed on the first region S21 of the second surface S2 of the silicon substrate 10 by a precision screen printing apparatus, and the alignment accuracy between the mask paste region and the first region S21 is controlled to be ≤±2 μm, so that the printed pattern matches the first region S21 as completely as possible. Drying and curing are performed at a temperature of 170°C to 190°C to make the mask cover firmly.

[0120] As shown Figure 2e , a wet etching process is used to remove the first doped glass layer 23 and the first doped layer 22 in the second region S22, expose the tunneling layer 21 in the second region S22, and remove the first mask layer 61. For example, an HF-HNO3-CH3COOH system etching solution can be used to etch the layer structure on the second region S22 not protected by the first mask layer 61 at room temperature, so as to simultaneously complete the patterning of the first doped layer 22, the removal of the first doped glass layer 23 and the removal of surface impurities. The etching selectivity ratio of the HF-HNO3-CH3COOH system etching solution to the first doped layer 22 and the tunneling layer 21 is controlled to be greater than 100:1, so as to ensure that the thickness variation of the tunneling layer 21 after etching is less than or equal to 0.2 nm, and the roughness of the side interface of the first doped layer 22 is less than or equal to 0.8 nm. Subsequently, the first mask layer 61 is removed by an alkaline solution.

[0121] Exemplarily, the masked silicon substrate is immersed in a mixed etching solution at room temperature with a volume ratio of 49% HF:68% HNO3:99.5% CH3COOH of 1:5:10. The reaction temperature is controlled at 25°C±1°C (room temperature), the etching time is 35s-45s, the mixture is continuously circulated and stirred during the etching process, and the flow rate of the mixed etching solution is maintained at 0.5m / s. Immediately after etching, rinse with dilute HCl for 1 min, perform overflow cleaning with deionized water for 3 min, and dry with hot air.

[0122] Wherein, HNO3 acts as an oxidant to oxidize polysilicon (Si) into SiO2 and control the pre-reaction rate of etching; HF acts as a complexing agent to react with the generated SiO2 to form soluble H2SiF6, so as to realize the precise removal of polysilicon; CH3COOH has both buffering and corrosion inhibiting effects, which stabilizes the etching rate, reduces the surface tension of the etching solution, suppresses pattern undercut, and ensures the steepness of the boundary of the subsequently formed PN junction.

[0123] The mixed etching solution at this volume ratio has an etching selectivity ratio as high as 160:1 for polysilicon and the tunneling layer. Etching 8 nm of polysilicon only consumes 0.05 nm of the tunneling layer. While completely removing polysilicon and BSG in the region not protected by the mask, the thickness of the underlying tunneling layer is only reduced by about 0.03 nm to 0.06 nm, which fully preserves the barrier integrity of the tunneling layer and fundamentally avoids electric leakage.

[0124] In another example, a dual corrosion inhibitor is added to the basic HNA system (HF-HNO3-CH3COOH system) to further improve the etching selectivity, suppress undercutting, and meet the patterning requirements of PN strips with a narrow pitch of less than 50 μm. Preferably, a mixed etching solution with a volume ratio of HF:HNO3:CH3COOH of 1:4:12 is used, and 0.1 g / L benzotriazole (BTA) and 0.5 vol% PEG-400 (polyethylene glycol) are additionally added thereto. The mixed etching solution at this volume ratio increases the etching selectivity of polysilicon to the tunneling layer to more than 200:1. While completely removing polysilicon and BSG in the regions not protected by the mask, the thickness variation of the underlying tunneling layer is less than 0.1 nm, and the undercut amount is less than 0.5 μm. The subsequently formed PN junction boundary is steeper, which adapts to ultra-narrow pitch PN patterns, and the mass production yield can be further increased by 0.5%-1%.

[0125] reference Figure 2f as shown, on the side facing away from the first surface S1 of the silicon substrate 10, that is, on the first doped glass layer 23 in the first region S21 and the tunneling layer 21 in the second region S22, a second intrinsic layer 32' is deposited; referring further to Figure 2g as shown, the second intrinsic layer 32' is doped to convert the second intrinsic layer 32' into a second doped layer 32, and a second doped glass layer 33 is formed on the surface of the second doped layer 32.

[0126] For example, in a low-pressure chemical vapor deposition (LPCVD) furnace tube, the low-pressure chemical vapor deposition process is adopted again to deposit the second intrinsic layer 32' in-situ, which provides a base for subsequent N-type doping. A tubular high-temperature diffusion furnace is used for phosphorus doping, and high-temperature phosphorus doping is performed at 850°C-870°C to form a surface doping concentration of 3×10 20 cm -3 -6×10 20 cm -3 , a uniform second doped layer 32 with a sheet resistance of 30 Ω / sq-80 Ω / sq, and the second doped glass layer 33 is generated in-situ during the doping process.

[0127] The second intrinsic layer 32' in this embodiment is an intrinsic polysilicon layer with a thickness of 10 nm-15 nm, which may be, for example, 10 nm, 12 nm, 14 nm, 15 nm, etc., or may be any range composed of the above values. The second doped layer 32 is an N-type doped polysilicon layer. The second doped glass layer 33 is phosphosilicate glass (PSG) naturally formed on the surface of the second doped layer 32 under a high-temperature process.

[0128] So far, the second doped layer 32 and the first doped layer 22 form an abrupt PN junction, and the width of the doping transition region of this PN junction is smaller than the width of the depletion region. Preferably, the width of the doping transition region of this PN junction is less than or equal to 5 nm, for example, may be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.1 nm, 0.01 nm, etc., or may be a range composed of any of the above values; the roughness of the side interface between the second doped layer 32 and the first doped layer 22 of this PN junction is less than or equal to 1 nm, for example, may be 1 nm, 0.5 nm, 0.1 nm, 0.05 nm, 0.02 nm, 0.01 nm, etc.; the surface of the second doped layer 32 of this PN junction is flush with the surface of the first doped layer 22; the thickness difference between the second doped layer 32 and the first doped layer 22 of this PN junction is less than or equal to 5 nm, for example, may be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.2 nm, 0.05 nm, etc., or may be a range composed of any of the above values.

[0129] In the above technical solution, a wet etching process is adopted to perform reactive etching at room temperature, no heat-affected zone is generated, the surface doping concentration of the second doped layer is more than 10 times the surface doping concentration of the first doped layer, the width of the doping transition region of the formed abrupt PN junction is ≤ 4 nm, which is far smaller than the width of its depletion region, and the interface roughness is ≤ 0.8 nm, maximizing the built-in electric field strength, realizing electrical self-isolation without physical trenches and no intrinsic isolation region, and ensuring the self-isolation effect.

[0130] See Figure 2h as shown, a screen printing process is used again to form a second mask layer 62 on the second doped glass layer 33 in the second region S22.

[0131] As an example, an alkali-resistant mask paste is printed on the second region S22 of the second surface S2 of the silicon substrate 10 by a precision screen printing apparatus, and the alignment accuracy between the mask paste region and the second region S22 is controlled to be ≤ ±2 μm, so that the printed pattern matches the second region S22 as completely as possible. Drying and curing are carried out at a temperature of 170°C-190°C to make the mask cover firmly.

[0132] See Figure 2i as shown, the first surface S1 of the silicon substrate 10 is subjected to acid texturing anti-reflection treatment (the textured surface is not shown), and the reflectivity of the textured surface of the first surface S1 is controlled to be ≤ 9%. The second doped glass layer 33 and the second doped layer 32 on the first region S21, the first doped glass layer 23, as well as the second mask layer 62 and the second doped glass layer 33 on the second region S22 are removed. For example, an alkali solution may be used to remove the second doped layer 32, and an acid solution may be used to remove the second doped glass layer 33, the first doped glass layer 23, and the second mask layer 62. In view of the fact that the above etching process may adopt existing processes and is not an innovation point of the present invention, the present invention does not elaborate on this in detail.

[0133] See Figure 2j as shown, a first dielectric layer 41 is prepared on the first surface S1 of the silicon substrate 10, and a second dielectric layer 42 is prepared on the second surface S2 of the silicon substrate 10.

[0134] Specifically, the first dielectric layer 41 and the second dielectric layer 42 may be a passivation layer and / or an anti-reflection layer, which is at least one of an aluminum oxide layer, a silicon oxide layer, a gallium oxide layer, a silicon nitride layer, an aluminum nitride layer, a silicon oxynitride layer and the like.

[0135] Exemplarily, the first dielectric layer 41 and the second dielectric layer 42 may be a stacked film of an aluminum oxide layer and a silicon nitride layer deposited by an ALD process and / or a PECVD process. The aluminum oxide layer serves as the passivation layer, and the thickness thereof is preferably 6 nm to 12 nm, for example, may be 6 nm, 7 nm, 9 nm, 11 nm, 12 nm, etc., or may be a range composed of any of the above values. The silicon nitride layer serves as the anti-reflection layer, the thickness thereof on the first surface S1 is preferably 70 nm to 80 nm, for example, may be 70 nm, 72 nm, 75 nm, 78 nm, 80 nm, etc., or may be a range composed of any of the above values; the thickness thereof on the second surface S2 is preferably 60 nm to 70 nm, for example, may be 60 nm, 63 nm, 65 nm, 67 nm, 70 nm, etc., or may be a range composed of any of the above values.

[0136] See Figure 2k as shown, a first electrode 51 in electrical contact with the first doped layer 22 is prepared in the first region S21 of the second surface S2 of the silicon substrate 10, and a second electrode 52 in electrical contact with the second doped layer 32 is prepared in the second region S22 of the second surface S2 of the silicon substrate 10.

[0137] Specifically, it may be prepared by a screen printing process, and the first electrode 51 and the second electrode 52 are formed by high-temperature sintering at 700°C to 800°C. The first electrode 51 is located in the first region S21 of the second surface S2 and is in electrical contact with the first doped layer 22, but cannot penetrate the underlying tunneling layer 21 to contact the silicon substrate 10; the second electrode 52 is located in the second region S22 of the second surface S2 and is in electrical contact with the second doped layer 32, but cannot penetrate the underlying tunneling layer 21 to contact the silicon substrate 10.

[0138] The TBC cell in this embodiment can be manufactured through the above steps.

[0139] It should be understood that the preparation method of this embodiment mainly describes the structures on the front surface and the back surface of the silicon substrate in detail. The side surface of the silicon substrate will also form a wrap-around deposition and an oxide layer during steps such as deposition and doping, and the side wrap-around deposition and the oxide layer will be removed in the subsequent wet etching process. The side wrap-around deposition and the oxide layer are not the core features of the present invention, and will not be described in detail here.

[0140] Example 2:

[0141] In this embodiment, the solar cell is also illustrated using a TBC cell (Tunnel Oxide Passivated ContactBack Contact Battery) as an example.

[0142] The fabrication method of the TBC battery in this embodiment differs from that in Example 1, starting from step S3. In step S3 of Example 1, the wet etching process only removes the first doped layer in the second region. However, in this embodiment, in step S3, the wet etching process removes both the first doped layer and the tunneling layer in the second region simultaneously. This results in a series of different subsequent process steps.

[0143] Specifically, the preparation method of the TBC battery in this embodiment includes the following steps:

[0144] S10, a silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacent first regions and second regions.

[0145] S20, a tunneling layer and a first doped layer are formed sequentially on the second surface.

[0146] S30, a wet etching process is used to remove the first doped layer and tunneling layer in the second region, while retaining the first doped layer and tunneling layer in the first region.

[0147] S40, a tunneling layer and a second doped layer are formed in sequence on the second region. The doping type of the second doped layer is opposite to that of the first doped layer. The second doped layer and the first doped layer are attached to each other at the side interface.

[0148] S50, a light-trapping structure is prepared on the first surface of a silicon substrate using a texturing process.

[0149] S60, a first passivation layer and / or a first antireflection layer are prepared on a first surface of a silicon substrate.

[0150] S70, a second passivation layer and / or a second antireflection layer are prepared on the second surface of the silicon substrate.

[0151] S80, electrodes are formed on the second surface of a silicon substrate that are in contact with the first doped layer and the second doped layer, respectively.

[0152] In step S20, a tunneling layer and a first doped layer can be sequentially stacked on the second surface by first forming a tunneling layer on the second surface, then forming a first intrinsic layer on the tunneling layer, then converting the first intrinsic layer into a first doped layer, and finally forming a first doped glass layer on the surface of the first doped layer. The surface doping concentration of the first doped layer is 3 × 10⁻⁶. 19 cm -3 -6×10 19 cm -3 For example, it can be 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq, for example, it can be 120Ω / sq, 150Ω / sq, 180Ω / sq, 210Ω / sq, 250Ω / sq, etc., or it can be a range of any of the above values.

[0153] In step S30, the first doped layer and tunneling layer of the second region are removed by a wet etching process, specifically including: forming a first mask layer on the first doped glass layer of the first region by a screen printing process; removing the first doped layer and tunneling layer on the second region by a first etching solution; and removing the first mask layer.

[0154] The first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid and acetic acid, or a mixed etching solution containing hydrofluoric acid, nitric acid, acetic acid, benzotriazole and polyethylene glycol.

[0155] In step S40, a tunneling layer can be formed first on the second region and on the first doped glass layer in the first region, and a second intrinsic layer can be formed on the tunneling layer; then, the second intrinsic layer can be converted into a second doped layer, and a second doped glass layer can be formed on the surface of the second doped layer; then, a second mask layer can be formed on the second doped glass layer in the second region, and the second doped glass layer, the second doped layer, and the tunneling layer on the first doped glass layer in the first region can be removed; finally, the second mask layer, the first doped glass layer in the first region, and the second doped glass layer in the second region can be removed; thus, a second doped layer is formed on the tunneling layer in the second region. The surface doping concentration of the second doped layer is 3 × 10⁻⁶. 20 cm -3 -6×10 20 cm -3 For example, it can be 3×10 20 cm -3 4×1020 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 etc., or may be a range composed of any of the above numerical values; the sheet resistance is 30Ω / sq to 80Ω / sq, for example, may be 30Ω / sq, 50Ω / sq, 70Ω / sq, 80Ω / sq, etc., or may be a range composed of any of the above numerical values. The second doped layer and the first doped layer form an abrupt PN junction, and the width of the doping transition region of the PN junction is smaller than the width of the depletion region.

[0156] Preferably, the width of the doping transition region of the PN junction is less than or equal to 5nm, for example, may be 5nm, 3nm, 1nm, 0.5nm, 0.1nm, 0.01nm, etc., or may be a range composed of any of the above numerical values. The roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1nm, for example, may be 1nm, 0.5nm, 0.1nm, 0.05nm, 0.02nm, 0.01nm, etc., or may be a range composed of any of the above numerical values. The surface of the second doped layer of the PN junction is flush with the surface of the first doped layer. The thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5nm, for example, may be 5nm, 3nm, 1nm, 0.5nm, 0.2nm, 0.05nm, etc., or may be a range composed of any of the above numerical values.

[0157] The following is combined with Figures 4a-4k to describe the preparation method of this embodiment in detail, so as to facilitate the understanding of the technical solution of this embodiment.

[0158] As shown in reference Figure 4a , a silicon substrate 10 is provided.

[0159] The silicon substrate 10 in this embodiment includes a first surface S1 (i.e., front surface or light-receiving surface) and a second surface S2 (i.e., back surface or light-back surface) which are arranged opposite to each other, and the second surface includes a first region S21 and a second region S22 which are alternately and adjacently distributed; that is, one second region S22 is arranged between two adjacent first regions S21, and one first region S21 is arranged between two adjacent second regions S22; there is no interval between the first region S21 and the second region S22.

[0160] Exemplarily, the silicon substrate 10 in this embodiment is an N-type monocrystalline silicon wafer. First, the silicon substrate 10 is subjected to alkali polishing and acid cleaning to remove damages and impurities on the surface of the silicon substrate 10, so as to obtain a clean and flat surface. For example, rough polishing is performed in a KOH alkali solution at 80°C to remove the slicing damage layer, followed by sequential cleaning with standard SC-1 (NH4OH:H2O2:H2O) and SC-2 (HCl:H2O2:H2O) cleaning solutions to remove metal ions and particle contaminants, and finally rinsing with deionized water and drying to obtain a silicon wafer with a clean and flat surface.

[0161] Refe Figure 4b shown, the tunneling layer 21 and the first intrinsic layer 22' are deposited over the entire surface on the second surface S2 of the silicon substrate 10; then refe Figure 4c shown, the first intrinsic layer 22' is doped to convert the first intrinsic layer 22' into the first doped layer 22, and the first doped glass layer 23 is formed on the surface of the first doped layer 22.

[0162] Exemplarily, the cleaned silicon substrate 10 is loaded into a low-pressure chemical vapor deposition (LPCVD) furnace tube, and the tunneling layer 21 is prepared first by using a low-pressure chemical vapor deposition process, and then the first intrinsic layer 22' is deposited in-situ. Boron doping is carried out using a tubular high-temperature diffusion furnace, and high-temperature boron doping is performed at 920°C-940°C to form a surface doping concentration of 3×10 19 cm -3 -6×10 19 cm -3 ; a uniform first doped layer 22 with a sheet resistance of 120Ω / sq-250Ω / sq, and the first doped glass layer 23 is generated in-situ during the doping process.

[0163] The tunneling layer 21 in this embodiment is a tunneling oxide layer, which may be any one or a combination of a silicon oxide layer and a silicon oxynitride layer, with a thickness of 1.2nm-1.8nm, for example, may be 1.2nm, 1.5nm, 1.7nm, 1.8nm, etc., or may be a range composed of any of the above values. The first intrinsic layer 22' is an intrinsic polysilicon layer, with a thickness of 5nm-10nm, for example, may be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc., or may be a range composed of any of the above values. The first doped layer 22 is a P-type doped polysilicon layer. The first doped glass layer 23 is borosilicate glass (BSG) naturally formed on the surface of the first doped layer 22 under a high-temperature process.

[0164] Refe Figure 4d shown, a first mask layer 61 is formed on the first doped glass layer 23 in the first region S21 by a screen printing process.

[0165] For example, acid-resistant mask paste is printed on the first region S21 of the second surface S2 of the silicon substrate 10 by a precision screen printing apparatus, and the alignment accuracy between the mask paste region and the first region S21 is controlled to be ≤±2 μm, so that the printed pattern matches the first region S21 as completely as possible. Drying and curing are carried out at a temperature of 170°C to 190°C to make the mask cover firmly.

[0166] As shown in Figure 4e , a wet etching process is used to remove the first doped glass layer 23, the first doped layer 22 and the tunneling layer 21 in the second region S22, expose the silicon substrate 10 in the second region S22, and remove the first mask layer 61. For example, an HF-HNO3-CH3COOH system etching solution can be used to etch the layer structure on the second region S22 that is not protected by the first mask layer 61 at room temperature, and simultaneously complete the removal of the first doped glass layer 23, the patterning of the first doped layer 22, the removal of the tunneling layer 21 and the removal of surface impurities. The volume ratio of each component in the HF-HNO3-CH3COOH system etching solution is controlled, so that the roughness of the side interface of the first doped layer 22 is controlled to be less than or equal to 0.8 nm. Subsequently, the first mask layer 61 is removed by an alkali solution.

[0167] As shown in Figure 4f , on the side facing away from the first surface S1 of the silicon substrate 10, that is, on the first doped glass layer 23 in the first region S21 and the silicon substrate 10 in the second region S22, the tunneling layer 21 is deposited again, and the second intrinsic layer 32' is deposited; then as shown in Figure 4g , the second intrinsic layer 32' is doped to convert the second intrinsic layer 32' into a second doped layer 32, and a second doped glass layer 33 is formed on the surface of the second doped layer 32.

[0168] For example, in a low-pressure chemical vapor deposition (LPCVD) furnace tube, the low-pressure chemical vapor deposition process is adopted again to in-situ deposit the tunneling layer 21 and the second intrinsic layer 32', so as to provide a base for subsequent N-type doping. A tubular high-temperature diffusion furnace is used for phosphorus doping, and high-temperature phosphorus doping is performed at 850°C to 870°C to form a surface doping concentration of 3×10 20 cm -3 -6×10 20 cm -3 , a uniform second doped layer 32 with a sheet resistance of 30 Ω / sq to 80 Ω / sq, and the second doped glass layer 33 is generated in-situ during the doping process.

[0169] The second intrinsic layer 32' in this embodiment is an intrinsic polysilicon layer, with a thickness of 10nm-15nm, for example, may be 10nm, 12nm, 14nm, 15nm, etc., or may be a range composed of any of the above values. The second doped layer 32 is an N-type doped polysilicon layer. The second doped glass layer 33 is phosphosilicate glass (PSG) naturally formed on the surface of the second doped layer 32 under a high-temperature process.

[0170] Thus, the second doped layer 32 and the first doped layer 22 form an abrupt PN junction, and the width of the doping transition region of the PN junction is smaller than the width of the depletion region. Preferably, the width of the doping transition region of the PN junction is less than or equal to 5nm, for example, may be 5nm, 3nm, 1nm, 0.5nm, 0.1nm, 0.01nm, etc., or may be a range composed of any of the above values; the roughness of the side interface between the second doped layer 32 and the first doped layer 22 of the PN junction is less than or equal to 1nm, for example, may be 1nm, 0.5nm, 0.1nm, 0.05nm, 0.02nm, 0.01nm, etc.; the surface of the second doped layer 32 of the PN junction is flush with the surface of the first doped layer 22; the thickness difference between the second doped layer 32 and the first doped layer 22 of the PN junction is less than or equal to 5nm, for example, may be 5nm, 3nm, 1nm, 0.5nm, 0.2nm, 0.05nm, etc., or may be a range composed of any of the above values.

[0171] In the above technical solution, a wet etching process is adopted to perform reactive etching at room temperature, no heat-affected zone is generated, the surface doping concentration of the second doped layer is more than 10 times the surface doping concentration of the first doped layer, the formed abrupt PN junction has a doping transition region width ≤4nm and an interface roughness ≤0.8nm, which maximizes the built-in electric field strength, realizes electrical self-isolation without physical grooving and no intrinsic isolation region, and ensures the self-isolation effect.

[0172] Refe Figure 4h as shown, a screen printing process is used again to form a second mask layer 62 on the second doped glass layer 33 in the second region S22.

[0173] Exemplarily, an alkali-resistant mask paste is printed on the second region S22 of the second surface S2 of the silicon substrate 10 by a precision screen printing apparatus, and the alignment accuracy between the mask paste region and the second region S22 is controlled to be ≤±2μm, so that the printed pattern matches the second region S22 as completely as possible. Drying and curing are performed at a temperature of 170°C-190°C to make the mask cover firmly.

[0174] Refe Figure 4iAs shown, the first surface S1 of the silicon substrate 10 is subjected to acid texturing for reflectance enhancement (the textured surface is not shown), and the textured surface reflectance of the first surface S1 is controlled to be ≤9%. The second doped glass layer 33 and the second doped layer 32 on the first region S21, the tunneling layer 21 and the first doped glass layer 23 on the first doped glass layer 23, as well as the second mask layer 62 and the second doped glass layer 33 on the second region S22 are removed. For example, an alkaline solution may be used to remove the second doped layer 32, and an acidic solution may be used to remove the second doped glass layer 33, the tunneling layer 21, the first doped glass layer 23 and the second mask layer 62. In view that the above etching process may adopt existing processes and is not an innovation point of the present invention, the present invention will not elaborate on this in detail.

[0175] Refe Figure 4j As shown, a first dielectric layer 41 is prepared on the first surface S1 of the silicon substrate 10, and a second dielectric layer 42 is prepared on the second surface S2 of the silicon substrate 10.

[0176] Specifically, the first dielectric layer 41 and the second dielectric layer 42 may be a passivation layer and / or an anti-reflection layer, which is at least one of an aluminum oxide layer, a silicon oxide layer, a gallium oxide layer, a silicon nitride layer, an aluminum nitride layer, a silicon oxynitride layer, and the like.

[0177] Exemplarily, the first dielectric layer 41 and the second dielectric layer 42 may be a stacked film of an aluminum oxide layer and a silicon nitride layer deposited by an ALD process and / or a PECVD process. The aluminum oxide layer serves as the passivation layer, and its thickness is preferably 6nm-12nm, for example, may be 6nm, 7nm, 9nm, 11nm, 12nm, etc., or may be a range composed of any of the above values. The silicon nitride layer serves as the anti-reflection layer, its thickness on the first surface S1 is preferably 70nm-80nm, for example, may be 70nm, 72nm, 75nm, 78nm, 80nm, etc., or may be a range composed of any of the above values; its thickness on the second surface S2 is preferably 60nm-70nm, for example, may be 60nm, 63nm, 65nm, 67nm, 70nm, etc., or may be a range composed of any of the above values.

[0178] Refe Figure 4k As shown, a first electrode 51 in electrical contact with the first doped layer 22 is prepared in the first region S21 of the second surface S2 of the silicon substrate 10, and a second electrode 52 in electrical contact with the second doped layer 32 is prepared in the second region S22 of the second surface S2 of the silicon substrate 10.

[0179] Specifically, the preparation can be performed using a screen printing process, followed by high-temperature sintering at 700°C-800°C to form the first electrode 51 and the second electrode 52. The first electrode 51 is located in the first region S21 of the second surface S2, and is in electrical contact with the first doped layer 22, but cannot penetrate the underlying tunnel layer 21 to contact the silicon substrate 10; the second electrode 52 is located in the second region S22 of the second surface S2, and is in electrical contact with the second doped layer 32, but cannot penetrate the underlying tunnel layer 21 to contact the silicon substrate 10.

[0180] The TBC cell in this embodiment can be manufactured through the above steps.

[0181] It should be understood that the preparation method of this embodiment mainly describes the structures on the front side and back side of the silicon substrate in detail. The side surface of the silicon substrate will also form wrap-around deposition and an oxide layer during steps such as deposition and doping, and the side wrap-around deposition and oxide layer will be removed in the subsequent wet etching process. The side wrap-around deposition and oxide layer are not core features of the present invention, and will not be elaborated herein.

[0182] The present invention further provides a solar cell, which is preferably prepared by the above-described method for preparing a solar cell.

[0183] Reference Figure 2k or reference Figure 4k as shown, the solar cell of the present invention comprises:

[0184] A silicon substrate 10, which includes a first surface S1 (i.e., front side or light-receiving surface) and a second surface S2 (i.e., back side or light-shielding surface) disposed opposite to each other. The second surface includes a first region S21 and a second region S22 that are alternately and adjacently distributed; that is, one second region S22 is disposed between two adjacent first regions S21, and one first region S21 is disposed between two adjacent second regions S22; there is no gap between the first region S21 and the second region S22.

[0185] A tunnel layer 21, wherein the tunnel layer 21 is located on the first surface S11 of the silicon substrate 10, and covers the first region S21 and the second region S22.

[0186] A first doped layer 22 and a second doped layer 32, wherein the first doped layer 22 is stacked on the side of the tunnel layer 21 away from the silicon substrate 10 and is located on the first region S21; the second doped layer 32 is stacked on the side of the tunnel layer 21 away from the silicon substrate 10 and is located on the second region S22. The doping type of the first doped layer 22 is opposite to the doping type of the second doped layer 32, and the first doped layer 22 and the second doped layer 32 are attached to each other at the side junction, thereby forming an abrupt PN junction, and the width of the doping transition region of the PN junction is smaller than the width of the depletion region.

[0187] In this embodiment, preferably, the width of the doped transition region of the PN junction is less than or equal to 5 nm, for example, it can be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.1 nm, 0.01 nm, etc., or a range of any of the above values. The roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm, for example, it can be 1 nm, 0.5 nm, 0.1 nm, 0.05 nm, 0.02 nm, 0.01 nm, etc., or a range of any of the above values. The surface of the second doped layer of the PN junction is flush with the surface of the first doped layer. The thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm, for example, it can be 5 nm, 3 nm, 1 nm, 0.5 nm, 0.2 nm, 0.05 nm, etc., or a range of any of the above values.

[0188] A first dielectric layer 41 and a second dielectric layer 42 are formed on a first surface S1 of a silicon substrate 10, and a second dielectric layer 42 is formed on a side away from the first surface S1 of the silicon substrate 10. The second dielectric layer 42 covers a first doped layer 22 in a first region S21 and a second doped layer 32 in a second region S22.

[0189] The first electrode 51 is located in the first region S21 and penetrates the first dielectric layer 41 to make electrical contact with the first doped layer 22. The second electrode 52 is located in the second region S22 and penetrates the second dielectric layer 42 to make electrical contact with the second doped layer 32.

[0190] The silicon substrate 10 in this invention can be an N-type silicon substrate or a P-type silicon substrate. In this embodiment, an N-type silicon substrate is used as an example for explanation. The first doped layer 22 and the second doped layer 32 have opposite doping types, namely P-type doping (such as boron doping) and N-type doping (such as phosphorus doping), respectively. Therefore, the first region S21 is the P-region on the back of the battery, and the second region S22 is the N-region on the back of the battery.

[0191] Preferably, the second surface S2 of the silicon substrate 10 is a polished surface, while the first surface S1 of the silicon substrate 10 is a light-trapping textured surface structure. For example, the first surface S1 can be a pyramid textured surface structure prepared by an acid texturing process.

[0192] In the TBC battery of this embodiment, the tunneling layer 21 can be any one or more combinations of silicon oxide layer and silicon oxynitride layer, with a thickness of 1.2nm-1.8nm, such as 1.2nm, 1.5nm, 1.7nm, 1.8nm, or any range of the above values. In other back contact batteries, the tunneling layer 21 can also be an oxide layer with a thickness greater than this range.

[0193] In addition, in this embodiment, a first dielectric layer 41 and a second dielectric layer 42 are respectively stacked on the first surface S1 and the second surface S2 of the silicon substrate. The first dielectric layer 41 and the second dielectric layer 42 can be passivation layers and / or anti-reflection layers, which are at least one of aluminum oxide layer, silicon oxide layer, gallium oxide layer, silicon nitride layer, aluminum nitride layer, silicon oxynitride layer, etc.

[0194] For example, the first dielectric layer 41 and the second dielectric layer 42 can be a stacked film of an aluminum oxide layer and a silicon nitride layer. The aluminum oxide layer serves as a passivation layer, and its thickness is preferably 6nm-12nm, such as 6nm, 7nm, 9nm, 11nm, 12nm, etc., or any range of the above values. The silicon nitride layer serves as an antireflection layer, and its thickness on the first surface S1 is preferably 70nm-80nm, such as 70nm, 72nm, 75nm, 78nm, 80nm, etc., or any range of the above values; and its thickness on the second surface S2 is preferably 60nm-70nm, such as 60nm, 63nm, 65nm, 67nm, 70nm, etc., or any range of the above values.

[0195] In addition, in this embodiment, the first electrode 51 is located in the first region S21 of the second surface S2 and is in electrical contact with the first doped layer 22, but cannot penetrate the underlying tunneling layer 21 to contact the silicon substrate 10; the second electrode 52 is located in the second region S22 of the second surface S2 and is in electrical contact with the second doped layer 32, but cannot penetrate the underlying tunneling layer 21 to contact the silicon substrate 10.

[0196] Compared with existing technologies, the solar cell fabrication method and solar cell of the present invention, through a wet etching patterning process, can form a steeply abrupt PN junction between the first and second doped layers—the doping concentration abruptly changes from one doping type to another at the PN junction interface. The width of the doped transition region is much smaller than the width of the entire depletion region (space charge region), and the doping distribution curve approximates a step function, thus exhibiting higher built-in electric field strength and lower recombination current. In this invention, the built-in electric field of the PN junction provides the first line of defense for lateral isolation. The carrier selectivity characteristics of the first and second doped layers form a reflective barrier for minority carriers, constituting the second line of defense. The tunneling layer only allows collected target carriers to selectively tunnel, preventing the injection of non-selective carriers, thereby cutting off the vertical channel for leakage from the PN junction to the silicon substrate, constituting the third line of defense. This achieves complete electrical isolation without the need for physical isolation trenches.

[0197] The solar cell fabrication method and solar cell of this invention eliminate the need for laser patterning, completely avoiding the impact of the heat-affected zone of picosecond / femtosecond lasers on the quality of the PN junction. Due to the absence of laser thermal interference, the PN junction boundary can maintain a steep metallurgical junction structure; that is, the PN junction has a steep metallurgical junction interface where the doping concentration abruptly changes from P-type to N-type, thus fully preserving the built-in electric field (with a reduction of less than 5%) and ensuring the self-isolation capability of the PN junction. Simultaneously, the absence of laser ablation means that the thin tunneling layer will not be broken down or damaged due to etching precision issues, eliminating the formation of leakage channels at the source and significantly reducing reverse leakage current.

[0198] The solar cell fabrication method and solar cell of the present invention achieve equivalent electrical isolation between the first and second doped layers without the need for physical isolation trenches through the synergistic effect of carrier selectivity of different types of heavily doped layers, tunneling layer barrier, and built-in electric field of PN junction, ensuring directional transport of carriers. Experimental and theoretical studies show that this structure can enable the theoretical conversion efficiency of the trenchless cell to reach over 25%, while also possessing high open-circuit voltage, high fill factor, and high short-circuit current density.

[0199] The solar cell fabrication method and solar cell of this invention eliminate the need for physical isolation processes such as laser grooving, insulating layer deposition, and patterned etching, completely avoiding interface defects and stress concentration points introduced by the isolation trench, and significantly improving the interface passivation quality and long-term cell reliability. Simultaneously, it fundamentally eliminates yield-loss factors such as residual impurities in the isolation trench and insulating layer detachment, enabling mass production yields to exceed 90%, thus breaking through the yield bottleneck that has long constrained the industrialization of solar cells.

[0200] The solar cell preparation method and solar cell of the present invention are highly compatible with mainstream solar cell process platforms, and can achieve technological upgrades without large-scale modifications to production lines. This feature significantly lowers the technology introduction threshold and is conducive to industrialization and application in the short term.

[0201] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0202] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that, include: A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacently distributed first regions and second regions; A tunneling layer and a first doped layer are formed sequentially on the second surface; The first doped layer in the second region is removed by a wet etching process, while the first doped layer in the first region is retained. A second doped layer is formed on the tunneling layer in the second region. The doping type of the second doped layer is opposite to that of the first doped layer. The second doped layer and the first doped layer are attached to each other at the side interface. Wherein, the ratio of the surface doping concentration of the second doped layer to the surface doping concentration of the first doped layer is greater than or equal to 10; the second doped layer and the first doped layer form a PN junction, and the width of the doped transition region of the PN junction is less than or equal to 5 nm.

2. The method for preparing a solar cell according to claim 1, characterized in that, A tunneling layer and a first doped layer are formed sequentially on the second surface, including: A tunneling layer is formed on the second surface; A first intrinsic layer is formed on the tunneling layer; The first intrinsic layer is converted into a first doped layer, and a first doped glass layer is formed on the surface of the first doped layer; The surface doping concentration of the first doped layer is 3×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq.

3. The method for preparing a solar cell according to claim 2, characterized in that, The first doped layer in the second region is removed using a wet etching process, including: A first mask layer is formed on the first doped glass layer in the first region using a screen printing process; The first doped layer on the second region is removed using a first etching solution; Remove the first mask layer; Specifically, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is controlled to be greater than 100:1, the thickness change of the tunneling layer after etching is less than or equal to 0.2 nm, and the roughness of the side interface of the first doped layer is less than or equal to 0.8 nm.

4. The method for preparing a solar cell according to claim 3, characterized in that, The first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid and acetic acid; By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is made greater than 100:

1. In the mixed etching solution, the ratio of hydrofluoric acid, nitric acid and acetic acid is 1:(4-5):(10-12).

5. The method for preparing a solar cell according to claim 3, characterized in that, The first etching solution is a mixed etching solution composed of hydrofluoric acid, nitric acid, acetic acid, benzotriazole and polyethylene glycol; By adjusting the volume ratio of each component in the mixed etching solution, the etching selectivity ratio of the first etching solution for the first doped layer and the tunneling layer is made greater than 200:

1. After etching, the thickness change of the tunneling layer is less than or equal to 0.1 nm, and the etching amount at the side interface of the first doped layer is less than or equal to 0.5 μm.

6. The method for preparing a solar cell according to claim 3, characterized in that, A second doped layer is formed on the tunneling layer in the second region, including: A second intrinsic layer is formed on the tunneling layer in the second region and the first doped glass layer in the first region; The second intrinsic layer is transformed into a second doped layer, and a second doped glass layer is formed on the surface of the second doped layer; A second mask layer is formed on the second doped glass layer in the second region; Remove the second doped glass layer and the second doped layer from the first region; Remove the second mask layer, the first doped glass layer on the first region, and the second doped glass layer on the second region; The surface doping concentration of the second doped layer is 3×10⁻⁶. 20 cm -3 -6×10 20 cm -3 The sheet resistance is 30Ω / sq-80Ω / sq. The second doped layer and the first doped layer form a PN junction. The width of the doped transition region of the PN junction is smaller than the width of the depletion region.

7. The method for preparing a solar cell according to claim 1, characterized in that, The roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm; and / or, the surface of the second doped layer of the PN junction is flush with the surface of the first doped layer; and / or, the thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm.

8. The method for preparing a solar cell according to claim 1, characterized in that, Also includes: A light-trapping structure is fabricated on the first surface of a silicon substrate using a texturing process. And / or, A first passivation layer and / or a first antireflection layer are prepared on a first surface of a silicon substrate; And / or, A second passivation layer and / or a second antireflection layer are prepared on a second surface of a silicon substrate; and / or, Electrodes are fabricated on the second surface of a silicon substrate, which are in contact with the first doped layer and the second doped layer, respectively.

9. A method for preparing a solar cell, characterized in that, include: A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including alternating and adjacently distributed first regions and second regions; A tunneling layer and a first doped layer are formed sequentially on the second surface; The first doped layer and tunneling layer of the second region are removed by wet etching process, while the first doped layer and tunneling layer of the first region are retained; A tunneling layer and a second doped layer are formed sequentially in the second region. The second doped layer has the opposite doping type to the first doped layer. The second doped layer and the first doped layer are attached to each other at the side interface. Wherein, the ratio of the surface doping concentration of the second doped layer to the surface doping concentration of the first doped layer is greater than or equal to 10; the second doped layer and the first doped layer form a PN junction, and the width of the doped transition region of the PN junction is less than or equal to 5 nm.

10. The method for preparing a solar cell according to claim 9, characterized in that, A tunneling layer and a first doped layer are formed sequentially on the second surface, including: A tunneling layer is formed on the second surface; A first intrinsic layer is formed on the tunneling layer; The first intrinsic layer is converted into a first doped layer, and a first doped glass layer is formed on the surface of the first doped layer; The surface doping concentration of the first doped layer is 3×10⁻⁶. 19 cm -3 -6×10 19 cm -3 The sheet resistance is 120Ω / sq-250Ω / sq.

11. The method for preparing a solar cell according to claim 10, characterized in that, The first doped layer and tunneling layer in the second region are removed using a wet etching process, including: A first mask layer is formed on the first doped glass layer in the first region using a screen printing process; The first doped layer and tunneling layer on the second region are removed using a first etching solution; Remove the first mask layer.

12. The method for preparing a solar cell according to claim 11, characterized in that, The first etching solution is a mixed etching solution containing hydrofluoric acid, nitric acid, and acetic acid; or, The first etching solution is a mixed etching solution composed of hydrofluoric acid, nitric acid, acetic acid, benzotriazole and polyethylene glycol.

13. The method for preparing a solar cell according to claim 11, characterized in that, A tunneling layer and a second doped layer are formed sequentially in the second region, including: A tunneling layer is formed on the second region and on the first doped glass layer in the first region; A second intrinsic layer is formed on the tunneling layer; The second intrinsic layer is transformed into a second doped layer, and a second doped glass layer is formed on the surface of the second doped layer; A second mask layer is formed on the second doped glass layer in the second region; Remove the second doped glass layer, the second doped layer, and the tunneling layer on the first doped glass layer in the first region; Remove the second mask layer, the first doped glass layer on the first region, and the second doped glass layer on the second region; The surface doping concentration of the second doped layer is 3×10⁻⁶. 20 cm -3 -6×10 20 cm -3 The sheet resistance is 30Ω / sq-80Ω / sq. The second doped layer and the first doped layer form a PN junction. The width of the doped transition region of the PN junction is smaller than the width of the depletion region.

14. The method for preparing a solar cell according to claim 9, characterized in that, The roughness of the side interface between the second doped layer and the first doped layer of the PN junction is less than or equal to 1 nm; and / or, the surface of the second doped layer of the PN junction is flush with the surface of the first doped layer; and / or, the thickness difference between the second doped layer and the first doped layer of the PN junction is less than or equal to 5 nm.

15. The method for preparing a solar cell according to claim 9, characterized in that, Also includes: A light-trapping structure is fabricated on the first surface of a silicon substrate using a texturing process. And / or, A first passivation layer and / or a first antireflection layer are prepared on a first surface of a silicon substrate; And / or, A second passivation layer and / or a second antireflection layer are prepared on a second surface of a silicon substrate; and / or, Electrodes are fabricated on the second surface of a silicon substrate, which are in contact with the first doped layer and the second doped layer, respectively.

16. A solar cell structure, characterized in that, It is prepared by the method of preparing a solar cell according to any one of claims 1-8, or by the method of preparing a solar cell according to any one of claims 9-15.

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