Photovoltaic cell and photovoltaic module

Abstract

This application relates to a photovoltaic cell and a photovoltaic module, and pertains to the field of photovoltaic technology. The photovoltaic cell includes a silicon substrate, a tunneling passivation contact structure, and a second edge passivation layer. The silicon substrate includes a third-order top wall portion, a third-order side wall portion, a fourth-order top wall portion, and a fourth-order side wall portion. A second height difference exists between the third-order top wall portion and the fourth-order top wall portion along the thickness direction of the silicon substrate. The tunneling passivation contact structure is disposed on the third-order top wall portion. The second edge passivation layer includes a fourth passivation portion, a fifth passivation portion, and a sixth passivation portion. The fourth passivation portion is disposed on the fourth-order side wall portion, at least a portion of the fifth passivation portion is disposed on the fourth-order top wall portion, and the sixth passivation portion is disposed on the side of the silicon substrate opposite to the fourth-order top wall portion. The passivation effect of the second edge passivation layer can reduce the recombination rate of electrons and holes in the edge and surrounding area of ​​the silicon substrate, thus resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

Description

[0001] This application is a divisional application. The original application has the application number 202511735235.X and the original application date is November 24, 2025. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a photovoltaic module. Background Technology

[0003] In related technologies, photovoltaic (PV) cells are used to convert solar energy into electrical energy, and they are widely used in various applications utilizing renewable energy sources. However, the photoelectric conversion efficiency of PV cells still needs improvement. Summary of the Invention

[0004] In view of this, this application provides a photovoltaic cell and a photovoltaic module to improve the photoelectric conversion efficiency of the photovoltaic cell and the output power of the photovoltaic module.

[0005] This application provides a photovoltaic cell, which includes a silicon substrate, a tunneling passivation contact structure, and a second edge passivation layer. The silicon substrate includes a third step and a fourth step. The third step includes a third-stage top wall portion and a third-stage side wall portion. The fourth step includes a fourth-stage top wall portion and a fourth-stage side wall portion. There is a second height difference between the third-stage top wall portion and the fourth-stage top wall portion along the thickness direction of the silicon substrate. The tunneling passivation contact structure is disposed on the third-stage top wall portion. The second edge passivation layer includes a fourth passivation portion, a fifth passivation portion, and a sixth passivation portion. The fourth passivation portion is disposed on the fourth-stage side wall portion. At least a portion of the fifth passivation portion is disposed on the fourth-stage top wall portion. The sixth passivation portion is disposed on the side of the silicon substrate opposite to the fourth-stage top wall portion.

[0006] In this application, the passivation effect of the second edge passivation layer can reduce the recombination rate of electrons and holes in the edge and nearby regions of the silicon substrate, so as to make the minority carrier lifetime relatively long, thereby making the photoelectric conversion efficiency of the photovoltaic cell relatively large.

[0007] This application also provides a photovoltaic module, which includes a cell string comprising at least two electrically connected photovoltaic cells. The photovoltaic cells are those described above and provided in this application. Because photovoltaic cells have high photoelectric conversion efficiency, the output power of the photovoltaic module is also relatively high.

[0008] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the first embodiment; Figure 2 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the second embodiment; Figure 3 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the third embodiment; Figure 4 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the fourth embodiment; Figure 5 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the fifth embodiment; Figure 6 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the sixth embodiment; Figure 7 A schematic diagram of the first, second, or other pyramidal structures from a three-dimensional perspective. Figure 8 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the seventh embodiment; Figure 9 This is a schematic diagram of the inverted pyramid structure from a three-dimensional perspective. Figure 10 This is a schematic diagram of the cylindrical structure of the second light-trapping structure from a stereoscopic perspective. Figure 11 This is a schematic diagram of the concave curved surface of the second light-trapping structure from a stereoscopic perspective. Figure 12 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the eighth embodiment; Figure 13 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the ninth embodiment; Figure 14 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the tenth embodiment; Figure 15 This is a partial cross-sectional view of the silicon substrate of a photovoltaic cell in the eleventh embodiment; Figure 16 This is a partial cross-sectional view of the photovoltaic cell in the twelfth embodiment; Figure 17 This is a partial cross-sectional view of the photovoltaic cell in the thirteenth embodiment; Figure 18 This is a partial cross-sectional view of the photovoltaic cell in the fourteenth embodiment; Figure 19 This is a partial cross-sectional view of the photovoltaic cell in the fifteenth embodiment; Figure 20 This is a partial cross-sectional view of the photovoltaic cell in the sixteenth embodiment; Figure 21 This is a partial cross-sectional view of the photovoltaic cell in the seventeenth embodiment; Figure 22 This is a partial cross-sectional view of the photovoltaic cell in the eighteenth embodiment; Figure 23 This is a partial cross-sectional view of the photovoltaic cell in the nineteenth embodiment; Figure 24 This is a partial cross-sectional view of the photovoltaic cell in the twentieth embodiment; Figure 25 This is a partial cross-sectional view of the photovoltaic cell in the twenty-first embodiment; Figure 26 This is a partial cross-sectional view of the photovoltaic cell in the twenty-second embodiment; Figure 27 This is a partial cross-sectional view of the photovoltaic cell in the twenty-third embodiment; Figure 28 This is a partial cross-sectional view of the photovoltaic cell in the twenty-fourth embodiment; Figure 29 This is a partial cross-sectional view of the photovoltaic cell in the twenty-fifth embodiment; Figure 30 This is a partial cross-sectional view of the photovoltaic cell in the twenty-sixth embodiment; Figure 31 This is a partial cross-sectional view of the photovoltaic cell in the twenty-seventh embodiment; Figure 32 This is a schematic cross-sectional view of the photovoltaic cell in the twenty-eighth embodiment; Figure 33 This is a cross-sectional structural diagram of a photovoltaic cell in the twenty-ninth embodiment; Figure 34 This is a cross-sectional view of the photovoltaic cell in the thirtieth embodiment; Figure 35 This is a cross-sectional view of a photovoltaic cell in the thirty-first embodiment; Figure 36 This is a cross-sectional view of the photovoltaic cell in the thirty-second embodiment; Figure 37 This is a cross-sectional view of the photovoltaic cell in the thirty-third embodiment; Figure 38 This is a cross-sectional view of the photovoltaic cell in the thirty-fourth embodiment.

[0011] Figure reference numerals: SG - Light-receiving side, BG - Backlight side, LC - First side, RC - Second side, QB - Cut edge, 10 - Photovoltaic cell, 1 - Silicon substrate, 1j - Base region, 1a - Active region, 1b - Passive region, 1c - Collection region, 1d - Non-collection region, 11 - First step, 111 - First-stage top wall, 1111 - First light-trapping structure, 1111a - First positive pyramid structure, 1111b - Positive pyramid structure, 112 - First-stage side wall, 12 - Second step, 121 - Second-stage top wall, 1211 - Second light-trapping structure, 1211a - Second positive pyramid structure, 1211b - Inverted pyramid structure, 1211c - Cylindrical structure, 1211d - Concave surface, 1212 - Polished surface, 122 - Second-stage side wall, 13 - Third step 131-Third-order top wall portion, 132-Third-order side wall portion, 14-Fourth step, 141-Fourth-order top wall portion, 142-Fourth-order side wall portion, 2-First edge passivation layer, 21-First passivation portion, 22-Second passivation portion, 221-First segment, 222-Second segment, 223-Third segment, 23-Third passivation portion, 3-First passivation layer, 31-Fourth segment, 32-Fifth segment, 33-Sixth segment, 4-Tunneling layer, 5-Doped polycrystalline silicon, 6-Second edge passivation layer, 61-Fourth passivation portion, 62-Fifth passivation portion, 621-Seventh segment, 622-Eighth segment, 623-Ninth segment, 63-Sixth passivation portion, 7-Second passivation layer, 71-Tenth segment, 72-Eleventh segment, 73-Twelfth segment, 8-Electrode, 81-First electrode, 82-Second electrode. Detailed Implementation

[0012] To better understand the technical solutions of this application, the embodiments of this application are described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The terminology used in the embodiments of this application is for the purpose of describing specific embodiments only, and is not intended to limit this application. The singular forms "a," "described," and "the" used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects are in an "or" relationship.

[0013] In the accompanying figures, the vertical and horizontal directions are perpendicular to each other. For photovoltaic cells or silicon substrates, the vertical direction can be the thickness direction of the photovoltaic cell or silicon substrate, and the horizontal direction can be the direction parallel to the front or back of the photovoltaic cell or silicon substrate. In addition, the vertical direction can be understood as the first direction, and the horizontal direction can be understood as the second direction.

[0014] Firstly, this application provides some embodiments of photovoltaic cells. In some embodiments, please refer to... Figure 1 or Figure 2 As shown, a photovoltaic cell may include a silicon substrate 1, which may have a passive region 1b and an active region 1a. The active region 1a and the passive region 1b may be spaced apart along the thickness direction of the photovoltaic cell or the thickness direction of the silicon substrate 1. The thickness direction of the photovoltaic cell or the thickness direction of the silicon substrate 1 may be the vertical direction as shown in the accompanying drawings.

[0015] In some embodiments, please refer to Figure 1 or Figure 2 As shown, silicon substrate 1 can be used to absorb sunlight and to generate electron-hole pairs. Silicon substrate 1 can be an N-type silicon substrate, which means that silicon substrate 1 can be doped with at least one N-type element (a group 5 element in the periodic table), such as phosphorus, arsenic, antimony, etc.

[0016] In some embodiments, please refer to Figure 1 or Figure 2As shown, the active region 1a can be a local area within the silicon substrate 1. For an N-type silicon substrate, the active region 1a can be doped with at least one P-type element (a group 3 element in the periodic table), such as boron, aluminum, gallium, etc. A PN junction can be formed between the N-type doped base region 1j and the P-type doped active region 1a within the silicon substrate 1. A built-in electric field exists within the PN junction. This built-in electric field can separate electron-hole pairs within the silicon substrate 1, causing holes to move away from the base region 1j within the active region 1a, and electrons to move away from the active region 1a within the base region 1j. This can also be understood as the holes and electrons separated by the built-in electric field moving in opposite directions along the thickness direction of the photovoltaic cell or the silicon substrate 1.

[0017] In the N-type silicon substrate, holes are the minority carriers and electrons are the majority carriers.

[0018] In some embodiments, please refer to Figure 1 or Figure 2 As shown, passive region 1b can be another local region within silicon substrate 1. Passive region 1b is not doped with p-type elements, or it is doped with a very small amount of p-type elements, such as boron with a concentration not exceeding E15 atoms / cm². 3 (1 per cubic centimeter) 10 15 (Number of boron atoms). Compared to the active region 1a, the passive region 1b is less prone to hole transport, and there is a spacing between the active region 1a and the passive region 1b along the thickness direction of the photovoltaic cell or the silicon substrate 1. Under this configuration, holes collected in the active region 1a are less likely to move to the edge and vicinity of the silicon substrate 1 via the passive region 1b, making it less likely for holes collected in the active region 1a to recombine with electrons located at the edge and vicinity of the silicon substrate 1. Therefore, some embodiments of photovoltaic cells provided in this application have the advantage of a relatively long minority carrier lifetime, and correspondingly, some embodiments of photovoltaic cells provided in this application have the advantage of a relatively high photoelectric conversion efficiency.

[0019] In some embodiments, please refer to Figure 1 or Figure 2 As shown, the active region 1a and the passive region 1b are both local regions defined on the same side of the silicon substrate 1 along its own thickness direction.

[0020] In some embodiments, if the photovoltaic cell is a sectional photovoltaic cell separated from an original whole photovoltaic cell, the edge of the silicon substrate 1 may have a dicing edge QB formed by a dicing process or a sectionalizing process. The dicing edge QB may be located on the side of the passive region 1b away from the active region 1a. Due to silicon substrate damage caused by dicing, there are relatively more lattice defects in and around the dicing edge QB. Correspondingly, there may be relatively more recombination centers (energy levels that promote electron-hole recombination) in and around the dicing edge QB. Therefore, holes collected in the active region 1a are not easily moved through the passive region 1b to the dicing edge QB and its vicinity of the silicon substrate 1, and holes collected in the active region 1a are not easily recombinated with electrons located in and around the dicing edge QB of the silicon substrate 1. Therefore, some embodiments of photovoltaic cells provided in this application have the advantage of a relatively long minority carrier lifetime, and correspondingly, some embodiments of photovoltaic cells provided in this application have the advantage of a relatively high photoelectric conversion efficiency.

[0021] In some embodiments, please refer to Figure 1 As shown, the silicon substrate 1 may include a first step 11 and a second step 12. The first step 11 may include an intersecting first-step top wall portion 111 and a first-step side wall portion 112. The second step 12 may include an intersecting second-step top wall portion 121 and a second-step side wall portion 122. The end of the first-step side wall portion 112 away from the first-step top wall portion 111 and the end of the second-step top wall portion 121 away from the second-step side wall portion 122 may intersect. The first-step top wall portion 111 and the second-step top wall portion 121 may have a first height difference G1 along the thickness direction of the photovoltaic cell or the thickness direction of the silicon substrate 1. The first-step top wall portion 111 may be provided with an active region 1a, and the second-step top wall portion 121 may be provided with a passive region 1b, so as to satisfy the above-mentioned setting of "there is a spacing distance between the active region 1a and the passive region 1b along the thickness direction of the photovoltaic cell or the thickness direction of the silicon substrate 1".

[0022] In some embodiments, the active region 1a may be a local region within the silicon substrate 1 that extends to a certain depth from the first-order top wall portion 111 into the silicon substrate 1, and the passive region 1b may be a local region within the silicon substrate 1 that extends to a certain depth from the second-order top wall portion 121 into the silicon substrate 1.

[0023] In some embodiments, the first-order top wall portion 111 may be one of the surfaces of the active region 1a, and the second-order top wall portion 121 may be one of the surfaces of the passive region 1b.

[0024] In some embodiments, the passive region 1b can be understood as a local region within the base region 1j near the second-order top wall portion 121.

[0025] In some embodiments, Figure 1The view shown can be one of the cross-sectional views of the silicon substrate 1. Without considering the vertical direction, the second step 12 is a step lower than the first step 11. The position of the top wall of the second step 121 is lower than the position of the top wall of the first step 111. Correspondingly, the position of the passive region 1b is lower than the position of the active region 1a.

[0026] In some embodiments, Figure 2 The view shown can be one of the cross-sectional views of the silicon substrate 1. Without considering the vertical direction, the position of the passive region 1b can be higher than the position of the active region 1a.

[0027] In some embodiments, please refer to Figure 1 As shown, the silicon substrate 1 may have a light-receiving side SG and a back-lighting side disposed opposite to each other in the thickness direction of the photovoltaic cell or in the thickness direction of the silicon substrate 1. The light-receiving side SG refers to the side of the photovoltaic cell that can be directly or primarily irradiated by sunlight. The first-order top wall portion 111, the active region 1a, the first-order side wall portion 112, the second-order top wall portion 121, and the passive region 1b are all located on the light-receiving side SG of the silicon substrate 1.

[0028] In some embodiments, please refer to Figure 3 As shown, the silicon substrate 1 may have a light-receiving side and a back-lighting side BG disposed opposite to each other in the thickness direction of the photovoltaic cell or in the thickness direction of the silicon substrate 1. The light-receiving side refers to the side of the photovoltaic cell that can be directly or primarily irradiated by sunlight. The first-order top wall portion 111, the active region 1a, the first-order side wall portion 112, the second-order top wall portion 121, and the passive region 1b are all located on the back-lighting side BG of the silicon substrate 1.

[0029] In some embodiments, please refer to Figure 1 or Figure 3 As shown, the silicon substrate 1 may include a first step 11 and a second step 12, and correspondingly, the silicon substrate 1 may be provided with an active region 1a and a passive region 1b.

[0030] In some embodiments, please refer to Figure 4 or Figure 5 As shown, the silicon substrate 1 may include two first steps 11 and two second steps 12. In the left-right direction, the two first steps 11 may be located between the two second steps 12. The two first steps 11 may have a common first step top wall portion 111. Correspondingly, the silicon substrate 1 may be provided with an active region 1a and two passive regions 1b. The active region 1a may be located between the two passive regions 1b.

[0031] In some embodiments, please refer to Figure 1 , Figure 3 , Figure 4 or Figure 5 As shown, the first height difference G1 can satisfy: 1.5 micrometers (µm) ≤ G1 ≤ 10 micrometers (µm). Specifically, the first height difference G1 can be 1.5µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, or 10µm. If the first height difference G1 is too large, for example, greater than 10µm, the thickness of the portion near the second step 12 of the silicon substrate 1 will be relatively small, resulting in relatively low structural strength. Under external forces, this portion of the silicon substrate 1 is prone to structural damage such as cracks. If the first height difference G1 is too small, for example, less than 1.5µm, it indicates that the area of ​​the first-order sidewall portion 112 is relatively small. A relatively small first-order sidewall portion 112 is less likely to absorb sunlight reflected by the second-order top wall portion 121. In other words, the first-order sidewall portion 112 and the second-order top wall portion 121 are less likely to form a light-trapping structure, resulting in a relatively small number of electron-hole pairs generated within the silicon substrate 1, and a relatively low photoelectric conversion efficiency for the photovoltaic cell. Therefore, a first height difference G1 within the range of 1.5µm to 10µm is relatively better.

[0032] In some other embodiments, the first height difference G1 may also be in the range of 1.5µm to 5µm, wherein the first height difference G1 may specifically be 1.5µm, 2µm, 2.5µm, 3µm, 3.5µm, 4µm, 4.5µm or 5µm.

[0033] In some other embodiments, the first height difference G1 may also be in the range of 5µm to 9µm, wherein the first height difference G1 may specifically be 5µm, 5.5µm, 6µm, 6.5µm, 7µm, 7.5µm, 8µm, 8.5µm or 9µm.

[0034] In some other embodiments, the first height difference G1 may also be in the range of 4µm to 8µm, wherein the first height difference G1 may specifically be 4µm, 4.5µm, 5µm, 5.5µm, 6µm, 6.5µm, 7µm, 7.5µm or 8µm.

[0035] In some embodiments, please refer to Figure 6As shown, the first-order top wall portion 111 may include a first light-trapping structure 1111, which may include multiple first positive pyramid structures 1111a. The second-order top wall portion 121 may include a second light-trapping structure 1211, which may include multiple second positive pyramid structures 1211a. The distance between the bottom of the first positive pyramid structure 1111a and the bottom of the second positive pyramid structure 1211a is a first height difference G1. The silicon substrate 1 with the first light-trapping structure 1111 and the second light-trapping structure 1211 has a relatively low light reflectivity, and the silicon substrate 1 can generate a relatively large number of electron-hole pairs, resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

[0036] In some embodiments, it should be noted that the distance between the bottom of the first positive pyramid structure 1111a and the bottom of the second positive pyramid structure 1211a can be measured using microscopic instruments such as scanning electron microscopes (SEM) or atomic force microscopes (AFM). For those in the art, in a cross-section within each pyramid structure that is parallel to both the vertical and horizontal directions, the bottom of the pyramid structure can be understood as the base of a triangle or the base of an approximate triangular geometric shape; further details will not be elaborated here.

[0037] Among them, the structure of the first positive pyramid structure 1111a of the first light-trapping structure 1111 in a stereoscopic view can be as follows: Figure 7 As shown, the structure of the second positive pyramid structure 1211a of the second light-trapping structure 1211 in a stereoscopic view can be as follows: Figure 7 As shown. In addition, both the first positive pyramid structure 1111a and the second positive pyramid structure 1211a are structures that bulge outward from the silicon substrate 1.

[0038] In some embodiments, please refer to Figure 8 As shown, the first-order top wall portion 111 may include a first light-trapping structure 1111, which may include multiple upright pyramid structures 1111b. The second-order top wall portion 121 may include a second light-trapping structure 1211, which may include multiple inverted pyramid structures 1211b. A first height difference G1 may exist between the bottom of the upright pyramid structure 1111b and the bottom of the inverted pyramid structure 1211b. The silicon substrate 1 with the first light-trapping structure 1111 and the second light-trapping structure 1211 has a relatively low light reflectivity, and the silicon substrate 1 can generate a relatively large number of electron-hole pairs, resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

[0039] Among them, the structure of the positive pyramid structure 1111b of the first light-trapping structure 1111 in a stereoscopic view can be as follows: Figure 7 As shown, the structure of the inverted pyramid structure 1211b of the second light-trapping structure 1211 in a stereoscopic view can be seen as follows: Figure 9 As shown. Furthermore, the upright pyramid structure 1111b protrudes outward from the silicon substrate 1, while the inverted pyramid structure 1211b is recessed inward from the silicon substrate 1. Moreover, the bottom of the inverted pyramid structure 1211b can have a quadrilateral or polygonal opening shape.

[0040] In some other embodiments, please refer to Figure 10 As shown, the second light-trapping structure 1211 of the second-order top wall portion 121 may also include multiple arrayed nanoscale cylindrical structures 1211c. The diameter and height of any one of the cylindrical structures 1211c can be nanoscale.

[0041] In some other embodiments, please refer to Figure 11 As shown, the second light-trapping structure 1211 of the second-order top wall portion 121 may also include a plurality of nanoscale concave curved surfaces 1211d arranged in an array. The length, width and depth of any concave curved surface 1211d can be nanoscale.

[0042] In some embodiments, please refer to Figure 12 As shown, the first-order top wall portion 111 may include a first light-trapping structure 1111, which may include multiple positive pyramid structures 1111b. The second-order top wall portion 121 may include a polished surface 1212. A first height difference G1 may exist between the bottom of the positive pyramid structure 1111b and the polished surface 1212. The silicon substrate 1 with the first light-trapping structure 1111 has a relatively low light reflectivity, and the silicon substrate 1 can generate a relatively large number of electron-hole pairs, resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell.

[0043] In some embodiments, please refer to Figure 13 As shown, the first-order top wall portion 111 and the first-order side wall portion 112 can have an included angle α, satisfying 90 degrees (°) ≤ α ≤ 150 degrees (°).

[0044] In some embodiments, please refer to Figure 13 As shown, when the included angle α is equal to 90°, the first-order top wall portion 111 is perpendicular to the first-order side wall portion 112.

[0045] In some embodiments, please refer to Figure 13As shown, when the included angle α is greater than 90°, and when the included angle α is less than or equal to 150°, the first-stage sidewall portion 112 is inclined relative to the first-stage top wall portion 111. This arrangement can, on the one hand, make the stress concentration at the connection between the first-stage top wall portion 111 and the first-stage sidewall portion 112 relatively small. Under the action of external force, structural damage problems such as cracks are not likely to occur at and near the connection between the first-stage top wall portion 111 and the first-stage sidewall portion 112. On the other hand, this arrangement can also make the passivation layer deposited at the connection between the first-stage top wall portion 111 and the first-stage sidewall portion 112 relatively uniform, and the passivation effect of the passivation layer at the connection between the first-stage top wall portion 111 and the first-stage sidewall portion 112 is relatively good.

[0046] In some other embodiments, the included angle α may also be in the range of 100° to 120°, wherein the included angle α can specifically be 100°, 101°, 102°, 103°, 104°, 105°, 106°, 107°, 108°, 109°, 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119° or 120°.

[0047] In some other embodiments, the included angle α may also be in the range of 130° to 150°, wherein the included angle α can specifically be 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139°, 140°, 141°, 142°, 143°, 144°, 145°, 146°, 147°, 148°, 149° or 150°.

[0048] In some other embodiments, the included angle α may also be in the range of 110° to 140°, wherein the included angle α can specifically be 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119°, 120°, 121°, 122°, 123°, 124°, 125°, 126°, 127°, 128°, 129°, 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139° or 140°.

[0049] In some embodiments, please refer to Figure 13 As shown, the first-order sidewall portion 112 and the second-order topwall portion 121 can have an included angle β, satisfying 90°≤β≤150°.

[0050] In some embodiments, please refer to Figure 13 As shown, when the included angle β is equal to 90°, the first-order sidewall portion 112 is perpendicular to the second-order topwall portion 121.

[0051] In some embodiments, please refer to Figure 13 As shown, when the included angle β is greater than 90°, and when the included angle β is less than or equal to 150°, the first-order sidewall portion 112 is inclined relative to the second-order top wall portion 121. This arrangement, on the one hand, makes the passivation layer deposited at the connection between the first-order sidewall portion 112 and the second-order top wall portion 121 relatively uniform, and the passivation effect of the passivation layer at the connection between the first-order sidewall portion 112 and the second-order top wall portion 121 is relatively good. On the other hand, this arrangement also makes the first-order sidewall portion 112 relatively inclined relative to the second-order top wall portion 121. Since the second-order top wall 121 is relatively steep, sunlight reflected by the second-order top wall 121 can more easily shine back onto the first-order side wall 112. Similarly, sunlight reflected by the first-order side wall 112 can more easily shine back onto the second-order top wall 121. It can also be understood that the first-order side wall 112 and the second-order top wall 121 form a good light-trapping structure, so that the light reflectivity of the silicon substrate 1 is relatively low, so that the number of electron-hole pairs that the silicon substrate 1 can generate is relatively large, and the photoelectric conversion efficiency of the photovoltaic cell is relatively large.

[0052] In some other embodiments, the included angle β may also be in the range of 100° to 120°, wherein the included angle β can specifically be 100°, 101°, 102°, 103°, 104°, 105°, 106°, 107°, 108°, 109°, 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119° or 120°.

[0053] In some other embodiments, the included angle β may also be in the range of 130° to 150°, wherein the included angle β can specifically be 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139°, 140°, 141°, 142°, 143°, 144°, 145°, 146°, 147°, 148°, 149° or 150°.

[0054] In some other embodiments, the included angle β may also be in the range of 110° to 140°, wherein the included angle β can specifically be 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119°, 120°, 121°, 122°, 123°, 124°, 125°, 126°, 127°, 128°, 129°, 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139° or 140°.

[0055] In some embodiments, when the included angle α is greater than 90° and when the included angle α is less than 150°, and when the included angle β is greater than 90° and when the included angle β is less than 150°, the structure of the first step 11 and the structure of the second step 12 of the silicon substrate 1 can also be as follows: Figure 14 As shown, under this configuration, the light trapping effect of the light trapping structure composed of the first-order sidewall portion 112 and the second-order top wall portion 121 is better, resulting in the silicon substrate 1 having a lower light reflectivity, the silicon substrate 1 being able to generate a relatively large number of electron-hole pairs, and the photovoltaic cell having a relatively high photoelectric conversion efficiency.

[0056] In some embodiments, when the included angle α is greater than 90° and when the included angle α is less than 150°, and when the included angle β is greater than 90° and when the included angle β is less than 150°, the structure of the first step 11 and the structure of the second step 12 of the silicon substrate 1 can also be as follows: Figure 15 As shown, under this setting, the passivation layers deposited at the connection between the first-stage top wall portion 111 and the first-stage side wall portion 112, the connection between the first-stage side wall portion 112 and the second-stage top wall portion 121, and the connection between the second-stage top wall portion 121 and the second-stage side wall portion 122 are relatively uniform, and the passivation effect is relatively good.

[0057] In some embodiments, please refer to Figure 13 As shown, the first-order sidewall portion 112 can have a first width W1, satisfying 1µm≤W1≤100µm. Specifically, the first width W1 can be 1µm, 5µm, 10µm, 20µm, 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, or 100µm. When the first width W1 is less than 1µm, it can be understood that the first-order sidewall portion 112 is nearly perpendicular to the first-order top wall portion 111. In this case, the passivation layer deposited at the junction between the first-order top wall portion 111 and the first-order sidewall portion 112 is prone to uneven deposition, meaning the passivation effect at this location is relatively poor. When the first width W1 is greater than 100µm, the first-order sidewall 112 is too flat, and sunlight reflected by the second-order top wall 121 is unlikely to re-irradiate the first-order sidewall 112. Similarly, sunlight reflected by the first-order sidewall 112 is also unlikely to re-irradiate the second-order top wall 121. The light reflectivity of the silicon substrate 1 is relatively high, and the number of electron-hole pairs generated by the silicon substrate 1 is relatively small. Therefore, when the first width W1 is in the range of 1µm to 100µm, the photoelectric conversion efficiency of the photovoltaic cell can be relatively high.

[0058] In some other embodiments, the first width W1 can be in the range of 1µm to 10µm, wherein the first width W1 can specifically be 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm or 10µm.

[0059] In some other embodiments, the first width W1 can be in the range of 10µm to 50µm, wherein the first width W1 can specifically be 10µm, 11µm, 12µm, 13µm, 14µm, 15µm, 16µm, 17µm, 18µm, 19µm, 20µm, 21µm, 22µm, 23µm, 24µm, 25µm, 26µm, 27µm, 28µm, 29µm, 30µm, 31µm, 32µm, 33µm, 34µm, 35µm, 36µm, 37µm, 38µm, 39µm, 40µm, 41µm, 42µm, 43µm, 44µm, 45µm, 46µm, 47µm, 48µm, 49µm or 50µm.

[0060] In some other embodiments, the first width W1 can be in the range of 50µm to 90µm, wherein the first width W1 can specifically be 50µm, 51µm, 52µm, 53µm, 54µm, 55µm, 56µm, 57µm, 58µm, 59µm, 60µm, 61µm, 62µm, 63µm, 64µm, 65µm, 66µm, 67µm, 68µm, 69µm, 70µm, 71µm, 72µm, 73µm, 74µm, 75µm, 76µm, 77µm, 78µm, 79µm, 80µm, 81µm, 82µm, 83µm, 84µm, 85µm, 86µm, 87µm, 88µm, 89µm or 90µm.

[0061] In some other embodiments, the first width W1 can be in the range of 30µm to 70µm, wherein the first width W1 can specifically be 30µm, 31µm, 32µm, 33µm, 34µm, 35µm, 36µm, 37µm, 38µm, 39µm, 40µm, 41µm, 42µm, 43µm, 44µm, 45µm, 46µm, 47µm, 48µm, 49µm, 50µm, 51µm, 52µm, 53µm, 54µm, 55µm, 56µm, 57µm, 58µm, 59µm, 60µm, 61µm, 62µm, 63µm, 64µm, 65µm, 66µm, 67µm, 68µm, 69µm or 70µm.

[0062] In some embodiments, please refer to Figure 16 or Figure 17As shown, the photovoltaic cell 10 may further include a first edge passivation layer 2. The first edge passivation layer 2 may include a first passivation portion 21 and a second passivation portion 22 connected together. The first passivation portion 21 may be deposited on the edge of the silicon substrate 1 (e.g., the diced edge QB mentioned above), and at least a portion of the structure of the second passivation portion 22 may be deposited on one side of the passive region 1b. The extension direction of the first passivation portion 21 and the extension direction of the second passivation portion 22 may intersect. In this configuration, the passivation effect of the first edge passivation layer 2 can reduce the recombination rate of electrons and holes in the passive region 1b, the diced edge QB, and the areas near them of the silicon substrate 1, resulting in a relatively long minority carrier lifetime and thus a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0063] In some embodiments, please refer to Figure 16 As shown, when the second-order sidewall portion 122 is one of the edges of the silicon substrate 1, or when the second-order sidewall portion 122 is the diced edge QB of the silicon substrate 1, the first passivation portion 21 can be deposited on the second-order sidewall portion 122, and the first passivation portion 21 can provide passivation for the second-order sidewall portion 122. When the second-order top wall portion 121 is provided with a passive region 1b, at least a portion of the structure of the second passivation portion 22 can be located on one side of the second-order top wall portion 121, and the second passivation portion 22 can provide passivation for both the second-order top wall portion 121 and the passive region 1b.

[0064] In some embodiments, please refer to Figure 16 As shown, the photovoltaic cell 10 may further include a first passivation layer 3. At least a portion of the structure of the first passivation layer 3 may be deposited on the second-order top wall portion 121, and the structure of the first passivation layer 3 deposited on the second-order top wall portion 121 may be covered by a second passivation portion 22. In this configuration, on the one hand, the second passivation portion 22 and the first passivation layer 3 can together provide passivation for the passive region 1b, reducing the recombination rate of electrons and holes in and around the passive region 1b, thereby making the photoelectric conversion efficiency of the photovoltaic cell 10 relatively high. On the other hand, the thickness of the edge and nearby portions of the photovoltaic cell 10 is relatively large, and the structural strength of the edge and nearby portions of the photovoltaic cell 10 is relatively high. Under external force, the edge and nearby portions of the photovoltaic cell 10 are less prone to structural damage problems such as cracks.

[0065] In some embodiments, please refer to Figure 16 As shown, the refractive index of the second passivation portion 22 can be less than that of the first passivation layer 3. Under this configuration, the photovoltaic cell 10 can have the advantage of relatively low light reflectivity, and the number of electron-hole pairs that can be generated in the silicon substrate 1 is relatively large, thereby making the photoelectric conversion efficiency of the photovoltaic cell 10 relatively high.

[0066] In some embodiments, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be in the range of 0.75 to 0.95. Specifically, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be 0.75, 0.76, 0.77, 0.78, 0.79, 0.8, 0.81, 0.82, 0.83, 0.84, 0.85, 0.86, 0.87, 0.88, 0.89, 0.9, 0.91, 0.92, 0.93, 0.94, or 0.95. Under this configuration, the difference between the refractive index of the second passivation portion 22 and the refractive index of the first passivation layer 3 is relatively small, and the stacked structure formed by the first passivation layer 3 and the second passivation portion 22 can have a good anti-reflection effect, thereby resulting in a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0067] In some other embodiments, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be in the range of 0.75 to 0.85. Specifically, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be 0.75, 0.76, 0.77, 0.78, 0.79, 0.8, 0.81, 0.82, 0.83, 0.84, or 0.85.

[0068] In other embodiments, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be in the range of 0.85 to 0.95. Specifically, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be 0.85, 0.86, 0.87, 0.88, 0.89, 0.9, 0.91, 0.92, 0.93, 0.94, or 0.95.

[0069] In other embodiments, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be in the range of 0.8 to 0.9. Specifically, the ratio of the refractive index of the second passivation portion 22 to the refractive index of the first passivation layer 3 can be 0.8, 0.81, 0.82, 0.83, 0.84, 0.85, 0.86, 0.87, 0.88, 0.89, or 0.9.

[0070] In some embodiments, the refractive index of the second passivation portion 22 may be in the range of 1.4 to 1.6. Specifically, the refractive index of the second passivation portion 22 may be 1.4, 1.45, 1.5, 1.55, or 1.6.

[0071] In some embodiments, the refractive index of the first passivation layer 3 can be in the range of 1.7 to 2. Specifically, the refractive index of the first passivation layer 3 can be 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 2.

[0072] In some embodiments, the method for determining the refractive index may be elliptically polarized light method, reflection / transmission spectroscopy method or interferometry, and the tool for determining the refractive index may be an elliptically polarized spectrometer or an ultraviolet-visible-near-infrared spectrophotometer.

[0073] In some embodiments, please refer to Figure 16 As shown, the first passivation layer 3 can also be deposited on the first-order sidewall portion 112 and the first-order top wall portion 111. The second passivation portion 22 extends from one side of the second-order top wall portion 121 to one side of the first-order top wall portion 111. The portion of the structure deposited in the first-order top wall portion 111 within the first passivation layer 3 can be covered by the second passivation portion 22. Under this configuration, on the one hand, the passivation effect of the stacked structure formed by the second passivation portion 22 and the first passivation layer 3 is better and the passivation range is larger, so that the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large. On the other hand, the thickness of the edge and nearby portion of the photovoltaic cell 10 is greater, and the structural strength of the edge and nearby portion of the photovoltaic cell 10 is greater. Under the action of external force, the edge and nearby portion of the photovoltaic cell 10 is less prone to structural damage problems such as cracks.

[0074] In some embodiments, please refer to Figure 16 As shown, the second passivation portion 22 may include a first segment 221, a second segment 222 and a third segment 223, and the first passivation layer 3 may include a fourth segment 31, a fifth segment 32 and a sixth segment 33. The fourth segment 31 may be deposited on the second-order top wall portion 121, the fifth segment 32 may be deposited on the first-order side wall portion 112, and the sixth segment 33 may be deposited on the first-order top wall portion 111. The first segment 221 may be deposited on the fourth segment 31, the second segment 222 may be deposited on the fifth segment 32, and the third segment 223 may be deposited on the local structure of the sixth segment 33.

[0075] In some other embodiments (not shown in the figures), the second passivation portion may be deposited primarily on one side of the passive region or on one side of the second-order top wall portion.

[0076] In some embodiments, please refer to Figure 16 As shown, the deposition thickness DH1 of the second passivation portion 22 can be greater than the deposition thickness SH1 of the first passivation layer 3. Under this configuration, the second passivation portion 22 can provide a relatively strong field passivation effect to reduce the recombination rate of electrons and holes at and near the edge of the photovoltaic cell 10, thereby resulting in a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0077] The deposition thickness can refer to the thickness in the direction perpendicular to the surface being deposited.

[0078] In some embodiments, please refer to Figure 16As shown, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be in the range of 1.1 to 2. Specifically, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.

[0079] In other embodiments, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be in the range of 1.1 to 1.5. Specifically, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, or 1.5.

[0080] In other embodiments, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be in the range of 1.5 to 2. Specifically, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 2.

[0081] In other embodiments, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be in the range of 1.4 to 1.8. Specifically, the ratio of the deposition thickness DH1 of the second passivation portion 22 to the deposition thickness SH1 of the first passivation layer 3 can be 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, or 1.8.

[0082] In some embodiments, please refer to Figure 16 As shown, the deposition thickness DH1 of the second passivation portion 22 can be in the range of 100 nanometers (nm) to 150 nanometers (nm). Specifically, the deposition thickness DH1 can be 100nm, 110nm, 120nm, 130nm, 140nm, or 150nm.

[0083] In other embodiments, the deposition thickness DH1 of the second passivation portion 22 may also be in the range of 100nm to 130nm. Specifically, the deposition thickness DH1 may be 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, or 130nm.

[0084] In some other embodiments, the deposition thickness DH1 of the second passivation portion 22 may also be in the range of 120nm to 150nm. Specifically, the deposition thickness DH1 may be 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, or 150nm.

[0085] In some other embodiments, the deposition thickness DH1 of the second passivation portion 22 may also be in the range of 110nm to 140nm. Specifically, the deposition thickness DH1 may be 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, or 140nm.

[0086] In some embodiments, please refer to Figure 16 As shown, the deposition thickness SH1 of the first passivation layer 3 can be in the range of 70nm to 90nm. Specifically, the deposition thickness SH1 can be 70nm, 75nm, 80nm, 85nm or 90nm.

[0087] In some embodiments, the first edge passivation layer 2 may include a silicon oxide layer (Si). x O y ), aluminum oxide layer (Al) x O y ), silicon nitride layer (Si x N y ), silicon oxynitride layer (SiO) x N y At least one of them.

[0088] In some embodiments, the first edge passivation layer 2 may be a single passivation layer.

[0089] In some embodiments, the first edge passivation layer 2 may include at least two passivation layers. For example, the first edge passivation layer 2 may be composed of a silicon oxide layer and an aluminum oxide layer, with the silicon oxide layer closer to the silicon substrate 1 than the aluminum oxide layer. Alternatively, the first edge passivation layer 2 may be composed of an aluminum oxide layer and a silicon nitride layer, with the aluminum oxide layer closer to the silicon substrate 1 than the silicon nitride layer. Or, the first edge passivation layer 2 may be composed of a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer, with the silicon oxide layer closer to the silicon substrate 1 than the aluminum oxide layer and the silicon nitride layer, and the aluminum oxide layer located between the silicon oxide layer and the silicon nitride layer.

[0090] In some embodiments, the first passivation layer 3 may include at least one of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0091] In some embodiments, the first passivation layer 3 may be a single passivation layer.

[0092] In some embodiments, the first passivation layer 3 may include at least two passivation layers. For example, the first passivation layer 3 may be composed of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0093] In some other embodiments (not shown in the figures), the second passivation portion may be deposited on the second-order top wall portion or the passive region, and the second passivation portion may be covered by the first passivation layer.

[0094] In some embodiments, please refer to Figure 18 As shown, the first edge passivation layer 2 may further include a third passivation portion 23. The end of the first passivation portion 21 away from the second passivation portion 22 is connected to the third passivation portion 23. The third passivation portion 23 may be deposited on the side of the silicon substrate 1 away from the second-order top wall portion 121 or the passive region 1b. The extension direction of the third passivation portion 23 intersects with the extension direction of the first passivation portion 21. Under this configuration, on the one hand, the thickness of the edge and nearby portion of the photovoltaic cell 10 is relatively large, and the structural strength of the edge and nearby portion of the photovoltaic cell 10 is greater. Under external force, the edge and nearby portion of the photovoltaic cell 10 are less prone to structural damage problems such as cracks. On the other hand, the third passivation portion 23 can also provide field passivation on the side of the silicon substrate 1 away from the second-order top wall portion 121 or the passive region 1b, so that the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large.

[0095] In some embodiments, please refer to Figure 18 As shown, the deposition width SW1 of the third passivation portion 23 can be smaller than the deposition width LW1 of the second passivation portion 22. It can also be understood that the deposition width SW1 of the third passivation portion 23 is relatively small, and the pads (part of the electrode structure of the photovoltaic cell, not shown in the figure) located on the side of the silicon substrate 1 away from the second passivation portion 22 and close to the edge of the silicon substrate 1 are not easily covered by the third passivation portion 23, so that the pads can be well soldered to the solder ribbon in the future, thereby forming a good cell string.

[0096] The deposition width can be the dimension along the direction perpendicular to the thickness of the photovoltaic cell 10, or it can be understood as the dimension along the left-right direction.

[0097] In some embodiments, please refer to Figure 18 As shown, the ratio of the deposition width SW1 of the third passivation section 23 to the deposition width LW1 of the second passivation section 22 can be in the range of 0.5 to 0.95, wherein the ratio can specifically be 0.5, 0.6, 0.7, 0.8, 0.9 or 0.95.

[0098] In some other embodiments, the ratio of the deposition width SW1 of the third passivation portion 23 to the deposition width LW1 of the second passivation portion 22 can be in the range of 0.5 to 0.7, wherein the ratio can specifically be 0.5, 0.55, 0.6, 0.65 or 0.7.

[0099] In some other embodiments, the ratio of the deposition width SW1 of the third passivation portion 23 to the deposition width LW1 of the second passivation portion 22 can be in the range of 0.7 to 0.9, wherein the ratio can specifically be 0.7, 0.75, 0.8, 0.85 or 0.9.

[0100] In some other embodiments, the ratio of the deposition width SW1 of the third passivation portion 23 to the deposition width LW1 of the second passivation portion 22 can be in the range of 0.6 to 0.8, wherein the ratio can specifically be 0.6, 0.65, 0.7, 0.75 or 0.8.

[0101] In some embodiments, please refer to Figure 18 As shown, the photovoltaic cell 10 may also include a tunneling layer 4 and doped polycrystalline silicon 5. When the active region 1a is disposed on the light-receiving side SG of the silicon substrate 1, the tunneling layer 4 and the doped polycrystalline silicon 5 may be disposed on the backlight side BG of the silicon substrate 1, with the tunneling layer 4 located between the silicon substrate 1 and the doped polycrystalline silicon 5.

[0102] In some embodiments, please refer to Figure 18 As shown, the tunneling layer 4 may include at least one of silicon oxide, silicon oxynitride, aluminum oxide, silicon nitride, amorphous silicon, and polycrystalline silicon. The thickness of the tunneling layer 4 can be in the range of 1 nm to 5 nm, specifically 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm. Furthermore, the tunneling layer 4 may exhibit quantum tunneling effects.

[0103] In some embodiments, please refer to Figure 18 As shown, both the doped polysilicon 5 and the silicon substrate 1 can be doped with at least one N-type element. The doping concentration of the doped polysilicon 5 is greater than that of the silicon substrate 1. This can be understood as the doped polysilicon 5 being a heavily doped region relative to the silicon substrate 1. A high / low junction (N / N) can be formed between the doped polysilicon 5 and the silicon substrate 1. + The built-in electric field of the high and low junction can attract electrons in the silicon substrate 1 to pass through the tunneling layer 4 and move towards the doped polycrystalline silicon 5. The built-in electric field of the high and low junction can prevent holes in the silicon substrate 1 from approaching the tunneling layer 4, thereby reducing the recombination rate of electrons and holes at the interface between the silicon substrate 1 and the tunneling layer 4, so that the photovoltaic cell 10 can have a relatively large photoelectric conversion efficiency.

[0104] In some embodiments, a tunneling passivation contact structure can be formed by at least the tunneling layer 4 and the doped polysilicon 5.

[0105] In some embodiments, please refer to Figure 18 As shown, the photovoltaic cell 10 may also include a second passivation layer 7, which may be disposed on the backlight side BG of the silicon substrate 1. The second passivation layer 7 is deposited on the doped polycrystalline silicon 5, and the local structure of the second passivation layer 7 may be covered by a third passivation portion 23.

[0106] In some embodiments, please refer to Figure 19 or Figure 20 As shown, the silicon substrate 1 can have a collecting region 1c and a non-collecting region 1d. There can be a spacing between the collecting region 1c and the non-collecting region 1d along the thickness direction of the photovoltaic cell 10 or the thickness direction of the silicon substrate 1. A tunneling passivation contact structure is deposited on the collecting region 1c. The tunneling passivation contact structure can include a tunneling layer 4 and doped polycrystalline silicon 5. The tunneling layer 4 can be located between the silicon substrate 1 and the doped polycrystalline silicon 5. No tunneling passivation contact structure is deposited on the non-collecting region 1d; that is, neither the tunneling layer 4 nor the doped polycrystalline silicon 5 is deposited on the non-collecting region 1d. Some possible configurations of the tunneling layer 4 and the doped polycrystalline silicon 5 have been described above and will not be repeated here. Based on the function of the tunneling passivation contact structure described above, electrons within the silicon substrate 1 can pass through the high / low junction (N / N... + Under the influence of the built-in electric field of the silicon substrate 1 and the quantum tunneling effect of the tunneling layer 4, holes move into the doped polycrystalline silicon 5. Holes in the silicon substrate 1 can move into the high / low junction (N / N) + Under the influence of the built-in electric field of the tunneling layer 4, the local area in the silicon substrate 1 that is in contact with the tunneling passivation contact structure can be called the collection region 1c. The collection region 1c can also be understood as the selective collection region or the selective passage region. The local area in the silicon substrate 1 that is not in contact with the tunneling passivation contact structure can be called the non-collection region 1d. The non-collection region 1d can also be understood as the non-selective collection region or the non-selective passage region.

[0107] In some embodiments, please refer to Figure 19 or Figure 20 As shown, both the collection region 1c and the non-collection region 1d are local areas defined on the same side of the silicon substrate 1 along its own thickness direction.

[0108] In some embodiments, both the collecting region 1c and the non-collecting region 1d can be local regions within the surface of the silicon substrate 1. Alternatively, both the collecting region 1c and the non-collecting region 1d can be local regions within the surface of the base region 1j. The local region within the surface of the silicon substrate 1 or the surface of the base region 1j where a tunneling passivation contact structure is deposited can be understood as the collecting region 1c.

[0109] In some embodiments, please refer to Figure 19 or Figure 20 As shown, since there can be a gap between the collection region 1c and the non-collection region 1d along the thickness direction of the photovoltaic cell 10 or the thickness direction of the silicon substrate 1, under this setting, the tunneling passivation contact structure or the doped polycrystalline silicon 5 is not likely to contact the active region 1a located on the side of the silicon substrate 1 away from the doped polycrystalline silicon 5. It can also be understood that the edge of the photovoltaic cell 10 is not likely to have a parasitic PN junction, and the edge of the photovoltaic cell 10 is not likely to have a leakage current path (an unexpected or abnormally designed current flow path). Therefore, the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large.

[0110] In some embodiments, please refer to Figure 19 or Figure 20 As shown, if the photovoltaic cell 10 is a sectional photovoltaic cell separated from an original whole photovoltaic cell, the edge of the silicon substrate 1 can have a cutting edge QB formed by a cutting process or a sectionalizing process. The cutting edge QB can be located on the side of the collection region 1c away from the non-collection region 1d. Due to the silicon substrate damage caused by cutting, there are relatively more lattice defects in and around the cutting edge QB. Correspondingly, there may be relatively more recombination centers in and around the cutting edge QB. Therefore, electrons collected in the doped polycrystalline silicon 5 are not easy to contact the lattice defects near the cutting edge QB, resulting in a relatively small recombination rate of the photovoltaic cell 10, thereby enabling the photovoltaic cell 10 to have a relatively large photoelectric conversion efficiency.

[0111] In some embodiments, please refer to Figure 19 As shown, the silicon substrate 1 may include a third step 13 and a fourth step 14. The third step 13 may include an intersecting third-stage top wall portion 131 and a third-stage side wall portion 132. The fourth step 14 may include an intersecting fourth-stage top wall portion 141 and a fourth-stage side wall portion 142. The end of the third-stage side wall portion 132 away from the third-stage top wall portion 131 intersects with the end of the fourth-stage top wall portion 141 away from the fourth-stage side wall portion 142. There may be a second height difference G2 between the third-stage top wall portion 131 and the fourth-stage top wall portion 141 along the thickness direction of the photovoltaic cell 10 or the thickness direction of the silicon substrate 1. The third-stage top wall portion 131 may be provided with a collection area 1c, and the fourth-stage top wall portion 141 may be provided with a non-collection area 1d, so as to satisfy the above-mentioned setting of "there is an interval distance between the collection area 1c and the non-collection area 1d along the thickness direction of the photovoltaic cell 10 or the thickness direction of the silicon substrate 1". Correspondingly, tunneling passivation contact structures may be deposited on the third-order top wall portion 131, while tunneling passivation contact structures may not be deposited on the fourth-order top wall portion 141.

[0112] In some embodiments, Figure 19The view shown can be one of the cross-sectional views of the photovoltaic cell 10. Without considering the vertical direction, the fourth step 14 is a lower step than the third step 13. The position of the top wall of the fourth step 141 can be lower than the position of the top wall of the third step 131. Correspondingly, the position of the non-collection area 1d can be lower than the position of the collection area 1c.

[0113] In some embodiments, Figure 20 The view shown can be one of the cross-sectional views of the photovoltaic cell 10. Without considering the vertical direction, the position of the non-collection area 1d can be higher than the position of the collection area 1c.

[0114] In some embodiments, please refer to Figure 19 As shown, the silicon substrate 1 may have a light-receiving side and a back-lighting side BG disposed opposite to each other in the thickness direction of the photovoltaic cell 10 or in the thickness direction of the silicon substrate 1. The light-receiving side refers to the side of the photovoltaic cell 10 that can be directly or primarily irradiated by sunlight. The third-order top wall portion 131, the collection area 1c, the third-order side wall portion 132, the fourth-order top wall portion 141, and the non-collection area 1d are all located on the back-lighting side BG of the silicon substrate 1.

[0115] In some embodiments, please refer to Figure 21 As shown, the silicon substrate 1 may have a light-receiving side SG and a back-lighting side disposed opposite to each other in the thickness direction of the photovoltaic cell 10 or in the thickness direction of the silicon substrate 1. The light-receiving side SG refers to the side of the photovoltaic cell 10 that can be directly or primarily irradiated by sunlight. The third-order top wall portion 131, the collection area 1c, the third-order side wall portion 132, the fourth-order top wall portion 141, and the non-collection area 1d are all located on the light-receiving side SG of the silicon substrate 1.

[0116] In some embodiments, please refer to Figure 19 or Figure 21 As shown, the silicon substrate 1 may include a third step 13 and a fourth step 14. Accordingly, the silicon substrate 1 may be provided with a collection region 1c and a non-collection region 1d.

[0117] In some embodiments, please refer to Figure 22 or Figure 23 As shown, the silicon substrate 1 may include two third steps 13 and two fourth steps 14. In the left-right direction, the two third steps 13 may be located between the two fourth steps 14. The two third steps 13 may have a common third-step top wall portion 131. Correspondingly, the silicon substrate 1 may be provided with a collection area 1c and two non-collection areas 1d. The collection area 1c may be located between the two non-collection areas 1d.

[0118] Please refer to Figure 22As shown, a third-order top wall portion 131, a collection region 1c, two third-order side wall portions 132, two fourth-order top wall portions 141, and two non-collection regions 1d can all be located on the backlight side BG of the silicon substrate 1.

[0119] Additionally, please refer to Figure 23 As shown, a third-order top wall portion 131, a collection region 1c, two third-order side wall portions 132, two fourth-order top wall portions 141, and two non-collection regions 1d can all be located on the light-receiving side SG of the silicon substrate 1.

[0120] In some embodiments, please refer to Figure 24 As shown, when the silicon substrate 1 has an active region 1a, a passive region 1b, a collection region 1c, and a non-collection region 1d, and when the active region 1a and the passive region 1b are both located on the light-receiving side SG of the silicon substrate 1, the collection region 1c and the non-collection region 1d can both be located on the backlight side BG of the silicon substrate 1. Correspondingly, the tunneling layer 4 and the doped polysilicon 5 can be located on the backlight side BG of the silicon substrate 1.

[0121] In some embodiments, please refer to Figure 25 As shown, when the silicon substrate 1 has an active region 1a, a passive region 1b, a collection region 1c, and a non-collection region 1d, and when the active region 1a and the passive region 1b are both located on the backlight side BG of the silicon substrate 1, the collection region 1c and the non-collection region 1d can both be located on the light-receiving side SG of the silicon substrate 1. Correspondingly, the tunneling layer 4 and the doped polysilicon 5 can be located on the light-receiving side SG of the silicon substrate 1.

[0122] In some embodiments, please refer to Figure 24 or Figure 25 As shown, the silicon substrate 1 may have a first side LC and a second side RC. The first side LC and the second side RC are arranged opposite to each other in a direction perpendicular to the thickness direction of the photovoltaic cell 10. Alternatively, the first side LC and the second side RC may be arranged opposite to each other in a left-right direction. The passive region 1b may be located on the second side RC relative to the active region 1a, and the non-collection region 1d may be located on the first side LC relative to the collection region 1c.

[0123] In some other embodiments (not shown in the figures), the passive region may be located on a first side relative to the active region, and the non-collection region may be located on a second side relative to the collection region.

[0124] In some other embodiments (not shown in the figures), the passive region may be located on the first side relative to the active region, and the non-collection region may also be located on the first side relative to the collection region.

[0125] In some other embodiments (not shown in the figures), the passive region may be located on the second side relative to the active region, and the non-collection region may also be located on the second side relative to the collection region.

[0126] In some embodiments, the second height difference G2 mentioned above can satisfy: 1µm≤G2≤10µm. Specifically, the second height difference G2 can be 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, or 10µm. If the second height difference G2 is too large, for example, greater than 10µm, the thickness of the portion near the fourth step 14 of the silicon substrate 1 will be relatively small, and the structural strength of the portion near the fourth step 14 of the silicon substrate 1 will be relatively weak. Under external forces, the portion near the fourth step 14 of the silicon substrate 1 is prone to structural damage problems such as cracks. If the second height difference G2 is too small, for example, less than 1µm, it indicates that the area of ​​the third-order sidewall portion 132 is relatively small. A relatively small third-order sidewall portion 132 is less likely to absorb sunlight reflected by the fourth-order top wall portion 141. In other words, the third-order sidewall portion 132 and the fourth-order top wall portion 141 are less likely to form a light-trapping structure, resulting in a relatively small number of electron-hole pairs generated within the silicon substrate 1, and a relatively low photoelectric conversion efficiency for the photovoltaic cell 10. Therefore, a second height difference G2 within the range of 1µm to 10µm is relatively better.

[0127] In some other embodiments, the second height difference G2 may also be in the range of 1µm to 5µm, wherein the second height difference G2 may specifically be 1µm, 1.5µm, 2µm, 2.5µm, 3µm, 3.5µm, 4µm, 4.5µm or 5µm.

[0128] In some other embodiments, the second height difference G2 may also be in the range of 5µm to 9µm, wherein the second height difference G2 may specifically be 5µm, 5.5µm, 6µm, 6.5µm, 7µm, 7.5µm, 8µm, 8.5µm or 9µm.

[0129] In some other embodiments, the second height difference G2 may also be in the range of 4µm to 8µm, wherein the second height difference G2 may specifically be 4µm, 4.5µm, 5µm, 5.5µm, 6µm, 6.5µm, 7µm, 7.5µm or 8µm.

[0130] In some embodiments, both the third-order top wall portion 131 and the fourth-order top wall portion 141 can be polished surfaces. The distance between the polished surfaces of the third-order top wall portion 131 and the fourth-order top wall portion 141 along the thickness direction of the photovoltaic cell 10 or the silicon substrate 1 can be a second height difference G2.

[0131] In some embodiments, the third-order top wall portion 131 may be a polished surface, and the fourth-order top wall portion 141 may have a light-trapping structure (not shown in the figure). The light-trapping structure of the fourth-order top wall portion 141 may include multiple upright pyramid structures or inverted pyramid structures. The shapes of the upright pyramid structures or inverted pyramid structures have been described above and will not be repeated here. Furthermore, the spacing between the polished surface of the third-order top wall portion 131 and the bottom of the fourth-order top wall portion 141 along the thickness direction of the photovoltaic cell 10 or the silicon substrate 1 may be a second height difference G2.

[0132] In some embodiments, please refer to Figure 26 As shown, the third-order top wall portion 131 and the third-order side wall portion 132 may have an included angle γ, satisfying 90 degrees (°) ≤ γ ≤ 150 degrees (°).

[0133] In some embodiments, please refer to Figure 26 As shown, when the included angle γ is equal to 90°, the third-order top wall portion 131 is perpendicular to the third-order side wall portion 132.

[0134] In some embodiments, please refer to Figure 26 As shown, when the included angle γ is greater than 90° and when the included angle γ is less than or equal to 150°, the third-order sidewall portion 132 is inclined relative to the third-order top wall portion 131. This arrangement can, on the one hand, make the stress concentration at the connection between the third-order top wall portion 131 and the third-order sidewall portion 132 relatively small. Under the action of external force, structural damage problems such as cracks are not likely to occur at and near the connection between the third-order top wall portion 131 and the third-order sidewall portion 132. On the other hand, this arrangement can also make the passivation layer deposited at the connection between the third-order top wall portion 131 and the third-order sidewall portion 132 relatively uniform, and the passivation effect of the passivation layer at the connection between the third-order top wall portion 131 and the third-order sidewall portion 132 is relatively good.

[0135] In some other embodiments, the included angle γ may also be in the range of 100° to 120°, wherein the included angle γ can specifically be 100°, 101°, 102°, 103°, 104°, 105°, 106°, 107°, 108°, 109°, 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119° or 120°.

[0136] In some other embodiments, the included angle γ may also be in the range of 130° to 150°, wherein the included angle γ can specifically be 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139°, 140°, 141°, 142°, 143°, 144°, 145°, 146°, 147°, 148°, 149° or 150°.

[0137] In some other embodiments, the included angle γ may also be in the range of 110° to 140°, wherein the included angle γ can specifically be 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119°, 120°, 121°, 122°, 123°, 124°, 125°, 126°, 127°, 128°, 129°, 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139° or 140°.

[0138] In some embodiments, please refer to Figure 26 As shown, the third-order sidewall portion 132 and the fourth-order topwall portion 141 can have an included angle δ, satisfying 90°≤δ≤150°.

[0139] In some embodiments, please refer to Figure 26 As shown, when the included angle δ is equal to 90°, the third-order sidewall portion 132 is perpendicular to the fourth-order topwall portion 141.

[0140] In some embodiments, please refer to Figure 26 As shown, when the included angle δ is greater than 90°, and when the included angle δ is less than or equal to 150°, the third-order sidewall portion 132 is inclined relative to the fourth-order top wall portion 141. This arrangement, on the one hand, makes the passivation layer deposited at the connection between the third-order sidewall portion 132 and the fourth-order top wall portion 141 relatively uniform, and the passivation effect of the passivation layer at the connection between the third-order sidewall portion 132 and the fourth-order top wall portion 141 is relatively good. On the other hand, this arrangement also makes the third-order sidewall portion 132 relatively inclined relative to the fourth-order top wall portion 141. The slope is relatively steep, and sunlight reflected by the fourth-order top wall 141 can more easily reach the third-order side wall 132. Similarly, sunlight reflected by the third-order side wall 132 can more easily reach the fourth-order top wall 141. It can also be understood that the third-order side wall 132 and the fourth-order top wall 141 form a good light-trapping structure, so that the light reflectivity of the silicon substrate 1 is relatively low, so that the number of electron-hole pairs generated by the silicon substrate 1 is relatively large, and the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large.

[0141] In some other embodiments, the included angle δ can also be in the range of 100° to 120°, wherein the included angle δ can specifically be 100°, 101°, 102°, 103°, 104°, 105°, 106°, 107°, 108°, 109°, 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119° or 120°.

[0142] In some other embodiments, the included angle δ can also be in the range of 130° to 150°, wherein the included angle δ can specifically be 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139°, 140°, 141°, 142°, 143°, 144°, 145°, 146°, 147°, 148°, 149° or 150°.

[0143] In some other embodiments, the included angle δ can also be in the range of 110° to 140°, wherein the included angle δ can specifically be 110°, 111°, 112°, 113°, 114°, 115°, 116°, 117°, 118°, 119°, 120°, 121°, 122°, 123°, 124°, 125°, 126°, 127°, 128°, 129°, 130°, 131°, 132°, 133°, 134°, 135°, 136°, 137°, 138°, 139° or 140°.

[0144] In some embodiments, when the included angle γ is greater than 90° and when the included angle γ is less than 150°, and when the included angle δ is greater than 90° and when the included angle δ is less than 150°, the structures of the third step 13 and the fourth step 14 of the silicon substrate 1 can also be as follows: Figure 27 As shown, under this configuration, the light-trapping structure composed of the third-order sidewall portion 132 and the fourth-order top wall portion 141 has a better light-trapping effect, a lower light reflectivity, a relatively large number of electron-hole pairs generated by the silicon substrate 1, and a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0145] In some embodiments, when the included angle γ is greater than 90° and when the included angle γ is less than 150°, and when the included angle δ is greater than 90° and when the included angle δ is less than 150°, the structures of the third step 13 and the fourth step 14 of the silicon substrate 1 can also be as follows: Figure 28 As shown, under this configuration, the passivation layers deposited at the connection between the third-order top wall portion 131 and the third-order side wall portion 132, the connection between the third-order side wall portion 132 and the fourth-order top wall portion 141, and the connection between the fourth-order top wall portion 141 and the fourth-order side wall portion 142 are relatively uniform, and the passivation effect is relatively good.

[0146] In some embodiments, please refer to Figure 26 As shown, the third-order sidewall portion 132 can have a second width W2, satisfying 1µm≤W2≤100µm. Specifically, the second width W2 can be 1µm, 5µm, 10µm, 20µm, 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, or 100µm. When the second width W2 is less than 1µm, it can be understood that the third-order sidewall portion 132 is nearly perpendicular to the third-order top wall portion 131. The passivation layer deposited at the junction between the third-order top wall portion 131 and the third-order sidewall portion 132 is prone to uneven deposition, meaning the passivation effect at this location is relatively poor. When the second width W2 is greater than 100µm, the third-order sidewall 132 is too flat, and sunlight reflected by the fourth-order top wall 141 is unlikely to re-irradiate the third-order sidewall 132. Similarly, sunlight reflected by the third-order sidewall 132 is also unlikely to re-irradiate the fourth-order top wall 141. The light reflectivity of the silicon substrate 1 is relatively high, and the number of electron-hole pairs generated by the silicon substrate 1 is relatively small. Therefore, when the second width W2 is in the range of 1µm to 100µm, the photoelectric conversion efficiency of the photovoltaic cell 10 can be relatively high.

[0147] In some other embodiments, the second width W2 can be in the range of 1µm to 10µm, wherein the second width W2 can specifically be 1µm, 2µm, 3µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm or 10µm.

[0148] In some other embodiments, the second width W2 can be in the range of 10µm to 50µm, wherein the second width W2 can specifically be 10µm, 11µm, 12µm, 13µm, 14µm, 15µm, 16µm, 17µm, 18µm, 19µm, 20µm, 21µm, 22µm, 23µm, 24µm, 25µm, 26µm, 27µm, 28µm, 29µm, 30µm, 31µm, 32µm, 33µm, 34µm, 35µm, 36µm, 37µm, 38µm, 39µm, 40µm, 41µm, 42µm, 43µm, 44µm, 45µm, 46µm, 47µm, 48µm, 49µm or 50µm.

[0149] In some other embodiments, the second width W2 can be in the range of 50µm to 90µm, wherein the second width W2 can specifically be 50µm, 51µm, 52µm, 53µm, 54µm, 55µm, 56µm, 57µm, 58µm, 59µm, 60µm, 61µm, 62µm, 63µm, 64µm, 65µm, 66µm, 67µm, 68µm, 69µm, 70µm, 71µm, 72µm, 73µm, 74µm, 75µm, 76µm, 77µm, 78µm, 79µm, 80µm, 81µm, 82µm, 83µm, 84µm, 85µm, 86µm, 87µm, 88µm, 89µm or 90µm.

[0150] In some other embodiments, the second width W2 can be in the range of 30µm to 70µm, wherein the second width W2 can specifically be 30µm, 31µm, 32µm, 33µm, 34µm, 35µm, 36µm, 37µm, 38µm, 39µm, 40µm, 41µm, 42µm, 43µm, 44µm, 45µm, 46µm, 47µm, 48µm, 49µm, 50µm, 51µm, 52µm, 53µm, 54µm, 55µm, 56µm, 57µm, 58µm, 59µm, 60µm, 61µm, 62µm, 63µm, 64µm, 65µm, 66µm, 67µm, 68µm, 69µm, or 70µm.

[0151] In some embodiments, please refer to Figure 29 or Figure 30 As shown, the photovoltaic cell 10 may further include a second edge passivation layer 6. The second edge passivation layer 6 may include a fourth passivation portion 61 and a fifth passivation portion 62 connected together. The fourth passivation portion 61 may be deposited on the edge of the silicon substrate 1 (e.g., the diced edge QB mentioned above), and at least a portion of the structure of the fifth passivation portion 62 may be deposited on one side of the non-collection region 1d. The extension direction of the fourth passivation portion 61 and the extension direction of the fifth passivation portion 62 may intersect. In this configuration, the passivation effect of the second edge passivation layer 6 can reduce the recombination rate of electrons and holes in the non-collection region 1d, the diced edge QB, and the areas near them of the silicon substrate 1, resulting in a relatively long minority carrier lifetime and thus a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0152] In some embodiments, please refer to Figure 29As shown, when the fourth-order sidewall portion 142 is one of the edges of the silicon substrate 1, or when the fourth-order sidewall portion 142 is the diced edge QB of the silicon substrate 1, the fourth passivation portion 61 can be deposited on the fourth-order sidewall portion 142, and the fourth passivation portion 61 can provide passivation for the fourth-order sidewall portion 142. When the fourth-order top wall portion 141 is provided with a non-collection region 1d, at least a portion of the structure of the fifth passivation portion 62 can be located on one side of the fourth-order top wall portion 141, and the fifth passivation portion 62 can provide passivation for both the fourth-order top wall portion 141 and the non-collection region 1d.

[0153] In some embodiments, please refer to Figure 29 As shown, the photovoltaic cell 10 may further include a second passivation layer 7. At least a portion of the structure of the second passivation layer 7 may be deposited on the fourth-order top wall portion 141, and the structure deposited on the fourth-order top wall portion 141 within the second passivation layer 7 may be covered by a fifth passivation portion 62. In this configuration, on the one hand, the fifth passivation portion 62 and the second passivation layer 7 together provide passivation for the non-collection region 1d, reducing the recombination rate of electrons and holes in and around the non-collection region 1d, thereby increasing the photoelectric conversion efficiency of the photovoltaic cell 10. On the other hand, the thickness of the edges and surrounding portions of the photovoltaic cell 10 is relatively large, resulting in relatively high structural strength. Under external forces, the edges and surrounding portions of the photovoltaic cell 10 are less prone to structural damage such as cracks.

[0154] In some embodiments, please refer to Figure 29 As shown, the refractive index of the fifth passivation layer 62 can be less than that of the second passivation layer 7. With this configuration, the photovoltaic cell 10 can have the advantage of relatively low light reflectivity, and the number of electron-hole pairs that can be generated within the silicon substrate 1 is relatively large, thereby resulting in a relatively high photoelectric conversion efficiency for the photovoltaic cell 10.

[0155] In some embodiments, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be in the range of 0.75 to 0.95. Specifically, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be 0.75, 0.76, 0.77, 0.78, 0.79, 0.8, 0.81, 0.82, 0.83, 0.84, 0.85, 0.86, 0.87, 0.88, 0.89, 0.9, 0.91, 0.92, 0.93, 0.94, or 0.95. Under this configuration, the difference between the refractive index of the fifth passivation portion 62 and the refractive index of the second passivation layer 7 is relatively small, and the stacked structure formed by the second passivation layer 7 and the fifth passivation portion 62 can have a good anti-reflection effect, thereby resulting in a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0156] In some other embodiments, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be in the range of 0.75 to 0.85. Specifically, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be 0.75, 0.76, 0.77, 0.78, 0.79, 0.8, 0.81, 0.82, 0.83, 0.84, or 0.85.

[0157] In some other embodiments, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be in the range of 0.85 to 0.95. Specifically, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be 0.85, 0.86, 0.87, 0.88, 0.89, 0.9, 0.91, 0.92, 0.93, 0.94, or 0.95.

[0158] In other embodiments, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be in the range of 0.8 to 0.9. Specifically, the ratio of the refractive index of the fifth passivation portion 62 to the refractive index of the second passivation layer 7 can be 0.8, 0.81, 0.82, 0.83, 0.84, 0.85, 0.86, 0.87, 0.88, 0.89, or 0.9.

[0159] In some embodiments, the refractive index of the fifth passivation portion 62 may be in the range of 1.4 to 1.6. Specifically, the refractive index of the fifth passivation portion 62 may be 1.4, 1.45, 1.5, 1.55, or 1.6.

[0160] In some embodiments, the refractive index of the second passivation layer 7 can be in the range of 1.7 to 2. Specifically, the refractive index of the second passivation layer 7 can be 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 2.

[0161] In some embodiments, please refer to Figure 29 As shown, the second passivation layer 7 can also be deposited on the third-order sidewall portion 132 and the third-order top wall portion 131. The fifth passivation portion 62 extends from one side of the fourth-order top wall portion 141 to one side of the third-order top wall portion 131, and the portion of the structure deposited in the third-order top wall portion 131 within the second passivation layer 7 is partially covered by the fifth passivation portion 62. Under this configuration, on the one hand, the passivation effect of the stacked structure formed by the fifth passivation portion 62 and the second passivation layer 7 is better and the passivation range is larger, so that the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large. On the other hand, the thickness of the edge and nearby portion of the photovoltaic cell 10 is greater, and the structural strength of the edge and nearby portion of the photovoltaic cell 10 is greater. Under the action of external force, the edge and nearby portion of the photovoltaic cell 10 is less prone to structural damage problems such as cracks.

[0162] In some embodiments, please refer to Figure 29 As shown, the fifth passivation portion 62 may include a seventh segment 621, an eighth segment 622, and a ninth segment 623. The second passivation layer 7 may include a tenth segment 71, an eleventh segment 72, and a twelfth segment 73. The tenth segment 71 may be deposited on the fourth-order top wall portion 141, the eleventh segment 72 may be deposited on the third-order side wall portion 132, the twelfth segment 73 may be deposited on the third-order top wall portion 131, the seventh segment 621 may be deposited on the tenth segment 71, the eighth segment 622 may be deposited on the eleventh segment 72, and the ninth segment 623 may be deposited on the local structure of the twelfth segment 73.

[0163] In some other embodiments (not shown in the figures), the fifth passivation portion may be deposited primarily on the side without a collection area or on the side of the fourth-order top wall portion.

[0164] In some embodiments, please refer to Figure 29 As shown, the deposition thickness DH2 of the fifth passivation layer 62 can be greater than the deposition thickness SH2 of the second passivation layer 7. Under this configuration, the fifth passivation layer 62 can provide a relatively strong field passivation effect to reduce the recombination rate of electrons and holes at and near the edge of the photovoltaic cell 10, thereby resulting in a relatively high photoelectric conversion efficiency of the photovoltaic cell 10.

[0165] The deposition thickness can refer to the thickness in the direction perpendicular to the surface being deposited.

[0166] In some embodiments, please refer to Figure 29 As shown, the ratio of the deposition thickness DH2 of the fifth passivation layer 62 to the deposition thickness SH2 of the second passivation layer 7 can be in the range of 1.1 to 2. Specifically, the ratio of the deposition thickness DH2 of the fifth passivation layer 62 to the deposition thickness SH2 of the second passivation layer 7 can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.

[0167] In other embodiments, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be in the range of 1.1 to 1.5. Specifically, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, or 1.5.

[0168] In other embodiments, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be in the range of 1.5 to 2. Specifically, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, or 2.

[0169] In other embodiments, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be in the range of 1.4 to 1.8. Specifically, the ratio of the deposition thickness DH2 of the fifth passivation portion 62 to the deposition thickness SH2 of the second passivation layer 7 can be 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, or 1.8.

[0170] In some embodiments, please refer to Figure 29 As shown, the deposition thickness DH2 of the fifth passivation section 62 can be in the range of 100nm to 150nm. Specifically, the deposition thickness DH2 can be 100nm, 110nm, 120nm, 130nm, 140nm, or 150nm.

[0171] In some other embodiments, the deposition thickness DH2 of the fifth passivation portion 62 may also be in the range of 100nm to 130nm. Specifically, the deposition thickness DH2 may be 100nm, 105nm, 110nm, 115nm, 120nm, 125nm, or 130nm.

[0172] In other embodiments, the deposition thickness DH2 of the fifth passivation portion 62 may also be in the range of 120nm to 150nm. Specifically, the deposition thickness DH2 may be 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, or 150nm.

[0173] In some other embodiments, the deposition thickness DH2 of the fifth passivation portion 62 may also be in the range of 110nm to 140nm. Specifically, the deposition thickness DH2 may be 110nm, 115nm, 120nm, 125nm, 130nm, 135nm, or 140nm.

[0174] In some embodiments, please refer to Figure 29 As shown, the deposition thickness SH2 of the second passivation layer 7 can be in the range of 70nm to 90nm. Specifically, the deposition thickness SH2 can be 70nm, 75nm, 80nm, 85nm, or 90nm.

[0175] In some embodiments, the second edge passivation layer 6 may include at least one of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0176] In some embodiments, the second edge passivation layer 6 may be a single passivation layer.

[0177] In some embodiments, the second edge passivation layer 6 may include at least two passivation layers. For example, the second edge passivation layer 6 may be composed of a silicon oxide layer and an aluminum oxide layer, with the silicon oxide layer closer to the silicon substrate 1 than the aluminum oxide layer. Alternatively, the second edge passivation layer 6 may be composed of an aluminum oxide layer and a silicon nitride layer, with the aluminum oxide layer closer to the silicon substrate 1 than the silicon nitride layer. Or, the second edge passivation layer 6 may be composed of a silicon oxide layer, an aluminum oxide layer, and a silicon nitride layer, with the silicon oxide layer closer to the silicon substrate 1 than the aluminum oxide layer and the silicon nitride layer, and the aluminum oxide layer located between the silicon oxide layer and the silicon nitride layer.

[0178] In some embodiments, the second passivation layer 7 may include at least one of a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0179] In some embodiments, the second passivation layer 7 may be a single passivation layer.

[0180] In some embodiments, the second passivation layer 7 may include at least two passivation layers. For example, the second passivation layer 7 may be composed of an aluminum oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0181] In some embodiments, please refer to Figure 31 As shown, the second edge passivation layer 6 may further include a sixth passivation portion 63. The end of the fourth passivation portion 61 away from the fifth passivation portion 62 is connected to the sixth passivation portion 63. The sixth passivation portion 63 may be deposited on the side of the silicon substrate 1 away from the fourth-order top wall portion 141 or the non-collection region 1d. The extension direction of the sixth passivation portion 63 intersects with the extension direction of the fourth passivation portion 61. Under this configuration, on the one hand, the thickness of the edge and nearby portion of the photovoltaic cell 10 is relatively large, and the structural strength of the edge and nearby portion of the photovoltaic cell 10 is greater. Under external force, the edge and nearby portion of the photovoltaic cell 10 is less prone to structural damage problems such as cracks. On the other hand, the sixth passivation portion 63 may also provide field passivation on the side of the silicon substrate 1 away from the fourth-order top wall portion 141 or the non-collection region 1d, so that the photoelectric conversion efficiency of the photovoltaic cell 10 is relatively large.

[0182] In some embodiments, please refer to Figure 31As shown, the deposition width SW2 of the sixth passivation portion 63 can be smaller than the deposition width LW2 of the fifth passivation portion 62. It can also be understood that the deposition width SW2 of the sixth passivation portion 63 is relatively small, and the pad (part of the structure of the metal electrode) located on the side of the silicon substrate 1 away from the fifth passivation portion 62 and close to the edge of the silicon substrate 1 is not easily covered by the sixth passivation portion 63, so that the pad can be well soldered to the solder ribbon in the future, thereby forming a good battery string.

[0183] The deposition width can be the dimension along the direction perpendicular to the thickness of the photovoltaic cell 10.

[0184] In some embodiments, please refer to Figure 31 As shown, the ratio of the deposition width SW2 of the sixth passivation section 63 to the deposition width LW2 of the fifth passivation section 62 can be in the range of 0.5 to 0.9, wherein the ratio can specifically be 0.5, 0.6, 0.7, 0.8 or 0.9.

[0185] In some other embodiments, the ratio of the deposition width SW2 of the sixth passivation portion 63 to the deposition width LW2 of the fifth passivation portion 62 can be in the range of 0.5 to 0.7, wherein the ratio can specifically be 0.5, 0.55, 0.6, 0.65 or 0.7.

[0186] In some other embodiments, the ratio of the deposition width SW2 of the sixth passivation portion 63 to the deposition width LW2 of the fifth passivation portion 62 can be in the range of 0.7 to 0.9, wherein the ratio can specifically be 0.7, 0.75, 0.8, 0.85 or 0.9.

[0187] In some other embodiments, the ratio of the deposition width SW2 of the sixth passivation portion 63 to the deposition width LW2 of the fifth passivation portion 62 can be in the range of 0.6 to 0.8, wherein the ratio can specifically be 0.6, 0.65, 0.7, 0.75 or 0.8.

[0188] In some embodiments, please refer to Figure 31 As shown, the photovoltaic cell 10 may also include the first passivation layer 3 mentioned above. The first passivation layer 3 may be disposed on the active region 1a of the silicon substrate 1. The local structure of the first passivation layer 3 may be covered by the sixth passivation part 63.

[0189] In some embodiments, please refer to Figures 32-38As shown, the photovoltaic cell 10 may also include an electrode 8, which may also be referred to as a grid line. The electrode 8 may include a first electrode 81 and a second electrode 82, which may be disposed opposite to each other in the thickness direction of the photovoltaic cell 10 or the thickness direction of the silicon substrate 1. The first electrode 81 may be electrically contacted with the active region 1a (also referred to as a metallized contact or an ohmic contact), and the second electrode 82 may be electrically contacted with the doped polycrystalline silicon 5. If the silicon substrate 1 is doped with an N-type element, i.e., the silicon substrate 1 is an N-type silicon substrate, the active region 1a is doped with a P-type element, and the doped polycrystalline silicon 5 is doped with an N-type element, i.e., the doped polycrystalline silicon 5 is an N-type doped polycrystalline silicon, then the first electrode 81 electrically contacting the active region 1a may serve as a positive electrode, and the second electrode 82 electrically contacting the doped polycrystalline silicon 5 may serve as a negative electrode.

[0190] In some other embodiments, if the silicon substrate 1 is doped with a P-type element, that is, the silicon substrate 1 is a P-type silicon substrate, the active region 1a is doped with an N-type element, and the doped polysilicon 5 is doped with a P-type element, that is, the doped polysilicon 5 is a P-type doped polysilicon, then the first electrode 81 electrically contacting the active region 1a can be used as a negative electrode, and the second electrode 82 electrically contacting the doped polysilicon 5 can be used as a positive electrode.

[0191] Secondly, this application provides some embodiments of photovoltaic modules. A photovoltaic module may include a battery string, and the battery string may include at least two electrically connected photovoltaic cells. The photovoltaic cells may adopt the embodiments of photovoltaic cells provided in the first aspect of this application. The photovoltaic module may have the advantage of relatively large output power.

[0192] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A photovoltaic cell, characterized in that, The photovoltaic cell (10) includes: A silicon substrate (1) includes a third step (13) and a fourth step (14). The third step (13) includes a third-order top wall portion (131) and a third-order side wall portion (132). The fourth step (14) includes a fourth-order top wall portion (141) and a fourth-order side wall portion (142). There is a second height difference between the third-order top wall portion (131) and the fourth-order top wall portion (141) along the thickness direction of the silicon substrate (1). A tunneling passivation contact structure is disposed on the third-order top wall portion (131); The second edge passivation layer (6) includes a fourth passivation portion (61), a fifth passivation portion (62) and a sixth passivation portion (63). The fourth passivation portion (61) is disposed on the fourth-order sidewall portion (142), at least a portion of the structure of the fifth passivation portion (62) is disposed on the fourth-order top wall portion (141), and the sixth passivation portion (63) is disposed on the side of the silicon substrate (1) opposite to the fourth-order top wall portion (141).

2. The photovoltaic cell according to claim 1, characterized in that, The fifth passivation section (62) includes a seventh segment (621) and an eighth segment (622). The seventh segment (621) is disposed on the fourth-order top wall section (141), and the eighth segment (622) is disposed on the third-order side wall section (132).

3. The photovoltaic cell according to claim 2, characterized in that, The fifth passivation section (62) further includes a ninth segment (623), which is disposed on the tunneling passivation contact structure.

4. The photovoltaic cell according to claim 3, characterized in that, The photovoltaic cell (10) further includes a second passivation layer (7), which includes a tenth segment (71), an eleventh segment (72) and a twelfth segment (73). The tenth segment (71) is located between the fourth-order top wall portion (141) and the seventh segment (621). The eleventh segment (72) is located between the third-order side wall portion (132) and the eighth segment (622). The twelfth segment (73) is disposed on the tunneling passivation contact structure, and a portion of the twelfth segment (73) is covered by the ninth segment (623).

5. The photovoltaic cell according to claim 4, characterized in that, The thickness of the fifth passivation portion (62) is greater than the thickness of the second passivation layer (7).

6. The photovoltaic cell according to claim 5, characterized in that, The ratio of the thickness of the fifth passivation portion (62) to the thickness of the second passivation layer (7) is 1.1 to 2.

7. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The width of the sixth passivation portion (63) is smaller than the width of the fifth passivation portion (62).

8. The photovoltaic cell according to claim 7, characterized in that, The ratio of the width of the sixth passivation portion (63) to the width of the fifth passivation portion (62) is 0.5 to 0.

95.

9. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The photovoltaic cell (10) further includes a first passivation layer (3), the silicon substrate (1) is located between the first passivation layer (3) and the tunneling passivation contact structure, and the sixth passivation part (63) is provided on a local structure of the first passivation layer (3).

10. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The sixth passivation part (63) is disposed on the light-receiving side (SG) of the silicon substrate (1), and the fifth passivation part (62) is disposed on the backlight side (BG) of the silicon substrate (1).

11. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The second height difference is 1 micrometer to 10 micrometers.

12. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The angle between the third-order top wall portion (131) and the third-order side wall portion (132) is 90 degrees to 150 degrees.

13. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The angle between the third-order sidewall portion (132) and the fourth-order top wall portion (141) is 90 degrees to 150 degrees.

14. The photovoltaic cell according to any one of claims 1 to 6, characterized in that, The silicon substrate (1) includes a first step (11) and a second step (12). The first step (11) includes a first-order top wall portion (111) and a first-order side wall portion (112). The second step (12) includes a second-order top wall portion (121) and a second-order side wall portion (122). There is a first height difference between the first-order top wall portion (111) and the second-order top wall portion (121) along the thickness direction of the silicon substrate (1). The first-order top wall portion (111) and the third-order top wall portion (131) are disposed opposite to each other in the thickness direction of the silicon substrate (1). The silicon substrate (1) includes a PN junction disposed on the first-order top wall portion (111).

15. The photovoltaic cell according to claim 14, characterized in that, The photovoltaic cell (10) further includes a first edge passivation layer (2), which is disposed opposite to the second edge passivation layer (6). The first edge passivation layer (2) includes a first passivation portion (21) and a second passivation portion (22). The first passivation portion (21) is disposed on the second-order sidewall portion (122), and at least a portion of the structure of the second passivation portion (22) is disposed on the second-order top wall portion (121).

16. The photovoltaic cell according to claim 15, characterized in that, The first edge passivation layer (2) further includes a third passivation portion (23), which is disposed on the side of the silicon substrate (1) away from the second-order top wall portion (121).

17. The photovoltaic cell according to claim 15, characterized in that, The second passivation portion (22) includes a first segment (221), a second segment (222) and a third segment (223). The first segment (221) is disposed on the top wall portion (121) of the second step, the second segment (222) is disposed on the side wall portion (112) of the first step, and the third segment (223) is disposed on the top wall portion (111) of the first step.

18. A photovoltaic module, characterized in that, The photovoltaic module includes a battery string, the battery string including at least two electrically connected photovoltaic cells, the photovoltaic cells being the photovoltaic cells (10) of any one of claims 1 to 17.

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