Topcon cell, preparation method and stacked cell

Abstract

This invention discloses a TOPCon cell, its fabrication method, and a tandem cell, relating to the field of photovoltaic technology. The TOPCon cell includes: a silicon substrate; a first tunneling oxide layer located on a first surface; a P-type doped polycrystalline silicon layer located on the side of the first tunneling oxide layer away from the silicon substrate; the P-type doped polycrystalline silicon layer includes a gallium-doped polycrystalline silicon layer and a doped polycrystalline silicon layer stacked sequentially, wherein the doping element of the doped polycrystalline silicon layer includes at least boron, and the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, and the doping concentration of the doped polycrystalline silicon layer gradually increases; a second tunneling oxide layer located on a second surface; and an N-type doped polycrystalline silicon layer located on the side of the second tunneling oxide layer away from the silicon substrate, thereby avoiding light-induced degradation caused by boron segregation, ensuring the passivation effect of the first tunneling oxide layer, improving the field passivation capability of the P-type doped polycrystalline silicon layer, and improving the conversion efficiency of the cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, specifically to a TOPCon cell, its preparation method, and a tandem cell. Background Technology

[0002] In related technologies, the front side of the silicon substrate of TOPCon cells is formed by boron diffusion and laser SE (selective emitter) doping to form a boron diffused emitter. However, the metal electrode on the front side is in direct contact with the silicon substrate, resulting in severe interface recombination and poor passivation effect on the front side.

[0003] To improve the passivation effect on the front side, related technologies involve depositing a tunneling oxide layer and a boron-doped polycrystalline silicon layer on the front side of the silicon substrate. However, boron tends to segregate towards the interface of the tunneling oxide layer and readily combines with oxygen at the interface to form BO complexes, inducing LID (light-induced degradation) and simultaneously compromising the passivation effect of the tunneling oxide layer. Furthermore, the boron-doped polycrystalline silicon layer exhibits weak field passivation capability, reducing the open-circuit voltage and conversion efficiency of the battery. Summary of the Invention

[0004] This invention discloses a TOPCon cell, its fabrication method, and a tandem cell to solve the problems of photo-induced degradation caused by boron segregation in the tunneling oxide layer, damage to the passivation effect of the tunneling oxide layer, and weak field passivation capability of the boron-doped polycrystalline silicon layer.

[0005] In a first aspect, the present invention discloses a TOPCon battery, comprising: a silicon substrate having a first surface and a second surface disposed opposite to each other; a first tunneling oxide layer located on the first surface; a P-type doped polycrystalline silicon layer located on the side of the first tunneling oxide layer away from the silicon substrate; the P-type doped polycrystalline silicon layer comprising a gallium-doped polycrystalline silicon layer and a doped polycrystalline silicon layer stacked sequentially, wherein the doping element of the doped polycrystalline silicon layer includes at least boron, and the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, and the doping concentration of the doped polycrystalline silicon layer gradually increases; a second tunneling oxide layer located on the second surface; an N-type doped polycrystalline silicon layer located on the side of the second tunneling oxide layer away from the silicon substrate; a first electrode in contact with the P-type doped polycrystalline silicon layer; and a second electrode in contact with the N-type doped polycrystalline silicon layer.

[0006] In some embodiments of the present invention, the doped polycrystalline silicon layer includes at least one of a boron-doped polycrystalline silicon layer and a gallium-boron-doped polycrystalline silicon layer.

[0007] In some embodiments of the present invention, the doped polysilicon layer includes a plurality of doped polysilicon sub-layers stacked sequentially, and the doping element of each doped polysilicon sub-layer includes at least boron; in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the plurality of doped polysilicon sub-layers increases sequentially.

[0008] In some embodiments of the present invention, the gallium-doped polysilicon layer includes a plurality of gallium-doped polysilicon sub-layers stacked sequentially; in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the plurality of gallium-doped polysilicon sub-layers increases sequentially.

[0009] In some embodiments of the present invention, the thickness of the plurality of doped polysilicon sub-layers increases sequentially in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, and / or the thickness of the plurality of gallium-doped polysilicon sub-layers increases sequentially.

[0010] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ; and / or, the gallium-doped polysilicon layer comprises a first gallium-doped polysilicon sublayer and a second gallium-doped polysilicon sublayer stacked sequentially, wherein the doping concentration of the first gallium-doped polysilicon sublayer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .

[0011] In some embodiments of the present invention, the doping concentration of the doped polysilicon layer is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 ; and / or, the doped polycrystalline silicon layer comprises a first doped polycrystalline silicon sublayer, a second doped polycrystalline silicon sublayer, and a third doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first doped polycrystalline silicon sublayer is 1×10⁻⁶. 18 cm -3 ~5×10 18 cm -3 The doping concentration of the second doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3The doping concentration of the third doped polycrystalline silicon sublayer is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 .

[0012] In some embodiments of the present invention, the TOPCon cell further includes an intrinsic polycrystalline silicon layer located between the first tunneling oxide layer and the P-type doped polycrystalline silicon layer.

[0013] In some embodiments of the present invention, the TOPCon cell further includes: a first passivation layer located on the side of the P-type doped polysilicon layer away from the first tunneling oxide layer, wherein the first electrode penetrates the first passivation layer and the doped polysilicon layer and contacts the gallium-doped polysilicon layer; and a second passivation layer located on the side of the N-type doped polysilicon layer away from the second tunneling oxide layer, wherein the second electrode penetrates the second passivation layer and contacts the N-type doped polysilicon layer.

[0014] In some embodiments of the present invention, the first surface includes alternating first metallized regions and first non-metallized regions, and the first tunneling oxide layer is located in the first metallized region; the second surface includes alternating second metallized regions and second non-metallized regions, and the second tunneling oxide layer is located in the second metallized region; the silicon substrate includes a P-type diffusion region located in the first non-metallized region, and the doping concentration of the P-type diffusion region is less than the doping concentration of the P-type doped polycrystalline silicon layer.

[0015] In a second aspect, the present invention discloses a method for fabricating a TOPCon battery, comprising: providing a silicon substrate having a first surface and a second surface disposed opposite to each other; sequentially stacking a first tunneling oxide layer and a P-type doped polycrystalline silicon layer on the first surface; the P-type doped polycrystalline silicon layer comprising a gallium-doped polycrystalline silicon layer and a doped polycrystalline silicon layer sequentially stacked, wherein the doping element of the doped polycrystalline silicon layer includes at least boron, and the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, and the doping concentration of the doped polycrystalline silicon layer gradually increases; sequentially stacking a second tunneling oxide layer and an N-type doped polycrystalline silicon layer on the second surface; forming a first electrode and a second electrode, wherein the first electrode is in contact with the P-type doped polycrystalline silicon layer, and the second electrode is in contact with the N-type doped polycrystalline silicon layer.

[0016] In some embodiments of the present invention, during the formation of the gallium-doped polycrystalline silicon layer, silane, a gallium source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 5 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500Pa to 50000Pa, and the radio frequency power is 1000W to 30000W.

[0017] In some embodiments of the present invention, during the formation of the boron-doped polycrystalline silicon layer, silane, a boron source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 10 sccm to 300 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500Pa to 50000Pa, and the radio frequency power is 1000W to 30000W.

[0018] Thirdly, the present invention discloses a stacked battery, comprising a bottom battery and a top battery stacked together, wherein the bottom battery comprises the TOPCon battery as described in the first aspect above.

[0019] This invention discloses a TOPCon battery and its fabrication method, as well as a tandem battery. The P-type doped polycrystalline silicon layer includes a gallium-doped polycrystalline silicon layer and a doped polycrystalline silicon layer stacked sequentially. The doping element of the doped polycrystalline silicon layer includes at least boron. Specifically, the gallium-doped polycrystalline silicon layer is positioned between the first tunneling oxide layer and the doped polycrystalline silicon layer to prevent boron segregation into the first tunneling oxide layer, reduce BO recombination defects, avoid light-induced degradation, and ensure the passivation effect of the first tunneling oxide layer, thereby improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases, and the doping concentration of the doped polycrystalline silicon layer gradually increases, improving carrier extraction, enhancing the field passivation capability of the P-type doped polycrystalline silicon layer, and further improving the open-circuit voltage and conversion efficiency of the battery. The first electrode is in contact with the P-type doped polycrystalline silicon layer but not in direct contact with the silicon substrate, improving the passivation effect and further improving the conversion efficiency of the battery. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0021] Figure 1 This is a schematic diagram of the first cross-sectional structure of a TOPCon battery disclosed in an embodiment of the present invention.

[0022] Figure 2This is a schematic diagram of the second cross-sectional structure of a TOPCon battery disclosed in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the third cross-sectional structure of a TOPCon battery disclosed in an embodiment of the present invention.

[0024] Figure 4 This is a flowchart of a method for preparing a TOPCon battery according to an embodiment of the present invention.

[0025] Figure 5 This is a first cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0026] Figure 6 This is a second cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0027] Figure 7 This is a third cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0028] Figure 8 This is a fourth cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0029] Figure 9 This is a fifth cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0030] Figure 10 This is a sixth cross-sectional structural diagram of the fabrication process of a TOPCon battery disclosed in an embodiment of the present invention.

[0031] Figure 11 This is a cross-sectional structural diagram of a stacked battery disclosed in an embodiment of the present invention. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0033] TopCon (TOPCon) technology, consisting of an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer, significantly reduces the probability of carrier recombination at the surface of a crystalline silicon solar cell, improving open-circuit voltage and conversion efficiency. The fabrication method of TOPCon cells involves first oxidizing an ultrathin SiOx layer at high temperature on the back side of a silicon substrate as a tunneling oxide layer. Then, intrinsic polycrystalline silicon is deposited on the tunneling oxide layer, and phosphorus is doped into the intrinsic polycrystalline silicon using diffusion to form N-type doped polycrystalline silicon (phosphorus doping). Boron diffusion combined with laser SE doping is then used on the front side of the silicon substrate to form a boron-diffused emitter. However, the front-side metal electrode is in direct contact with the silicon substrate, resulting in severe interfacial recombination and poor front-side passivation.

[0034] To improve the passivation effect on the front side, related technologies form a passivation contact structure consisting of a tunneling oxide layer (SiOx) and p-type doped polycrystalline silicon (boron-doped) between the front side of the silicon substrate and the metal electrode. However, the segregation coefficient of boron in Si / SiOx is approximately 1 / 10. During the cooling process after high temperature, boron tends to segregate to the interface of the tunneling oxide layer, forming BO complexes with oxygen at the interface, which induces photo-induced degradation and destroys the passivation effect of the tunneling oxide layer, reducing the open-circuit voltage and conversion efficiency of the battery. Moreover, the boron doping in p-type doped polycrystalline silicon is uniform, resulting in weak field passivation capability, further reducing the open-circuit voltage and conversion efficiency of the battery.

[0035] Based on this, the present invention discloses a TOPCon battery, a fabrication method, and a tandem battery. By placing a gallium-doped polysilicon layer between the first tunneling oxide layer and the doped polysilicon layer (the doping element of the doped polysilicon layer includes at least boron), boron segregation into the first tunneling oxide layer is avoided, reducing BO recombination defects and preventing light-induced degradation. Simultaneously, the passivation effect of the first tunneling oxide layer is ensured, improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, improving carrier extraction and the field passivation capability of the P-type doped polysilicon layer, further improving the open-circuit voltage and conversion efficiency of the battery. The first electrode contacts the P-type doped polysilicon layer but not directly contacts the silicon substrate, improving the passivation effect and further improving the battery's conversion efficiency.

[0036] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a TOPCon battery.

[0037] like Figure 1 As shown, Figure 1 This is a cross-sectional structural diagram of a TOPCon cell disclosed in an embodiment of the present invention. The TOPCon cell includes a silicon substrate 1, a first tunneling oxide layer 2, a P-type doped polycrystalline silicon layer 3, a second tunneling oxide layer 4, an N-type doped polycrystalline silicon layer 5, a first electrode 8, and a second electrode 9.

[0038] The silicon substrate 1 has a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 is the light-receiving surface (front side), and the second surface 12 is the back-lighting surface (back side). The silicon substrate 1 can be N-type or P-type doped. As an example, the silicon substrate 1 is an N-type single-crystal silicon substrate.

[0039] The first tunneling oxide layer 2 is located on the first surface 11. The first tunneling oxide layer 2 can be located over the entire area of ​​the first surface 11 or only a portion thereof. The material of the first tunneling oxide layer 2 may include silicon oxide (SiOx), etc. The thickness of the first tunneling oxide layer 2 can be 0.5 nm to 2 nm. The relatively thin thickness of the first tunneling oxide layer 2 allows charge carriers to pass through via quantum tunneling, while effectively chemically passivating dangling bonds on the surface of the silicon substrate 1, reducing the interface state density.

[0040] The P-type doped polysilicon layer 3 is located on the side of the first tunneling oxide layer 2 away from the silicon substrate 1. The P-type doped polysilicon layer 3 includes a gallium-doped polysilicon layer 31 and a doped polysilicon layer 32 stacked sequentially. The doping element of the doped polysilicon layer 32 includes at least boron. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the doped polysilicon layer 32 gradually increases.

[0041] In this configuration, the gallium-doped polysilicon layer 31 is positioned close to the first tunneling oxide layer 2. The gallium-doped polysilicon layer 31 can be a single-layer structure or a stacked structure. The dopant element in the gallium-doped polysilicon layer 31 is gallium, and the doping concentration of the gallium-doped polysilicon layer 31 refers to the gallium doping concentration. Along the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the gallium doping concentration in the gallium-doped polysilicon layer 31 gradually increases; that is, the closer to the first tunneling oxide layer 2, the lower the gallium doping concentration; and the farther away from the first tunneling oxide layer 2, the higher the gallium doping concentration. Here, "gradually increasing" can refer to a continuous increase or a gradient increase. A gradient increase can refer to a uniform gradient increase or a non-uniform gradient increase.

[0042] The doped polysilicon layer 32 is disposed away from the first tunneling oxide layer 2. The doped polysilicon layer 32 can be a single-layer structure or a stacked structure. The doping element of the doped polysilicon layer 32 includes at least boron, but may also include only boron, or boron and other Group III elements (such as gallium). The doping concentration of the doped polysilicon layer 32 can refer to the doping concentration of all P-type doping elements in the doped polysilicon layer 32. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the doped polysilicon layer 32 gradually increases; that is, the closer to the first tunneling oxide layer 2, the lower the doping concentration of the doped polysilicon layer 32; the farther away from the first tunneling oxide layer 2, the higher the doping concentration of the doped polysilicon layer 32. Here, "gradually increasing" can refer to a continuous increase or a gradient increase. A gradient increase can refer to a uniform gradient increase or a non-uniform gradient increase.

[0043] Since the segregation coefficient of gallium in Si / SiOx is approximately 20 / 1, meaning that gallium will largely remain in the polycrystalline silicon, placing the gallium-doped polycrystalline silicon layer 31 close to the first tunneling oxide layer 2 avoids segregation problems and prevents boron segregation into the first tunneling oxide layer 2, reducing BO recombination defects and preventing light-induced degradation. Simultaneously, it ensures the passivation effect of the first tunneling oxide layer 2, improving the open-circuit voltage (Voc) and conversion efficiency of the battery. Furthermore, the P-type doped polycrystalline silicon layer 3 facilitates carrier (hole) transport. From the first tunneling oxide layer 2 to the P-type doped polycrystalline silicon layer 3, the doping concentration of the gallium-doped polycrystalline silicon layer 31 gradually increases, and the doping concentration of the doped polycrystalline silicon layer 32 gradually increases. This creates a stepped energy band within the P-type doped polycrystalline silicon layer 3, accelerating carrier transport and improving carrier extraction, thereby enhancing the field passivation capability of the P-type doped polycrystalline silicon layer 3 and further improving the open-circuit voltage and conversion efficiency of the battery.

[0044] The second tunneling oxide layer 4 is located on the second surface 12. The second tunneling oxide layer 4 may be located in the entire area of ​​the second surface 12 or in a part of the second surface 12. The material of the second tunneling oxide layer 4 may include silicon oxide (SiOx) or the like.

[0045] The N-type doped polysilicon layer 5 is located on the side of the second tunneling oxide layer 4 facing away from the silicon substrate 1. In some embodiments of the present invention, the N-type doped polysilicon layer 5 includes a phosphorus-doped polysilicon layer. The doping element of the phosphorus-doped polysilicon layer is phosphorus. Of course, the present invention is not limited thereto. In other embodiments, the N-type doped polysilicon layer 5 may also be doped with group V elements such as arsenic, which will not be elaborated here.

[0046] The first electrode 8 is in contact with the P-type doped polysilicon layer 3. Specifically, the first electrode 8 is located on the side of the P-type doped polysilicon layer 3 opposite to the first tunneling oxide layer 2, and extends into the P-type doped polysilicon layer 3, contacting it. Alternatively, the first electrode 8 may extend into the doped polysilicon layer 32 and contact it; or it may extend into the gallium-doped polysilicon layer 31 and contact it. The first electrode 8 is a metal electrode.

[0047] The second electrode 9 is in contact with the N-type doped polysilicon layer 5. Specifically, the second electrode 9 is located on the side of the N-type doped polysilicon layer 5 away from the second tunneling oxide layer 4, and extends into the N-type doped polysilicon layer 5 to contact it. The second electrode 9 is a metal electrode.

[0048] The first electrode 8 is in contact with the P-type doped polycrystalline silicon layer 3, but not directly with the silicon substrate 1, which improves the passivation effect and further improves the cell's conversion efficiency. Furthermore, compared to the N-type doped polycrystalline silicon layer (the contact resistance between the N-type doped polycrystalline silicon layer and the metal electrode is approximately 0.5~1.5 mΩ·cm), the first electrode 8... 2 The contact resistance between the P-type doped polycrystalline silicon layer and the metal electrode is relatively large (approximately 1~5 mΩ·cm). 2 This can easily lead to a deterioration in the fill factor (FF), affecting the conversion efficiency. Therefore, in this embodiment of the invention, the variation in the doping concentration of the P-type doped polysilicon layer 3 can effectively improve the contact resistance between the P-type doped polysilicon layer 3 and the first electrode 8, increase the fill factor, and further improve the conversion efficiency of the battery.

[0049] In some embodiments of the present invention, the doped polysilicon layer 32 includes at least one of a boron-doped polysilicon layer and a gallium-boron-doped polysilicon layer.

[0050] When the doped polysilicon layer 32 includes a boron-doped polysilicon layer, the P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a boron-doped polysilicon layer stacked sequentially. The doping concentration of the boron-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3. Here, the doping concentration of the boron-doped polysilicon layer refers to the boron doping concentration.

[0051] When the doped polysilicon layer 32 includes a gallium-boron-doped polysilicon layer, the P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a gallium-boron-doped polysilicon layer stacked sequentially. The doping concentration of the gallium-boron-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3. Here, the doping concentration of the gallium-boron-doped polysilicon layer refers to the doping concentration of the gallium-boron co-doped layer.

[0052] When the doped polysilicon layer 32 includes a boron-doped polysilicon layer and a gallium-boron-doped polysilicon layer, the P-type doped polysilicon layer includes a gallium-doped polysilicon layer, a gallium-boron-doped polysilicon layer, and a boron-doped polysilicon layer stacked sequentially. The doping concentration of the boron-doped polysilicon layer is greater than that of the gallium-boron-doped polysilicon layer. Here, the doping concentration of the boron-doped polysilicon layer refers to the boron doping concentration, and the doping concentration of the gallium-boron-doped polysilicon layer refers to the co-doping concentration of gallium and boron. In some embodiments of the present invention, the doping concentration of the gallium-boron-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, and the doping concentration of the boron-doped polysilicon layer also gradually increases.

[0053] In some embodiments of the present invention, the doped polysilicon layer 32 includes a plurality of doped polysilicon sublayers 321 stacked sequentially, and the doping element of each doped polysilicon sublayer 321 includes at least boron. As an example, each doped polysilicon sublayer 321 can be a boron-doped polysilicon layer or a gallium-boron-doped polysilicon layer. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the plurality of doped polysilicon sublayers 321 increases sequentially.

[0054] Among the multiple doped polycrystalline silicon sublayers 321, the doped polycrystalline silicon sublayer 321 closest to the gallium-doped polycrystalline silicon layer 31 has the lowest doping concentration, while the doped polycrystalline silicon sublayer 321 furthest from the gallium-doped polycrystalline silicon layer 31 has the highest doping concentration. The doping concentration is uniform within each doped polycrystalline silicon sublayer 321.

[0055] For example Figure 1 As shown, the doped polysilicon layer 32 includes three doped polysilicon sublayers 321 stacked sequentially. These three sublayers are a first doped polysilicon sublayer 321a, a second doped polysilicon sublayer 321b, and a third doped polysilicon sublayer 321c. The first doped polysilicon sublayer 321a is positioned close to the gallium-doped polysilicon layer 31, while the third doped polysilicon sublayer 321c is positioned away from the gallium-doped polysilicon layer 31. The second doped polysilicon sublayer 321b is located between the first doped polysilicon sublayer 321a and the third doped polysilicon sublayer 321c. The doping concentration of the first doped polysilicon sublayer 321a, the second doped polysilicon sublayer 321b, and the third doped polysilicon sublayer 321c gradually increases. Of course, the present invention is not limited to this; in other embodiments, the doped polysilicon layer 32 may also include two or more doped polysilicon sublayers 321, which will not be elaborated further here.

[0056] The doped polycrystalline silicon layer 32 is composed of multiple doped polycrystalline silicon sub-layers 321 with progressively increasing doping concentration. The process is highly controllable. By adjusting the number of doped polycrystalline silicon sub-layers 321 and the concentration difference, the required doped polycrystalline silicon layer 32 can be flexibly designed to meet the requirements of different silicon substrate resistivity or different battery structures for field passivation strength and conductivity.

[0057] In some embodiments of the present invention, when the doped polysilicon layer 32 includes multiple doped polysilicon sublayers 321, the first electrode 8 can extend into any doped polysilicon sublayer 321 and contact it. As an example, the first electrode 8 at least penetrates the outermost doped polysilicon sublayer 321 (i.e., the doped polysilicon sublayer 321 with the highest doping concentration), and the first electrode 8 directly contacts the doped polysilicon sublayer 321 with the highest doping concentration, further reducing the contact resistance.

[0058] In some embodiments of the present invention, the thickness of the plurality of doped polysilicon sublayers 321 increases sequentially in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3.

[0059] Among the multiple doped polycrystalline silicon sublayers 321, the doped polycrystalline silicon sublayer 321 closest to the gallium-doped polycrystalline silicon layer 31 has the lowest doping concentration and the smallest thickness, while the doped polycrystalline silicon sublayer 321 furthest from the gallium-doped polycrystalline silicon layer 31 has the highest doping concentration and the largest thickness.

[0060] For example Figure 1 As shown, the doping concentrations of the first doped polycrystalline silicon sublayer 321a, the second doped polycrystalline silicon sublayer 321b, and the third doped polycrystalline silicon sublayer 321c increase sequentially, and their thicknesses also increase sequentially.

[0061] The doped polycrystalline silicon layer 32 consists of multiple doped polycrystalline silicon sub-layers 321 with successively increasing doping concentration and thickness, which further improves carrier extraction and field passivation capability.

[0062] In some embodiments of the present invention, such as Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a plurality of gallium-doped polysilicon sublayers 311 stacked sequentially. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the plurality of gallium-doped polysilicon sublayers 311 increases sequentially.

[0063] Among the multiple gallium-doped polycrystalline silicon sublayers 311, the gallium-doped polycrystalline silicon sublayer 311 closest to the first tunneling oxide layer 2 has the lowest doping concentration, while the gallium-doped polycrystalline silicon sublayer 311 furthest from the first tunneling oxide layer 2 has the highest doping concentration. The doping concentration is uniform within each gallium-doped polycrystalline silicon sublayer 311.

[0064] For example Figure 2As shown, the gallium-doped polysilicon layer 31 includes two gallium-doped polysilicon sublayers 311 stacked sequentially. The two gallium-doped polysilicon sublayers 311 are a first gallium-doped polysilicon sublayer 311a and a second gallium-doped polysilicon sublayer 311b, respectively. The first gallium-doped polysilicon sublayer 311a is disposed closer to the first tunneling oxide layer 2, and the second gallium-doped polysilicon sublayer 311b is disposed farther from the first tunneling oxide layer 2. The doping concentration of the first gallium-doped polysilicon sublayer 311a and the second gallium-doped polysilicon sublayer 311b gradually increases. Of course, the present invention is not limited to this; in other embodiments, the gallium-doped polysilicon layer 31 may also include two or more gallium-doped polysilicon sublayers 311, which will not be elaborated here.

[0065] The gallium-doped polycrystalline silicon layer 31 is composed of multiple gallium-doped polycrystalline silicon sub-layers 311 with progressively increasing doping concentration. The process is highly controllable. By adjusting the number of gallium-doped polycrystalline silicon sub-layers 311 and the concentration difference, the required gallium-doped polycrystalline silicon layer 31 can be flexibly designed.

[0066] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 comprises multiple gallium-doped polysilicon sublayers 311, the first electrode 8 can extend into any gallium-doped polysilicon sublayer 311 and make contact with it. As an example, the first electrode 8 at least penetrates the doped polysilicon layer 32 and makes contact with the gallium-doped polysilicon layer 31, further reducing contact resistance, reducing recombination in the contact area, and improving the battery open-circuit voltage and long-term stability.

[0067] In some embodiments of the present invention, the thickness of a plurality of gallium-doped polysilicon sublayers 311 increases sequentially in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3.

[0068] Among the multiple gallium-doped polycrystalline silicon sublayers 311, the gallium-doped polycrystalline silicon sublayer 311 closest to the first tunneling oxide layer 2 has the lowest doping concentration and the smallest thickness, while the gallium-doped polycrystalline silicon sublayer 311 furthest from the first tunneling oxide layer 2 has the highest doping concentration and the largest thickness.

[0069] For example Figure 2 As shown, the doping concentration of the first gallium-doped polycrystalline silicon sublayer 311a and the thickness of the second gallium-doped polycrystalline silicon sublayer 311b increase sequentially.

[0070] The gallium-doped polycrystalline silicon layer 31 consists of multiple gallium-doped polycrystalline silicon sub-layers 311 with successively increasing doping concentration and thickness, which further improves carrier extraction and field passivation capability.

[0071] In some embodiments of the present invention, the doping concentration of the doped polysilicon layer 32 is greater than the doping concentration of the gallium-doped polysilicon layer 31. The minimum doping concentration of the doped polysilicon layer 32 can be greater than the maximum doping concentration of the gallium-doped polysilicon layer 31. It should be noted that the minimum doping concentration of the doped polysilicon layer 32 can also be equal to the maximum doping concentration of the gallium-doped polysilicon layer 31, ensuring that the overall doping concentration of the doped polysilicon layer 32 is greater than the overall doping concentration of the gallium-doped polysilicon layer 31.

[0072] In the case where the doped polysilicon layer 32 includes multiple doped polysilicon sublayers 321 and the gallium-doped polysilicon layer 31 includes multiple gallium-doped polysilicon sublayers 311, the doping concentration of the doped polysilicon sublayer 321 closest to the gallium-doped polysilicon layer 31 is greater than or equal to the doping concentration of the gallium-doped polysilicon sublayer 311 closest to the doped polysilicon layer 32.

[0073] The doping concentration of the doped polysilicon layer 32 is aligned with that of the gallium-doped polysilicon layer 31, so that the P-type doped polysilicon layer 3 forms a gradient energy band structure with increasing valence band energy levels, which further improves carrier extraction and field passivation capability.

[0074] In some embodiments of the present invention, the doping concentration of the P-type doped polysilicon layer 3 is 1×10⁻⁶. 17 cm -3 ~1×10 20 cm -3 The doping concentration of the p-type doped polysilicon layer 3 is 1×10⁻⁶. 17 cm -3 ~1×10 20 cm -3 The doping concentration varies between these values. The minimum doping concentration of the P-type doped polysilicon layer 3 is not less than 1 × 10⁻⁶. 17 cm -3 The maximum doping concentration of the P-type doped polysilicon layer 3 is no greater than 1 × 10⁻⁶. 20 cm -3 .

[0075] The doping concentration of the P-type doped polycrystalline silicon layer 3 varies within the above range, which can balance passivation performance, conductivity and process feasibility.

[0076] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 The doping concentration varies between these values. The minimum doping concentration of the gallium-doped polysilicon layer 31 is not less than 1 × 10⁻⁶.17 cm -3 The maximum doping concentration of the gallium-doped polysilicon layer 31 is no greater than 1×10⁻⁶. 18 cm -3 The doping concentration of the polycrystalline silicon layer 32 is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The doping concentration of the polycrystalline silicon layer 32 is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 The doping concentration varies between these values. The minimum doping concentration of the doped polysilicon layer 32 is not less than 1 × 10⁻⁶. 18 cm -3 The maximum doping concentration of the polycrystalline silicon layer 32 is no greater than 1×10⁻⁶. 20 cm -3 .

[0077] Varying the doping concentrations of gallium-doped polysilicon layer 31 and doped polysilicon layer 32 within the above range can significantly improve the field passivation capability of P-type doped polysilicon layer 3.

[0078] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a and a second gallium-doped polysilicon sublayer 311b stacked sequentially, the doping concentration of the first gallium-doped polysilicon sublayer 311a is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer 311b is 5 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 This ensures an effective gradient distribution, which is easily achieved through appropriate processes and can significantly improve the field passivation capability of the P-type doped polysilicon layer 3.

[0079] In some embodiments of the present invention, when the doped polysilicon layer 32 includes a first doped polysilicon sublayer 321a, a second doped polysilicon sublayer 321b, and a third doped polysilicon sublayer 321c stacked sequentially, the doping concentration of the first doped polysilicon sublayer 321a is 1×10⁻⁶. 18 cm -3 ~5×10 18 cm -3 The doping concentration of the second doped polycrystalline silicon sublayer 321b is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm-3 The doping concentration of the third doped polycrystalline silicon sublayer 321c is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 This ensures an effective gradient distribution, which is easily achieved through appropriate processes and can significantly improve the field passivation capability of the P-type doped polysilicon layer 3.

[0080] In some embodiments of the present invention, the thickness of the doped polysilicon layer 32 is greater than the thickness of the gallium-doped polysilicon layer 31.

[0081] In the case where the doped polysilicon layer 32 includes multiple doped polysilicon sublayers 321, and the gallium-doped polysilicon layer 31 includes multiple gallium-doped polysilicon sublayers 311, the thickness of each doped polysilicon sublayer 321 can be greater than the thickness of the gallium-doped polysilicon sublayer 311, or the thickness of some doped polysilicon sublayers 321 can be greater than the thickness of the gallium-doped polysilicon sublayer 311, while the thickness of the remaining doped polysilicon sublayers 321 is less than or equal to the thickness of the gallium-doped polysilicon sublayer 311. No specific limitation is made here; it is only necessary to ensure that the overall thickness of the doped polysilicon layer 32 is greater than the overall thickness of the gallium-doped polysilicon layer 31. As an example, the thickness of the doped polysilicon sublayer 321 closest to the gallium-doped polysilicon layer 31 is greater than or equal to the thickness of the gallium-doped polysilicon sublayer 311 closest to the doped polysilicon layer 32.

[0082] The gallium-doped polysilicon layer 31 primarily serves interface stability, and its thickness can be set relatively thin, sufficient to prevent boron segregation towards the interface. The doped polysilicon layer 32 undertakes the main tasks of conductivity and field passivation, requiring sufficient thickness to accommodate the high-concentration doped region and achieve low sheet resistance.

[0083] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a and a second gallium-doped polysilicon sublayer 311b stacked sequentially, the thickness of the first gallium-doped polysilicon sublayer 311a is 0.5 nm to 2 nm, and the thickness of the second gallium-doped polysilicon sublayer 311b is 2 nm to 10 nm. This ensures an effective gradient distribution, is easily implemented with suitable processes, and significantly improves the field passivation capability of the p-type doped polysilicon layer 3.

[0084] In some embodiments of the present invention, when the doped polysilicon layer 32 includes a first doped polysilicon sublayer 321a, a second doped polysilicon sublayer 321b, and a third doped polysilicon sublayer 321c stacked sequentially, the thickness of the first doped polysilicon sublayer 321a is 10 nm to 30 nm, the thickness of the second doped polysilicon sublayer 321b is 30 nm to 100 nm, and the thickness of the third doped polysilicon sublayer 321c is 100 nm to 150 nm. This significantly improves the field passivation capability of the p-type doped polysilicon layer 3.

[0085] In some embodiments of the present invention, the TOPCon cell further includes an intrinsic polycrystalline silicon layer, which is located between the first tunneling oxide layer 2 and the P-type doped polycrystalline silicon layer 3. The intrinsic polycrystalline silicon layer is relatively thin, such as 0.5 nm to 2 nm.

[0086] An intrinsic polysilicon layer is provided between the first tunneling oxide layer 2 and the P-type doped polysilicon layer 3, which can further prevent boron segregation into the first tunneling oxide layer, avoid photo-induced degradation, and further improve the passivation effect of the first tunneling oxide layer 2.

[0087] In some embodiments of the present invention, the TOPCon battery further includes a first passivation layer 6 and a second passivation layer 7.

[0088] The first passivation layer 6 is located on the side of the p-type doped polysilicon layer 3 facing away from the first tunneling oxide layer 2. The first electrode 8 penetrates the first passivation layer 6 and the doped polysilicon layer 32, and contacts the gallium-doped polysilicon layer 31 to further reduce the contact resistance. In some embodiments of the present invention, the first passivation layer 6 can be a single-layer structure or a stacked structure. For example, the first passivation layer 6 includes a first aluminum oxide (AlOx) layer 61 and a first silicon nitride (SiNx) layer 62 stacked together. The thickness of the first silicon nitride layer 62 can be 10 nm to 100 nm.

[0089] The second passivation layer 7 is located on the side of the N-type doped polysilicon layer 5 opposite to the second tunneling oxide layer 4. The second electrode 9 penetrates the second passivation layer 7 and contacts the N-type doped polysilicon layer 5. In some embodiments of the present invention, the second passivation layer 7 can be a single-layer structure or a stacked structure. For example, the second passivation layer 7 includes a second alumina (AlOx) layer 71 and a second silicon nitride (SiNx) layer 72 stacked together. The thickness of the second silicon nitride layer 72 can be 10 nm to 150 nm.

[0090] The first passivation layer 6 and the second passivation layer 7 adopt a stacked passivation structure composed of an aluminum oxide layer and a silicon nitride layer to achieve a dual passivation mechanism, which takes into account both excellent passivation effect, optical gain and long-term device stability.

[0091] In some embodiments of the present invention, the first surface 11 includes alternating first metallized regions 111 and first non-metallized regions 112, the first tunneling oxide layer 2 is located in the first metallized region 111, and the first passivation layer 6 is also located in the first non-metallized region 112.

[0092] The second surface 12 includes alternating second metallized regions 121 and second non-metallized regions 122. The second tunneling oxide layer 4 is located in the second metallized region 121, and the second passivation layer 7 is located in the second non-metallized region 122. The positions of the first metallized region 111 and the second metallized region 121 are corresponding, and the positions of the first non-metallized region 112 and the second non-metallized region 122 are corresponding.

[0093] The tunneling oxide layer and the doped polysilicon layer are located in the metallization region, not in the non-metallization region. On the one hand, this can eliminate the parasitic light absorption of polysilicon in the non-metallization region, improve the light absorption utilization rate and short-circuit current; on the other hand, it can reduce grain boundary recombination and impurity defects caused by large-area doped layers, and reduce global carrier recombination loss.

[0094] In some embodiments of the present invention, such as Figure 3 As shown, the silicon substrate 1 includes a P-type diffusion region 13 located in the first non-metallization region 112. As an example, the P-type diffusion region 13 includes a boron diffusion region, where the doping element is boron. Of course, the invention is not limited to this; in other embodiments, the P-type diffusion region 13 may also be doped with group III elements such as gallium, which will not be elaborated here. Providing the P-type diffusion region 13 in the first non-metallization region 112 helps to improve carrier lateral transport and reduce transport resistance.

[0095] In some embodiments of the present invention, the doping concentration of the P-type diffusion region 13 is less than the doping concentration of the P-type doped polysilicon layer 3, so as to reduce optical loss and increase short-circuit current.

[0096] In some embodiments of the present invention, such as Figure 3 As shown, the surface of the first non-metallized region 112 is textured to reduce the loss of light reflection from the front and improve the collection efficiency of photogenerated carriers.

[0097] In some embodiments of the present invention, such as Figure 3 As shown, the surfaces of the first metallized region 111, the second metallized region 121, and the second non-metallized region 122 are all polished surfaces to optimize the passivation layer interface quality, reduce contact resistance, and reduce interface recombination.

[0098] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a method for preparing a TOPCon battery, which can prepare a TOPCon battery as disclosed in any of the above embodiments. Figure 4 As shown, Figure 4 This is a flowchart of a method for preparing a TOPCon battery according to an embodiment of the present invention. The method includes steps S101 to S104: S101, A silicon substrate is provided, the silicon substrate having a first surface and a second surface disposed opposite to each other.

[0099] In some embodiments of the present invention, combined with Figure 5 As shown, the silicon substrate 1 can be an N-type single-crystal silicon substrate. After providing the silicon substrate 1, the surface of the silicon substrate 1 can be pretreated with NaOH or KOH solution. The concentration of the NaOH or KOH solution used is 5wt%~30wt%, the temperature is 50℃~90℃, and the time is 50s~500s.

[0100] The silicon substrate 1 has a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 is the light-receiving surface (front side), and the second surface 12 is the back light-receiving surface (back side).

[0101] S102. A first tunneling oxide layer and a P-type doped polysilicon layer are sequentially stacked on the first surface. The P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a doped polysilicon layer that are sequentially stacked. The doping element of the doped polysilicon layer includes at least boron. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, and the doping concentration of the doped polysilicon layer gradually increases.

[0102] In some embodiments of the present invention, combined with Figure 5 As shown, a first tunneling oxide layer 2 is first deposited on the first surface 11 using a PECVD process. Then, a gallium-doped polysilicon layer 31 is formed on the side of the first tunneling oxide layer 2 facing away from the silicon substrate 1 using a PECVD in-situ doping process. Next, a doped polysilicon layer 32 is formed on the side of the gallium-doped polysilicon layer 31 facing away from the first tunneling oxide layer 2 using a PECVD in-situ doping process. Along the direction from the silicon substrate 1 to the first tunneling oxide layer 2, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the doped polysilicon layer 32 also gradually increases.

[0103] The first tunneling oxide layer 2 can also be formed using other processes, such as LPCVD, which will not be elaborated here. The gallium-doped polysilicon layer 31 and the doped polysilicon layer 32 can also be formed using other processes, such as LPCVD plus diffusion doping, which will not be elaborated here.

[0104] In some embodiments of the present invention, the doping concentration of the P-type doped polysilicon layer 3 is 1×10⁻⁶. 17 cm -3 ~1×10 20 cm -3 .

[0105] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .

[0106] In some embodiments of the present invention, the doping concentration of the polysilicon layer 32 is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0107] In some embodiments of the present invention, during the formation of the first tunneling oxide layer 2, nitrous oxide (N2O) is introduced, with a flow rate of 300 sccm to 30000 sccm; the cavity temperature is 200℃ to 600℃; the pressure is 500 Pa to 50000 Pa; the radio frequency power is 1000 W to 30000 W; the deposition time is 5 s to 500 s; and the thickness is 0.5 nm to 2 nm.

[0108] In some embodiments of the present invention, during the formation of the gallium-doped polycrystalline silicon layer 31, silane, a gallium source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 5 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, the deposition time is 5 s to 1000 s, the thickness is 0.5 nm to 100 nm, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 This forms a gallium-doped polycrystalline silicon layer 31 that meets the requirements.

[0109] The gallium source can include TMG, TEG, etc., and can also include other gallium-containing gases or liquids; no specific limitation is made here. The carrier gas can include H2, Ar, etc., and can also include other gases; no specific limitation is made here.

[0110] In some embodiments of the present invention, during the formation of the gallium-doped polysilicon layer 31, the flow rate of the gallium source can be gradually increased so that the doping concentration of the gallium-doped polysilicon layer 31 gradually increases in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0111] In some embodiments of the present invention, combined with Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a plurality of gallium-doped polysilicon sublayers 311 formed by sequential stacking. During the sequential formation of the plurality of gallium-doped polysilicon sublayers 311, the flow rate of the gallium source can be increased sequentially, that is, the flow rate of the gallium source introduced into the formation of the subsequent gallium-doped polysilicon sublayer 311 is greater than the flow rate of the gallium source introduced into the formation of the previous gallium-doped polysilicon sublayer 311, so that the doping concentration of the plurality of gallium-doped polysilicon sublayers 311 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0112] In some embodiments of the present invention, combined with Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a and a second gallium-doped polysilicon sublayer 311b stacked sequentially. During the formation of the first gallium-doped polysilicon sublayer 311a, the flow rate of the introduced gallium source is 5 sccm to 20 sccm, and the doping concentration of the first gallium-doped polysilicon sublayer 311a is 1 × 10⁻⁶. 17 cm -3 ~5×10 17 cm -3 During the formation of the second gallium-doped polycrystalline silicon sublayer 311b, the flow rate of the gallium source was 20 sccm to 100 sccm, and the doping concentration of the second gallium-doped polycrystalline silicon sublayer 311b was 5 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 .

[0113] In some embodiments of the present invention, during the process of sequentially forming multiple gallium-doped polycrystalline silicon sublayers 311, the deposition time can be increased sequentially, that is, the deposition time of the subsequent gallium-doped polycrystalline silicon sublayer 311 is greater than the deposition time of the previous gallium-doped polycrystalline silicon sublayer 311, so that the thickness of the multiple gallium-doped polycrystalline silicon sublayers 311 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0114] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a and a second gallium-doped polysilicon sublayer 311b stacked sequentially, the thickness of the first gallium-doped polysilicon sublayer 311a is 0.5nm to 2nm, and the thickness of the second gallium-doped polysilicon sublayer 311b is 2nm to 10nm.

[0115] In some embodiments of the present invention, during the formation of the doped polycrystalline silicon layer 32, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 1 sccm to 300 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, and the doping concentration is 1 × 10⁻⁶. 17 cm -3 ~1×10 20 cm -3 This forms a doped polycrystalline silicon layer 32 that meets the requirements.

[0116] The boron source may include BF3, B2H6, TMB, etc., and may also include other boron-containing gases or liquids; no specific limitation is made here. The carrier gas may include H2, Ar, etc., and may also include other gases; no specific limitation is made here.

[0117] In some embodiments of the present invention, the doped polysilicon layer 32 includes at least one of a boron-doped polysilicon layer and a gallium-boron-doped polysilicon layer.

[0118] In the case where the doped polysilicon layer 32 includes a gallium-boron-doped polysilicon layer, silane, a boron source, a gallium source, and a carrier gas are introduced during the formation of the doped polysilicon layer 32. The gallium source may include TMG, TEG, etc.

[0119] In some embodiments of the present invention, during the formation of the doped polysilicon layer 32, the flow rate of the boron source (and gallium source) can be gradually increased so that the doping concentration of the doped polysilicon layer 32 gradually increases in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0120] In some embodiments of the present invention, the doped polysilicon layer 32 includes a plurality of doped polysilicon sublayers 321 formed by sequential stacking. During the sequential formation of the plurality of doped polysilicon sublayers 321, the flow rates of the boron source (and gallium source) can be increased sequentially, that is, the flow rate of the boron source (and gallium source) introduced into the formation of the subsequent doped polysilicon sublayer 321 is greater than the flow rate of the boron source (and gallium source) introduced into the formation of the previous doped polysilicon sublayer 321, so that the doping concentration of the plurality of doped polysilicon sublayers 321 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0121] As an example, combined Figure 1 As shown, the doped polycrystalline silicon layer 32 includes a first doped polycrystalline silicon sublayer 321a, a second doped polycrystalline silicon sublayer 321b, and a third doped polycrystalline silicon sublayer 321c, which are stacked sequentially. The first doped polycrystalline silicon sublayer 321a, the second doped polycrystalline silicon sublayer 321b, and the third doped polycrystalline silicon sublayer 321c are all boron-doped polycrystalline silicon sublayers, and the doping concentration of the first doped polycrystalline silicon sublayer 321a, the second doped polycrystalline silicon sublayer 321b, and the third doped polycrystalline silicon sublayer 321c gradually increases.

[0122] During the formation of the first doped polycrystalline silicon sublayer 321a, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 1 sccm to 20 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, the deposition time is 1 s to 1000 s, the thickness is 1 nm to 100 nm, and the doping concentration is 1 × 10⁻⁶. 18 cm-3 ~5×10 18 cm -3 .

[0123] During the formation of the second doped polycrystalline silicon sublayer 321b, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 20 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The chamber temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, the deposition time is 1 s to 1000 s, the thickness is 5 nm to 200 nm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 .

[0124] During the formation of the third doped polycrystalline silicon sublayer 321c, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 100 sccm to 300 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The chamber temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, the deposition time is 1 s to 1000 s, the thickness is 10 nm to 300 nm, and the deposition rate is 1 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 .

[0125] In some embodiments of the present invention, during the process of sequentially forming multiple doped polycrystalline silicon sublayers 321, the deposition time can be increased sequentially, that is, the deposition time of the later doped polycrystalline silicon sublayer 321 is greater than the deposition time of forming the previous doped polycrystalline silicon sublayer 321, so that the thickness of the multiple doped polycrystalline silicon sublayers 321 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0126] In some embodiments of the present invention, when the doped polysilicon layer 32 includes a first doped polysilicon sublayer 321a, a second doped polysilicon sublayer 321b, and a third doped polysilicon sublayer 321c stacked sequentially, the thickness of the first doped polysilicon sublayer 321a is 10nm~30nm, the thickness of the second doped polysilicon sublayer 321b is 30nm~100nm, and the thickness of the third doped polysilicon sublayer 321c is 100nm~150nm.

[0127] In some embodiments of the present invention, the doping concentration of the doped polysilicon layer 32 is greater than the doping concentration of the gallium-doped polysilicon layer 31.

[0128] In some embodiments of the present invention, the thickness of the doped polysilicon layer 32 is greater than the thickness of the gallium-doped polysilicon layer 31.

[0129] By setting a gallium-doped polysilicon layer 31 between the first tunneling oxide layer 2 and the doped polysilicon layer 32 (the doping element of the doped polysilicon layer 32 includes at least boron), boron segregation to the first tunneling oxide layer 2 is avoided, BO recombination defects are reduced, photo-induced degradation is avoided, and the passivation effect of the first tunneling oxide layer 2 is ensured, thereby improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the doped polysilicon layer 32 gradually increases, thereby improving the extraction of charge carriers, improving the field passivation capability of the P-type doped polysilicon layer 3, and further improving the open-circuit voltage and conversion efficiency of the battery.

[0130] S103, a second tunneling oxide layer and an N-type doped polysilicon layer are sequentially stacked on the second surface.

[0131] In some embodiments of the present invention, combined with Figure 6 As shown, a second tunneling oxide layer 4 is first deposited on the second surface 12 using a PECVD process. As an example, during the formation of the second tunneling oxide layer 4, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa, the flow rate of nitrous oxide (N2O) is 300sccm~30000sccm, the radio frequency power is 1000W~30000W, the deposition time is 5s~500s, and the thickness is 0.5nm~2nm.

[0132] Then, using a PECVD process, an N-type doped polysilicon layer 5 is formed on the side of the second tunneling oxide layer 4 facing away from the silicon substrate 1. As an example, during the formation of the N-type doped polysilicon layer 5, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa; the introduced gases include silane, a phosphorus source, and a carrier gas, with a silane flow rate of 10sccm~10000sccm, a phosphorus source flow rate of 300sccm~3000sccm, and a carrier gas flow rate of 300sccm~30000sccm; the RF power is 1000W~30000W, the deposition time is 1s~1000s, the thickness is 10nm~300nm, and the doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 22 cm -3 The phosphorus source may include PH3, or other phosphorus-containing gases or liquids; no specific limitation is made here. The carrier gas may include H2, Ar, or other gases; no specific limitation is made here.

[0133] It should be noted that the second tunneling oxide layer 4 and the N-type doped polysilicon layer 5 can also be formed using other processes, which are not specifically limited here.

[0134] Then, to Figure 6 The structure shown is subjected to high-temperature annealing. As an example, the chamber temperature is 700℃~1000℃ and the pressure is 500Pa~50000Pa; O2 and N2 are introduced during the high-temperature annealing process, with the flow rate of O2 being 1000sccm~50000sccm and the flow rate of N2 being 1000sccm~50000sccm.

[0135] In some embodiments of the present invention, the first surface 11 includes alternating first metallized regions 111 and first non-metallized regions 112, and the second surface 12 includes alternating second metallized regions 121 and second non-metallized regions 122. The positions of the first metallized regions 111 and the second metallized regions 121 correspond to each other, and the positions of the first non-metallized regions 112 and the second non-metallized regions 122 correspond to each other.

[0136] Combination Figure 7 As shown, for Figure 7 The structure shown is patterned (e.g., laser grooving, using a 532nm green picosecond laser with a power of 10W~50W), the first tunneling oxide layer 2 and the P-type doped polysilicon layer 3 of the first non-metallized region 112 are removed, and the first tunneling oxide layer 2 and the P-type doped polysilicon layer 3 of the first metallized region 111 are retained; the second tunneling oxide layer 4 and the N-type doped polysilicon layer 4 of the second non-metallized region 122 are removed, and the second tunneling oxide layer 4 and the N-type doped polysilicon layer 4 of the second metallized region 121 are retained.

[0137] In some embodiments of the present invention, a mask may also be formed on the first surface 11, and the first tunneling oxide layer 2 and the P-type doped polysilicon layer 3 may be sequentially stacked on the first metallization region 111 through the mask to simplify the process flow. Then, the mask is removed.

[0138] In some embodiments of the present invention, a mask may also be formed on the second surface 12, and the second tunneling oxide layer 4 and the N-type doped polysilicon layer 5 may be sequentially stacked on the second metallization region 121 through the mask to simplify the process flow. Then, the mask is removed.

[0139] Then, to Figure 7 The structure shown is polished on both sides. As an example, the first non-metallic region 112 and the second non-metallic region 122 are pretreated with NaOH or KOH solution. The concentration of the NaOH or KOH solution used is 5wt%~30wt%, the temperature is 50℃~90℃, and the time is 50s~500s.

[0140] In some embodiments of the present invention, after step S103, the preparation method further includes: texturing the first non-metallized region 112 and the second non-metallized region 122 to make the surfaces of the first non-metallized region 112 and the second non-metallized region 122 textured. As an example, a NaOH or KOH solution is used for texturing, with a NaOH or KOH solution concentration of 5wt%~30wt%, a temperature of 50℃~90℃, and a time of 100s~1000s; the amount of additive is 1L~10L.

[0141] In some embodiments of the present invention, after step S103, the preparation method further includes: forming a first passivation layer and a second passivation layer, wherein the first passivation layer is located on the side of the P-type doped polysilicon layer away from the first tunneling oxide layer, and the second passivation layer is located on the side of the N-type doped polysilicon layer away from the second tunneling oxide layer.

[0142] Combination Figure 1 As shown, when the first surface 11 includes a first metallized region 111 and a first non-metallized region 112, the first passivation layer 6 covers the P-type doped polysilicon layer 3 and the first non-metallized region 112. When the second surface 12 includes a second metallized region 121 and a second non-metallized region 122, the second passivation layer 7 covers the N-type doped polysilicon layer 5 and the second non-metallized region 122.

[0143] In some embodiments of the present invention, combined with Figure 1 As shown, the first passivation layer 6 includes a first aluminum oxide layer 61 and a first silicon nitride layer 62 formed sequentially.

[0144] In some embodiments of the present invention, the second passivation layer 7 includes a second aluminum oxide layer 71 and a second silicon nitride layer 72 formed by sequentially stacking.

[0145] A first alumina layer 61 covering a P-type doped polycrystalline silicon layer 3 and a first non-metallization region 112, and a second alumina layer 71 covering an N-type doped polycrystalline silicon layer 5 and a second non-metallization region 122 are formed using the ALD process. The first alumina layer 61 and the second alumina layer 71 can be formed using the same fabrication process. As an example, during the fabrication of the first alumina layer 61 and the second alumina layer 71, the temperature is 50℃~500℃, the pressure is 0.1 Torr~10 Torr, the N2 flow rate is 10 sccm~1000 sccm, the TMA pulse is 10 ms~100 ms, the DI water pulse is 10 ms~100 ms, and the number of cycles is 10~50.

[0146] Then, a first silicon nitride layer 62 is formed on the side of the first alumina layer 61 facing away from the silicon substrate 1 using a PECVD process. As an example, during the fabrication of the first silicon nitride layer 62, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa; the gas flow rate is as follows: silane flow rate is 10sccm~1000sccm, NH3 flow rate is 100sccm~10000sccm, N2O flow rate is 10sccm~10000sccm, and N2 flow rate is 300sccm~30000sccm; the RF power is 1000W~30000W, the deposition time is 1s~1000s; and the thickness is 10nm~100nm.

[0147] Then, a second silicon nitride layer 72 is formed on the side of the second alumina layer 71 facing away from the silicon substrate 1 using a PECVD process. As an example, during the fabrication of the second silicon nitride layer 72, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa; the gas flow rate is as follows: silane flow rate is 10sccm~1000sccm, NH3 flow rate is 100sccm~10000sccm, N2O flow rate is 10sccm~10000sccm, and N2 flow rate is 300sccm~30000sccm; the RF power is 1000W~30000W, the deposition time is 1s~1000s; and the thickness is 10nm~150nm.

[0148] S104. Form a first electrode and a second electrode. The first electrode is in contact with the P-type doped polysilicon layer, and the second electrode is in contact with the N-type doped polysilicon layer.

[0149] In some embodiments of the present invention, combined with Figure 1 As shown, the first electrode 8 penetrates the first passivation layer 6 and the doped polysilicon layer 32, and extends into the gallium-doped polysilicon layer 31, contacting the gallium-doped polysilicon layer 31. The second electrode 9 penetrates the second passivation layer 7, and extends into the N-type doped polysilicon layer 5, contacting the N-type doped polysilicon layer 5.

[0150] N-type main gate paste, N-type secondary gate paste, P-type main gate paste, and P-type secondary gate paste can be screen-printed. Then, high-temperature sintering is performed at 600℃~900℃ for 1s~100s. Finally, light injection is performed to form a first electrode 8 and a second electrode 9. The first electrode 8 includes a P-type main gate and a P-type secondary gate, and the second electrode 9 includes an N-type main gate and an N-type secondary gate.

[0151] It should be noted that after the battery is manufactured, it can be tested and sorted. The test and sorting is used to detect the battery's electrical performance and appearance defects, classify it according to efficiency, and remove defective cells to ensure component matching and product quality.

[0152] In some embodiments of the present invention, the silicon substrate includes a P-type diffusion region located in the first non-metallization region, wherein the doping concentration of the P-type diffusion region is less than the doping concentration of the P-type doped polycrystalline silicon layer.

[0153] Combination Figure 8 As shown, a silicon substrate 1 is first provided. The silicon substrate 1 is then texturized on both sides using a NaOH or KOH solution. The concentration of the NaOH or KOH solution used is 5wt%~30wt%, the temperature is 50℃~90℃, the time is 100s~1000s, and the additive is 1~10L. After texturing, both the first surface 11 and the second surface 12 are textured surfaces.

[0154] Then, the first surface 11 is subjected to a doping element diffusion treatment to form a P-type diffusion region 13 and a BSG (not shown in the figure) on the first surface 11, wherein the doping element is a P-type dopant, such as boron. As an example, the first surface 11 is boron diffused at a temperature of 900~1100℃, and the flow rate of the introduced boron source (such as BCL3) is 50sccm~500sccm, the flow rate of small O2 is 100sccm~1000sccm, the flow rate of N2 is 100sccm~10000sccm, and the flow rate of large O2 is 5000sccm~50000sccm. The P-type diffusion region 13 is a boron diffusion region. The thickness of the BSG is 10nm~80nm.

[0155] Then, combine Figure 9 As shown, the first surface 11 is patterned (e.g., laser grooving, using a 532nm green picosecond laser with a power of 10W~50W) to groove the first metallized region 111.

[0156] Then, the BSG on the first surface 11 is removed in a chain process, and the second surface 12 and the first metallized region 111 are polished to make the surfaces of the second surface 12 and the first metallized region 111 polished surfaces. As an example, NaOH or KOH solution is used, with a concentration of 5~30wt%, a temperature of 50~90℃, and a time of 50~500s.

[0157] Then, combine Figure 10 As shown, a first tunneling oxide layer 2 is deposited in the first metallization region 111 using a PECVD process. Then, a gallium-doped polysilicon layer 31 is formed on the side of the first tunneling oxide layer 2 facing away from the silicon substrate 1 using a PECVD in-situ doping process. Next, a doped polysilicon layer 32 is formed on the side of the gallium-doped polysilicon layer 31 facing away from the first tunneling oxide layer 2 using a PECVD in-situ doping process. Along the direction from the silicon substrate 1 to the first tunneling oxide layer 2, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the doped polysilicon layer 32 also gradually increases.

[0158] Then, a second tunneling oxide layer 4 is deposited in the second metallization region 121 using a PECVD process. An N-type doped polysilicon layer 5 is formed on the side of the second tunneling oxide layer 4 facing away from the silicon substrate 1 using a PECVD process.

[0159] It should be noted that, alternatively, a first initial tunneling oxide layer, an initial gallium-doped polysilicon layer, and an initial doped polysilicon layer can be deposited sequentially on the first surface 11. Then, the first initial tunneling oxide layer, the initial gallium-doped polysilicon layer, and the initial doped polysilicon layer are patterned, and the first initial tunneling oxide layer, the initial gallium-doped polysilicon layer, and the initial doped polysilicon layer of the first non-metallized region 112 are removed. The first initial tunneling oxide layer of the first metallized region 111 is retained to form the first tunneling oxide layer 2, the initial gallium-doped polysilicon layer of the first metallized region 111 is retained to form the gallium-doped polysilicon layer 31, and the initial doped polysilicon layer of the first metallized region 111 is retained to form the doped polysilicon layer 32.

[0160] Similarly, a second initial tunneling oxide layer and an initial N-type doped polysilicon layer can be deposited sequentially on the second surface 12. Then, the second initial tunneling oxide layer and the initial N-type doped polysilicon layer are patterned, the second initial tunneling oxide layer and the initial N-type doped polysilicon layer of the second non-metallization region 122 are removed, the second initial tunneling oxide layer of the second metallization region 121 is retained to form the second tunneling oxide layer 4, and the initial N-type doped polysilicon layer of the second metallization region 121 is retained to form the N-type doped polysilicon layer 5.

[0161] Then, combine Figure 3 As shown, an ALD process is used to form a first alumina layer 61 covering a P-type doped polysilicon layer 3 and a first non-metallization region 112, and a second alumina layer 71 covering an N-type doped polysilicon layer 5 and a second non-metallization region 122. Then, a PECVD process is used to form a first silicon nitride layer 62 on the side of the first alumina layer 61 facing away from the silicon substrate 1. Similarly, a PECVD process is used to form a second silicon nitride layer 72 on the side of the second alumina layer 71 facing away from the silicon substrate 1. The first alumina layer 61 and the first silicon nitride layer 62 constitute a first passivation layer 6, and the second alumina layer 71 and the second silicon nitride layer 72 constitute a second passivation layer 7.

[0162] Then, a first electrode 8 and a second electrode 9 are formed by screen printing. The first electrode 8 penetrates the first passivation layer 6 and the doped polysilicon layer 32, and extends into the gallium-doped polysilicon layer 31, contacting the gallium-doped polysilicon layer 31. The second electrode 9 penetrates the second passivation layer 7, and extends into the N-type doped polysilicon layer 5, contacting the N-type doped polysilicon layer 5.

[0163] The following specific embodiments illustrate a method for preparing a TOPCon battery disclosed in this invention.

[0164] Example 1: S1. Pre-treatment of single-crystal silicon substrate polishing: The single-crystal silicon substrate is pre-treated with NaOH or KOH solution at a concentration of 15wt%, a temperature of 75℃, and a time of 250s.

[0165] S2. PECVD method for frontal deposition of the first tunneling oxide layer: chamber temperature 450℃, pressure 20000Pa; gas introduced: nitrous oxide (N2O) flow rate 15000sccm; radio frequency power 15000W, deposition time 200s; thickness 1.5nm.

[0166] S3. PECVD method for front-side deposition of the first gallium-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane (SiH4) flow rate 6000sccm, gallium source TMG or TEG flow rate 10sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 50s; thickness 10nm, doping concentration 3×10⁻⁶ 17 cm -3 .

[0167] S4. PECVD method for front-side deposition of the second gallium-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane (SiH4) flow rate 5000sccm, gallium source TMG or TEG flow rate 20sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 100s; thickness 20nm, doping concentration 5×10⁻⁶ 17 cm -3 .

[0168] S5. PECVD method for front-side deposition of the first boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane SiH4 flow rate 5000sccm, boron source BF3, B2H6 or TMB flow rate 20sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 100s; thickness 20nm, doping concentration 2×10⁻⁶ 18 cm -3 .

[0169] S6. PECVD method for front-side deposition of the second boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 10000Pa; gas supply: silane SiH4 flow rate 4000sccm, boron source BF3, B2H6 or TMB flow rate 50sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 200s; thickness 40nm, doping concentration 5×10⁻⁶ 18 cm -3 .

[0170] S7. PECVD method for front-side deposition of the third boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 10000Pa; gas supply: silane SiH4 flow rate 3000sccm, boron source BF3, B2H6 or TMB flow rate 150sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 400s; thickness 100nm, doping concentration 5×10⁻⁶ 19 cm -3 .

[0171] S8. PECVD method for back-side deposition of second tunneling oxide layer: chamber temperature 450℃, pressure 20000Pa; gas introduced: nitrous oxide (N2O) flow rate 13000sccm; radio frequency power 15000W, deposition time 100s; thickness 1.3nm.

[0172] S9. Backside deposition of N-type doped polycrystalline silicon layer using PECVD method: chamber temperature 450℃, pressure 20000Pa; gas supply: silane SiH4 flow rate 2000sccm, phosphorus source PH3 flow rate 1000sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 700s; thickness 200nm, doping concentration 1×10⁻⁶ 19 cm -3 ~1×10 22 cm -3 .

[0173] S10, High-temperature annealing: Cavity temperature 900℃, pressure 8000Pa, O2 flow rate 5000sccm, N2 flow rate 20000sccm.

[0174] S11, Laser Frontal Graphics: Laser wavelength 532nm green picosecond, power 40W.

[0175] S12, Laser Backside Graphics: Laser wavelength 532nm green picosecond, power 40W.

[0176] S13. Double-sided polishing: Clean and polish the laser-treated silicon substrate using NaOH or KOH solution. The NaOH or KOH solution concentration is 20wt%, the temperature is 80℃, and the time is 200s.

[0177] S14. Texturing: NaOH or KOH solution concentration 15wt%, temperature 75℃, time 400s; additive 5L.

[0178] S15, ALD deposition of alumina thin films: temperature 200℃, pressure 50 Torr, N2 flow rate 800 sccm; TMA pulse 7ms, DI water pulse 8ms, number of cycles 40.

[0179] S16, PECVD front-side SiNx thin film deposition: chamber temperature 500℃, pressure 1000Pa; gas flow: silane SiH4 flow rate 500sccm, NH3 flow rate 4000sccm, N2O flow rate 7000sccm, N2 flow rate 10000sccm; RF power 5000W, deposition time 500s; thickness 80nm.

[0180] S17, PECVD backside SiNx thin film deposition: chamber temperature 500℃, pressure 1000Pa; gas introduced: silane SiH4 flow rate 700sccm, NH3 flow rate 6000sccm, N2O flow rate 6000sccm, N2 flow rate 15000sccm; RF power 6000W, deposition time 500s; thickness 80nm.

[0181] S18, Screen printing + sintering + photoinjection: ① Print main grid paste ② Print N sub-grid paste ③ Print P sub-grid paste ④ Sintering: Temperature 750℃, Time 20s; ⑤ Photoinjection.

[0182] Example 2: The difference between Example 2 and Example 1 is that in step S7, the flow rate of the boron source BF3, B2H6, or TMB is 300 sccm, and the doping concentration is 1×10⁻⁶. 20 cm -3 .

[0183] Example 3: The difference between Example 3 and Example 1 is that in step S3, the deposition time is 100s and the thickness is 20nm.

[0184] Example 4: The difference between Example 4 and Example 1 is that in step S3, the gallium source TMG or TEG flow rate is 5 sccm, the deposition time is 20 s, the thickness is 4 nm, and the doping concentration is 1×10⁻⁶. 17 cm -3 .

[0185] Example 5: The difference between Example 5 and Example 1 is that in step S4, the gallium source TMG or TEG flow rate is 50 sccm and the doping concentration is 7 × 10⁻⁶. 17 cm -3 .

[0186] Comparative Example 1: The difference between Comparative Example 1 and Example 1 is that steps S2-S7 are replaced by LPCVD front-side deposition of a first tunneling oxide layer and an intrinsic polysilicon layer, followed by boron diffusion to form a P-type doped polysilicon layer: ① First tunneling oxide layer: chamber temperature 600℃, pressure 600mbar, time 2000s, O2 flow rate 15000sccm; ② Intrinsic polysilicon layer: chamber temperature 580℃, pressure 200mbar, time 1500s, SiH4 flow rate 1000sccm. Boron diffusion: chamber temperature 950℃, pressure 200mbar, time 300s, O2 flow rate 5000sccm; BCl3 flow rate 200sccm, N2 flow rate 5000sccm.

[0187] The test results for eta (conversion efficiency), Voc (open-circuit voltage), Jsc (short-circuit current density), and FF (fill factor) are shown in Table 1.

[0188] Table 1 As shown in Table 1, compared with the test results of the battery in Comparative Example 1, the TOPCon battery disclosed in this invention effectively improves the open circuit voltage, fill factor and conversion efficiency.

[0189] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a stacked battery. For example... Figure 11 As shown, Figure 11 This is a cross-sectional structural diagram of a stacked battery disclosed in an embodiment of the present invention. The stacked battery includes a bottom battery 100 and a top battery 200 stacked together. The bottom battery 100 includes a TOPCon battery as disclosed in any of the above embodiments.

[0190] In some embodiments of the present invention, the top cell 200 includes a perovskite solar cell. The perovskite solar cell includes a first transparent conductive layer 203, a first charge transport layer 204, a perovskite light-absorbing layer 205, a second charge transport layer 206, a second transparent conductive layer 207, and an electrode 208, which are sequentially stacked. One of the first charge transport layer 204 and the second charge transport layer 206 is an electron transport layer, and the other is a hole transport layer. As an example, the first charge transport layer 204 is an electron transport layer, and the second charge transport layer 206 is a hole transport layer. Of course, the present invention is not limited to this; in other embodiments, the top cell 200 may also include other solar cells, which will not be elaborated here.

[0191] In some embodiments of the present invention, the stacked battery further includes a component glass 201 and a barrier layer 202, wherein the barrier layer 202 is located on the side of the first transparent conductive layer 203 away from the first charge transport layer 204, and the component glass 201 is located on the side of the barrier layer 202 away from the first transparent conductive layer 203.

[0192] In some embodiments of the present invention, the stacked battery further includes a backplate 300, a first adhesive film 400, and a second adhesive film 500. The front side of the bottom battery 100 is bonded to the top battery 200 through the first adhesive film 400, and the back side of the bottom battery is bonded to the backplate 300 through the second adhesive film 500.

[0193] As an optional implementation of the disclosed content of this invention, an embodiment of this invention discloses a method for preparing a stacked battery, which can prepare a stacked battery as disclosed in any of the above embodiments. The method for preparing the stacked battery includes steps S210 to S230: S210, bottom cell fabrication.

[0194] In some embodiments of the present invention, the bottom battery includes a TOPCon battery, which is prepared using the TOPCon battery preparation method disclosed in any of the above embodiments.

[0195] S220, top cell fabrication.

[0196] In some embodiments of the present invention, the top cell includes a perovskite solar cell.

[0197] The following describes step S220 in detail, using a perovskite solar cell as the top cell example. Step S220 includes steps S221 to S228: S221, Component glass fixing.

[0198] The module glass is horizontally fixed on a temperature-controlled, dust-free stage. The frame around the module is sealed with high-temperature resistant silicone strips, exposing only the effective area of ​​the module glass. For example, the stage preheating temperature is 30~60℃, the ambient humidity is ≤40%RH, and the cleanliness level is Class 1000. The module glass uses tempered ultra-clear front glass with a light transmittance ≥92% and a thickness of 1~5mm.

[0199] S222, Pretreatment of component glass surface.

[0200] ① Glass surface cleaning: Low-temperature plasma cleaning is used to remove organic matter, particles, and moisture from the glass surface. For example, the power is 50-200W, the pressure of the O2 and Ar mixed gas is 50-200Pa, and the time is 20-200s.

[0201] ② Second cleaning: Use a mixture of anhydrous ethanol and isopropanol for low-temperature spraying, followed by low-speed drying with high-purity nitrogen. High-temperature baking is prohibited to avoid damaging the internal encapsulant and electrodes of the component. For example, the ratio of anhydrous ethanol to isopropanol is 1:1, the spraying temperature is 20-30°C, and the nitrogen purity is 99.999%.

[0202] ③ Barrier layer preparation: An ultrathin Al2O3 film was deposited using the ALD method as a barrier layer to form a dense ion-barrier layer. As an example, the temperature ranged from 50 to 500 °C, the TMA pulse duration was 10 to 100 ms, the DI water pulse duration was 10 to 100 ms, the number of cycles was 10 to 50, and the film thickness was 2 to 6 nm.

[0203] ④ Preparation of the first transparent conductive layer: Magnetron sputtering of ITO serves as the first transparent conductive layer, providing a good conductive path for perovskite solar cells. As an example, the temperature ranges from 50 to 200°C, the power output from 50 to 100 W, and the film thickness from 50 to 150 nm.

[0204] ⑤ Low-temperature annealing: As an example, the temperature is 50~200℃, the pressure is 50~500mbarr, and the time is 10~50min.

[0205] S223, Electron transport layer fabrication (ETL).

[0206] ① Coating / Spin Coating: SnO2 nanocolloid solution is used for slit coating / spin-coating to ensure uniform coating and no pinholes. As an example, the SnO2 nanocolloid solution has a concentration of 15~20wt% and is an ethanol / water mixed solvent; the coating / spin-coating speed is 50~80mm / s and the wet film thickness is 300~500nm.

[0207] ② Low-temperature annealing: As an example, the temperature is 90~110℃, the atmosphere is air, and the time is 10~15min; the ETL thickness after annealing is 10~50nm.

[0208] ③ Post-processing: Oxygen plasma modification reduces surface defects and enhances electron extraction capabilities, adapting to the carrier transport requirements of perovskite light-absorbing layers. As an example, the power is 50-80W, and the duration is 30-60s.

[0209] S224, preparation of perovskite light-absorbing layer.

[0210] As an example, a perovskite precursor solution: Cs x FA 1-x Pb(I 1-y Br y)3, band gap 1.69~1.73eV, x=0.05-0.15, y=0.25-0.35; solvent DMF / DMSO: volume ratio 4:1, concentration 1.2~1.5mol / L, with 5~10mol% MACl added as a crystallization regulator to improve the crystallization quality and stability of perovskite films.

[0211] ① Coating: Slot coating / dossler coating should be used to ensure uniform coating without any missed areas or thick edges. For example, the wet film thickness should be 400~600 nm, the ambient temperature 25±3℃, and the humidity ≤25%RH.

[0212] ② Antisolvent extraction: Within 3-5 seconds after coating, spray a chlorobenzene / ethyl ether mixed antisolvent (volume ratio 9:1) to quickly extract the solvent, induce uniform crystallization, and reduce defects in the perovskite film.

[0213] ③ Low-temperature annealing: Step 1: Remove residual solvent by applying pressure at 70±5℃ and 10-20 mbar for 10 minutes. Step 2: Temperature 110±5℃, nitrogen protection, time 15-20min, to complete perovskite crystallization.

[0214] The film thickness is 400~600nm, and the grain size is 300~800nm.

[0215] ④ Optical inspection: Controlling the transmittance of the effective area to 29-31% adapts to the long-wave absorption of the module, maximizing the overall efficiency of the stacked module.

[0216] S225, Hole Transport Layer (HTL) fabrication.

[0217] PTAA / SAM composite was selected as the hole transport layer.

[0218] ① Self-assembled monolayer (SAM) spraying: As an example, the isopropanol concentration was 0.5~1 mmol / L, and the self-assembly was carried out at room temperature for 30~60 seconds, followed by drying with nitrogen.

[0219] ② Slit coating with PTAA toluene solution: As an example, the concentration of PTAA toluene solution is 8~12 mg / mL, and the wet film thickness is 200~300 nm.

[0220] ③ Annealing: As an example, an ultrathin HTL with a thickness of 10~15nm was formed at a temperature of 100±5℃, a nitrogen atmosphere, and a time of 10min.

[0221] S226, Preparation of the second transparent conductive layer.

[0222] ① Evaporation of an ultra-thin Ag layer (to reduce costs): As an example, the thickness is 8~12nm and the speed is 0.5~1Å / s.

[0223] ② Evaporated ITO coating: As an example, the thickness is 40~60nm, the temperature is 90~100℃, and the speed is 1~2Å / s.

[0224] Electrode parameters: sheet resistance 40~60Ω / □, visible light transmittance ≥75%, cavity vacuum pressure ≤5×10 -4 Pa.

[0225] S227, laser etching.

[0226] As an example, laser: infrared picosecond laser, wavelength 1064nm, power 3~5W, spot diameter 15~25μm.

[0227] ① Etch through the first transparent conductive layer + ETL to isolate the negative electrode of adjacent sub-cells and avoid short circuits; ②Etch through the perovskite light absorption layer + HTL to connect the positive electrode of the front sub-cell to the negative electrode of the rear sub-cell, thus realizing the series connection of sub-cells; ③ A fully functional layer is etched through the edge to form edge isolation, with a dead zone width ≤80μm, improving the overall efficiency of the top cell.

[0228] S228, Electrode bus and edge insulation.

[0229] ① Printing silver paste: Low-temperature conductive silver paste is used to print busbars on the positive and negative terminal areas of the top cell, ensuring a tight connection between the busbars and the top electrode. As an example, the curing temperature is 30~120℃, and the printed electrode width is 1~2mm, with a thickness of 10~30μm.

[0230] ②Curing: As an example, the temperature was 105±5℃, the time was 10~50min, and the atmosphere was nitrogen.

[0231] ③ Edge processing: The area around the battery's perimeter, 2-3mm in diameter, is sealed with UV-cured insulating adhesive to prevent moisture intrusion and to avoid edge plating and leakage.

[0232] Fabrication of S230, bottom cell and top cell stacked module.

[0233] The following describes step S230 in detail with reference to a specific embodiment. Step S230 includes steps S231 and S232: S231, Stringing and Layout.

[0234] ① Printed insulating adhesive: Insulating adhesive is printed on the non-electrode area of ​​the back of the bottom battery using screen printing. As an example, the insulating adhesive is a low-temperature curing resin adhesive with a line width of 0.1~1mm and a printing thickness of 5~50μm; post-printing curing: temperature 30~100℃, time 2~20min.

[0235] ② Printing solder paste: Print solder paste on the main grid and PAD points. Solder paste: low temperature lead-free, melting point 150~300℃, printing thickness 10~50μm; drying after printing: temperature 30~100℃, time 2~20min.

[0236] ③ String soldering: The bottom cells are connected in series using solder ribbon. Solder ribbon: low-temperature tin-plated copper solder ribbon, 0.1~1mm wide, 0.05~0.5mm thick; soldering temperature 100~300℃, soldering time 2~20s.

[0237] ④ Layout: Arrange the wire-welded battery strings according to the module type, with a cell spacing of 1~5mm and an overall flatness error of ≤0.5mm.

[0238] S232, Component encapsulation.

[0239] ① Packaging material installation: In the second stage, an EVA or POE film is laid on the glass and top cell of the module. The arranged bottom cell string is then placed on the film, ensuring a tight fit between the bottom cell string and the glass and film, free of bubbles and misalignment. Subsequently, another layer of EVA or POE film is laid on the back of the cell string, and finally, a backsheet is covered. As an example, the EVA or POE film thickness is 0.1~1mm.

[0240] ②Lamination: The laid components are placed into a laminator, and a segmented lamination process is used. Preheating: temperature 50~200℃, time 1~10min; pressurization: temperature 50~200℃, pressure 0.1~2MPa, time 10~100min; cooling: temperature ≤50℃, time 1~10min.

[0241] ③ Edge trimming and cleaning: After lamination, trim any excess EVA or POE film from the edges of the module to ensure that the edges are smooth and burr-free. Then, use a lint-free cloth dampened with anhydrous ethanol to clean the surface of the module and remove any remaining film to prevent residual impurities from affecting the subsequent fabrication of the top cell.

[0242] ④ Frame mounting and junction box installation: An aluminum alloy frame is installed around the module, and the connection between the frame and the glass and back panel is sealed with sealant to ensure a tight seal and block moisture and oxygen. A junction box is installed on the back of the module, and the positive and negative leads of the bottom battery series are connected to the junction box to ensure that the wiring is firm and well insulated, avoiding the risk of short circuit.

[0243] ⑤ Component finished product testing: The encapsulated bottom and top battery stacked modules were subjected to EL and IV tests, and no dark spots, leakage current, or sealing performance were found to be qualified.

[0244] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0245] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A TOPCon battery, characterized in that, include: A silicon substrate having a first surface and a second surface disposed opposite to each other; A first tunneling oxide layer is located on the first surface; A P-type doped polysilicon layer is located on the side of the first tunneling oxide layer away from the silicon substrate. The P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a doped polysilicon layer stacked sequentially. The doping element of the doped polysilicon layer includes at least boron. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, and the doping concentration of the doped polysilicon layer gradually increases. A second tunneling oxide layer is located on the second surface; An N-type doped polycrystalline silicon layer is located on the side of the second tunneling oxide layer away from the silicon substrate; The first electrode is in contact with the P-type doped polycrystalline silicon layer; The second electrode is in contact with the N-type doped polycrystalline silicon layer.

2. The TOPCon battery according to claim 1, characterized in that, The doped polycrystalline silicon layer includes at least one of boron-doped polycrystalline silicon layer and gallium-boron-doped polycrystalline silicon layer.

3. The TOPCon battery according to claim 1, characterized in that, The doped polysilicon layer comprises a plurality of doped polysilicon sublayers stacked sequentially, and the doping element of each doped polysilicon sublayer includes at least boron; the doping concentration of the plurality of doped polysilicon sublayers increases sequentially in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer; and / or, The gallium-doped polysilicon layer includes a plurality of gallium-doped polysilicon sub-layers stacked sequentially; in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the plurality of gallium-doped polysilicon sub-layers increases sequentially.

4. The TOPCon battery according to claim 3, characterized in that, In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the thickness of the plurality of doped polysilicon sublayers increases sequentially, and / or the thickness of the plurality of gallium-doped polysilicon sublayers increases sequentially.

5. The TOPCon battery according to claim 1, characterized in that, The gallium-doped polysilicon layer has a doping concentration of 1×10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ; and / or, The gallium-doped polycrystalline silicon layer comprises a first gallium-doped polycrystalline silicon sublayer and a second gallium-doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first gallium-doped polycrystalline silicon sublayer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 17 cm -3 ~1×10 18 cm -3 ; and / or, The doping concentration of the doped polycrystalline silicon layer is 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 ; and / or, The doped polycrystalline silicon layer comprises a first doped polycrystalline silicon sublayer, a second doped polycrystalline silicon sublayer, and a third doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first doped polycrystalline silicon sublayer is 1×10⁻⁶. 18 cm -3 ~5×10 18 cm -3 The doping concentration of the second doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The doping concentration of the third doped polycrystalline silicon sublayer is 1×10⁻⁶. 19 cm -3 ~1×10 20 cm -3 .

6. The TOPCon battery according to claim 1, characterized in that, The TOPCon battery also includes: The intrinsic polysilicon layer is located between the first tunneling oxide layer and the P-type doped polysilicon layer.

7. The TOPCon battery according to any one of claims 1-6, characterized in that, The first surface includes alternating first metallized regions and first non-metallized regions, with the first tunneling oxide layer located in the first metallized region; the second surface includes alternating second metallized regions and second non-metallized regions, with the second tunneling oxide layer located in the second metallized region. The silicon substrate includes a P-type diffusion region located in the first non-metallization region, and the doping concentration of the P-type diffusion region is less than the doping concentration of the P-type doped polysilicon layer.

8. A method for preparing a TOPCon battery, characterized in that, include: A silicon substrate is provided, the silicon substrate having a first surface and a second surface disposed opposite to each other; A first tunneling oxide layer and a P-type doped polysilicon layer are sequentially stacked on the first surface; the P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a doped polysilicon layer sequentially stacked, the doping element of the doped polysilicon layer includes at least boron, and the doping concentration of the gallium-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, and the doping concentration of the doped polysilicon layer gradually increases; A second tunneling oxide layer and an N-type doped polycrystalline silicon layer are sequentially stacked on the second surface; A first electrode and a second electrode are formed, wherein the first electrode is in contact with the P-type doped polysilicon layer and the second electrode is in contact with the N-type doped polysilicon layer.

9. The method for preparing a TOPCon battery according to claim 8, characterized in that, During the formation of the gallium-doped polycrystalline silicon layer, silane, a gallium source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 5 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the RF power is 1000 W to 30000 W; and / or, During the formation of the doped polycrystalline silicon layer, silane, a boron source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 1 sccm to 300 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500Pa to 50000Pa, and the radio frequency power is 1000W to 30000W.

10. A stacked battery, characterized in that, It includes a bottom battery and a top battery stacked together, wherein the bottom battery includes the TOPCon battery as described in any one of claims 1-7.

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