Back contact battery, preparation method and tandem battery

Abstract

This invention discloses a back-contact solar cell, its fabrication method, and a tandem solar cell, relating to the field of photovoltaic technology. The back-contact solar cell includes: a silicon substrate with a first surface comprising a first region and a second region; a first tunneling oxide layer located in the first region; a P-type doped polycrystalline silicon layer located on the side of the first tunneling oxide layer away from the silicon substrate; the P-type doped polycrystalline silicon layer includes a gallium-doped polycrystalline silicon layer and a boron-doped polycrystalline silicon layer stacked sequentially, with the doping concentration of the gallium-doped polycrystalline silicon layer gradually increasing from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, and the doping concentration of the boron-doped polycrystalline silicon layer gradually increasing; a second tunneling oxide layer located in the second region; and an N-type doped polycrystalline silicon layer located on the side of the second tunneling oxide layer away from the silicon substrate, thereby avoiding light-induced degradation caused by boron segregation, ensuring the passivation effect of the first tunneling oxide layer, improving the field passivation capability and contact resistance of the P-type doped polycrystalline silicon layer, and improving the conversion efficiency of the solar cell.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, specifically to a back-contact cell, its preparation method, and a tandem cell. Background Technology

[0002] In related technologies, the P-type doped polycrystalline silicon layer in back-contact batteries (such as TBC batteries) is a uniformly doped boron-doped polycrystalline silicon layer. However, boron tends to segregate towards the tunnel oxide interface and readily combines with oxygen at the interface to form BO complexes, inducing LID (Light-Induced Degradation) and simultaneously compromising the passivation effect of the tunnel oxide layer. Furthermore, uniformly doped boron-doped polycrystalline silicon layers have weak field passivation capabilities, reducing the battery's open-circuit voltage and conversion efficiency. Additionally, their high contact resistance with the metal electrode results in a poor fill factor, further impacting the battery's conversion efficiency. Summary of the Invention

[0003] This invention discloses a back-contact battery, its preparation method, and a stacked battery to solve the problems of light-induced degradation caused by boron segregation in the tunneling oxide layer, damage to the passivation effect of the tunneling oxide layer, and weak field passivation capability and poor contact resistance of the boron-doped polycrystalline silicon layer.

[0004] In a first aspect, the present invention discloses a back-contact battery, comprising: a silicon substrate having a first surface and a second surface disposed opposite to each other, the first surface comprising an alternately distributed first region and a second region; a first tunneling oxide layer located in the first region; a P-type doped polycrystalline silicon layer located on the side of the first tunneling oxide layer away from the silicon substrate; the P-type doped polycrystalline silicon layer comprising a gallium-doped polycrystalline silicon layer and a boron-doped polycrystalline silicon layer stacked sequentially, wherein the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases and the doping concentration of the boron-doped polycrystalline silicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer; a second tunneling oxide layer located in the second region; and an N-type doped polycrystalline silicon layer located on the side of the second tunneling oxide layer away from the silicon substrate.

[0005] In some embodiments of the present invention, the boron-doped polycrystalline silicon layer comprises a plurality of boron-doped polycrystalline silicon sub-layers stacked sequentially; in the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, the doping concentration of the plurality of boron-doped polycrystalline silicon sub-layers increases sequentially.

[0006] In some embodiments of the present invention, the thickness of the plurality of boron-doped polysilicon sublayers increases sequentially in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer.

[0007] In some embodiments of the present invention, the gallium-doped polysilicon layer includes a plurality of gallium-doped polysilicon sub-layers stacked sequentially; in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the plurality of gallium-doped polysilicon sub-layers increases sequentially.

[0008] In some embodiments of the present invention, the thickness of the plurality of gallium-doped polysilicon sub-layers increases sequentially in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer.

[0009] In some embodiments of the present invention, the doping concentration of the boron-doped polysilicon layer is greater than that of the gallium-doped polysilicon layer; and / or, the thickness of the boron-doped polysilicon layer is greater than that of the gallium-doped polysilicon layer.

[0010] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer is 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 ; and / or, the gallium-doped polysilicon layer comprises a first gallium-doped polysilicon sublayer, a second gallium-doped polysilicon sublayer, and a third gallium-doped polysilicon sublayer stacked sequentially, wherein the doping concentration of the first gallium-doped polysilicon sublayer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The doping concentration of the third gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0011] In some embodiments of the present invention, the doping concentration of the boron-doped polycrystalline silicon layer is 5 × 10⁻⁶. 19 cm -3 ~1×10 22 cm -3 ; and / or, the boron-doped polycrystalline silicon layer comprises a first boron-doped polycrystalline silicon sublayer, a second boron-doped polycrystalline silicon sublayer, and a third boron-doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first boron-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second boron-doped polycrystalline silicon sublayer is 1×10⁻⁶. 20 cm -3 ~5×10 20cm -3 The doping concentration of the third boron-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 20 cm -3 ~1×10 22 cm -3 .

[0012] In some embodiments of the present invention, the P-type doped polycrystalline silicon layer further includes a gallium-boron-doped polycrystalline silicon layer; the gallium-boron-doped polycrystalline silicon layer is located between the gallium-doped polycrystalline silicon layer and the boron-doped polycrystalline silicon layer.

[0013] In some embodiments of the present invention, the back contact battery further includes: an intrinsic polycrystalline silicon layer located between the first tunneling oxide layer and the P-type doped polycrystalline silicon layer.

[0014] In some embodiments of the present invention, the first surface further includes a spacer region located between the first region and the second region; the back contact battery further includes: a first passivation layer covering the P-type doped polysilicon layer, the N-type doped polysilicon layer and the spacer region; a second passivation layer located on the second surface; a first electrode penetrating the first passivation layer and in contact with the P-type doped polysilicon layer; and a second electrode penetrating the first passivation layer and in contact with the N-type doped polysilicon layer.

[0015] In a second aspect, the present invention discloses a method for fabricating a back-contact battery, comprising: providing a silicon substrate having a first surface and a second surface disposed opposite to each other, the first surface comprising an alternately distributed first region and a second region; sequentially stacking a first tunneling oxide layer and a P-type doped polycrystalline silicon layer in the first region; the P-type doped polycrystalline silicon layer comprising a gallium-doped polycrystalline silicon layer and a boron-doped polycrystalline silicon layer sequentially stacked, wherein the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases and the doping concentration of the boron-doped polycrystalline silicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer; and sequentially stacking a second tunneling oxide layer and an N-type doped polycrystalline silicon layer in the second region.

[0016] In some embodiments of the present invention, during the formation of the gallium-doped polycrystalline silicon layer, silane, a gallium source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 1 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500Pa to 50000Pa, and the radio frequency power is 1000W to 30000W.

[0017] In some embodiments of the present invention, during the formation of the boron-doped polycrystalline silicon layer, silane, a boron source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 50 sccm to 500 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the radio frequency power is 1000 W to 30000 W.

[0018] Thirdly, the present invention discloses a stacked battery, comprising a bottom battery and a top battery stacked together, wherein the bottom battery includes a back contact battery as described in the first aspect above.

[0019] This invention discloses a back-contact battery, its fabrication method, and a tandem battery. The P-type doped polycrystalline silicon layer includes a gallium-doped polycrystalline silicon layer and a boron-doped polycrystalline silicon layer stacked sequentially. Specifically, the gallium-doped polycrystalline silicon layer is positioned between a first tunneling oxide layer and a boron-doped polycrystalline silicon layer to prevent boron segregation into the first tunneling oxide layer, reduce BO recombination defects, avoid light-induced degradation, and ensure the passivation effect of the first tunneling oxide layer, thereby improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, the doping concentration of the gallium-doped polycrystalline silicon layer gradually increases, and the doping concentration of the boron-doped polycrystalline silicon layer gradually increases, improving carrier extraction, enhancing the field passivation capability of the P-type doped polycrystalline silicon layer, further improving the open-circuit voltage and conversion efficiency of the battery, and also improving the contact resistance of the P-type doped polycrystalline silicon layer, increasing the fill factor, and further improving the conversion efficiency of the battery. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0021] Figure 1 This is a schematic diagram of the first cross-sectional structure of a back contact battery disclosed in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the second cross-sectional structure of a back contact battery disclosed in an embodiment of the present invention.

[0023] Figure 3 This is a flowchart of a method for preparing a back contact battery according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the first cross-sectional structure during the fabrication process of a back contact battery disclosed in an embodiment of the present invention.

[0025] Figure 5 This is a second cross-sectional structural diagram of the fabrication process of a back contact battery disclosed in an embodiment of the present invention.

[0026] Figure 6 This is a third cross-sectional structural diagram of the fabrication process of a back contact battery disclosed in an embodiment of the present invention.

[0027] Figure 7 This is a fourth cross-sectional structural diagram of the fabrication process of a back contact battery disclosed in an embodiment of the present invention.

[0028] Figure 8 This is a fifth cross-sectional structural diagram of the fabrication process of a back contact battery disclosed in an embodiment of the present invention.

[0029] Figure 9 This is a cross-sectional structural diagram of a stacked battery disclosed in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0031] Tunneling oxide passivation contact technology (TOPCon) consists of an ultrathin tunneling oxide layer and a doped polycrystalline silicon layer. It can significantly reduce surface recombination in crystalline silicon cells and improve open-circuit voltage and conversion efficiency. The fabrication method for back-contact cells (such as TBC cells) in related technologies involves first oxidizing an ultrathin SiOx layer at high temperature on a silicon substrate as a tunneling oxide layer. Then, intrinsic polycrystalline silicon is deposited on the tunneling oxide layer, and phosphorus / boron elements are doped into the intrinsic polycrystalline silicon using a diffusion method to form N-type doped polycrystalline silicon (phosphorus doping) / P-type doped polycrystalline silicon (boron doping).

[0032] However, the segregation coefficient of boron in Si / SiOx is approximately 1 / 10. During the cooling process after high temperature, boron tends to segregate towards the tunneling oxide layer interface, forming BO complexes with oxygen at the interface. This induces photo-induced degradation and simultaneously impairs the passivation effect of the tunneling oxide layer, reducing the open-circuit voltage and conversion efficiency of the battery. Furthermore, the uniform boron doping in P-type doped polycrystalline silicon results in weak field passivation capability, further reducing the open-circuit voltage and conversion efficiency of the battery. Additionally, the higher contact resistance with the metal electrode leads to a poorer fill factor, impacting the battery's conversion efficiency.

[0033] Based on this, the present invention discloses a back-contact battery and its fabrication method, as well as a tandem battery. By setting a gallium-doped polysilicon layer between the first tunneling oxide layer and the boron-doped polysilicon layer, boron segregation into the first tunneling oxide layer is avoided, reducing BO recombination defects and preventing light-induced degradation. At the same time, the passivation effect of the first tunneling oxide layer is ensured, improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, and the doping concentration of the boron-doped polysilicon layer gradually increases, improving carrier extraction, enhancing the field passivation capability of the P-type doped polysilicon layer, further improving the open-circuit voltage and conversion efficiency of the battery, and improving the contact resistance of the P-type doped polysilicon layer, increasing the fill factor, and further improving the conversion efficiency of the battery.

[0034] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a back contact battery, which can be a TBC (Tunnel Oxide Passivated Back Contact) battery.

[0035] like Figure 1 As shown, Figure 1 This is a cross-sectional structural diagram of a back contact battery disclosed in an embodiment of the present invention. The back contact battery includes a silicon substrate 1, a first tunneling oxide layer 2, a P-type doped polycrystalline silicon layer 3, a second tunneling oxide layer 4, and an N-type doped polycrystalline silicon layer 5.

[0036] The silicon substrate 1 has a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 includes alternating first regions 111 and second regions 112. The first surface 11 is the backlight surface (back side), and the second surface 12 is the light-receiving surface (front side). The first region 111 is a P-region, and the second region 112 is an N-region. The silicon substrate 1 can be N-type or P-type doped. As an example, the silicon substrate 1 is an N-type single-crystal silicon substrate.

[0037] The first tunneling oxide layer 2 is located in the first region 111. The material of the first tunneling oxide layer 2 includes silicon oxide (SiOx). The thickness of the first tunneling oxide layer 2 is 0.5 nm to 2 nm. The relatively thin thickness of the first tunneling oxide layer 2 allows charge carriers to pass through via quantum tunneling, while effectively chemically passivating the dangling bonds on the surface of the silicon substrate 1, reducing the interface state density.

[0038] The P-type doped polysilicon layer 3 is located on the side of the first tunneling oxide layer 2 away from the silicon substrate 1. The P-type doped polysilicon layer 3 includes a gallium-doped polysilicon layer 31 and a boron-doped polysilicon layer 32 stacked sequentially. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the boron-doped polysilicon layer 32 gradually increases.

[0039] In this configuration, the gallium-doped polysilicon layer 31 is positioned close to the first tunneling oxide layer 2. The gallium-doped polysilicon layer 31 can be a single-layer structure or a stacked structure. The dopant element in the gallium-doped polysilicon layer 31 is gallium, and the doping concentration of the gallium-doped polysilicon layer 31 refers to the gallium doping concentration. Along the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the gallium doping concentration in the gallium-doped polysilicon layer 31 gradually increases; that is, the closer to the first tunneling oxide layer 2, the lower the gallium doping concentration; and the farther away from the first tunneling oxide layer 2, the higher the gallium doping concentration. Here, "gradually increasing" can refer to a continuous increase or a gradient increase. A gradient increase can refer to a uniform gradient increase or a non-uniform gradient increase.

[0040] The boron-doped polysilicon layer 32 is positioned away from the first tunneling oxide layer 2. The boron-doped polysilicon layer 32 can be a single-layer structure or a multilayer structure. The dopant element in the boron-doped polysilicon layer 32 is boron, and the doping concentration of the boron-doped polysilicon layer 32 can refer to the boron doping concentration. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the boron doping concentration in the boron-doped polysilicon layer 32 gradually increases; that is, the closer to the first tunneling oxide layer 2, the lower the boron doping concentration; and the farther away from the first tunneling oxide layer 2, the higher the boron doping concentration. Here, "gradually increasing" can refer to a continuous increase or a gradient increase. A gradient increase can refer to a uniform gradient increase or a non-uniform gradient increase.

[0041] Since the segregation coefficient of gallium in Si / SiOx is approximately 20 / 1, meaning that a large amount of gallium will remain in the polycrystalline silicon, the gallium-doped polycrystalline silicon layer 31 is positioned close to the first tunneling oxide layer 2 to avoid segregation problems and prevent boron segregation into the first tunneling oxide layer 2, thereby reducing BO recombination defects and preventing light-induced degradation. At the same time, it ensures the passivation effect of the first tunneling oxide layer 2, improving the open-circuit voltage (Voc) and conversion efficiency of the battery. Furthermore, the function of the P-type doped polysilicon layer 3 is to realize the transport of charge carriers (holes). In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the boron-doped polysilicon layer 32 gradually increases. This can form a stepped energy band inside the P-type doped polysilicon layer 3, thereby accelerating the transport of charge carriers, improving the extraction of charge carriers, thereby improving the field passivation capability of the P-type doped polysilicon layer 3, further improving the open-circuit voltage and conversion efficiency of the battery, and improving the contact resistance of the P-type doped polysilicon layer, increasing the fill factor, and further improving the conversion efficiency of the battery.

[0042] The second tunneling oxide layer 4 is located in the second region 112. The material of the second tunneling oxide layer 4 includes silicon oxide (SiOx) and the like.

[0043] The N-type doped polysilicon layer 5 is located on the side of the second tunneling oxide layer 4 facing away from the silicon substrate 1. In some embodiments of the present invention, the N-type doped polysilicon layer 5 includes a phosphorus-doped polysilicon layer. The doping element of the phosphorus-doped polysilicon layer is phosphorus. Of course, the present invention is not limited thereto. In other embodiments, the N-type doped polysilicon layer 5 may also be doped with group V elements such as arsenic, which will not be elaborated here.

[0044] In some embodiments of the present invention, the boron-doped polysilicon layer 32 includes a plurality of boron-doped polysilicon sublayers 321 stacked sequentially. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the plurality of boron-doped polysilicon sublayers 321 increases sequentially.

[0045] Among the multiple boron-doped polycrystalline silicon sublayers 321, the boron-doped polycrystalline silicon sublayer 321 closest to the gallium-doped polycrystalline silicon layer 31 has the lowest doping concentration, while the boron-doped polycrystalline silicon sublayer 321 furthest from the gallium-doped polycrystalline silicon layer 31 has the highest doping concentration. The doping concentration is uniform within each boron-doped polycrystalline silicon sublayer 321.

[0046] For example Figure 1 As shown, the boron-doped polysilicon layer 32 includes a first boron-doped polysilicon sublayer 321a, a second boron-doped polysilicon sublayer 321b, and a third boron-doped polysilicon sublayer 321c, which are stacked sequentially. Specifically, the first boron-doped polysilicon sublayer 321a is positioned close to the gallium-doped polysilicon layer 31, the third boron-doped polysilicon sublayer 321c is positioned away from the gallium-doped polysilicon layer 31, and the second boron-doped polysilicon sublayer 321b is located between the first boron-doped polysilicon sublayer 321a and the third boron-doped polysilicon sublayer 321c. The doping concentration of the first boron-doped polysilicon sublayer 321a, the second boron-doped polysilicon sublayer 321b, and the third boron-doped polysilicon sublayer 321c gradually increases. Of course, the present invention is not limited to this; in other embodiments, the boron-doped polysilicon layer 32 may also include two or more boron-doped polysilicon sublayers 321, which will not be elaborated further here.

[0047] The boron-doped polycrystalline silicon layer 32 is composed of multiple boron-doped polycrystalline silicon sub-layers 321 with progressively increasing doping concentrations. The process is highly controllable. By adjusting the number of boron-doped polycrystalline silicon sub-layers 321 and the concentration difference, the required boron-doped polycrystalline silicon layer 32 can be flexibly designed to meet the requirements of different silicon substrate resistivity or different cell structures for field passivation strength and conductivity.

[0048] In some embodiments of the present invention, the thicknesses of the multiple boron-doped polycrystalline silicon sublayers 321 are the same or different.

[0049] In some embodiments of the present invention, the thickness of a plurality of boron-doped polysilicon sublayers 321 increases sequentially in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3.

[0050] Among the multiple boron-doped polycrystalline silicon sublayers 321, the boron-doped polycrystalline silicon sublayer 321 closest to the gallium-doped polycrystalline silicon layer 31 has the lowest doping concentration and the smallest thickness, while the boron-doped polycrystalline silicon sublayer 321 furthest from the gallium-doped polycrystalline silicon layer 31 has the highest doping concentration and the largest thickness.

[0051] For example Figure 1 As shown, the doping concentrations of the first boron-doped polycrystalline silicon sublayer 321a, the second boron-doped polycrystalline silicon sublayer 321b, and the third boron-doped polycrystalline silicon sublayer 321c increase sequentially, and their thicknesses also increase sequentially.

[0052] The boron-doped polycrystalline silicon layer 32 consists of multiple boron-doped polycrystalline silicon sub-layers 321 with successively increasing doping concentration and thickness, which further improves carrier extraction and field passivation capability.

[0053] In some embodiments of the present invention, such as Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a plurality of gallium-doped polysilicon sublayers 311 stacked sequentially. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the plurality of gallium-doped polysilicon sublayers 311 increases sequentially.

[0054] Among the multiple gallium-doped polycrystalline silicon sublayers 311, the gallium-doped polycrystalline silicon sublayer 311 closest to the first tunneling oxide layer 2 has the lowest doping concentration, while the gallium-doped polycrystalline silicon sublayer 311 furthest from the first tunneling oxide layer 2 has the highest doping concentration. The doping concentration is uniform within each gallium-doped polycrystalline silicon sublayer 311.

[0055] For example Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a, a second gallium-doped polysilicon sublayer 311b, and a third gallium-doped polysilicon sublayer 311c, which are stacked sequentially. Specifically, the first gallium-doped polysilicon sublayer 311a is disposed close to the first tunneling oxide layer 2, the third gallium-doped polysilicon sublayer 311c is disposed away from the first tunneling oxide layer 2, and the second gallium-doped polysilicon sublayer 311b is located between the first gallium-doped polysilicon sublayer 311a and the third gallium-doped polysilicon sublayer 311c. The doping concentration of the first gallium-doped polysilicon sublayer 311a, the second gallium-doped polysilicon sublayer 311b, and the third gallium-doped polysilicon sublayer 311c gradually increases. Of course, the present invention is not limited to this; in other embodiments, the gallium-doped polysilicon layer 31 may also include two or more gallium-doped polysilicon sublayers 311, which will not be elaborated further here.

[0056] The gallium-doped polycrystalline silicon layer 31 is composed of multiple gallium-doped polycrystalline silicon sub-layers 311 with progressively increasing doping concentration. The process is highly controllable. By adjusting the number of gallium-doped polycrystalline silicon sub-layers 311 and the concentration difference, the required gallium-doped polycrystalline silicon layer 31 can be flexibly designed.

[0057] In some embodiments of the present invention, the thicknesses of the plurality of gallium-doped polycrystalline silicon sublayers 311 may be the same or different. The thicknesses of the gallium-doped polycrystalline silicon sublayers 311 and the boron-doped polycrystalline silicon sublayers 321 may be the same or different.

[0058] In some embodiments of the present invention, the thickness of a plurality of gallium-doped polysilicon sublayers 311 increases sequentially in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3.

[0059] Among the multiple gallium-doped polycrystalline silicon sublayers 311, the gallium-doped polycrystalline silicon sublayer 311 closest to the first tunneling oxide layer 2 has the lowest doping concentration and the smallest thickness, while the gallium-doped polycrystalline silicon sublayer 311 furthest from the first tunneling oxide layer 2 has the highest doping concentration and the largest thickness.

[0060] For example Figure 2 As shown, the doping concentrations of the first gallium-doped polycrystalline silicon sublayer 311a, the second gallium-doped polycrystalline silicon sublayer 311b, and the third gallium-doped polycrystalline silicon sublayer 311c increase sequentially, and their thicknesses also increase sequentially.

[0061] The gallium-doped polycrystalline silicon layer 31 consists of multiple gallium-doped polycrystalline silicon sub-layers 311 with successively increasing doping concentration and thickness, which further improves carrier extraction and field passivation capability.

[0062] In some embodiments of the present invention, the doping concentration of the boron-doped polysilicon layer 32 is greater than the doping concentration of the gallium-doped polysilicon layer 31. The minimum doping concentration of the boron-doped polysilicon layer 32 can be greater than the maximum doping concentration of the gallium-doped polysilicon layer 31. It should be noted that the minimum doping concentration of the boron-doped polysilicon layer 32 can also be equal to the maximum doping concentration of the gallium-doped polysilicon layer 31, ensuring that the overall doping concentration of the boron-doped polysilicon layer 32 is greater than the overall doping concentration of the gallium-doped polysilicon layer 31.

[0063] In the case where the boron-doped polysilicon layer 32 includes a plurality of boron-doped polysilicon sublayers 321 and the gallium-doped polysilicon layer 31 includes a plurality of gallium-doped polysilicon sublayers 311, the doping concentration of the boron-doped polysilicon sublayer 321 closest to the gallium-doped polysilicon layer 31 is greater than or equal to the doping concentration of the gallium-doped polysilicon sublayer 311 closest to the boron-doped polysilicon layer 32.

[0064] The doping concentration of the boron-doped polysilicon layer 32 is aligned with that of the gallium-doped polysilicon layer 31, so that the P-type doped polysilicon layer 3 forms a gradient band structure with increasing valence band energy levels, which further improves carrier extraction and field passivation capability.

[0065] In some embodiments of the present invention, the doping concentration of the P-type doped polysilicon layer 3 is 1×10⁻⁶. 17 cm -3 ~1×10 22 cm -3 The doping concentration of the p-type doped polysilicon layer 3 is 1×10⁻⁶.17 cm -3 ~1×10 22 cm -3 The doping concentration varies between these values. The minimum doping concentration of the P-type doped polysilicon layer 3 is not less than 1 × 10⁻⁶. 17 cm -3 The maximum doping concentration of the P-type doped polysilicon layer 3 is no greater than 1 × 10⁻⁶. 22 cm -3 .

[0066] The doping concentration of the P-type doped polycrystalline silicon layer 3 varies within the above range, which can balance passivation performance, conductivity and process feasibility.

[0067] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 The doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 The doping concentration varies between these values. The minimum doping concentration of the gallium-doped polysilicon layer 31 is not less than 1 × 10⁻⁶. 17 cm -3 The maximum doping concentration of the gallium-doped polysilicon layer 31 is no greater than 5 × 10⁻⁶. 19 cm -3 The doping concentration of the boron-doped polycrystalline silicon layer 32 is 5 × 10⁻⁶. 19 cm -3 ~1×10 22 cm -3 The doping concentration of the boron-doped polycrystalline silicon layer 32 is 5 × 10⁻⁶. 19 cm -3 ~1×10 22 cm -3 The doping concentration varies between these values. The minimum doping concentration of the boron-doped polycrystalline silicon layer 32 is not less than 5 × 10⁻⁶. 19 cm -3 The maximum doping concentration of the boron-doped polycrystalline silicon layer 32 is no greater than 1×10⁻⁶. 22 cm -3 .

[0068] Varying the doping concentrations of gallium-doped polysilicon layer 31 and boron-doped polysilicon layer 32 within the above range can significantly improve carrier extraction and significantly improve the field passivation capability of P-type doped polysilicon layer 3.

[0069] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a, a second gallium-doped polysilicon sublayer 311b, and a third gallium-doped polysilicon sublayer 311c stacked sequentially, the doping concentration of the first gallium-doped polysilicon sublayer 311a is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer 311b is 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The doping concentration of the third gallium-doped polycrystalline silicon sublayer 311c is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 This ensures an effective gradient distribution, which is easily achieved through a suitable process and can significantly improve carrier extraction and field passivation capability of the p-type doped polysilicon layer 3.

[0070] In some embodiments of the present invention, when the boron-doped polysilicon layer 32 includes a first boron-doped polysilicon sublayer 321a, a second boron-doped polysilicon sublayer 321b, and a third boron-doped polysilicon sublayer 321c stacked sequentially, the doping concentration of the first boron-doped polysilicon sublayer 321a is 5 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second boron-doped polycrystalline silicon sublayer 321b is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The doping concentration of the third boron-doped polycrystalline silicon sublayer 321c is 5 × 10⁻⁶. 20 cm -3 ~1×10 22 cm -3 This ensures an effective gradient distribution, which is easily achieved through a suitable process and can significantly improve carrier extraction and field passivation capability of the p-type doped polysilicon layer 3.

[0071] In some embodiments of the present invention, the thickness of the boron-doped polysilicon layer 32 is greater than the thickness of the gallium-doped polysilicon layer 31. When the boron-doped polysilicon layer 32 comprises multiple boron-doped polysilicon sub-layers 321, and the gallium-doped polysilicon layer 31 comprises multiple gallium-doped polysilicon sub-layers 311, the thickness of each boron-doped polysilicon sub-layer 321 can be greater than the thickness of the gallium-doped polysilicon sub-layer 311. Alternatively, the thickness of some boron-doped polysilicon sub-layers 321 can be greater than the thickness of the gallium-doped polysilicon sub-layer 311, while the thickness of the remaining boron-doped polysilicon sub-layers 321 is less than or equal to the thickness of the gallium-doped polysilicon sub-layer 311. No specific limitation is made here; it is sufficient to ensure that the overall thickness of the boron-doped polysilicon layer 32 is greater than the overall thickness of the gallium-doped polysilicon layer 31. As an example, the thickness of the boron-doped polysilicon sub-layer 321 closest to the gallium-doped polysilicon layer 31 is greater than the thickness of the gallium-doped polysilicon sub-layer 311 closest to the boron-doped polysilicon layer 32.

[0072] The gallium-doped polysilicon layer 31 primarily serves interface stability, and its thickness can be set relatively thin, sufficient to prevent boron segregation to the interface. The boron-doped polysilicon layer 32 undertakes the main tasks of conductivity and field passivation, requiring sufficient thickness to accommodate the high-concentration doped region and achieve low sheet resistance.

[0073] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a, a second gallium-doped polysilicon sublayer 311b, and a third gallium-doped polysilicon sublayer 311c stacked sequentially, the thickness of the first gallium-doped polysilicon sublayer 311a is 0.5 nm to 2 nm, the thickness of the second gallium-doped polysilicon sublayer 311b is 2 nm to 10 nm, and the thickness of the third gallium-doped polysilicon sublayer 311c is 10 nm to 30 nm. This ensures an effective gradient distribution, is easily implemented through suitable processes, and significantly improves carrier extraction and the field passivation capability of the p-type doped polysilicon layer 3.

[0074] In some embodiments of the present invention, when the boron-doped polysilicon layer 32 comprises a first boron-doped polysilicon sublayer 321a, a second boron-doped polysilicon sublayer 321b, and a third boron-doped polysilicon sublayer 321c stacked sequentially, the thickness of the first boron-doped polysilicon sublayer 321a is 10 nm to 30 nm, the thickness of the second boron-doped polysilicon sublayer 321b is 30 nm to 100 nm, and the thickness of the third boron-doped polysilicon sublayer 321c is 100 nm to 150 nm. This ensures an effective gradient distribution, is easily implemented through suitable processes, and significantly improves carrier extraction and field passivation capability of the p-type doped polysilicon layer 3.

[0075] In some embodiments of the present invention, the P-type doped polysilicon layer 3 may further include a gallium-boron-doped polysilicon layer, which is located between the gallium-doped polysilicon layer 31 and the boron-doped polysilicon layer 32. The doping concentration of the gallium-boron-doped polysilicon layer can be greater than that of the gallium-doped polysilicon layer 31 and less than that of the boron-doped polysilicon layer 32, thereby achieving a smooth transition between the gallium-doped polysilicon layer 31 and the boron-doped polysilicon layer 32, ensuring band continuity, smooth carrier transport, and reducing series resistance.

[0076] In some embodiments of the present invention, the doping concentration of the gallium-boron-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3. The doping elements of the gallium-boron-doped polysilicon layer are gallium and boron. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of gallium-boron co-doping in the gallium-boron-doped polysilicon layer gradually increases.

[0077] The gallium-boron-doped polysilicon layer is set with a gradient doping concentration to further improve the field passivation capability of the P-type doped polysilicon layer 3 and improve the conversion efficiency.

[0078] In some embodiments of the present invention, the back contact battery further includes an intrinsic polycrystalline silicon layer, which is located between the first tunneling oxide layer 2 and the P-type doped polycrystalline silicon layer 3. The intrinsic polycrystalline silicon layer is relatively thin, such as 0.5 nm to 2 nm.

[0079] An intrinsic polysilicon layer is provided between the first tunneling oxide layer 2 and the P-type doped polysilicon layer 3, which can further prevent boron segregation into the first tunneling oxide layer, avoid photo-induced degradation, and further improve the passivation effect of the first tunneling oxide layer 2.

[0080] In some embodiments of the present invention, the first surface 11 further includes a spacer region 113 located between the first region 111 and the second region 112 to separate the first region 111 and the second region 112 and prevent leakage caused by short circuit.

[0081] In some embodiments of the present invention, the surface of the interval region 113 is textured to reduce surface reflectivity and optical loss.

[0082] In some embodiments of the present invention, the surfaces of the first region 111 and the second region 112 are polished surfaces to improve the passivation effect and reduce the contact resistance.

[0083] In some embodiments of the present invention, the second surface 12 is textured to improve light utilization, reduce reflection, and increase short-circuit current.

[0084] In some embodiments of the present invention, the back contact battery further includes a first passivation layer 6, a second passivation layer 7, a first electrode 8, and a second electrode 9.

[0085] The first passivation layer 6 covers the P-type doped polysilicon layer 3, the N-type doped polysilicon layer 5, and the spacer region 113. The second passivation layer 7 is located on the second surface 12. The first electrode 8 penetrates the first passivation layer 6 and is in contact with the P-type doped polysilicon layer 3. The second electrode 9 penetrates the first passivation layer 6 and is in contact with the N-type doped polysilicon layer 5. Both the first electrode 8 and the second electrode 9 are metal electrodes.

[0086] The first electrode 8 is located on the side of the first passivation layer 6 opposite to the P-type doped polysilicon layer 3, and extends through the first passivation layer 6 into the P-type doped polysilicon layer 3. The first electrode 8 can extend into the boron-doped polysilicon layer 32 and contact it; the first electrode 8 can also extend into the gallium-doped polysilicon layer 31 and contact it. The second electrode 9 is located on the side of the first passivation layer 6 opposite to the N-type doped polysilicon layer 5, and extends through the first passivation layer 6 into the N-type doped polysilicon layer 5, contacting it.

[0087] When the boron-doped polysilicon layer 32 comprises multiple boron-doped polysilicon sublayers 321, the first electrode 8 can extend into any boron-doped polysilicon sublayer 321 and contact it. When the gallium-doped polysilicon layer 31 comprises multiple gallium-doped polysilicon sublayers 311, the first electrode 8 can also extend into any gallium-doped polysilicon sublayer 311 and contact it.

[0088] Compared to N-type doped polysilicon layers (where the contact resistance between the N-type doped polysilicon layer and the metal electrode is approximately 0.5~1.5 mΩ·cm²), P-type doped polysilicon layers have a higher contact resistance (approximately 1~5 mΩ·cm²), which can easily lead to a deterioration in the fill factor (FF) and affect the conversion efficiency. Therefore, in this embodiment of the invention, the variation in the doping concentration of the P-type doped polysilicon layer 3 can effectively improve the contact resistance between the P-type doped polysilicon layer 3 and the first electrode 8, increase the fill factor, and further improve the conversion efficiency of the battery. Compared to related technologies (where the P-type doped polysilicon layer is a uniformly doped boron-doped polysilicon layer), the contact resistance of the P-type doped polysilicon layer ranges from 1~5 mΩ·cm². 2 Improved to 0.5~2mΩ·cm 2 .

[0089] In some embodiments of the present invention, the first passivation layer 6 can be a single-layer structure or a stacked structure. For example, the first passivation layer 6 includes a first aluminum oxide (AlOx) layer 61 and a first silicon nitride (SiNx) layer 62 stacked together. The thickness of the first silicon nitride layer 62 can be 10 nm to 150 nm.

[0090] In some embodiments of the present invention, the second passivation layer 7 can be a single-layer structure or a stacked structure. For example, the second passivation layer 7 includes a second aluminum oxide (AlOx) layer 71 and a second silicon nitride (SiNx) layer 72 stacked together. The thickness of the second silicon nitride layer 72 can be 10 nm to 100 nm.

[0091] The first passivation layer 6 and the second passivation layer 7 adopt a stacked passivation structure composed of an aluminum oxide layer and a silicon nitride layer to achieve a dual passivation mechanism, which takes into account both excellent passivation effect, optical gain and long-term device stability.

[0092] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a method for preparing a back contact battery, which can be a TBC battery, and the method for preparing the back contact battery can prepare a back contact battery as disclosed in any of the above embodiments. Figure 3 As shown, Figure 3 This is a flowchart of a method for preparing a back contact battery according to an embodiment of the present invention. The method includes steps S101 to S103: S101. A silicon substrate is provided, the silicon substrate having a first surface and a second surface disposed opposite to each other, the first surface including an alternately distributed first region and a second region.

[0093] In some embodiments of the present invention, combined with Figure 4 As shown, the silicon substrate 1 can be an N-type single-crystal silicon substrate. After providing the silicon substrate 1, the surface of the silicon substrate 1 can be pretreated with NaOH or KOH solution. The concentration of the NaOH or KOH solution used is 5wt%~30wt%, the temperature is 50℃~90℃, and the time is 50s~500s.

[0094] The silicon substrate 1 has a first surface 11 and a second surface 12 disposed opposite to each other. The first surface 11 includes alternating first regions 111 and second regions 112. The first surface 11 is a backlight surface, and the second surface 12 is a light-receiving surface. The first region 111 is a P-region, and the second region 112 is an N-region.

[0095] In some embodiments of the present invention, the first surface 11 further includes a spacer region 113 located between the first region 111 and the second region 112 to separate the first region 111 and the second region 112 and prevent leakage caused by short circuit.

[0096] S102. A first tunneling oxide layer and a P-type doped polysilicon layer are sequentially stacked in the first region. The P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a boron-doped polysilicon layer that are sequentially stacked. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, and the doping concentration of the boron-doped polysilicon layer gradually increases.

[0097] In some embodiments of the present invention, combined with Figure 4 As shown, a first initial tunneling oxide layer 2' is deposited on the first surface 11 using a PECVD process. Then, an initial gallium-doped polysilicon layer 31' is formed on the side of the first initial tunneling oxide layer 2' facing away from the silicon substrate 1 using a PECVD in-situ doping process. Next, an initial boron-doped polysilicon layer 32' is formed on the side of the initial gallium-doped polysilicon layer 31' facing away from the first initial tunneling oxide layer 2' using a PECVD in-situ doping process. The doping concentration of the initial gallium-doped polysilicon layer 31' gradually increases in the direction from the silicon substrate 1 to the first initial tunneling oxide layer 2', and the doping concentration of the initial boron-doped polysilicon layer 32' also gradually increases. In some embodiments, the initial boron-doped polysilicon layer 32' comprises a plurality of initially boron-doped polysilicon sublayers 321' stacked sequentially. The doping concentration of the plurality of initial boron-doped polysilicon sublayers 321' gradually increases in the direction from the silicon substrate 1 to the first initial tunneling oxide layer 2'.

[0098] The first initial tunneling oxide layer 2' can also be formed using other processes, such as LPCVD, which will not be elaborated here. The initial gallium-doped polysilicon layer 31' and the initial boron-doped polysilicon layer 32' can also be formed using other processes, such as LPCVD plus diffusion doping, which will not be elaborated here.

[0099] Then, combine Figure 5 As shown, for Figure 4 The structure shown is subjected to high-temperature annealing, forming a BSG (borosilicate glass) 33 on the side of the initial boron-doped polysilicon layer 32' opposite to the initial gallium-doped polysilicon layer 31'. As an example, the annealing temperature is 500℃~1000℃, the annealing time is 100s~7200s, and the annealing pressure is 500Pa~50000Pa. N2 is introduced during the high-temperature annealing process, with a flow rate of 100sccm~50000sccm.

[0100] Then, combine Figure 6 As shown, for Figure 5The structure shown is patterned (e.g., laser grooving using a 532nm green picosecond laser with a power of 10W~50W). The first initial tunneling oxide layer 2', the initial gallium-doped polysilicon layer 31', the initial boron-doped polysilicon layer 32', and the BSG 33 in the second region 112 and the spacer region 113 are removed. The first initial tunneling oxide layer 2' in the first region 111 is retained to form the first tunneling oxide layer 2. The initial gallium-doped polysilicon layer 31' in the first region 111 is retained to form the gallium-doped polysilicon layer 31. The initial boron-doped polysilicon layer 32' in the first region 111 is retained to form the boron-doped polysilicon layer 32. The BSG 33 in the first region 111 is retained. The gallium-doped polysilicon layer 31 and the boron-doped polysilicon layer 32 constitute the P-type doped polysilicon layer 3. In the case where the initial boron-doped polysilicon layer 32' comprises multiple initially boron-doped polysilicon sub-layers 321' stacked together, the initial boron-doped polysilicon sub-layers 321' of the second region 112 and the spacer region 113 are removed by patterning, and the initial boron-doped polysilicon sub-layers 321' of the first region 111 are retained to form the boron-doped polysilicon sub-layers 321, so that the boron-doped polysilicon layer 32 comprises multiple boron-doped polysilicon sub-layers 321 stacked together sequentially. Other processes, such as photolithography, can also be used for patterning, which will not be elaborated here.

[0101] Then, use NaOH or KOH solution to... Figure 6 The structure shown is then cleaned and polished. As an example, the concentration of NaOH or KOH solution is 5wt%~30wt%, the temperature is 50℃~90℃, and the time is 50s~500s.

[0102] In some embodiments of the present invention, a mask may also be formed on the first surface 11, and the first tunneling oxide layer 2, the gallium-doped polysilicon layer 31, and the boron-doped polysilicon layer 32 may be sequentially stacked on the first region 111 directly through the mask to simplify the process flow. Then, the mask is removed. The gallium-doped polysilicon layer 31 and the boron-doped polysilicon layer 32 constitute a P-type doped polysilicon layer 3.

[0103] In some embodiments of the present invention, the doping concentration of the P-type doped polysilicon layer 3 is 1×10⁻⁶. 17 cm -3 ~1×10 22 cm -3 .

[0104] In some embodiments of the present invention, the doping concentration of the gallium-doped polysilicon layer 31 is 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 .

[0105] In some embodiments of the present invention, the doping concentration of the boron-doped polycrystalline silicon layer 32 is 5 × 10⁻⁶. 19 cm-3 ~1×10 22 cm -3 .

[0106] In some embodiments of the present invention, during the formation of the first tunneling oxide layer 2, nitrous oxide (N2O) is introduced, with a flow rate of 300 sccm to 30000 sccm; the cavity temperature is 200℃ to 600℃; the pressure is 500 Pa to 50000 Pa; the radio frequency power is 1000 W to 30000 W; the deposition time is 5 s to 500 s; and the thickness is 0.5 nm to 2 nm.

[0107] In some embodiments of the present invention, during the formation of the gallium-doped polysilicon layer 31, silane, a gallium source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 1 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, the RF power is 1000 W to 30000 W, and the deposition time is 5 s to 1000 s. This ensures the formation of the required gallium-doped polysilicon layer 31.

[0108] The gallium source can include TMG, TEG, etc., and can also include other gallium-containing gases or liquids; no specific limitation is made here. The carrier gas can include H2, Ar, etc., and can also include other gases; no specific limitation is made here.

[0109] In some embodiments of the present invention, during the formation of the gallium-doped polysilicon layer 31, the flow rate of the gallium source can be gradually increased so that the doping concentration of the gallium-doped polysilicon layer 31 gradually increases in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0110] In some embodiments of the present invention, combined with Figure 2 As shown, the gallium-doped polysilicon layer 31 includes a plurality of gallium-doped polysilicon sublayers 311 formed by sequential stacking. During the sequential formation of the plurality of gallium-doped polysilicon sublayers 311, the flow rate of the gallium source can be increased sequentially, that is, the flow rate of the gallium source introduced into the formation of the subsequent gallium-doped polysilicon sublayer 311 is greater than the flow rate of the gallium source introduced into the formation of the previous gallium-doped polysilicon sublayer 311, so that the doping concentration of the plurality of gallium-doped polysilicon sublayers 311 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0111] In some embodiments of the present invention, the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a, a second gallium-doped polysilicon sublayer 311b, and a third gallium-doped polysilicon sublayer 311c, which are sequentially stacked. During the formation of the first gallium-doped polysilicon sublayer 311a, the flow rate of the introduced gallium source is 1 sccm to 10 sccm, and the doping concentration of the first gallium-doped polysilicon sublayer 311a is 1 × 10⁻⁶.17 cm -3 ~5×10 17 cm -3 During the formation of the second gallium-doped polycrystalline silicon sublayer 311b, the flow rate of the gallium source was 10 sccm to 50 sccm, and the doping concentration of the second gallium-doped polycrystalline silicon sublayer 311b was 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 During the formation of the third gallium-doped polycrystalline silicon sublayer 311c, the flow rate of the gallium source was 50 sccm to 100 sccm, and the doping concentration of the third gallium-doped polycrystalline silicon sublayer 311c was 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0112] In some embodiments of the present invention, during the process of sequentially forming multiple gallium-doped polycrystalline silicon sublayers 311, the deposition time can be increased sequentially, that is, the deposition time of the subsequent gallium-doped polycrystalline silicon sublayer 311 is greater than the deposition time of the previous gallium-doped polycrystalline silicon sublayer 311, so that the thickness of the multiple gallium-doped polycrystalline silicon sublayers 311 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0113] In some embodiments of the present invention, when the gallium-doped polysilicon layer 31 includes a first gallium-doped polysilicon sublayer 311a, a second gallium-doped polysilicon sublayer 311b, and a third gallium-doped polysilicon sublayer 311c stacked sequentially, the thickness of the first gallium-doped polysilicon sublayer 311a is 0.5 nm to 2 nm, the thickness of the second gallium-doped polysilicon sublayer 311b is 2 nm to 10 nm, and the thickness of the third gallium-doped polysilicon sublayer 311c is 10 nm to 30 nm.

[0114] In some embodiments of the present invention, during the formation of the boron-doped polysilicon layer 32, silane, a boron source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 50 sccm to 500 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the radio frequency power is 1000 W to 30000 W. This ensures the formation of the required boron-doped polysilicon layer 32.

[0115] The boron source may include BF3, B2H6, TMB, etc., and may also include other boron-containing gases or liquids; no specific limitation is made here. The carrier gas may include H2, Ar, etc., and may also include other gases; no specific limitation is made here.

[0116] In some embodiments of the present invention, during the formation of the boron-doped polysilicon layer 32, the flow rate of the boron source can be gradually increased so that the doping concentration of the boron-doped polysilicon layer 32 gradually increases in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0117] In some embodiments of the present invention, the boron-doped polysilicon layer 32 includes a plurality of boron-doped polysilicon sublayers 321 formed by sequential stacking. During the sequential formation of the plurality of boron-doped polysilicon sublayers 321, the flow rate of the boron source can be increased sequentially, that is, the flow rate of the boron source introduced into the formation of the subsequent boron-doped polysilicon sublayer 321 is greater than the flow rate of the boron source introduced into the formation of the previous boron-doped polysilicon sublayer 321, so that the doping concentration of the plurality of boron-doped polysilicon sublayers 321 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0118] In some embodiments of the present invention, when the boron-doped polysilicon layer 32 includes a first boron-doped polysilicon sublayer 321a, a second boron-doped polysilicon sublayer 321b, and a third boron-doped polysilicon sublayer 321c stacked sequentially, the doping concentration of the first boron-doped polysilicon sublayer 321a is 5 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second boron-doped polycrystalline silicon sublayer 321b is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The doping concentration of the third boron-doped polycrystalline silicon sublayer 321c is 5 × 10⁻⁶. 20 cm -3 ~1×10 22 cm -3 .

[0119] During the formation of the first boron-doped polycrystalline silicon sublayer 321a, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 50 sccm to 150 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the radio frequency power is 1000 W to 30000 W.

[0120] During the formation of the second boron-doped polycrystalline silicon sublayer 321b, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 150 sccm to 300 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the radio frequency power is 1000 W to 30000 W.

[0121] During the formation of the third boron-doped polycrystalline silicon sublayer 321c, silane, a boron source, and a carrier gas are introduced. The flow rate of silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 300 sccm to 500 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the radio frequency power is 1000 W to 30000 W.

[0122] In some embodiments of the present invention, during the sequential formation of multiple boron-doped polycrystalline silicon sublayers 321, the deposition time can be increased sequentially, that is, the deposition time of the later boron-doped polycrystalline silicon sublayer 321 is greater than the deposition time of the earlier boron-doped polycrystalline silicon sublayer 321, so that the thickness of the multiple boron-doped polycrystalline silicon sublayers 321 increases sequentially in the direction from the silicon substrate 1 to the first tunneling oxide layer 2.

[0123] In some embodiments of the present invention, when the boron-doped polycrystalline silicon layer 32 includes a first boron-doped polycrystalline silicon sublayer 321a, a second boron-doped polycrystalline silicon sublayer 321b, and a third boron-doped polycrystalline silicon sublayer 321c stacked sequentially, the thickness of the first boron-doped polycrystalline silicon sublayer 321a is 30nm~50nm, the thickness of the second boron-doped polycrystalline silicon sublayer 321b is 50nm~100nm, and the thickness of the third boron-doped polycrystalline silicon sublayer 321c is 100nm~150nm.

[0124] In some embodiments of the present invention, the doping concentration of the boron-doped polysilicon layer 32 is greater than that of the gallium-doped polysilicon layer 31.

[0125] In some embodiments of the present invention, the thickness of the boron-doped polycrystalline silicon layer 32 is greater than the thickness of the gallium-doped polycrystalline silicon layer 31.

[0126] By setting a gallium-doped polysilicon layer 31 between the first tunneling oxide layer 2 and the boron-doped polysilicon layer 32, boron segregation into the first tunneling oxide layer 2 is avoided, reducing BO recombination defects and preventing light-induced degradation. At the same time, the passivation effect of the first tunneling oxide layer 2 is ensured, improving the open-circuit voltage and conversion efficiency of the battery. In the direction from the first tunneling oxide layer 2 to the P-type doped polysilicon layer 3, the doping concentration of the gallium-doped polysilicon layer 31 gradually increases, and the doping concentration of the boron-doped polysilicon layer 32 gradually increases. This improves carrier extraction, enhances the field passivation capability of the P-type doped polysilicon layer 3, further improves the open-circuit voltage and conversion efficiency of the battery, and improves the contact resistance of the P-type doped polysilicon layer 3, increasing the fill factor and further improving the conversion efficiency of the battery.

[0127] S103, a second tunneling oxide layer and an N-type doped polysilicon layer are sequentially stacked in the second region.

[0128] In some embodiments of the present invention, combined with Figure 7As shown, a second initial tunneling oxide layer 4' is first deposited on the surfaces of the second region 112, the spacer region 113, and the BSG 33 using an LPCVD process. As an example, during the formation of the second initial tunneling oxide layer 4', the chamber temperature is 500℃~700℃, the pressure is 100mbar~1000mbar, the time is 100s~5000s, and the O2 flow rate is 3000sccm~50000sccm.

[0129] Then, using an LPCVD process, an intrinsic polycrystalline silicon layer is formed on the side of the second initial tunneling oxide layer 4' facing away from the silicon substrate 1. As an example, during the formation of the intrinsic polycrystalline silicon layer, the chamber temperature is 500℃~700℃, the pressure is 50mbar~500mbar, the time is 100s~5000s, and the flow rate of SiH4 introduced is 100sccm~3000sccm.

[0130] Phosphorus diffusion is performed on the intrinsic polycrystalline silicon layer to form an initial N-type doped polycrystalline silicon layer 5', and a PSG 51 is formed on the side of the initial N-type doped polycrystalline silicon layer 5' opposite to the second initial tunneling oxide layer 4'. As an example, during the phosphorus diffusion process, the chamber temperature is 700℃~1000℃, the pressure is 100mbar~1000mbar, and the time is 100s~5000s; the flow rate of O2 is 100sccm~10000sccm; the flow rate of phosphorus-carrying source N2 is 300sccm~3000sccm, and the flow rate of N2 is 100sccm~10000sccm.

[0131] It should be noted that the second initial tunneling oxide layer 4' and the initial N-type doped polysilicon layer 5' can also be formed using other processes, which are not specifically limited here.

[0132] Then, combine Figure 8 As shown, for Figure 7 The structure shown is patterned (e.g., laser grooving, using a 355nm purple picosecond laser with a power of 10W~50W), and the initial N-type doped polysilicon layer 5' and the second initial tunneling oxide layer 4' of PSG 51, BSG 33, the first region 111 and the spacer region 113 are removed. The second initial tunneling oxide layer 4' of the second region 112 is retained to form the second tunneling oxide layer 4, and the initial N-type doped polysilicon layer 5' of the second region 112 is retained to form the N-type doped polysilicon layer 5.

[0133] Then, the second surface 12 and edges of the silicon substrate 1 are cleaned with HNO3, HF, H2SO4 and DI water for polycrystalline silicon wrap-around plating. As an example, HNO3: 50L~500L; HF: 5L~50L; H2SO4: 10L~100L; DI water: 50L~500L; temperature: 5℃~25℃; belt speed: 2m / min~20m / min.

[0134] In some embodiments of the present invention, a mask may also be formed on the first surface 11, and the second tunneling oxide layer 4 and the N-type doped polysilicon layer 5 may be sequentially stacked in the second region 112 directly through the mask to simplify the process flow. Then, the mask is removed.

[0135] In some embodiments of the present invention, after step S103, the preparation method further includes: texturing the spacer region 113 and the second surface 12, so that the surface of the spacer region 113 and the second surface 12 are texturized. As an example, NaOH or KOH solution is used for texturing, the concentration of NaOH or KOH solution is 5wt%~30wt%, the temperature is 50℃~90℃, and the time is 100s~1000s; the additive is 1L~10L.

[0136] In some embodiments of the present invention, combined with Figure 1 As shown, after step S103, the preparation method further includes: forming a first passivation layer 6 covering the P-type doped polysilicon layer 3, the N-type doped polysilicon layer 5 and the spacer region 113, and forming a second passivation layer 7 covering the second surface 12.

[0137] In some embodiments of the present invention, the first passivation layer 6 includes a first aluminum oxide layer 61 and a first silicon nitride layer 62 formed sequentially.

[0138] In some embodiments of the present invention, the second passivation layer 7 includes a second aluminum oxide layer 71 and a second silicon nitride layer 72 formed by sequentially stacking.

[0139] Combination Figure 1 As shown, an ALD process is used to form a first alumina layer 61 covering a P-type doped polysilicon layer 3, an N-type doped polysilicon layer 5, and a spacer region 113, and a second alumina layer 71 covering a second surface 12. The first alumina layer 61 and the second alumina layer 71 can be formed using the same fabrication process. As an example, during the fabrication of the first alumina layer 61 and the second alumina layer 71, the temperature is 50℃~500℃, the pressure is 0.1 Torr~10 Torr, the N2 flow rate is 10 sccm~1000 sccm, the TMA pulse is 10 ms~100 ms, the DI water pulse is 10 ms~100 ms, and the number of cycles is 10~50.

[0140] Then, a second silicon nitride layer 72 is formed on the side of the second alumina layer 71 facing away from the silicon substrate 1 using a PECVD process. As an example, during the fabrication of the second silicon nitride layer 72, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa; the gas flow rate is as follows: silane flow rate is 10sccm~1000sccm, NH3 flow rate is 100sccm~10000sccm, N2O flow rate is 10sccm~10000sccm, and N2 flow rate is 300sccm~30000sccm; the RF power is 1000W~30000W, the deposition time is 1s~1000s; and the thickness is 10nm~100nm.

[0141] Then, a first silicon nitride layer 62 is formed on the side of the first alumina layer 61 facing away from the silicon substrate 1 using a PECVD process. As an example, during the fabrication of the first silicon nitride layer 62, the chamber temperature is 200℃~600℃, the pressure is 500Pa~50000Pa; the gas flow rate is as follows: silane flow rate is 10sccm~1000sccm, NH3 flow rate is 100sccm~10000sccm, N2O flow rate is 10sccm~10000sccm, and N2 flow rate is 300sccm~30000sccm; the RF power is 1000W~30000W, the deposition time is 1s~1000s; and the thickness is 10nm~150nm.

[0142] In some embodiments of the present invention, combined with Figure 1 As shown, after forming the first passivation layer 6 and the second passivation layer 7, the fabrication method further includes forming a first electrode 8 and a second electrode 9. The first electrode 8 penetrates the first passivation layer 6 and is in contact with the P-type doped polysilicon layer 3. The second electrode 9 penetrates the first passivation layer 6 and is in contact with the N-type doped polysilicon layer 5.

[0143] N-type main gate paste, N-type secondary gate paste, P-type main gate paste, and P-type secondary gate paste can be screen-printed. Then, high-temperature sintering is performed at 600℃~900℃ for 1s~100s. Finally, light injection is performed to form a first electrode 8 and a second electrode 9. The first electrode 8 includes a P-type main gate and a P-type secondary gate, and the second electrode 9 includes an N-type main gate and an N-type secondary gate.

[0144] It should be noted that after the battery is manufactured, it can be tested and sorted. The test and sorting is used to detect the battery's electrical performance and appearance defects, classify it according to efficiency, and remove defective cells to ensure component matching and product quality.

[0145] The following specific embodiments illustrate a method for preparing a back contact battery disclosed in this invention.

[0146] Example 1: S1. Pre-treatment of single-crystal silicon substrate polishing: The single-crystal silicon substrate is pre-treated with NaOH or KOH solution at a concentration of 15wt%, a temperature of 75℃, and a time of 250s.

[0147] S2. PECVD method for back-side deposition of the first tunneling oxide layer: chamber temperature 450℃, pressure 20000Pa; gas introduced: nitrous oxide (N2O) flow rate 15000sccm; radio frequency power 15000W, deposition time 200s; thickness 1.5nm.

[0148] S3. PECVD deposition of the first gallium-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane (SiH4) flow rate 8000sccm, gallium source TMG or TEG flow rate 10sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 10s; thickness 1nm, doping concentration 5×10⁻⁶ 17 cm -3 .

[0149] S4. PECVD deposition of the second gallium-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane (SiH4) flow rate 6000sccm, gallium source TMG or TEG flow rate 20sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 100s; thickness 10nm, doping concentration 6×10⁻⁶. 17 cm -3 .

[0150] S5. PECVD deposition of the third gallium-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane (SiH4) flow rate 4000sccm, gallium source TMG or TEG flow rate 100sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 300s; thickness 30nm, doping concentration 5×10⁻⁶. 19 cm -3 .

[0151] S6. PECVD deposition of the first boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 20000Pa; gas supply: silane SiH4 flow rate 4000sccm, boron source BF3, B2H6 or TMB flow rate 100sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 100s; thickness 20nm, doping concentration 7×10⁻⁶ 19 cm -3 .

[0152] S7. PECVD deposition of the second boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 10000Pa; gas supply: silane SiH4 flow rate 3000sccm, boron source BF3, B2H6 or TMB flow rate 200sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 200s; thickness 40nm, doping concentration 2×10⁻⁶ 20 cm -3 .

[0153] S8. PECVD deposition of the third boron-doped polycrystalline silicon sublayer: chamber temperature 450℃, pressure 10000Pa; gas supply: silane SiH4 flow rate 2000sccm, boron source BF3, B2H6 or TMB flow rate 400sccm, H2 or Ar flow rate 15000sccm; RF power 10000W, deposition time 400s; thickness 100nm, doping concentration 1×10⁻⁶. 21 cm -3 .

[0154] S9. High-temperature annealing: Annealing temperature 900℃, annealing time 5000s, annealing pressure 30000Pa, N2 flow rate 10000sccm.

[0155] S10, Laser grooving: Laser wavelength 532nm green picosecond, power 30W.

[0156] S11. Polishing: Clean and polish the laser-treated silicon substrate using NaOH or KOH solution. The NaOH or KOH solution concentration is 20wt%, the temperature is 80℃, and the time is 200s.

[0157] S12, LPCVD method for back-side deposition of a second tunneling oxide layer and an intrinsic polycrystalline silicon layer: ① Second tunneling oxide layer: chamber temperature 600℃, pressure 200mbar, time 2000s, O2 flow rate 20000sccm; ② Intrinsic polycrystalline silicon layer: chamber temperature 600℃, pressure 200mbar, time 1000s, SiH4 flow rate 1000sccm.

[0158] S13, Phosphorus diffusion: Chamber temperature 900℃, pressure 200mbar, time 1000s, O2 flow rate 5000sccm; phosphorus-carrying source N2 flow rate 2000sccm, N2 flow rate 8000sccm.

[0159] S14. Laser grooving: Laser wavelength 355nm purple picosecond, power 30W.

[0160] S15. Etching: Clean the polysilicon winding plating on the front and edge of the silicon substrate: HNO3 100L, HF 40L, H2SO4 70L, DI water 300L; temperature 15℃, belt speed 10m / min.

[0161] S16. Texturing: NaOH or KOH solution concentration 15wt%, temperature 80℃, time 400s; additive 4L.

[0162] S17, ALD deposition of alumina thin films: temperature 200℃, pressure 50 Torr, N2 flow rate 800 sccm; TMA pulse 7ms, DI water pulse 8ms, number of cycles 40.

[0163] S18, PECVD front-side SiNx thin film deposition: chamber temperature 500℃, pressure 1000Pa; gas flow: silane SiH4 flow rate 500sccm, NH3 flow rate 4000sccm, N2O flow rate 7000sccm, N2 flow rate 10000sccm; RF power 5000W, deposition time 500s; thickness 80nm.

[0164] S19, PECVD backside SiNx thin film deposition: chamber temperature 500℃, pressure 1000Pa; gas flow: silane SiH4 flow rate 700sccm, NH3 flow rate 6000sccm, N2O flow rate 6000sccm, N2 flow rate 15000sccm; RF power 6000W, deposition time 700s; thickness 100nm.

[0165] S20, Screen Printing + Sintering + Photoinjection: ① Print main grid paste ② Print N sub-grid paste ③ Print P sub-grid paste ④ Sintering: Temperature 700℃, Time 20s; ⑤ Photoinjection.

[0166] Example 2: The difference between Example 2 and Example 1 is that in step S3, the deposition time is 20s and the thickness is 2nm.

[0167] Example 3: The difference between Example 3 and Example 1 is that in step S8, the flow rate of the boron source BF3, B2H6, or TMB is 300 sccm, and the doping concentration is 5 × 10⁻⁶. 20 cm -3 .

[0168] Example 4: The difference between Example 4 and Example 1 is that in step S8, the deposition time is 200s and the thickness is 50nm.

[0169] Example 5: The difference between Example 5 and Example 1 is that in step S3, the gallium source TMG or TEG flow rate is 0 sccm and the doping concentration is 0 cm⁻¹. -3 The first gallium-doped polycrystalline silicon sublayer is replaced with an intrinsic polycrystalline silicon layer.

[0170] Comparative Example 1: The difference between Comparative Example 1 and Example 1 is that steps S2-S9 are replaced by back-side deposition of a first tunneling oxide layer and an intrinsic polysilicon layer using LPCVD, and boron diffusion is performed on the intrinsic polysilicon layer to form a P-type doped polysilicon layer: ① First tunneling oxide layer: chamber temperature 600℃, pressure 400mbar, time 1000s, O2 flow rate 10000sccm; ② Intrinsic polysilicon layer: chamber temperature 580℃, pressure 200mbar, time 1500s, SiH4 flow rate 1000sccm; Boron diffusion: chamber temperature 950℃, pressure 200mbar, time 300s, O2 flow rate 5000sccm; BCl3 flow rate 200sccm, N2 flow rate 5000sccm.

[0171] The test results for eta (conversion efficiency), Voc (open-circuit voltage), Jsc (short-circuit current density), and FF (fill factor) are shown in Table 1.

[0172] Table 1 As shown in Table 1, compared with the test results of the battery in Comparative Example 1, the back contact battery disclosed in this invention effectively improves the open circuit voltage, fill factor and conversion efficiency.

[0173] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a stacked battery. For example... Figure 9 As shown, Figure 9 This is a cross-sectional structural diagram of a stacked battery disclosed in an embodiment of the present invention. The stacked battery includes a bottom battery 100 and a top battery 200 stacked together. The bottom battery 100 includes a back-contact battery as disclosed in any of the above embodiments.

[0174] In some embodiments of the present invention, the top cell 200 includes a perovskite solar cell. The perovskite solar cell includes a first transparent conductive layer 203, a first charge transport layer 204, a perovskite light-absorbing layer 205, a second charge transport layer 206, a second transparent conductive layer 207, and an electrode 208, which are sequentially stacked. One of the first charge transport layer 204 and the second charge transport layer 206 is an electron transport layer, and the other is a hole transport layer. As an example, the first charge transport layer 204 is an electron transport layer, and the second charge transport layer 206 is a hole transport layer. Of course, the present invention is not limited to this; in other embodiments, the top cell 200 may also include other solar cells, which will not be elaborated here.

[0175] In some embodiments of the present invention, the stacked battery further includes a component glass 201 and a barrier layer 202, wherein the barrier layer 202 is located on the side of the first transparent conductive layer 203 away from the first charge transport layer 204, and the component glass 201 is located on the side of the barrier layer 202 away from the first transparent conductive layer 203.

[0176] In some embodiments of the present invention, the stacked battery further includes a backplate 300, a first adhesive film 400, and a second adhesive film 500. The front side of the bottom battery 100 is bonded to the top battery 200 through the first adhesive film 400, and the back side of the bottom battery is bonded to the backplate 300 through the second adhesive film 500.

[0177] As an optional implementation of the disclosed content of this invention, an embodiment of this invention discloses a method for preparing a stacked battery, which can prepare a stacked battery as disclosed in any of the above embodiments. The method for preparing the stacked battery includes steps S210 to S230: S210, bottom cell fabrication.

[0178] In some embodiments of the present invention, the bottom battery includes a back contact battery, which is prepared using the back contact battery preparation method disclosed in any of the above embodiments.

[0179] S220, top cell fabrication.

[0180] Fabrication of S230, bottom cell and top cell stacked module.

[0181] In some embodiments of the present invention, the top cell includes a perovskite solar cell.

[0182] The following describes step S220 in detail, using a perovskite solar cell as the top cell example. Step S220 includes steps S221 to S228: S221, Component glass fixing.

[0183] The module glass is horizontally fixed on a temperature-controlled, dust-free stage. The frame around the module is sealed with high-temperature resistant silicone strips, exposing only the effective area of ​​the module glass. For example, the stage preheating temperature is 30~60℃, the ambient humidity is ≤40%RH, and the cleanliness level is Class 1000. The module glass uses tempered ultra-clear front glass with a light transmittance ≥92% and a thickness of 1~5mm.

[0184] S222, Pretreatment of component glass surface.

[0185] ① Glass surface cleaning: Low-temperature plasma cleaning is used to remove organic matter, particles, and moisture from the glass surface. For example, the power is 50-200W, the pressure of the O2 and Ar mixed gas is 50-200Pa, and the time is 20-200s.

[0186] ② Second cleaning: Use a mixture of anhydrous ethanol and isopropanol for low-temperature spraying, followed by low-speed drying with high-purity nitrogen. High-temperature baking is prohibited to avoid damaging the internal encapsulant and electrodes of the component. For example, the ratio of anhydrous ethanol to isopropanol is 1:1, the spraying temperature is 20-30°C, and the nitrogen purity is 99.999%.

[0187] ③ Barrier layer preparation: An ultrathin Al2O3 film was deposited using the ALD method as a barrier layer to form a dense ion-barrier layer. As an example, the temperature ranged from 50 to 500 °C, the TMA pulse duration was 10 to 100 ms, the DI water pulse duration was 10 to 100 ms, the number of cycles was 10 to 50, and the film thickness was 2 to 6 nm.

[0188] ④ Preparation of the first transparent conductive layer: Magnetron sputtering of ITO serves as the first transparent conductive layer, providing a good conductive path for perovskite solar cells. As an example, the temperature ranges from 50 to 200°C, the power output from 50 to 100 W, and the film thickness from 50 to 150 nm.

[0189] ⑤ Low-temperature annealing: As an example, the temperature is 50~200℃, the pressure is 50~500mbarr, and the time is 10~50min.

[0190] S223, Electron transport layer fabrication (ETL).

[0191] ① Coating / Spin Coating: SnO2 nanocolloid solution is used for slit coating / spin-coating to ensure uniform coating and no pinholes. As an example, the SnO2 nanocolloid solution has a concentration of 15~20wt% and is an ethanol / water mixed solvent; the coating / spin-coating speed is 50~80mm / s and the wet film thickness is 300~500nm.

[0192] ② Low-temperature annealing: As an example, the temperature is 90~110℃, the atmosphere is air, and the time is 10~15min; the ETL thickness after annealing is 10~50nm.

[0193] ③ Post-processing: Oxygen plasma modification reduces surface defects and enhances electron extraction capabilities, adapting to the carrier transport requirements of perovskite light-absorbing layers. As an example, the power is 50-80W, and the duration is 30-60s.

[0194] S224, preparation of perovskite light-absorbing layer.

[0195] As an example, a perovskite precursor solution: Cs x FA 1-x Pb(I 1-y Br y )3, band gap 1.69~1.73eV, x=0.05-0.15, y=0.25-0.35; solvent DMF / DMSO: volume ratio 4:1, concentration 1.2~1.5mol / L, with 5~10mol% MACl added as a crystallization regulator to improve the crystallization quality and stability of perovskite films.

[0196] ① Coating: Slot coating / dossler coating should be used to ensure uniform coating without any missed areas or thick edges. For example, the wet film thickness should be 400~600 nm, the ambient temperature 25±3℃, and the humidity ≤25%RH.

[0197] ② Antisolvent extraction: Within 3-5 seconds after coating, spray a chlorobenzene / ethyl ether mixed antisolvent (volume ratio 9:1) to quickly extract the solvent, induce uniform crystallization, and reduce defects in the perovskite film.

[0198] ③ Low-temperature annealing: Step 1: Remove residual solvent by applying pressure at 70±5℃ and 10-20 mbar for 10 minutes. Step 2: Temperature 110±5℃, nitrogen protection, time 15-20min, to complete perovskite crystallization.

[0199] The film thickness is 400~600nm, and the grain size is 300~800nm.

[0200] ④ Optical inspection: Controlling the transmittance of the effective area to 29-31% adapts to the long-wave absorption of the module, maximizing the overall efficiency of the stacked module.

[0201] S225, Hole Transport Layer (HTL) fabrication.

[0202] PTAA / SAM composite was selected as the hole transport layer.

[0203] ① Self-assembled monolayer (SAM) spraying: As an example, the isopropanol concentration was 0.5~1 mmol / L, and the self-assembly was carried out at room temperature for 30~60 seconds, followed by drying with nitrogen.

[0204] ② Slit coating with PTAA toluene solution: As an example, the concentration of PTAA toluene solution is 8~12 mg / mL, and the wet film thickness is 200~300 nm.

[0205] ③ Annealing: As an example, an ultrathin HTL with a thickness of 10~15nm was formed at a temperature of 100±5℃, a nitrogen atmosphere, and a time of 10min.

[0206] S226, Preparation of the second transparent conductive layer.

[0207] ① Evaporation of an ultra-thin Ag layer (to reduce costs): As an example, the thickness is 8~12nm and the speed is 0.5~1Å / s.

[0208] ② Evaporated ITO coating: As an example, the thickness is 40~60nm, the temperature is 90~100℃, and the speed is 1~2Å / s.

[0209] Electrode parameters: sheet resistance 40~60Ω / sq, visible light transmittance ≥75%, cavity vacuum pressure ≤5×10 -4 Pa.

[0210] S227, laser etching.

[0211] As an example, laser: infrared picosecond laser, wavelength 1064nm, power 3~5W, spot diameter 15~25μm.

[0212] ① Etch through the first transparent conductive layer + ETL to isolate the negative electrode of adjacent sub-cells and avoid short circuits; ②Etch through the perovskite light absorption layer + HTL to connect the positive electrode of the front sub-cell to the negative electrode of the rear sub-cell, thus realizing the series connection of sub-cells; ③ A fully functional layer is etched through the edge to form edge isolation, with a dead zone width ≤80μm, improving the overall efficiency of the top cell.

[0213] S228, Electrode bus and edge insulation.

[0214] ① Printing silver paste: Low-temperature conductive silver paste is used to print busbars on the positive and negative terminal areas of the top cell, ensuring a tight connection between the busbars and the top electrode. As an example, the curing temperature is 30~120℃, and the printed electrode width is 1~2mm, with a thickness of 10~30μm.

[0215] ②Curing: As an example, the temperature was 105±5℃, the time was 10~50min, and the atmosphere was nitrogen.

[0216] ③ Edge processing: The area around the battery's perimeter, 2-3mm in diameter, is sealed with UV-cured insulating adhesive to prevent moisture intrusion and to avoid edge plating and leakage.

[0217] The following describes step S230 in detail with reference to a specific embodiment. Step S230 includes steps S231 and S232: S231, Stringing and Layout.

[0218] ① Printed insulating adhesive: Insulating adhesive is printed on the non-electrode area of ​​the back of the bottom battery using screen printing. As an example, the insulating adhesive is a low-temperature curing resin adhesive with a line width of 0.1~1mm and a printing thickness of 5~50μm; post-printing curing: temperature 30~100℃, time 2~20min.

[0219] ② Printing solder paste: Print solder paste on the main grid and PAD points. Solder paste: low temperature lead-free, melting point 150~300℃, printing thickness 10~50μm; drying after printing: temperature 30~100℃, time 2~20min.

[0220] ③ String soldering: The bottom cells are connected in series using solder ribbon. Solder ribbon: low-temperature tin-plated copper solder ribbon, 0.1~1mm wide, 0.05~0.5mm thick; soldering temperature 100~300℃, soldering time 2~20s.

[0221] ④ Layout: Arrange the wire-welded battery strings according to the module type, with a cell spacing of 1~5mm and an overall flatness error of ≤0.5mm.

[0222] S232, Component encapsulation.

[0223] ① Packaging material installation: In the second stage, an EVA or POE film is laid on the glass and top cell of the module. The arranged bottom cell string is then placed on the film, ensuring a tight fit between the bottom cell string and the glass and film, free of bubbles and misalignment. Subsequently, another layer of EVA or POE film is laid on the back of the cell string, and finally, a backsheet is covered. As an example, the EVA or POE film thickness is 0.1~1mm.

[0224] ②Lamination: The laid components are placed into a laminator, and a segmented lamination process is used. Preheating: temperature 50~200℃, time 1~10min; pressurization: temperature 50~200℃, pressure 0.1~2MPa, time 10~100min; cooling: temperature ≤50℃, time 1~10min.

[0225] ③ Edge trimming and cleaning: After lamination, trim any excess EVA or POE film from the edges of the module to ensure that the edges are smooth and burr-free. Then, use a lint-free cloth dampened with anhydrous ethanol to clean the surface of the module and remove any remaining film to prevent residual impurities from affecting the subsequent fabrication of the top cell.

[0226] ④ Frame mounting and junction box installation: An aluminum alloy frame is installed around the module, and the connection between the frame and the glass and back panel is sealed with sealant to ensure a tight seal and block moisture and oxygen. A junction box is installed on the back of the module, and the positive and negative leads of the bottom battery series are connected to the junction box to ensure that the wiring is firm and well insulated, avoiding the risk of short circuit.

[0227] ⑤ Component finished product testing: The encapsulated bottom and top battery stacked modules were subjected to EL and IV tests, and no dark spots, leakage current, or sealing performance were found to be qualified.

[0228] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0229] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate having a first surface and a second surface disposed opposite to each other, the first surface comprising alternating first and second regions; The first tunneling oxide layer is located in the first region; A P-type doped polysilicon layer is located on the side of the first tunneling oxide layer away from the silicon substrate. The P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a boron-doped polysilicon layer stacked sequentially. In the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the gallium-doped polysilicon layer gradually increases, and the doping concentration of the boron-doped polysilicon layer gradually increases. The second tunneling oxide layer is located in the second region; An N-type doped polycrystalline silicon layer is located on the side of the second tunneling oxide layer away from the silicon substrate.

2. The back contact battery according to claim 1, characterized in that, The boron-doped polysilicon layer comprises a plurality of boron-doped polysilicon sublayers stacked sequentially; the doping concentration of the plurality of boron-doped polysilicon sublayers increases sequentially in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer; and / or, The gallium-doped polysilicon layer includes a plurality of gallium-doped polysilicon sub-layers stacked sequentially; in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, the doping concentration of the plurality of gallium-doped polysilicon sub-layers increases sequentially.

3. The back contact battery according to claim 2, characterized in that, In the direction from the first tunneling oxide layer to the P-type doped polycrystalline silicon layer, the thickness of the plurality of boron-doped polycrystalline silicon sublayers increases sequentially, and / or the thickness of the plurality of gallium-doped polycrystalline silicon sublayers increases sequentially.

4. The back contact battery according to claim 1, characterized in that, The gallium-doped polysilicon layer has a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 19 cm -3 ; and / or, The gallium-doped polycrystalline silicon layer comprises a first gallium-doped polycrystalline silicon sublayer, a second gallium-doped polycrystalline silicon sublayer, and a third gallium-doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first gallium-doped polycrystalline silicon sublayer is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 The doping concentration of the second gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 17 cm -3 ~5×10 18 cm -3 The doping concentration of the third gallium-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 ; and / or, The doping concentration of the boron-doped polycrystalline silicon layer is 5 × 10⁻⁶. 19 cm -3 ~1×10 22 cm -3 ; and / or, The boron-doped polycrystalline silicon layer comprises a first boron-doped polycrystalline silicon sublayer, a second boron-doped polycrystalline silicon sublayer, and a third boron-doped polycrystalline silicon sublayer stacked sequentially, wherein the doping concentration of the first boron-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 19 cm -3 ~1×10 20 cm -3 The doping concentration of the second boron-doped polycrystalline silicon sublayer is 1×10⁻⁶. 20 cm -3 ~5×10 20 cm -3 The doping concentration of the third boron-doped polycrystalline silicon sublayer is 5 × 10⁻⁶. 20 cm -3 ~1×10 22 cm -3 .

5. The back contact battery according to claim 1, characterized in that, The P-type doped polycrystalline silicon layer also includes a gallium boron doped polycrystalline silicon layer; The gallium-boron-doped polycrystalline silicon layer is located between the gallium-doped polycrystalline silicon layer and the boron-doped polycrystalline silicon layer.

6. The back contact battery according to claim 1, characterized in that, The back contact battery also includes: The intrinsic polysilicon layer is located between the first tunneling oxide layer and the P-type doped polysilicon layer.

7. The back contact battery according to any one of claims 1-6, characterized in that, The first surface also includes a spacer region located between the first region and the second region; The back contact battery also includes: A first passivation layer covers the P-type doped polysilicon layer, the N-type doped polysilicon layer, and the spacer region; A second passivation layer is located on the second surface; The first electrode penetrates the first passivation layer and is in contact with the P-type doped polysilicon layer. The second electrode penetrates the first passivation layer and is in contact with the N-type doped polysilicon layer.

8. A method for preparing a back contact battery, characterized in that, include: A silicon substrate is provided, the silicon substrate having a first surface and a second surface disposed opposite to each other, the first surface including alternating first regions and second regions; A first tunneling oxide layer and a P-type doped polysilicon layer are sequentially stacked in the first region; the P-type doped polysilicon layer includes a gallium-doped polysilicon layer and a boron-doped polysilicon layer sequentially stacked, and the doping concentration of the gallium-doped polysilicon layer gradually increases in the direction from the first tunneling oxide layer to the P-type doped polysilicon layer, and the doping concentration of the boron-doped polysilicon layer gradually increases. A second tunneling oxide layer and an N-type doped polysilicon layer are sequentially stacked in the second region.

9. The method for preparing a back contact battery according to claim 8, characterized in that, During the formation of the gallium-doped polycrystalline silicon layer, silane, a gallium source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the gallium source is 1 sccm to 100 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500 Pa to 50000 Pa, and the RF power is 1000 W to 30000 W; and / or, During the formation of the boron-doped polycrystalline silicon layer, silane, a boron source, and a carrier gas are introduced. The flow rate of the silane is 10 sccm to 10000 sccm, the flow rate of the boron source is 50 sccm to 500 sccm, and the flow rate of the carrier gas is 300 sccm to 30000 sccm. The cavity temperature is 200℃ to 600℃, the pressure is 500Pa to 50000Pa, and the radio frequency power is 1000W to 30000W.

10. A stacked battery, characterized in that, It includes a bottom battery and a top battery stacked together, wherein the bottom battery includes a back contact battery as described in any one of claims 1-7.

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