A back-contact battery and photovoltaic module
By designing staggered regions and textured structures in IBC cells, combined with conductive layers and electrodes, the problems of doping instability and low efficiency were solved, resulting in higher photoelectric conversion efficiency and reflectivity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG JINKO SOLAR CO LTD
- Filing Date
- 2022-06-08
- Publication Date
- 2026-07-31
AI Technical Summary
Existing IBC batteries suffer from high costs, unstable doping, and cumbersome cleaning steps during the separation of boron-doped and phosphorus-doped regions, resulting in low battery efficiency.
By employing staggered first and second regions, and by forming interval regions and pyramid-shaped textured structures on the back surface of the substrate, combined with the design of conductive layers and boundary regions, conductive layers and electrodes are formed using laser film opening and texturing processes, thereby increasing light reflection and absorption.
It effectively separates the boron-doped and phosphorus-doped regions, reduces interfacial recombination, improves photoelectric conversion efficiency, enhances light absorption and reflection, and improves battery performance.
Smart Images
Figure CN122497159A_ABST
Abstract
Description
[0001] This application is a divisional application. The original application has the application number 202210647861.3 and the original application date is June 8, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field
[0002] This application relates to the field of photovoltaic cell technology, and in particular to a back contact cell and a photovoltaic module. Background Technology
[0003] IBC (Interdigitated Back Contact) solar cells are characterized by the absence of electrodes on the light-receiving side, with the positive and negative electrodes arranged in a finger-like, intersecting pattern on the back side of the cell. Compared to solar cells with shaded light-receiving sides, IBC cells exhibit higher short-circuit current and photoelectric conversion efficiency.
[0004] There are currently three main methods for fabricating the separated doped regions in IBC batteries: 1. Photolithography, which involves multiple masking and photolithography processes to form separate boron and phosphorus doped regions; 2. Ion implantation, which involves masking and laser grooving, followed by ion implantation into a specific area to form separate boron and phosphorus doped regions; 3. Doping paste printing, which involves masking and laser grooving to form diffusion regions, followed by printing boron / phosphorus paste to form the doped regions. Among these methods, photolithography is expensive, ion implantation results in unstable doping, and the doping paste printing and cleaning process involves numerous steps. Summary of the Invention
[0005] In view of the above problems, this application provides a back contact cell and photovoltaic module to solve the technical problems in the prior art. It can separate the boron-doped region and phosphorus-doped region of the IBC cell, avoid the two electrodes from recombination, and improve the efficiency of the IBC cell.
[0006] In a first aspect, this application provides a back contact battery, comprising: The substrate has a front surface and a back surface. The back surface has a first region and a second region arranged alternately along a first direction. There is a gap between adjacent first regions and second regions that is recessed into the substrate. A plurality of first pyramid-shaped textured structure regions are formed on the back surface corresponding to the gap regions. A first conductive layer formed on the first region; A second conductive layer is formed on the second region, the second conductive layer having a conductivity type opposite to that of the first conductive layer; in: A plurality of second pyramid-shaped textured structure regions are formed on the back surface corresponding to the first conductive layer and / or the second conductive layer; the interval region has a boundary region with the adjacent first conductive layer and / or the second conductive layer, and the boundary region of the back surface corresponding to the boundary region has a linear concave-convex textured structure.
[0007] In one possible embodiment, the linear texture structure is a strip or linear texture structure arranged at intervals.
[0008] In one possible embodiment, one end of the strip or line texture structure is connected to the first pyramid texture structure area, and the other end is connected to the second pyramid texture structure area.
[0009] In one possible embodiment, a back passivation layer is further included, which is located on the surface of the first conductive layer, the second conductive layer, and the spacer region; the back passivation layer has a first electrode and a second electrode, the first electrode forming an electrical contact with the first conductive layer, and the second electrode forming an electrical contact with the second conductive layer.
[0010] In one possible embodiment, a front passivation layer is formed on the front surface of the substrate.
[0011] In one possible embodiment, the substrate is an N-type substrate, the first conductive layer includes a P-type doped layer, and the second conductive layer includes an N-type doped layer.
[0012] In one possible embodiment, a dielectric layer is disposed between at least one of the first conductive layer and the second conductive layer and the back surface of the substrate.
[0013] In one possible embodiment, the dielectric layer comprises silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.
[0014] In one possible embodiment, the thickness of the dielectric layer is between 0.5 nm and 3 nm.
[0015] In one possible embodiment, the dielectric layer does not cover the back surface of the substrate corresponding to the spacer region.
[0016] In one possible embodiment, the distance between the top and bottom surfaces of the first pyramid-shaped textured structure region ranges from 2µm to 4µm.
[0017] In one possible embodiment, the distance between the top and bottom surfaces of the second pyramid-shaped textured structure region ranges from 1µm to 3µm.
[0018] In one possible embodiment, the distance of the boundary region along the first direction ranges from 3µm to 5µm.
[0019] In one possible embodiment, the distance between the top and bottom surfaces of the linear textured structure ranges from 1µm to 4µm.
[0020] In one possible embodiment, the distance of the interval along the first direction ranges from 50 to 200 μm.
[0021] In one possible embodiment, the distance of the spacer region along the normal direction of the back surface of the substrate ranges from 1 to 6 μm.
[0022] In one possible embodiment, the ratio of the area of the spacer region to the area of the back surface of the substrate is 10%-35%.
[0023] Secondly, this application also provides a back contact battery, comprising: The substrate has a front surface and a back surface. The back surface has a first region and a second region arranged alternately along a first direction. There is a gap between adjacent first regions and second regions that is recessed into the substrate. A plurality of first pyramid-shaped textured structure regions are formed on the back surface corresponding to the gap regions. A first conductive layer formed on the first region; A second conductive layer is formed on the second region, the second conductive layer having a conductivity type opposite to that of the first conductive layer; in: A plurality of stepped flat texture structures are formed on the back surface corresponding to the first conductive layer and / or the second conductive layer; there is a boundary region between the interval region and the adjacent first conductive layer and / or the second conductive layer, and the boundary region of the back surface corresponding to the boundary region is formed with a linear concave-convex texture structure.
[0024] In one possible embodiment, the linear texture structure is a strip or linear texture structure arranged at intervals.
[0025] In one possible embodiment, one end of the strip or line texture structure is connected to the first pyramid texture structure area, and the other end is connected to the second pyramid texture structure area.
[0026] In one possible embodiment, a back passivation layer is further included, which is located on the surface of the first conductive layer, the second conductive layer, and the spacer region; the back passivation layer has a first electrode and a second electrode, the first electrode forming an electrical contact with the first conductive layer, and the second electrode forming an electrical contact with the second conductive layer.
[0027] In one possible embodiment, a front passivation layer is formed on the front surface of the substrate.
[0028] In one possible embodiment, the substrate is an N-type substrate, the first conductive layer includes a P-type doped layer, and the second conductive layer includes an N-type doped layer.
[0029] In one possible embodiment, a dielectric layer is disposed between at least one of the first conductive layer and the second conductive layer and the back surface of the substrate.
[0030] In one possible embodiment, the dielectric layer comprises silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.
[0031] In one possible embodiment, the thickness of the dielectric layer is between 0.5 nm and 3 nm.
[0032] In one possible embodiment, the dielectric layer does not cover the back surface of the substrate corresponding to the spacer region.
[0033] In one possible embodiment, the distance between the top and bottom surfaces of the first pyramid-shaped textured structure region ranges from 2µm to 4µm.
[0034] In one possible embodiment, the distance of the boundary region along the first direction ranges from 3µm to 5µm.
[0035] In one possible embodiment, the distance between the top and bottom surfaces of the linear textured structure ranges from 1µm to 4µm.
[0036] In one possible embodiment, the distance of the interval along the first direction ranges from 50 to 200 μm.
[0037] In one possible embodiment, the distance of the spacer region along the normal direction of the back surface of the substrate ranges from 1 to 6 μm.
[0038] In one possible embodiment, the ratio of the area of the spacer region to the area of the back surface of the substrate is 10%-35%.
[0039] Thirdly, this application also provides a method for preparing a solar cell, comprising the following steps: A substrate is provided, the substrate having a front surface and a back surface opposite to the front surface, the back surface having a first region and a second region arranged alternately along a first direction, and a spacer region recessed into the substrate between adjacent first regions and second regions. A first conductive layer is formed on the back surface of the substrate; Laser ablation is performed on the back surface of the substrate to remove the first conductive layer located in the second region and the spacer region; A second conductive layer is formed on the interval region and the second region; A first protective layer is formed on the surface of the second conductive layer at the location corresponding to the second region; Remove the second conductive layer that is not covered by the first protective layer; Remove the first protective layer; The texturing process involves forming a plurality of first pyramid-shaped textured structures on the back surface corresponding to the interval area, forming a plurality of second pyramid-shaped textured structures on the second conductive layer, having a boundary area between adjacent first pyramid-shaped textured structures and adjacent second pyramid-shaped textured structures, and forming a linear concave-convex textured structure on the back surface at the boundary area. A first electrode is formed on the first conductive layer, and a second electrode is formed on the second conductive layer.
[0040] In the method for preparing a solar cell as described above, preferably, the first protective layer is an ink INK protective layer.
[0041] Fourthly, this application also provides a photovoltaic module, comprising: A battery string, wherein the battery string is formed by connecting the aforementioned back-contact batteries; Encapsulation layer, the encapsulation layer being used to cover the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.
[0042] Compared with the prior art, the present invention optimizes the local structural design of the IBC battery. The spacer effectively separates the first conductive layer and the second conductive layer, reducing interfacial recombination. Furthermore, there is a boundary region between adjacent first pyramidal textured structure regions and adjacent second pyramidal textured structure regions. A linear concave-convex textured structure is formed on the back surface at the boundary region, thereby increasing the incident light reflection on the back surface of the substrate, increasing the amount of light absorbed by the back contact battery, and improving the conversion efficiency of the back contact battery. Attached Figure Description
[0043] Figure 1-1 This is a schematic diagram of the structure of the first type of back contact battery provided in this application; Figure 1-2 This is a schematic diagram of the structure of the second type of back contact battery provided in this application; Figure 1-3 This is a schematic diagram of the structure of the third type of back contact battery provided in this application; Figure 2This is a SEM image of the spacer region and the second conductive layer of the back contact battery provided by the present invention. Figure 3 yes Figure 2 A magnified view of a portion of the image; Figure 4 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application; Figure 5 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 2 ; Figure 6 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 3 ; Figure 7 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 4 ; Figure 8 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 5 ; Figure 9 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 6 ; Figure 10 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 7 ; Figure 11 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 8 ; Figure 12 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 9 ; Figure 13 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 10 ; Figure 14 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 10 one; Figure 15 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 10 two; Figure 16 This is a schematic diagram of the fabrication process of the first type of back contact battery provided in this application. Figure 10 three; Figure 17This is a schematic diagram of the structure of the photovoltaic module provided in this application.
[0044] Explanation of reference numerals in the attached figures: 1-Substrate, 101-First region, 102-Second region, 2-Front surface, 3-Back surface, 4-Spacer region, 5-Boundary region, 6-First conductive layer, 7-Second conductive layer, 8-First electrode, 9-Second electrode, 10-First pyramidal textured structure region, 11-Second pyramidal textured structure region, 12-Linear concave-convex textured structure, 13-Back passivation layer, 14-Front passivation layer, 15-Dielectric layer, 16-BSG layer, 17-PSG layer, 18-First protective layer, 19-Battery string, 20-Encapsulation layer, 21-Cover plate, 22-Antireflective layer; D1 - First direction. Detailed Implementation
[0045] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0046] Finger-shaped cross-back contact batteries, also known as IBC batteries, present a significant technical challenge: effectively separating the boron-doped and phosphorus-doped regions of the IBC battery while simultaneously improving its efficiency.
[0047] To address the aforementioned technical problems, embodiments of the present invention provide a solar cell, wherein the solar cell is an IBC cell, such as... Figure 1-1 , Figure 1-2 or Figure 1-3 As shown, a solar cell includes at least a substrate 1, a first conductive layer 6, a second conductive layer 7, a first electrode 8, and a second electrode 9, wherein: The substrate 1 has a front surface 2 and a back surface 3 opposite to the front surface 2. The front surface 2 is the light-receiving surface facing the direction of sunlight, and the back surface 3 is the surface opposite to the front surface 2.
[0048] The substrate 1 may be, for example, a crystalline semiconductor (e.g., crystalline silicon) containing dopants of a first conductivity type. The crystalline semiconductor may be single-crystal silicon, and the first conductivity type dopants may be N-type dopants such as those containing group V elements including phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb), or P-type dopants such as those containing group III elements including boron (B), aluminum (Al), gallium (Ga), and indium (In).
[0049] The back surface 3 has a first region 101 and a second region 102 arranged alternately along the first direction D1. There is a spacer region 4 between adjacent first regions 101 and second regions 102 that is recessed into the substrate 1. A first conductive layer 6 is formed on the first region 101 and a second conductive layer 7 is formed on the second region 102. The second conductive layer 7 has the opposite conductivity type to the first conductive layer 6. The spacer region 4 is used to physically separate the first conductive layer 6 and the second conductive layer 7, so that the first conductive layer 6 and the second conductive layer 7 are insulated from each other or the first electrode 8 and the second electrode 9 are insulated from each other, so as to avoid short circuits between the positive and negative electrodes of the battery or battery leakage, and improve the reliability of the battery.
[0050] The first electrode 8 forms an electrical contact with the first conductive layer 6, and the second electrode 9 forms an electrical contact with the second conductive layer 7. In some embodiments, the materials of the first electrode 8 and the second electrode 9 include at least one conductive metal material such as silver, aluminum, copper, and nickel.
[0051] Reference Figure 2 as well as Figure 3 As shown, several first pyramid-shaped textured structure regions 10 are formed on the back surface 3 corresponding to the interval region 4. The first pyramid-shaped textured structure regions 10 can be formed by texturing (or etching) processes. The texturing process can be chemical etching, laser etching, mechanical etching, plasma etching, etc. The first pyramid-shaped textured structure regions 10 have good light trapping and anti-reflection effects, so that the light incident on the back surface 3 can also be utilized, increasing the effective contact area of light, realizing further utilization of light energy, and improving power generation efficiency.
[0052] In some embodiments, a plurality of non-first pyramidal textured structure regions, such as stepped flat textured structures, are formed on the back surface 3 corresponding to the first region 101 and the second region 102, respectively.
[0053] A second pyramid-shaped textured structure region 11 is formed on the first conductive layer 6. The second pyramid-shaped textured structure region 11 can be formed by a texturing process, such as chemical etching, laser etching, mechanical etching, plasma etching, etc. The second pyramid-shaped textured structure region 11 has good light trapping and anti-reflection effects, so that the light incident on the back surface 3 can also be utilized, increasing the effective contact area of light, realizing further utilization of light energy, and improving the battery power generation efficiency.
[0054] In one feasible implementation, distinct from the first pyramidal textured structure region 10 and the second pyramidal textured structure region 11, a plurality of truncated pyramidal textured structure regions (not shown) are formed on the back surface 3 corresponding to the first conductive layer 6 and / or the second conductive layer 7. The truncated pyramidal textured structure regions can also have good light trapping and anti-reflection effects.
[0055] Continue to refer to Figure 2 as well as Figure 3 As shown, there is a boundary region 5 between adjacent first pyramidal textured structure region 10 and adjacent second pyramidal textured structure region 11. A linear concave-convex textured structure 12 is formed on the back surface 3 at the boundary region 5. The linear concave-convex textured structure 12 forms different light-trapping structures with the surfaces of the first pyramidal textured structure region 10 and / or the second pyramidal textured structure region 11, which can reduce interface recombination, increase the incident light reflection on the back surface 3 of the substrate 1, increase the amount of light absorbed by the solar cell, and allow the light to be reused by the cell, thereby improving the photoelectric conversion efficiency of the IBC cell.
[0056] Reference Figure 3 As shown, the linear textured structure 12 consists of stripes or lines arranged at intervals, with several stripes or lines parallel to each other. The opposite ends of the stripes or lines respectively contact the first pyramidal textured structure region 10 and the second pyramidal textured structure region 11. The reflectivity of incident light on the back of the battery can be increased by 2%-6%, allowing more incident light to reach the back of the battery and be reflected back into the substrate 1 for absorption, further improving the photoelectric conversion efficiency by 0.07%-0.15%.
[0057] like Figure 1-1 or Figure 1-2 As shown, the solar cell has an N-type cell structure. The substrate 1 is an N-type crystalline silicon substrate 1. The first conductive layer 6 includes a P-type doped layer (i.e., the emitter), and the second conductive layer 7 includes an N-type doped layer (i.e., the base).
[0058] In some embodiments, such as Figure 1-1 As shown, a first conductive layer 6 is formed inside the substrate 1 or on its back surface 3. For example, the first conductive layer 6 is formed by doping a predetermined region of the back surface 3 of the substrate 1 with a P-type dopant via methods such as deposition, diffusion, or printing. In this case, the P-type dopant can be any impurity with a conductivity type opposite to that of the substrate 1. That is, Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In) can be used. The crystal structure of the first conductive layer 6 is the same as that of the substrate 1, for example, monocrystalline silicon. A dielectric layer 15 is disposed between the second conductive layer 7 and the substrate 1. As an optional technical solution of this application, the dielectric layer 15 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride. The second conductive layer 7 is formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc., with an N-type dopant. The N-type dopant can be any dopant with the same conductivity type as the substrate 1. That is, Group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) can be used. Preferably, the second conductive layer 7 is a phosphorus-doped polycrystalline silicon layer. The crystal structure of the second conductive layer 7 is different from the crystal structure of the substrate 1.
[0059] In some embodiments, such as Figure 1-2 As shown, the second conductive layer 7 and... Figure 1-1 The second conductive layer 7 is the same as that described here, and will not be repeated. The difference is that a dielectric layer 15 is also disposed between the first conductive layer 6 and the silicon substrate 1. As an optional technical solution of this application, the dielectric layer 15 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride. The first conductive layer 6 is formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc., with a P-type dopant. That is, P-type dopants of group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In) can be used. Preferably, the first conductive layer 6 is a boron-doped polycrystalline silicon layer. The crystal structure of the first conductive layer 6 is different from the crystal structure of the substrate 1.
[0060] In some embodiments, refer to Figure 1-3 As shown, the solar cell has a P-type cell structure. The substrate 1 is a P-type crystalline silicon substrate, the first conductive layer 6 includes a P-type doped layer (i.e., the base), and the second conductive layer 7 includes an N-type doped layer (i.e., the emitter).
[0061] The P-type doped layer can be formed by creating an opening above the substrate 1 using processes such as laser etching, dry etching, wet etching, or mechanical scribing, exposing the P-type crystalline silicon substrate. Then, a first electrode 8 can be directly formed on the back surface 3 of the P-type crystalline silicon substrate, allowing the first electrode 8 to contact the back surface 3. This facilitates the diffusion of metal atoms from the first electrode 8 into the back surface 3, forming a base layer. The P-type doped layer includes an alloy layer (e.g., an Al-Si alloy layer) formed between the metal electrode and the substrate 1.
[0062] A dielectric layer 15 is disposed between the second conductive layer 7 and the substrate 1. As an optional technical solution in this application, the dielectric layer 15 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride. The second conductive layer 7 is formed by doping amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc., with an N-type dopant. The N-type dopant can be any dopant having the same conductivity type as the substrate 1. That is, group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), or antimony (Sb) can be used.
[0063] In the embodiments of this application, the IBC cell structure of this application is described using an N-type crystalline silicon substrate as an example.
[0064] Reference Figure 1-1 , Figure 15 as well as Figure 16As shown, it also includes a back passivation layer 13, which passivates the back surface of the battery, reduces the carrier recombination velocity on the back surface 3, and improves the photoelectric conversion efficiency by passivating the dangling bonds in the first conductive layer 6, the second conductive layer 7, and the spacer region 4. The back passivation layer 13 is located on the surfaces of the first conductive layer 6, the second conductive layer 7, and the spacer region 4. After the first electrode 8 penetrates the back passivation layer 13, it forms an electrical contact with the first conductive layer 6, and after the second electrode 9 penetrates the back passivation layer 13, it forms an electrical contact with the second conductive layer 7. As an optional technical solution of this application, the back passivation layer 13 may be provided with an opening to allow the first electrode 8 and the second electrode 9 to pass through and make electrical contact with the first conductive layer 6 and the second conductive layer 7, respectively. This reduces the contact area between the metal electrode and the first conductive layer 6 and the second conductive layer 7, further reducing the contact resistance and increasing the open-circuit voltage.
[0065] Optionally, the back passivation layer 13 includes a stacked structure of at least one or more of the following: silicon oxide layer, silicon nitride layer, aluminum oxide layer, and silicon oxynitride layer.
[0066] In some embodiments, the thickness of the back passivation layer 13 ranges from 10nm to 120nm, specifically 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 120nm, etc., and of course, other values within the above range are also possible, which are not limited here.
[0067] Optionally, a front passivation layer 14 is formed on the front surface 2 of the substrate 1. The front passivation layer 14 can passivate the front surface 2 of the substrate 1, reduce the recombination of charge carriers at the interface, improve the transport efficiency of charge carriers, and thus improve the photoelectric conversion efficiency of the IBC cell.
[0068] Optionally, the front passivation layer 14 includes a stacked structure of at least one or more of the following: silicon oxide layer, silicon nitride layer, aluminum oxide layer, and silicon oxynitride layer.
[0069] Optionally, an anti-reflection layer 22 is further provided on the surface of the front passivation layer 14. The anti-reflection layer 22 can reduce the reflection of incident light and improve the refraction of light, thereby improving the utilization rate of light and thus improving the photoelectric conversion efficiency. In some embodiments, similar to the anti-reflection layer 22, the front passivation layer 14 can also play a role in reducing the reflection of incident light.
[0070] Optionally, an ultrathin dielectric layer 15 is disposed between at least one of the first conductive layer 6 and the second conductive layer 7 and the back surface 3 of the substrate 1. The dielectric layer 15 is used to passivate the interface of the back surface 3 of the substrate 1, reduce the recombination of charge carriers at the interface, and ensure the transport efficiency of charge carriers. In the technical solution provided in this embodiment, refer to Figures 9 to 16As shown, the dielectric layer 15 may be disposed between the second conductive layer 7 and the back surface 3 of the substrate 1.
[0071] As an optional technical solution in this application, the dielectric layer 15 includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.
[0072] In some embodiments, the thickness of the dielectric layer 15 is between 0.5 nm and 3 nm. If the thickness of the dielectric layer 15 is too large, the tunneling effect of majority carriers is affected, making it difficult for carriers to transport through the dielectric layer 15, thereby affecting the tunneling and passivation effects of the dielectric layer 15, and the photoelectric conversion efficiency of the battery will gradually decrease. If the thickness of the dielectric layer 15 is too small, it is not conducive to contact with the electrode paste. Preferably, the thickness of the dielectric layer 15 is between 0.5 nm and 3 nm. Specifically, the thickness of the dielectric layer 15 is 0.5 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3 nm, etc., and other values within the above range are also possible and are not limited here.
[0073] In some embodiments, the dielectric layer 15 does not cover the back surface 3 of the substrate 1 corresponding to the spacer region 4. When the first conductive layer 6 is a P-type doped layer and the second conductive layer 7 is an N-type doped layer, the dielectric layer 15 is preferably a tunneling oxide layer. The tunneling oxide layer allows majority carriers to tunnel into the first conductive layer 6 and the second conductive layer 7 while blocking minority carriers from passing through. Consequently, majority carriers are laterally transported within the first conductive layer 6 and the second conductive layer 7 and collected by the first electrode 8 or the second electrode 9. The tunneling oxide layer, together with the first conductive layer 6 and the second conductive layer 7, constitutes a tunneling oxide passivation contact structure, which can achieve excellent interface passivation and selective collection of charge carriers, reduce carrier recombination, and improve the photoelectric conversion efficiency of the IBC cell. It should be noted that the tunneling oxide layer may not actually possess a perfect tunnel barrier, as it may contain defects such as pinholes, which can cause other charge carrier transport mechanisms (e.g., drift, diffusion) to dominate relative to the tunneling effect.
[0074] In some embodiments, the distance between the top and bottom surfaces of the first pyramidal textured structure region 10 ranges from 2µm to 4µm. Specifically, the distance can be 2.0µm, 2.5µm, 3.0µm, 3.5µm, 4.0µm, etc., or other values within the above range, which are not limited here. When the distance between the top and bottom surfaces of the first pyramidal textured structure region 10 is limited to the above range, the first pyramidal textured structure region 10 has good light-trapping and anti-reflection effects, thereby further improving the photoelectric conversion efficiency.
[0075] In some embodiments, the distance between the top and bottom surfaces of the second pyramidal textured structure region 11 ranges from 1µm to 3µm. Specifically, the distance can be 1µm, 1.5µm, 2.0µm, 2.5µm, 3.0µm, etc., or other values within the above range, which are not limited here. When the distance between the top and bottom surfaces of the second pyramidal textured structure region 11 is limited to the above range, the second pyramidal textured structure region 11 has good light-trapping and anti-reflection effects, thereby further improving the photoelectric conversion efficiency.
[0076] In some embodiments, the distance of the boundary region 5 along the first direction D1 ranges from 3µm to 5µm. Specifically, the distance can be 3.0µm, 3.5µm, 4.0µm, 4.5µm, 5.0µm, etc., or other values within the above range, which are not limited here. If the boundary region 5 is too wide, the effective area of the back surface 3 may be wasted, and effective charge carriers may be difficult to collect, thereby reducing battery performance. If the boundary region 5 is too narrow, it will not provide good insulation between the positive and negative electrodes.
[0077] In some embodiments, refer to Figure 2 as well as Figure 3 As shown, the distance between the top surface and the bottom surface of the linear textured structure 12 ranges from 1µm to 4µm. Specifically, the distance can be 1µm, 1.5µm, 2.0µm, 2.5µm, 3.0µm, etc., or other values within the above range. No limitation is made here. When the distance between the top surface and the bottom surface of the linear textured structure 12 is limited to the above range, the linear textured structure 12 can increase the reflection of incident light, thereby further improving the photoelectric conversion efficiency.
[0078] In some embodiments, the distance of the spacer region 4 along the first direction D1 ranges from 50 to 200 μm. Specifically, the distance can be 50 μm, 70 μm, 90 μm, 110 μm, 130 μm, 150 μm, 170 μm, 190 μm, 200 μm, etc., or other values within the above range, which are not limited here. If the spacer region 4 is too wide, the effective area of the back surface 3 may be wasted, and effective charge carriers may be difficult to collect, thereby reducing battery performance. If the spacer region 4 is too narrow, it will not provide good insulation between the positive and negative electrodes.
[0079] In some embodiments, the distance of the spacer 4 along the normal direction of the back surface 3 of the substrate ranges from 1 to 6 μm. Specifically, the distance can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, etc., or other values within the above range, which are not limited here.
[0080] In some embodiments, the ratio of the area of the spacer region 4 to the area of the back surface 3 of the substrate 1 is 10%-35%. Specifically, the ratio can be 10%, 15%, 20%, 25%, 30%, 35%, etc., or other values within the above range, which are not limited here. If the area of the spacer region 4 is too large, the effective area of the back surface 3 may be wasted, and effective charge carriers may be difficult to collect, thereby reducing battery performance. If the area of the spacer region 4 is too small, it will not provide good insulation between the positive and negative electrodes.
[0081] Based on the above embodiments, this application also provides a method for preparing an N-type solar cell, comprising the following steps: A substrate 1 is provided, the substrate 1 having a front surface 2 and a back surface 3 opposite to the front surface 2, the back surface 3 having a first region 101 and a second region 102 arranged alternately along a first direction D1, and a gap region 4 between adjacent first regions 101 and second regions 102. A first conductive layer 6 is formed on the back surface 3 of the substrate 1; Laser ablation is performed on the back surface 3 of substrate 1 to remove the first conductive layer 6 located in the second region 102 and the spacer region 4. A second conductive layer 7 is formed on the back surface 3 of the substrate 1; A first protective layer 18 is formed on the surface of the second conductive layer 7 at the location corresponding to the second region 102; Remove the second conductive layer 7 that is not covered by the first protective layer 18; Remove the first protective layer 18; In the texturing process, a plurality of first pyramid-shaped textured structure regions 10 are formed on the back surface 3 corresponding to the interval region 4, and a plurality of second pyramid-shaped textured structure regions 11 are formed on the second conductive layer 7. There is a boundary region 5 between adjacent first pyramid-shaped textured structure regions 10 and adjacent second pyramid-shaped textured structure regions 11, and a linear concave-convex textured structure 12 is formed on the back surface 3 at the boundary region 5. A first electrode 8 is formed on the first conductive layer 6, and a second electrode 9 is formed on the second conductive layer 7.
[0082] The solar cell fabricated using the above-described method has optimized local structural design of the IBC cell. The spacer region 4 effectively separates the first conductive layer 6 and the second conductive layer 7, reducing interfacial recombination. Furthermore, there is a boundary region 5 between adjacent first pyramidal textured structure regions 10 and adjacent second pyramidal textured structure regions 11. A linear concave-convex textured structure 12 is formed on the back surface 3 at the boundary region 5, thereby increasing the incident light reflection on the back surface 3 of the substrate 1, increasing the amount of light absorbed by the solar cell, and improving the conversion efficiency of the solar cell.
[0083] The following is a detailed introduction to this plan: In step S10, refer to Figure 4 As shown, the substrate 1 is preferably an N-type crystalline silicon substrate 1, the front surface 2 is the light-receiving surface facing the direction of sunlight, the back surface 3 is the surface opposite to the front surface 2, the first conductive layer 6 is formed on the first region 101, the second conductive layer 7 is formed on the second region 102, the second conductive layer 7 has the opposite conductivity type to the first conductive layer 6, and the spacing region 4 is used to separate the first conductive layer 6 and the second conductive layer 7 to improve the insulation performance of the positive and negative electrodes, avoid the occurrence of battery leakage, and improve the reliability of the battery.
[0084] In step S20, refer to Figure 5 and Figure 6 As shown, the substrate 1 is texturized to form a first conductive layer 6 on the back surface 3 of the substrate 1. In this embodiment, the first conductive layer 6 includes a P-type doped layer (i.e., emitter). Boron is doped into the substrate 1 by diffusion at a temperature of 800-1200℃ for 2-5 hours, forming the first conductive layer 6 on the back surface 3 of the N-type silicon wafer substrate 1. The diffusion sheet resistance is 70-120 ohm / sq. A diffused borosilicate glass (BSG) layer 16 is also formed on the doped layer, serving as an isolation layer to better protect the first conductive layer 6. The thickness of the BSG layer 16 is 100-200 nm. Understandably, during the boron diffusion process, a P-type doped layer and part of the BSG layer 16 are also formed on the front surface 2 of the substrate 1. This part of the borosilicate glass needs to be removed. Optionally, a 2%-15% chain-type HF acid can be used to remove the BSG layer 16 located on the front surface 2.
[0085] In step S30, refer to Figure 7 as well as Figure 8 As shown, laser ablation is performed on the back surface 3 of substrate 1 to remove the first conductive layer 6 located in the second region 102 and the spacer region 4. Specifically, laser ablation is first performed on the back surface 3, and the laser ablation pattern is interdigitated, corresponding to the sum of the second region 102 and the spacer region 4. After removing the BSG layer 16 in the corresponding region, the laser damage is removed by polishing. Specifically, the laser power is 8W-15W, the ablation width is 300um-600um, the polishing temperature is 50℃-65℃, the polishing time is 400s-800s, and the polishing solution includes 1%-5% NaOH or 1%-3% KOH and 0.5%-2.5% additives by volume. The polishing depth is 2-5um.
[0086] In step S40, refer to Figure 9As shown, a second conductive layer 7 is formed on the back surface 3 of the substrate 1. The second conductive layer 7 includes an N-type doped layer (i.e., the base). Specifically, a dielectric layer 15 (tunneling oxide layer) is first grown by thermal oxidation. The thickness of the dielectric layer 15 is 0.1-1 nm. Intrinsic polycrystalline silicon is deposited on the dielectric layer 15 by low-pressure chemical vapor deposition. The thickness of the polycrystalline silicon is in the range of 100-200 nm. Diffusion is carried out at a temperature of 700-1000 °C for 1-3 hours to dope phosphorus into the intrinsic polycrystalline silicon. A passivation contact structure is formed on the back side of the N-type silicon wafer substrate 1. The passivation contact structure is a stack of the dielectric layer 15 and the second conductive layer 7. The sheet resistance of the second conductive layer 7 is 25-45 ohm / sq. A phosphorus silicate glass (PSG) layer 17 is also diffused on the N-type polycrystalline silicon. The PSG layer 17 can be used as a barrier layer. The thickness of the PSG layer 17 is 20-100 nm.
[0087] In step S50, refer to Figure 10 As shown, a first protective layer 18 is formed on the surface of the second conductive layer 7 corresponding to the second region 102. In some feasible embodiments, the first protective layer 18 is an ink INK protective layer. A layer of interdigitated ink INK protective layer is coated on the PSG layer 17 of the second conductive layer 7 by screen printing or inkjet coating. The pattern of the ink INK protective layer is the grid pattern of the manufactured IBC battery.
[0088] In step S60, the second conductive layer 7 not covered by the first protective layer 18 is removed, and then the first protective layer 18 is removed; then texturing is performed, and a plurality of first pyramid-shaped textured structure regions 10 are formed on the back surface 3 corresponding to the spacing region 4, and a plurality of second pyramid-shaped textured structure regions 11 are formed on the first conductive layer 6. There is a boundary region 5 between adjacent first pyramid-shaped textured structure regions 10 and adjacent second pyramid-shaped textured structure regions 11, and a linear concave-convex textured structure 12 is formed on the back surface 3 at the boundary region 5. Specifically: S601, see reference Figure 11 As shown, HF acid with a volume fraction of 1%-20% is used to etch the PSG layer 17 that is not covered by the first protective layer 18, and the etching time is 5s-60s.
[0089] S602, see reference Figure 12 As shown, after removing the PSG layer 17 that is not covered by the first protective layer 18, the first protective layer 18 is washed away with an alkaline solution. The alkaline solution is a NaOH solution with a concentration of 1%-10% for 180s-300s.
[0090] S603, refer to Figure 13As shown, texturing or alkaline polishing is performed in an alkaline solution with a NaOH concentration of 0.5%-5%, at a temperature of 60-80℃, and a reaction time of 240s-500s. The second conductive layer 7 without PSG layer 17 protection is then etched away to form the spacer region 4.
[0091] S603, refer to Figure 14 As shown, the texturing substrate 1 is subjected to RCA cleaning, and then cleaned in a 1%-10% HF solution to clean the surface of the substrate 1 and remove the dielectric layer 15, BSG layer 16 and PSG layer 17 on the surface of the substrate 1, thereby forming structures with different morphologies in different regions of the back surface 3; a first pyramid-shaped textured structure region 10 is formed in the spacer region 4, and the distance (or height) between the top and bottom of the first pyramid-shaped textured structure region 10 ranges from 2-4 μm; a plurality of second pyramid-shaped textured structure regions 11 are formed on the second conductive layer 7, and the distance (or height) between the top and bottom of the second pyramid-shaped textured structure region 11 ranges from 1-3 μm; there is a boundary region 5 between adjacent first pyramid-shaped textured structure regions 10 and adjacent second pyramid-shaped textured structure regions 11, and the width of the boundary region 5 is 3-5 μm; a linear concave-convex textured structure 12 is formed on the back surface 3 at the boundary region 5.
[0092] In step S70, refer to Figure 15 as well as Figure 16 As shown, a front passivation layer 14 and a back passivation layer 13 are deposited on the front surface 2 and back surface 3 of the substrate 1, respectively. The front passivation layer 14 is a stack of aluminum oxide, silicon oxide, and silicon nitride, and the back passivation layer 13 is aluminum oxide and silicon nitride. Silver aluminum paste and silver paste are printed on the back surface 3 of the substrate 1. The silver aluminum paste is aligned with the first conductive layer 6 to form the first electrode 8, and the silver paste is aligned with the second conductive layer 7 to form the second electrode 9. Metallization is completed by sintering.
[0093] Based on the above embodiments, referring to Figure 17 As shown, this application also provides a photovoltaic module, including: a battery string 19, the battery string 19 being formed by connecting the aforementioned solar cells, and adjacent battery strings 19 being connected by a conductive strip such as a solder ribbon; an encapsulation layer 20, the encapsulation layer 20 being used to cover the surface of the battery string 19; and a cover plate 21, the cover plate 21 being used to cover the surface of the encapsulation layer 20 away from the battery string 19.
[0094] In some embodiments, the number of battery strings 19 is at least two, and the battery strings 19 are electrically connected by means of parallel and / or series connection.
[0095] In some embodiments, the encapsulation layer 20 includes encapsulation layers disposed on the front and back sides of the battery string 19, and the material of the encapsulation layer 20 includes, but is not limited to, EVA, POE or PET films.
[0096] In some embodiments, the cover plate 21 includes a cover plate 21 disposed on the front and back of the battery string 19, and the cover plate 21 is made of a material with good light transmittance, including but not limited to glass, plastic and the like.
[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.
Claims
1. A back contact cell, characterized in that, include: The substrate has a front surface and a back surface. The back surface has a first region and a second region arranged alternately along a first direction. There is a gap between adjacent first regions and second regions that is recessed into the substrate. A plurality of first pyramid-shaped textured structure regions are formed on the back surface corresponding to the gap regions. A first conductive layer formed on the first region; A second conductive layer is formed on the second region, the second conductive layer having a conductivity type opposite to that of the first conductive layer; in: A plurality of second pyramid-shaped textured structure regions are formed on the back surface corresponding to the first conductive layer and / or the second conductive layer; the interval region has a boundary region with the adjacent first conductive layer and / or the second conductive layer, and the boundary region of the back surface corresponding to the boundary region has a linear concave-convex textured structure.
2. The back contact cell of claim 1, wherein: The linear texture structure is a strip or line texture structure arranged at intervals.
3. The back contact cell of claim 2, wherein: One end of the strip-shaped or line-shaped texture structure is connected to the first pyramid-shaped texture structure area, and the other end is connected to the second pyramid-shaped texture structure area.
4. The back contact battery according to claim 1, characterized in that: It also includes a back passivation layer, which is located on the surface of the first conductive layer, the second conductive layer and the spacer region; the back passivation layer has a first electrode and a second electrode, the first electrode forming an electrical contact with the first conductive layer and the second electrode forming an electrical contact with the second conductive layer.
5. The back contact battery according to claim 1, characterized in that: A front passivation layer is formed on the front surface of the substrate.
6. The back contact battery according to claim 1, characterized in that: The substrate is an N-type substrate, the first conductive layer includes a P-type doped layer, and the second conductive layer includes an N-type doped layer.
7. The back contact battery according to claim 1, characterized in that: A dielectric layer is disposed between at least one of the first conductive layer and the second conductive layer and the back surface of the substrate.
8. The back contact battery according to claim 7, characterized in that: The dielectric layer includes silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.
9. The back contact battery according to claim 7, characterized in that: The thickness of the dielectric layer is between 0.5 nm and 3 nm.
10. The back contact battery according to claim 7, characterized in that: The dielectric layer does not cover the back surface of the substrate corresponding to the spacer region.
11. The back contact battery according to claim 1, characterized in that: The distance between the top and bottom surfaces of the first pyramid-shaped textured structure region ranges from 2µm to 4µm.
12. The back contact battery according to claim 1, characterized in that: The distance between the top and bottom surfaces of the second pyramid-shaped textured structure region ranges from 1µm to 3µm.
13. The back contact battery according to claim 1, characterized in that: The distance of the boundary region along the first direction ranges from 3um to 5um.
14. The back contact battery according to claim 1, characterized in that: The distance between the top and bottom surfaces of the linear textured structure ranges from 1µm to 4µm.
15. The back contact battery according to claim 1, characterized in that: The distance of the interval along the first direction ranges from 50 to 200 μm.
16. The back contact battery according to claim 1, characterized in that: The distance of the spacer zone along the normal direction of the back surface of the substrate ranges from 1 to 6 μm.
17. The back contact battery according to claim 1, characterized in that: The ratio of the area of the spacer region to the area of the back surface of the substrate is 10%-35%.
18. A back-contact battery, characterized in that, include: The substrate has a front surface and a back surface. The back surface has a first region and a second region arranged alternately along a first direction. There is a gap between adjacent first regions and second regions that is recessed into the substrate. A plurality of first pyramid-shaped textured structure regions are formed on the back surface corresponding to the gap regions. A first conductive layer formed on the first region; A second conductive layer is formed on the second region, the second conductive layer having a conductivity type opposite to that of the first conductive layer; in: A plurality of stepped flat texture structures are formed on the back surface corresponding to the first conductive layer and / or the second conductive layer; there is a boundary region between the interval region and the adjacent first conductive layer and / or the second conductive layer, and the boundary region of the back surface corresponding to the boundary region is formed with a linear concave-convex texture structure.
19. The back contact battery according to claim 18, characterized in that: The linear texture structure is a strip or line texture structure arranged at intervals.
20. The back contact battery according to claim 19, characterized in that: One end of the strip-shaped or line-shaped texture structure is connected to the first pyramid-shaped texture structure area, and the other end is connected to the second pyramid-shaped texture structure area.
21. The back contact battery according to claim 18, characterized in that: It also includes a back passivation layer, which is located on the surface of the first conductive layer, the second conductive layer and the spacer region; the back passivation layer has a first electrode and a second electrode, the first electrode forming an electrical contact with the first conductive layer and the second electrode forming an electrical contact with the second conductive layer.
22. The back contact battery according to claim 18, characterized in that: A front passivation layer is formed on the front surface of the substrate.
23. The back contact battery according to claim 18, characterized in that: The substrate is an N-type substrate, the first conductive layer includes a P-type doped layer, and the second conductive layer includes an N-type doped layer.
24. The back contact battery according to claim 18, characterized in that: A dielectric layer is disposed between at least one of the first conductive layer and the second conductive layer and the back surface of the substrate.
25. The back contact battery according to claim 24, characterized in that: The dielectric layer includes silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.
26. The back contact battery according to claim 24, characterized in that: The thickness of the dielectric layer is between 0.5 nm and 3 nm.
27. The back contact battery according to claim 24, characterized in that: The dielectric layer does not cover the back surface of the substrate corresponding to the spacer region.
28. The back contact battery according to claim 18, characterized in that: The distance between the top and bottom surfaces of the first pyramid-shaped textured structure region ranges from 2µm to 4µm.
29. The back contact battery according to claim 18, characterized in that: The distance of the boundary region along the first direction ranges from 3um to 5um.
30. The back contact battery according to claim 18, characterized in that: The distance between the top and bottom surfaces of the linear textured structure ranges from 1µm to 4µm.
31. The back contact battery according to claim 18, characterized in that: The distance of the interval along the first direction ranges from 50 to 200 μm.
32. The back contact battery according to claim 18, characterized in that: The distance of the spacer zone along the normal direction of the back surface of the substrate ranges from 1 to 6 μm.
33. The back contact battery according to claim 18, characterized in that: The ratio of the area of the spacer region to the area of the back surface of the substrate is 10%-35%.
34. A photovoltaic module, characterized in that, include: A battery string, wherein the battery string is formed by connecting back-contact batteries according to any one of claims 1 to 17 or any one of claims 18 to 33; Encapsulation layer, the encapsulation layer being used to cover the surface of the battery string; A cover plate for covering the surface of the encapsulation layer away from the battery string.