A deep ultraviolet light emitting diode chip, a preparation method and a packaging structure thereof

Abstract

This invention discloses a deep ultraviolet (DUV) light-emitting diode (LED) chip, its fabrication method, and packaging structure. Addressing the issue of chip breakdown in existing DUV chips under negative ion environments, this invention introduces a multi-layer passivation stack structure based on the traditional chip structure. Insulating layers and metal shielding layers are incorporated within the multi-layer passivation stack. The metal shielding layer is then led out from within the multi-layer passivation stack, forming an independent electrical connection and electrically connecting to a metal discharge electrode. Simultaneously, this invention provides a DUV LED packaging structure adapted to the chip structure. By incorporating discharge pins within the packaging structure and electrically connecting them to the chip's discharge electrode, the negative charge accumulated around and on the chip's surface during operation can be discharged to an external ground terminal through the discharge electrode, structurally preventing the DUV LED chip from being damaged. This invention features a simple structure and compatible processes, significantly improving the reliability and lifespan of the DUV LED chip in negative ion coexistence environments.

Description

Technical Field

[0001] This invention relates to the technical field of light-emitting diode chips and their packaging structures, and more particularly to a deep ultraviolet light-emitting diode chip, its fabrication method, and its packaging structure. Background Technology

[0002] Light-emitting diodes (LEDs) are commonly used light-emitting devices that efficiently convert electrical energy into light energy, and they have a wide range of applications in modern society. Deep ultraviolet (DUV) LEDs based on group III nitride materials have gained increasing attention and importance in the field of sterilization and disinfection in recent years due to their advantages such as environmental friendliness, compact size and portability, low power consumption, and low voltage. They are widely used in industrial and daily life scenarios such as air sterilization, water sterilization, and surface sterilization. Their most widespread application is in disinfection cabinets. Typically, germicidal LED beads are installed on the top, side, and bottom walls of the disinfection cabinet. The UV light emitted by the LEDs directly irradiates the interior of the cabinet, thus sterilizing the surfaces of objects placed inside. However, UV sterilization has certain shortcomings. First, there are inevitably blind spots in the light penetration; second, UV light has poor penetration, and it cannot effectively sterilize the interior of containers or obstructed objects. Therefore, to ensure sterilization effectiveness, negative ion sterilization technology is often used in practice. Specifically, negative ion generators are used to produce negative ions to enhance the sterilization effect while UV sterilization is being performed.

[0003] The mechanism of a negative ion generator involves using a pulsed, oscillating circuit to create a DC negative high voltage. This high voltage is then discharged through a carbon brush tip, generating a corona discharge that releases a large number of electrons into the air. These electrons are immediately captured by oxygen in the air, forming negative ions. Under the repulsive force of the negative electric field, they rapidly diffuse into the surrounding space. However, in practical applications, it has been found that the continuous and large amount of negative charge generated by the negative ion generator, especially in confined spaces such as disinfection cabinets, creates a localized high-voltage electric field. This type of charge accumulation is characterized by its long duration, short range, and stable field strength. Negative charges easily accumulate on the surface of deep ultraviolet (DUV) light-emitting diodes (LEDs) and their encapsulation. Although the DUV encapsulation structure typically contains electrostatic discharge (ESD) protection mechanisms, these only protect against static electricity generated by the human body and the environment; the continuous discharge from negative ions remains difficult to prevent.

[0004] Therefore, how to solve the breakdown damage problem of deep ultraviolet light-emitting diode chips in application scenarios where they coexist with negative ions, from the perspective of chip structure and manufacturing process, has become an urgent technical problem to be solved in this field. Summary of the Invention

[0005] This invention addresses the problem of overly simplistic solutions in existing technologies by providing a significantly different approach. The invention provides a deep ultraviolet (DUV) light-emitting diode (LED) chip, its fabrication method, and packaging structure to solve the problem of DUVs being unable to withstand negative ion breakdown damage in specific application scenarios. It achieves a highly reliable and compatible chip structure design that resists negative ion breakdown without significantly altering existing flip-chip processes and structures.

[0006] The embodiments of the present invention adopt the following technical solution: a deep ultraviolet light-emitting diode chip and its preparation method and packaging structure. The deep ultraviolet light-emitting diode chip structure includes, from bottom to top, an epitaxial stack, a first current spreading layer, a second current spreading layer, a reflective layer, a passivation stack, a first metal electrode with P-type properties, a second metal electrode with N-type properties, and a third metal electrode with electrical neutrality. The epitaxial stack includes a substrate of conventional structure, a buffer layer disposed on one side of the substrate from bottom to top, a first semiconductor layer, an active layer, and a second semiconductor layer; A partial area of ​​the first semiconductor layer is exposed, and a patterned first current spreading layer is laid on the partially exposed first semiconductor layer to form an electrical connection; a patterned second current spreading layer is laid on the remaining second semiconductor layer to form a wire connection. A patterned reflective layer is disposed on the second current spreading layer, or it is patterned into multiple independent parts and disposed on the exposed first semiconductor layer and the second current spreading layer simultaneously; the reflective layer may be a stack of one or more metals, or a patterned optical stack with a DBR reflective structure made of insulating oxide material. The passivation stack covers the entire surface of the exposed first and second semiconductor layers, first and second current spreading layers, and reflective layer. The passivation stack is composed of multiple insulating layers and metal layers stacked from bottom to top. Its structural feature is that the first and last layers are insulating layers, the middle layer is a metal layer, or it is composed of metal layers and insulating layers stacked sequentially.

[0007] Each layer of the passivation stack has conductive vias of different sizes, shapes and positions. The conductive vias of the stack are superimposed from the vertical projection direction to form a first conductive via with P-type properties, a second conductive via with N-type properties, and a third conductive via with electrical neutral properties. The third conductive via partially penetrates the passivation stack. A first metal electrode passes through the first conductive via and is electrically connected to the first current spreading layer. The second metal electrode passes through the second conductive via and is electrically connected to the second current spreading layer. The third metal electrode penetrates the third conductive via and forms an electrical connection with the metal layer within the passivation stack.

[0008] A second aspect of the present invention provides a method for manufacturing a deep ultraviolet light-emitting diode, comprising: An epitaxial stack is formed by growing a semiconductor layer on a substrate, including a buffer layer, a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially. Partial removal of the second semiconductor layer and the active layer exposes part of the first semiconductor layer; A first current spreading layer and a second current spreading layer are sequentially deposited on the upper surfaces of the first semiconductor layer and the partially exposed second semiconductor layer, and the first current spreading layer and the second current spreading layer are sequentially subjected to high-temperature annealing. A metal reflective layer is deposited on top of the second semiconductor layer or at another suitable location; Alternatively, a non-metallic reflective stack may be deposited on top of the second semiconductor layer or at another suitable location, and openings may be etched into the non-metallic reflective stack to expose the first current spreading layer and the second current spreading layer. A first insulating layer is deposited on the surface of the semiconductor multilayer structure, and the first insulating layer constitutes the first layer of the passivation stack. After patterning the first insulating layer, selective etching is performed to create openings, thereby exposing the first current spreading layer and the second current spreading layer. A patterned protective material is applied to the opening located above the first insulating layer; A first metal layer is deposited on the surface of the first insulating layer, and the first metal layer constitutes the second layer of the passivation stack. The protective material and a portion of the first metal layer thereon are stripped away, leaving the first and second current spreading layers exposed by the openings in the first insulating layer exposed; due to the isolation of the first insulating layer, the first metal layer is electrically isolated from the first and second current spreading layers. A second insulating layer is deposited on the surface of the semiconductor multilayer structure, and the second insulating layer constitutes the third layer of the passivation stack. Selective etching is performed on the second insulating layer to create openings, thereby keeping the aforementioned partially exposed first and second current spreading layers exposed; and partially exposing the first metal layer. A first metal electrode, a second metal electrode, and a third metal electrode are formed on the via corresponding to the properties of the second insulating layer.

[0009] A third aspect of the present invention provides a packaging structure for a deep ultraviolet light-emitting diode, comprising: A support is provided, which consists of a substrate and a surrounding dam. A deep ultraviolet light-emitting diode chip provided by the present invention is soldered inside the cup of the support. An optical lens is located on the top surface of the supporting dam. The optical lens and the support form a sealed structure to encapsulate the deep ultraviolet light-emitting diode chip provided by the present invention.

[0010] The substrate has a first pad, a second pad, and a third pad on its upper surface. The positions and spacing of the first pad, second pad, and third pad correspond to the first metal electrode, second metal electrode, and third metal electrode of the deep ultraviolet light-emitting diode chip of the present invention, and they form electrical connections after soldering. Conductive vias are provided inside the substrate, and the first pad, second pad, and third pad are electrically connected to the first pin, second pin, and third pin on the back of the substrate via these conductive vias. The first pin is connected to the positive terminal of an external circuit, the second pin is connected to the negative terminal of an external circuit, and the third electrode is connected to an external discharge circuit or a preset ground terminal.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: Firstly, to address the problem that existing deep ultraviolet LED chips are prone to chip breakdown in the presence of negative ions, a multi-layer passivation stack structure is introduced on the basis of the traditional flip chip structure. By setting an insulating layer and a metal shielding layer in the multi-layer passivation stack, and selectively opening holes on each stack, the metal shielding layer is led out from the inside of the multi-layer passivation stack to form an independent electrical connection and connect to an independent metal electrode. Secondly, in existing technologies, conventional deep ultraviolet LED chips mostly adopt a flip-chip structure, with a single or multiple insulating oxide layer, such as silicon oxide, as an insulating protective layer on top of their epitaxial stack, and the chip only has P-type and N-type electrodes. The insulating protective layer is used to construct the insulation measures inside the chip to prevent improper conduction of conductive layers with different properties, such as P-type and N-type electrodes, and their corresponding conductive layers, extension layers, and semiconductor layers. When the deep ultraviolet LED chip is in an environment with a large accumulation of charge, such as inside a disinfection cabinet filled with negative ions, harmful charges accumulate continuously on the surface of the chip or the package electrically connected to it and cannot be effectively discharged. This can easily break through the internal insulating protective layer of the chip, leading to internal leakage, failure, or even burnout, seriously restricting the reliability and service life of the equipment. The deep ultraviolet light-emitting diode chip of the present invention, in addition to having the P-type and N-type electrodes of the conventional chip structure, also has an independent discharge electrode. The discharge electrode is directly connected to the intermediate metal shielding layer of the multi-layered structure, which can discharge the negative charge that accumulates around and on the surface of the chip during operation to the external grounding terminal, eliminating the high-voltage electric field on the chip surface and structurally preventing the deep ultraviolet LED chip from being damaged by breakdown. This invention has a simple structure and compatible processes, significantly improving the reliability and service life of deep ultraviolet LED chips in negative ion coexistence environments. Thirdly, the deep ultraviolet light-emitting diode (LED) packaging structure provided by this invention aims to provide a packaging structure adapted to the electrode structure characteristics of the deep ultraviolet light-emitting diode chip of this invention. In this packaging structure, in addition to the positive and negative electrode pins of a conventional packaging structure, a discharge pin is also provided to electrically connect to the third electrode of the deep ultraviolet light-emitting diode chip of this invention inside the packaging structure. This allows the charge accumulated on or around the surface of the deep ultraviolet diode chip to be discharged through the discharge pin, eliminating the risk of chip breakdown. Attached Figure Description

[0012] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 A cross-sectional view of a deep ultraviolet light-emitting diode chip provided in an embodiment of the present invention; Figure 2 A schematic diagram of the metal electrode and its opening in a deep ultraviolet light-emitting diode chip provided in an embodiment of the present invention. Figure 3A schematic diagram of the metal electrode and its opening in another deep ultraviolet light-emitting diode chip provided in an embodiment of the present invention; Figure 4 A schematic diagram of a packaging structure adapted to a deep ultraviolet light-emitting diode chip provided in an embodiment of the present invention; Figure 5 This is a flowchart illustrating a method for fabricating a deep ultraviolet light-emitting diode chip, as provided in an embodiment of the present invention.

[0014] Figure label: 11. Substrate; 12. First semiconductor layer; 13. Active layer; 14. Second semiconductor layer; 21. First current spreading layer; 22. Second current spreading layer; 23. Reflective layer; 24. First insulating layer; 25. First metal layer; 26. Last insulating layer; 27. First metal electrode; 28. Second metal electrode; 29. ​​Third metal electrode; 30. Substrate; 31. Dam; 32. Optical lens; 33. First pad; 34. Second pad; 35. Third pad; 36. Conductive via. Detailed Implementation

[0015] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0016] The components of the embodiments of the invention described and shown in the accompanying drawings can typically be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0017] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0020] The deep ultraviolet light-emitting diode consists of, from bottom to top, an epitaxial stack, a first current spreading layer 21, a second current spreading layer 22, a reflective layer 23, a passivation stack, a first metal electrode 27 with P-type properties, a second metal electrode 28 with N-type properties, and a third metal electrode 29 with a discharge function. The epitaxial stack includes a conventional substrate 11, a buffer layer disposed on one side of the substrate 11 from bottom to top, a first semiconductor layer 12, an active layer 13, and a second semiconductor layer 14; Specifically, the substrate 11 can be made of non-metallic materials such as sapphire or silicon carbide, the first semiconductor layer 12 can be a P-type semiconductor layer made of group III nitride material, the second semiconductor layer 14 is an N-type semiconductor layer, and the active layer 13 is a light-emitting layer. It should be understood that an electron blocking layer can also be formed between the active layer 13 and the second semiconductor layer 14.

[0021] A partial area of ​​the first semiconductor layer 12 is exposed, and a patterned first current spreading layer 21 is laid on the partially exposed first semiconductor layer 12 to form an electrical connection; a patterned second current spreading layer 22 is laid on the remaining second semiconductor layer 14 to form a wire connection. The first current spreading layer 21 can be made of one or more of the following materials: titanium, gold, aluminum, platinum, silver, nickel, etc.

[0022] The gold-semiconductor interface between the first current spreading layer 21 and the first semiconductor layer 12 needs to be obtained by a high-temperature rapid annealing process to achieve ohmic contact. The annealing temperature is in the range of 800-1100℃, depending on the type of metal and the semiconductor doping concentration. The second current spreading layer 22 can be made of metal oxides such as zinc oxide and indium tin oxide, or materials such as carbon nanotubes, or metal materials such as titanium, gold, aluminum, platinum, silver, nickel, and rhodium, or a stack of these materials.

[0023] The gold-semiconductor interface between the second current spreading layer 22 and the second semiconductor layer 14 also needs to be rapidly annealed to obtain ohmic contact. A patterned reflective layer 23 is disposed on the second current spreading layer 22, or it is patterned into multiple independent parts and disposed on the exposed first semiconductor layer 12 and the second current spreading layer 22 simultaneously; the reflective layer 23 may be a stack of one or more metals, or a patterned optical stack with a DBR reflective structure made of insulating oxide material. The passivation stack covers the entire surface of the exposed first and second semiconductor layers 14, first and second current spreading layers, and reflective layer 23. The passivation stack is composed of multiple insulating layers and metal layers stacked from bottom to top. Its structural feature is that its first and last layers are insulating layers, and its material is, for example, silicon oxide, aluminum oxide, aluminum nitride, magnesium fluoride, etc.

[0024] Its intermediate layer is a metal layer, which is made of materials such as titanium, gold, aluminum, platinum, silver, nickel, rhodium, etc., or is composed of a stack of these materials.

[0025] The intermediate layer can also be composed of multiple pairs of metal layers and insulating layers stacked sequentially.

[0026] Each layer of the passivation stack has conductive vias 36 of different sizes, shapes and positions. The conductive vias 36 of each stack are superimposed from the vertical projection direction to form a first conductive via 36 with P-type properties, a second conductive via 36 with N-type properties, and a third conductive via 36 with electrical neutral properties. The third conductive via 36 partially penetrates the passivation stack. The first metal electrode 27 passes through the first conductive via 36 and is electrically connected to the first current spreading layer 21. The second metal electrode 28 passes through the second conductive via 36 and is electrically connected to the second current spreading layer 22; The third metal electrode 29 penetrates the third conductive via 36 and is electrically connected to the metal layer within the passivation stack.

[0027] The arrangement of the first metal electrode 27, the second metal electrode 28, and the third metal electrode 29, and their respective first conductive vias 36, second conductive vias 36, and third conductive vias 36 on the chip is as follows: Figure 2 or Figure 3 As shown.

[0028] The method for fabricating a deep ultraviolet light-emitting diode in this embodiment includes: Step 1: A semiconductor layer is grown on the substrate 11 to form an epitaxial stack, including a buffer layer, a first semiconductor layer 12, an active layer 13 and a second semiconductor layer 14 stacked sequentially. Optionally, an electron blocking layer may be deposited between the active layer 13 and the second semiconductor layer 14.

[0029] Step 2: Pattern the second semiconductor layer 14 and the active layer 13 to expose a portion of the first semiconductor layer 12. A patterning method is used to remove a portion of the second semiconductor layer 14 and the active layer 13, exposing a portion of the first semiconductor layer 12, wherein the second semiconductor layer 14 and the active layer 13 can be aligned. For example, photolithography or plasma etching can be used to remove a portion of the second semiconductor layer 14 and the active layer 13 on the first semiconductor layer 12.

[0030] Step 3: Deposit a first current spreading layer 21 on the partially exposed first semiconductor layer 12, and perform high-temperature annealing on the first current spreading layer 21. Specifically, the first current spreading layer 21, which is in electrical contact with the first semiconductor layer 12, is formed on the first semiconductor layer 12 by sputtering, evaporation, or other methods. The first current spreading layer 21 can be made of one or more of titanium, gold, aluminum, platinum, silver, nickel, etc., in a stack.

[0031] After the first current extension layer 21 is formed, a high-temperature annealing temperature is selected according to the composition of the metal and the semiconductor doping concentration of the first current extension layer 21, so as to perform high-temperature annealing on the first current extension layer 21 and improve the ohmic contact performance between the first current extension layer 21 and the first semiconductor layer 12. The high-temperature annealing temperature can be 800-1100℃.

[0032] Step 4: Deposit a second current spreading layer 22 on the second semiconductor layer 14, and perform rapid annealing on the second current spreading layer 22. Specifically, the second current spreading layer 22 is formed on the second semiconductor layer 14 by sputtering, evaporation, or other methods. The second current spreading layer 22 is disposed on the second semiconductor layer 14 and is in electrical contact with the second semiconductor layer 14. The material of the second current spreading layer 22 can be zinc oxide, indium tin oxide, carbon nanotubes, etc.; it can also be metal materials such as Ni, Au, Cr, W, Ti, Rh, or an alloy of multiple materials.

[0033] After the second current extension layer 22 is formed, it is rapidly annealed at a temperature of 400-600°C to improve the ohmic contact between the second current extension layer 22 and the second semiconductor layer 14.

[0034] Step 5: Deposit a reflective layer 23 or a reflective stack on the second current extension layer 22 or at other suitable locations. For example, it may be a metallic aluminum reflective layer 23, or a reflective stack composed of oxides such as silicon oxide or magnesium fluoride. When the reflective layer 23 is a metallic reflective layer 23, it can be directly attached to the second current extension layer 22 to form an electrical connection. When the reflective layer 23 is an insulating oxide reflective stack, it needs to be photolithographically etched and etched to expose part of the second current extension layer 22 by creating openings. Step 6: Deposit a first insulating layer on the surface of the semiconductor multilayer structure. The first insulating layer constitutes the first layer of the passivation stack, and its material can be, for example, silicon oxide. The first insulating layer completely covers the partially exposed first semiconductor layer 12, first current spreading layer 21, second semiconductor layer 14, second current spreading layer 22, and reflective layer 23 or reflective stack. Step 7: Pattern the first insulating layer and selectively etch openings in the first insulating layer to form a first opening on the first current spreading layer 21 and a second opening on the second current spreading layer 22. The first current spreading layer 21 and the second current spreading layer 22 inside the first opening and the second opening are exposed. The first opening and the second opening can be located in one or more places and can be one or more shapes. In this embodiment, for the convenience of subsequent description, the inventors make hypothetical settings for the shape and size of the first opening and the second opening, for example, defining the first opening and the second opening as circular shapes with a diameter of 20um. Step 8: A patterned protective material is applied to the openings located on the first insulating layer. The protective material can typically be photoresist. Specifically, the photoresist is spin-coated onto the first insulating layer and then photolithographically etched and developed, leaving only the portions above the first and second openings on the first insulating layer intact, ensuring that the interior and sidewalls of the first and second openings are completely covered by the photoresist. As described above, the protective material is a cylinder with a diameter greater than 20 μm, and its center position overlaps with the center position of the corresponding first and second openings. Step 9: Deposit a first metal layer 25 on the surface of the first insulating layer; clean and strip the photoresist covering the opening area and the first metal layer 25 thereon, so that the current spreading layer at the bottom of the first opening and the second opening is exposed again, and the first metal layer 25 and the current spreading layer are electrically isolated by the first insulating layer. Step 10: Deposit a second insulating layer on the first metal layer 25. When the structure is "insulating layer-metal layer-insulating layer", the second insulating layer is the third layer (top layer) or the last layer of the passivation stack. The second insulating layer completely covers the first metal layer 25, the first current spreading layer 21 and the second current spreading layer 22 partially exposed at the first and second opening positions, and the reflective layer 23 or reflective stack. Step 11: Selectively etch openings in the second insulating layer to form a first opening, a second opening, and a third opening on the second insulating layer. The first and second openings on the second insulating layer correspond sequentially in shape and position to the first and second openings on the first insulating layer, and their diameters are equal to or smaller than those of the first and second openings on the first insulating layer. This ensures that the exposed portions of the first current spreading layer 21 and the second current spreading layer 22 within the aforementioned opening locations remain exposed; the third opening on the second insulating layer exposes the opening in the first metal layer 25 below it. In this embodiment, the first insulating layer-first metal layer 25-second insulating layer with each opening constitutes a three-layer passivation stack. In another preferred embodiment, it can also be a multi-layer stack composed of first insulating layer 24-first metal layer 25-second insulating layer-second metal layer-last insulating layer 26. Step 12: A first metal electrode 27, a second metal electrode 28, and a third metal electrode 29 are laminated on the second insulating layer. The first metal electrode 27 covers the first opening and is electrically connected to the first current spreading layer 21. The second metal electrode 28 covers the second opening and is electrically connected to the second current spreading layer 22. The third metal electrode 29 covers the third opening and is electrically connected to the first metal layer 25. The first to third metal electrodes 29 may be made of one or more of the following materials: titanium, gold, aluminum, platinum, silver, nickel, tin, and gold-tin alloy. Step 13: Thinning and dicing the deep ultraviolet light-emitting diode chip to obtain the final shape. This thinning and dicing method can be any existing method, and this embodiment is not limited to it.

[0035] like Figure 4 As shown, the packaging structure of a deep ultraviolet light-emitting diode in this embodiment includes: A support is provided, comprising a substrate 30 and a surrounding dam 31 forming a semi-enclosed structure with an open top. A first pad 33, a second pad 34, and a third pad 35 are disposed within a cup-shaped portion of the substrate 30 facing the dam 31. The positions and spacing of the first pad 33, the second pad 34, and the third pad 35 correspond to the first metal electrode 27, the second metal electrode 28, and the third metal electrode 29 of a deep ultraviolet light-emitting diode chip of the present invention. In this embodiment, the first, second, and third metal electrodes 29 of the deep ultraviolet light-emitting diode chip are sequentially soldered onto the first pad 33, the second pad 34, and the third pad 35, respectively, and each forms an electrical connection. An optical lens 32 is located at the top of the dam 31, and the optical lens 32 and the support form a sealed structure, encapsulating the deep ultraviolet light-emitting diode chip provided in this embodiment within it.

[0036] The substrate 30 can be made of ceramic, such as aluminum nitride ceramic or alumina ceramic, or it can be made of metal or plastic. Conductive vias 36 are provided inside the substrate 30. The first pad 33, the second pad 34, and the third pad 35 are electrically connected to the first, second, and third pins on the back of the substrate 30 via the conductive vias 36. In practical applications, the first pin is connected to the positive terminal of an external circuit, the second pin is connected to the negative terminal of an external circuit, and the third pin is connected to an external discharge circuit or a preset ground terminal.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A deep ultraviolet light emitting diode chip, characterized by: It includes an epitaxial stack, a first current spreading layer (21), a second current spreading layer (22), a reflective layer (23) and a passivation stack arranged sequentially from bottom to top, as well as a first metal electrode (27), a second metal electrode (28) and a third metal electrode (29). The epitaxial stack includes a substrate (11) and a buffer layer, a first semiconductor layer (12), an active layer (13), and a second semiconductor layer (14) disposed sequentially from bottom to top on one side of the substrate (11). A local area of ​​the first semiconductor layer (12) is exposed, and the first current spreading layer (21) is patterned on the exposed first semiconductor layer (12) and electrically connected thereto; The second current spreading layer (22) is patterned on the second semiconductor layer (14) and electrically connected thereto; The first metal electrode (27), the second metal electrode (28), and the third metal electrode (29) have P-type conductivity, N-type conductivity, and electrical neutrality, respectively.

2. The deep ultraviolet light emitting diode chip of claim 1, wherein: The reflective layer (23) is patterned on the second current extension layer (22), or patterned into multiple independent regions and respectively disposed on the exposed first semiconductor layer (12) and the second current extension layer (22); the reflective layer (23) is a single metal layer, a multi-layer metal stack, or a patterned optical stack made of insulating oxide material and having a distributed Bragg reflection (DBR) structure.

3. The deep ultraviolet light emitting diode chip of claim 1, wherein: The passivation stack covers the entire surface of the exposed first semiconductor layer (12), second semiconductor layer (14), first current spreading layer (21), second current spreading layer (22) and reflective layer (23); the passivation stack is composed of insulating layers and metal layers stacked alternately from bottom to top, and the top and bottom layers of the passivation stack are both insulating layers.

4. The deep ultraviolet light emitting diode chip of claim 3, wherein: Each layer of the passivation stack is provided with a conductive via (36). The conductive vias (36) are stacked in the vertical projection direction to form a first conductive via (36), a second conductive via (36), and a third conductive via (36). The first conductive via (36), the second conductive via (36), and the third conductive via (36) correspond to P-type conductivity, N-type conductivity, and neutral conductivity, respectively. The third conductive via (36) partially penetrates the passivation stack.

5. The deep ultraviolet light emitting diode chip of claim 4, wherein: The first metal electrode (27) penetrates the first conductive via (36) and is electrically connected to the first current spreading layer (21); the second metal electrode (28) penetrates the second conductive via (36) and is electrically connected to the second current spreading layer (22); the third metal electrode (29) penetrates the third conductive via (36) and is electrically connected to the metal layer in the passivation stack.

6. The method of claim 1-5, wherein the method further comprises: Includes the following steps; S1. A buffer layer, a first semiconductor layer (12), an active layer (13), and a second semiconductor layer (14) are epitaxially grown sequentially on a substrate (11) to form an epitaxial stack. S2. Etch away part of the second semiconductor layer (14) and the active layer (13) to expose part of the first semiconductor layer (12); S3. A first current spreading layer (21) and a second current spreading layer (22) are deposited on the exposed first semiconductor layer (12) and the remaining second semiconductor layer (14), respectively, and then subjected to high-temperature annealing treatment in sequence. S4. A metal reflective layer (23) or a non-metallic radiating layer is deposited on the second current spreading layer (22), and the reflective layer (23) is etched to create openings, so that it is partially exposed. S5. A first insulating layer is deposited on the surface of the device as the first layer of the passivation stack. The first insulating layer is patterned and etched to form a first opening, exposing part of the first current extension layer (21) and the second current extension layer (22). S6. Fill the first opening with a patterned protective material and deposit a first metal layer (25) on the surface of the first insulating layer as an intermediate metal layer of the passivation stack. S7. Remove the protective material and part of the first metal layer (25) covering it, so that the first current spreading layer (21) and the second current spreading layer (22) exposed in step S5 are exposed again, and the first metal layer (25) is electrically isolated from the first current spreading layer (21) and the second current spreading layer (22). S8. A second insulating layer is deposited on the surface of the device as the last layer of the passivation stack. The second insulating layer is selectively etched to form a second opening, so that the aforementioned partially exposed first current spreading layer (21) and second current spreading layer (22) remain exposed; and a portion of the first metal layer (25) is partially exposed. S9. A first metal electrode (27), a second metal electrode (28), and a third metal electrode (29) are deposited at the corresponding positions of the second opening.

7. A deep ultraviolet light emitting diode package structure, characterized by: The device includes a support and an optical lens (32). The support consists of a substrate (30) and a dam (31) with an opening at the top and surrounding the substrate (30). A cup is formed on the side of the substrate (30) facing the dam (31). A first pad (33), a second pad (34), and a third pad (35) are provided in the cup. The deep ultraviolet light-emitting diode chip according to any one of claims 1 to 5 is disposed in the cup, and the first metal electrode (27), the second metal electrode (28), and the third metal electrode (29) of the chip are electrically connected to the first pad (33), the second pad (34), and the third pad (35), respectively. The optical lens (32) covers the top of the dam (31) and together with the support, forms a sealed encapsulation cavity. The deep ultraviolet light-emitting diode chip is encapsulated in the encapsulation cavity.

8. The deep ultraviolet light emitting diode package structure of claim 7, wherein: The positional distribution and spacing of the first pad (33), the second pad (34) and the third pad (35) match the positional distribution and spacing of the first metal electrode (27), the second metal electrode (28) and the third metal electrode (29) of the deep ultraviolet light-emitting diode chip.

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